Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a manufacturing method thereof and a photovoltaic module, relates to the technical field of photovoltaic, and is used for optimizing the cell efficiency of the solar cell with an amorphous silicon film layer. The solar cell comprises a semiconductor substrate having a first surface and a second surface opposite to each other; the first semiconductor layer is arranged on the first face, the first semiconductor layer comprises a plurality of first strip-shaped parts extending in the first direction, each first strip-shaped part comprises a first part and a second part, the first parts are located in the middle areas of the extending directions of the first strip-shaped parts, and the second parts are located in the middle areas of the extending directions of the second strip-shaped parts; the second parts are located in edge areas of the two ends of the first strip-shaped part in the extending direction, the edge areas are adjacent to the edge of the first face, the crystallization rate of the first parts is larger than that of the second parts, and the first semiconductor layer comprises at least one of amorphous silicon and nanocrystalline silicon.

Description

[0001] This application claims priority to Chinese Patent Application No. 202411017051.5, filed on July 26, 2024, entitled "A Solar Cell and a Method for Manufacturing the Same, and a Photovoltaic Module", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of photovoltaic technology, and in particular to a solar cell and its manufacturing method, and a photovoltaic module. Background Technology

[0003] In solar cell structures, laser treatment of the textured amorphous silicon layer causes the layer to heat up upon light absorption, leading to the release of hydrogen (H) and increased effective doping. Furthermore, laser treatment reduces the contact resistance of the solar cell, thereby decreasing energy loss during current collection and improving cell efficiency. However, improper laser treatment can lead to increased recombination in certain areas of the solar cell, negatively impacting efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a solar cell and its manufacturing method, as well as a photovoltaic module, to reduce contact resistance, decrease recombination, and improve cell efficiency.

[0005] In a first aspect, the present invention provides a solar cell, comprising: A semiconductor substrate having a first surface and a second surface opposite to each other; A first semiconductor layer is disposed on a first surface. The first semiconductor layer includes a plurality of first strip portions extending along a first direction. Each first strip portion includes a first part and a second part. The first part is located in the middle region of the extension direction of the first strip portion, and the second part is located in the edge regions at both ends of the extension direction of the first strip portion. The edge regions are adjacent to the edges of the first surface. The crystallinity of the first part is greater than that of the second part. The first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

[0006] In the above technical solution, the first semiconductor layer only forms a crystalline structure in the first portion located in the middle region of the semiconductor substrate. This results in a first portion containing both crystalline and non-crystalline parts, while the second portion of the first semiconductor layer located at the edge of the semiconductor substrate remains uncrystallized, retaining its original amorphous structure. This makes the overall crystallinity of the first portion of the first semiconductor layer greater than that of the second portion. The crystalline structure in the first portion is formed by laser irradiation. Due to the non-uniformity of the laser beam across its entire width and the non-uniformity of the thickness of the first semiconductor layer, when the laser acts on the edge of the semiconductor substrate, it damages the passivation of the first semiconductor layer at the edge, thereby increasing recombination at the edge. Therefore, this application does not form a crystalline structure at the edge using laser irradiation, retaining the amorphous structure at the edge of the first semiconductor layer and reserving the second portion at the edge. This ensures the passivation effect of the second portion at the edge, reduces edge recombination, and, since the middle region of the first semiconductor layer has a relatively high crystallinity, the contact resistance is reduced. Therefore, by setting a reasonable region with a crystalline structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized, improving the overall cell efficiency.

[0007] In some possible implementations, the solar cell further includes a third amorphous semiconductor layer disposed on the second surface. This third semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer, with the first semiconductor layer and the third amorphous semiconductor layer having different conductivity types. With this configuration, when the third semiconductor layer includes an amorphous silicon layer, both sides of the semiconductor substrate are provided with a full-surface amorphous silicon layer, and both amorphous silicon layers can form heterojunction structures, thus forming a bifacial heterojunction cell. When the third semiconductor layer includes polycrystalline silicon, a polycrystalline silicon passivation structure can be formed on the second surface, and an amorphous silicon layer or a nanocrystalline silicon layer passivation structure can be formed on the first surface, thus forming a bifacial hybrid cell. As long as an amorphous silicon layer and / or a nanocrystalline silicon layer are present, bifacial heterojunction cells and bifacial hybrid cells can also be applied to the cell structure of this application, where the edges are amorphous and the middle region has a crystalline structure, to improve cell efficiency.

[0008] In some possible implementations, the third semiconductor layer is a polycrystalline silicon layer, which is arranged in a strip on the second surface, or the entire third semiconductor layer is arranged on the second surface, and the third semiconductor layer includes a thicker portion arranged in a strip and a thinner portion other than the thicker portion.

[0009] In some possible implementations, the solar cell further includes a second semiconductor layer disposed on the first surface. The second semiconductor layer includes multiple second strip-shaped portions extending along a first direction. The first and second strip-shaped portions are arranged alternately along a second direction. The first and second semiconductor layers have different conductivity types, and the first and second directions intersect. To achieve the arrangement of P-regions and N-regions on the first surface, the first semiconductor layer is one of P-regions and N-regions, and the second semiconductor layer is the other of P-regions and N-regions. For the strip-shaped first strip-shaped portion, the first portion is located in the middle region of the extending direction of the first strip-shaped portion, and the second portion is located in the end edge regions of the extending direction. This achieves the setting of an amorphous structure at the edges of the first semiconductor layer.

[0010] In some possible implementations, within the first strip, the first portion includes a strip-shaped middle portion extending along a first direction and strip-shaped edge portions disposed on both sides of the middle portion along a second direction. The crystallinity of the middle portion is greater than that of the edge portions. That is, in the second direction, the first portion is not entirely composed of portions with the same crystallinity; rather, the crystallinity of the middle portion is greater than that of the two edge portions. Amorphous structures are reserved on both sides of the first portion in the second direction, and their crystallinity can be the same as that of the second portion. This ensures that the middle portion, with its relatively higher crystallinity, does not include the overlapping portion of the first strip on the second strip, thus providing better insulation between the first and second strips of different conductivity types at the overlapping portion and reducing leakage current.

[0011] In some possible implementations, within the first strip, the width of the edge portion on one side of the middle portion along the second direction is less than or equal to 100 μm. This configuration maximizes the area of ​​the middle portion by minimizing the width of the edge portion, thereby reducing contact resistance and improving current collection capability.

[0012] In some possible implementations, the second semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. With this configuration, by selecting different materials for the second semiconductor layer, back contact batteries with different structures in the P-region and N-region can be formed. As long as an amorphous silicon layer is present, various back contact batteries can also be applied to the battery structure of this application, where the edges are amorphous and the central region has a crystalline structure, to improve battery efficiency.

[0013] In some possible implementations, along the second direction, the crystallinity of at least one first strip near the edge of the first surface is the same as the crystallinity of the second portion. With this configuration, for the strip-shaped first strip, multiple first strips are arranged along the second direction, and in this arrangement direction, the entire area of ​​at least one first strip near the edge of the first surface has the same crystallinity as the second portion. That is, at least one first strip near the edge does not undergo laser crystallization processing, while the remaining first strips only form amorphous second portions at their two ends along the extension direction, thus realizing the edge amorphization structure of the first semiconductor layer.

[0014] In some possible implementations, the contact resistance of the first part is less than that of the second part. Since the first part can have a crystalline structure and the second part has an amorphous structure, the effective doping of the crystalline structure of the first part is increased, which reduces the contact resistance of the first part relative to the second part. This reduces the energy loss during the current collection process of the first part and improves the battery efficiency.

[0015] In some possible implementations, the first strip portion has a stacked portion superimposed on the second strip portion, and the first portion does not include the stacked portion; and / or, the solar cell further includes a first transparent conductive layer covering a portion of the first portion, and the projection of the middle portion onto the first transparent conductive layer is at least within the boundary of the first transparent conductive layer. This configuration, by providing a transparent conductive layer, improves the carrier transport capability of the first semiconductor layer, enabling good ohmic contact with the electrode and improving conductivity. Furthermore, the middle portion with a crystalline structure does not extend beyond the boundary of the first transparent conductive layer, thereby reducing contact resistance within the effective conductive area of ​​the first transparent conductive layer, improving conductivity, and increasing cell efficiency.

[0016] In some possible implementations, the solar cell further includes a second transparent conductive layer and a third transparent conductive layer, wherein the second transparent conductive layer covers the partially stacked portion and a portion of the second strip portion; and the third transparent conductive layer covers a portion of the second portion. A PN isolation region exists between adjacent first and second transparent conductive layers; There are edge isolation regions between the first and third transparent conductive layers, as well as between the second and third transparent conductive layers.

[0017] With the above technical solution, electrical insulation between the P and N regions is achieved through the PN isolation region, and electrical insulation between the middle and edge regions is achieved through the edge isolation region. Furthermore, the projection of the middle portion of the first strip is located within the boundary of the first transparent conductive layer. Therefore, the middle portion will not enter the boundary of the edge isolation region and / or the boundary of the PN isolation region. Consequently, the laser irradiation range will not enter the edge isolation region and the PN isolation region. Since the isolation region does not have a crystalline structure, the electrical insulation effect of the isolation region is guaranteed.

[0018] In some possible implementations, the brightness of the first part in the image obtained from the EL test of the solar cell is greater than that of the second part. When the solar cell is tested under the same conditions, the fact that the brightness of the first part is greater than that of the second part in the resulting image indicates that the contact resistance of the first part, which has a crystalline structure, is smaller than that of the second part, which does not have a crystalline structure. Therefore, when the solar cell is energized and tested, the electroluminescence brightness of the first part, with its smaller contact resistance, is greater, while the electroluminescence brightness of the second part is smaller.

[0019] In some possible implementations, the solar cell further includes a first grid electrode extending along a first direction. The first grid electrode is conductively disposed on a first portion of the first semiconductor layer and extends from the first portion to a second portion. The extension direction of the first grid electrode is consistent with the extension direction of the first semiconductor layer, and it can collect charge carriers from both the first portion and a portion of the second portion. Therefore, it can improve the charge carrier collection capability of the first grid electrode for the first semiconductor layer.

[0020] In some possible implementations, the width of the second part, along the direction from the first part to the second part and perpendicular to the edge length of the semiconductor substrate, is 0.3mm to 12mm. This means that a 0.3mm to 12mm edge region of the semiconductor substrate is left untreated by laser crystallization. If the width of the second part is too wide, the area of ​​the first part of the solar cell as a whole is small, resulting in less reduction in series resistance and greater losses during current collection. If the width of the second part is too small, on the one hand, the edge of the first semiconductor layer is thinner due to limitations in the coating process; on the other hand, the laser irradiation angle at the edge of the solar cell is larger, causing deviations in the energy distribution within the laser spot, which can easily lead to excessively high laser energy density in some areas, damaging the passivation of the first semiconductor layer in the edge region. Therefore, considering the overall reduction of the contact resistance of the solar cell and minimizing damage to the passivation, a width of 0.3mm to 12mm is chosen for the second part.

[0021] In some possible implementations, the semiconductor substrate includes a recessed portion on a first surface, which is recessed toward a second surface relative to the remainder of the first surface, with a central portion located within the recessed portion. This configuration, where the recessed portion is formed by etching to the surface of the semiconductor substrate, typically has a textured surface. Placing the central portion, which has a relatively high crystallinity, within the recessed portion increases the contact area of ​​the central portion, facilitating current collection.

[0022] In a second aspect, the present invention also provides a photovoltaic module, including a solar cell, wherein the solar cell is any of the solar cells described above.

[0023] Since the photovoltaic module uses the solar cells of any of the first aspects or above, the photovoltaic module has the same beneficial effects as the first aspect, which will not be elaborated here.

[0024] Thirdly, the present invention also provides a method for manufacturing a solar cell, comprising: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces; A first semiconductor layer is formed on a first surface. The first semiconductor layer includes a plurality of first strips extending along a first direction. Each first strip includes a first portion and a second portion. The first portion is located in the middle region of the extending direction of the first strip, and the second portion is located in the edge regions at both ends of the extending direction of the first strip. The edge regions are adjacent to the edges of the first surface. The first part is irradiated with a laser, while the second part is not irradiated, such that the crystallinity of the first part is greater than that of the second part; the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

[0025] In the above technical solution, a laser is used to crystallize the first portion of the middle region of the first semiconductor layer, thereby increasing the crystallinity. The second portion of the first semiconductor layer located at its two edge regions along the first direction is not irradiated by the laser, retaining its amorphous structure. Due to the non-uniformity of the laser beam across its entire width and the non-uniform thickness of the first semiconductor layer, when the laser acts on the edge region of the first semiconductor layer, it can damage the passivation of the edge region, thus increasing recombination. Therefore, this application does not form a crystallized structure in the edge region using a laser, retaining the amorphous structure of the edge region of the first semiconductor layer. This ensures the passivation effect in the edge region, reduces edge recombination, and the laser crystallization in the middle region of the first semiconductor layer forms the first portion, reducing contact resistance. Therefore, by reasonably controlling the laser irradiation area on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized, improving the overall cell efficiency. When the first semiconductor layer includes an amorphous silicon layer and / or a nanocrystalline silicon layer, laser irradiation can improve the crystallinity.

[0026] In some possible implementations, the first face has a first side and a second side that are arranged opposite to each other along a first direction; The middle section is irradiated with a laser, including: The laser is used to irradiate from a position at a first distance from the first side, and passes through the first part in a first direction, stopping at a position at a second distance from the second side.

[0027] When the above technical solution is adopted, the laser irradiates the first semiconductor layer along the direction from the first side to the second side. The starting point of the first part of the irradiation is a first distance from the first side, and the ending point of the first part of the irradiation is a second distance from the second side. Only the first part of the first semiconductor layer is irradiated, and the laser irradiation stops at the first part located on both sides of the first part. The irradiation can be repeated multiple times along the first direction so that the range of the first part perpendicular to the first direction is irradiated by the laser.

[0028] In some possible implementations, the first distance and / or the second distance is 0.2mm to 12mm. This leaves room for an un-irradiated portion of the first semiconductor layer. If the second portion is too wide, the overall area of ​​the first part of the solar cell is small, resulting in less reduction in series resistance and greater current collection losses. If the width of the second part of the first semiconductor layer is too small, on the one hand, due to limitations in the coating process, the first semiconductor layer in the second part is relatively thin; on the other hand, the laser irradiation angle at the edge of the solar cell is too large, causing a deviation in the energy distribution within the laser spot, which can easily lead to excessively high laser energy density in some areas, damaging the passivation of the first semiconductor layer in the second part. Therefore, considering the reduction of the overall contact resistance of the solar cell and minimizing damage to the passivation, a first distance and / or the second distance of 0.2mm to 12mm is chosen.

[0029] In some possible implementations, the first semiconductor layer includes an amorphous silicon layer. After the first portion is irradiated with a laser, a portion of the amorphous silicon layer crystallizes to form nanocrystals. When the first semiconductor layer is an amorphous silicon layer, the portion not irradiated by the laser exhibits better passivation and improved insulation in the isolation region.

[0030] In some possible implementations, the laser wavelength is 325 nm to 532 nm; and / or, the laser energy density is 200 mJ / cm². 2 ~6000 mJ / cm 2By setting this wavelength range, the laser can be absorbed by the amorphous semiconductor layer, which is beneficial for achieving crystallization of the amorphous semiconductor layer. If the laser energy density is too high, the high-temperature range will expand, and the temperature at the tip of the textured structure will be too high, thus affecting the passivation of the tip region of the textured structure. If the laser energy density is too low, the energy accumulation time will be too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, selecting a laser energy density within this range allows only the tip of the textured structure to reach a high temperature, achieving morphological changes and forming a crystalline structure. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a solar cell without electrodes on the first side, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a first side of a solar cell containing an electrode, provided by an embodiment of the present invention; Figure 3 for Figure 2 A magnified view of a portion of the image; Figure 4 This is a partial schematic diagram of the arrangement of the transparent conductive layer on the first surface of a solar cell according to an embodiment of the present invention; Figure 5 for Figure 4 A schematic cross-sectional view of section AA in the diagram; Figure 6 for Figure 4 A schematic cross-sectional view of section BB in the diagram; Figure 7 for Figure 2 A magnified view of a portion of the image; Figures 8-19 A schematic flowchart illustrating the steps of a method for manufacturing a solar cell according to an embodiment of the present invention; Figure 20 A schematic diagram comparing EL test images of a solar cell provided in an embodiment of the present invention and a conventional solar cell with a crystallization region; Figure 21 This is a schematic diagram comparing the P-region contact resistance of a solar cell provided in an embodiment of the present invention and a conventional solar cell without a crystallization region.

[0032] Reference numerals: 100 is the first semiconductor layer, 1 is the first strip, 11 is the first portion, 12 is the second portion, 13 is the intrinsic amorphous silicon layer, 14 is the p-type amorphous silicon layer, 15 is the stacked portion, 2 is the second semiconductor layer, 21 is the tunneling oxide layer, 22 is the n-type doped polycrystalline silicon layer, 3 is the edge isolation region, 4 is the first gate electrode, 5 is the second gate electrode, 6 is the semiconductor substrate, 7 is the transparent conductive layer, 71 is the first transparent conductive layer, 72 is the second transparent conductive layer, 73 is the third transparent conductive layer, 8 is the passivation layer, 9 is the antireflection layer, and 10 is the PN isolation region. Detailed Implementation

[0033] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0034] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature marked with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0036] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] like Figures 1-7 As shown, this embodiment of the invention provides a solar cell, including a semiconductor substrate 6 and a first semiconductor layer 100. The semiconductor substrate 6 has opposing first and second surfaces. The first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6 and includes a plurality of first strip-shaped portions 1 extending along a first direction. Each first strip-shaped portion 1 includes a first portion 11 and a second portion 12. The first portion 11 is located in the middle region of the extending direction of the first strip-shaped portion 1, and the second portion 12 is located at both end edge regions of the extending direction of the first strip-shaped portion 1. The edge regions are adjacent to the edges of the first surface, meaning that the first portion 11 does not extend to the edge of the semiconductor substrate 6 in its extending direction, but rather has a second portion 12 between it and the edge of the semiconductor substrate 6. The crystallinity of the first portion 11 is greater than that of the second portion 12. The first semiconductor layer 100 includes at least one of amorphous silicon and nanocrystalline silicon, meaning that the first semiconductor layer 100 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon. After laser crystallization, its crystallinity can be improved. For example, when the first semiconductor layer 100 is an amorphous silicon layer, in the laser-crystallized portion, some of the amorphous silicon layer will crystallize to form nanocrystals. When the first semiconductor layer 100 is a nanocrystalline silicon layer or a combination of amorphous silicon and nanocrystals, in the laser-crystallized portion, the crystallinity or crystallization rate of the first semiconductor layer 100 will increase.

[0039] In practical applications, this embodiment of the invention does not specifically limit the material and conductivity type of the semiconductor substrate 6. For example, the semiconductor substrate 6 can be a silicon substrate. Alternatively, the semiconductor substrate 6 can also be a substrate made of any semiconductor material, such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 6 can be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0040] Secondly, the first surface of the semiconductor substrate 6 corresponds to the back surface of the solar cell, and the second surface of the semiconductor substrate 6 corresponds to the light-facing surface of the solar cell, i.e., the front surface.

[0041] When the above technical solution is adopted, the first semiconductor layer 100 only forms a crystallized structure in the first part 11 located in the middle region of the first strip 1, so that the first part 11 has both a crystallized part and an uncrystallized part. The first part 11 is not entirely a crystallized structure, but mostly an amorphous structure, with only a portion forming a crystallized structure, such as nanocrystals. The second part 12 of the first semiconductor layer 100 located at the two edge regions of the first strip 1 along the first direction is not crystallized and retains the original amorphous structure (it should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon, the crystallinity or crystallinity of the nanocrystalline silicon in the second part 12 remains unchanged), so that the overall crystallinity of the first part 11 of the first semiconductor layer 100 is greater than the overall crystallinity of the second part 12. The crystalline structure in the first part 11 is formed by laser irradiation. Due to the non-uniformity of the laser beam across the entire surface and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge of the semiconductor substrate 6, it will damage the passivation of the first semiconductor layer 100 at the edge, thereby increasing the recombination at the edge. Therefore, this application does not form a crystalline structure at the edge of the first semiconductor layer 100 by laser, but retains the amorphous structure at the edge of the first semiconductor layer 100, reserving the second part 12 at the edge, thereby ensuring the passivation effect of the second part 12 at the edge and reducing the recombination at the edge. In addition, the first part 11 with a crystalline structure is formed in the middle region of the first semiconductor layer 100. The crystalline structure in the first part 11 reduces the contact resistance. At the same time, the amorphous structure in the first part 11 has a good passivation effect. Therefore, by setting reasonable crystalline and amorphous regions on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0042] In some possible implementations, the contact resistance of the first portion 11 is less than that of the second portion 12. Since the first portion 11 has a crystalline structure or higher crystallinity, while the second portion 12 has an amorphous structure or lower crystallinity, the effective doping of the first portion 11 is increased. This increases the contact resistance of the first portion 11 relative to the second portion 12, thereby reducing energy loss during current collection in the first portion 11 and improving battery efficiency. For example, such as... Figure 21 As shown, when the first semiconductor layer 100 is disposed in the P region, it can be seen from the comparison of the P region contact resistance of the cell in the amorphous region and the cell in the crystalline region that the overall contact resistance of the solar cell with the first part 11 in the first semiconductor layer 100 is less than the overall contact resistance of the solar cell without the first part 11 in the first semiconductor layer 100.

[0043] Based on this, a third semiconductor layer with the opposite conductivity type to the first semiconductor layer 100 is disposed on the second surface. The third semiconductor layer includes a polycrystalline silicon layer or an amorphous silicon layer. For example, if the entire second surface is covered with an amorphous silicon layer, the third semiconductor layer can also form a heterojunction structure. The structure of the third semiconductor layer can be similar to that of the first semiconductor layer 100, also having a first part and a second part, with the crystallinity of the first part being greater than that of the second part.

[0044] In one example, assuming the first semiconductor layer has a P-type conductivity and the third semiconductor layer has an N-type conductivity, the first semiconductor layer includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer positioned close to the first surface. The third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface, with the third intrinsic amorphous silicon layer positioned close to the second surface, forming a bifacial heterojunction solar cell. Of course, the first semiconductor layer can also have an N-type conductivity and the third semiconductor layer can have a P-type conductivity, which will not be elaborated further.

[0045] In another example, a polycrystalline silicon layer is disposed on the second surface. The third semiconductor layer can then form a tunneling passivation contact structure. Specifically, the first semiconductor layer has a P-type conductivity, and the third semiconductor layer has an N-type conductivity. The first semiconductor layer includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer positioned close to the first surface. The third semiconductor layer includes an N-type doped polycrystalline silicon layer disposed on the second surface. A tunneling oxide layer is also disposed between the N-type doped polycrystalline silicon layer and the second surface. The tunneling oxide layer and the N-type doped polycrystalline silicon layer constitute a tunneling passivation contact structure. The third semiconductor layer can be partially disposed on the second surface, for example, in multiple strip-like configurations, forming a poly-finger structure. Doped field regions can be selectively formed on the substrate between the polyfingers. Alternatively, the third semiconductor layer can be formed entirely on the second surface, with a thicker portion in the metallized contact area and a thinner portion in the non-metallized area. If the first semiconductor layer can be a heterojunction structure, a bifacial hybrid solar cell is formed. Of course, the conductivity type of the first semiconductor layer can also be N-type, and the conductivity type of the third semiconductor layer can be P-type, which will not be elaborated further.

[0046] Bifacial heterojunction cells and bifacial hybrid solar cells can also be applied to the cell structure in this application, where the edges are amorphous and the middle region is crystalline, as long as they have an amorphous silicon layer and / or a nanocrystalline silicon layer, in order to improve cell efficiency.

[0047] like Figure 1As shown, this embodiment provides another type of solar cell. The solar cell further includes a second semiconductor layer 2 disposed on a first surface. The first semiconductor layer 100 includes multiple first strip-shaped portions 1 extending along a first direction, and the second semiconductor layer 2 includes multiple second strip-shaped portions extending along the first direction. The first strip-shaped portions 1 and the second strip-shaped portions are arranged alternately along a second direction. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the first and second directions intersect. In the case where the first semiconductor layer 100 is disposed on the first surface, to achieve the arrangement of P-regions and N-regions on the first surface, the first semiconductor layer 100 is one of P-regions and N-regions, and the second semiconductor layer 2 is the other of P-regions and N-regions. For the strip-shaped first strip-shaped portion 1, the first portion 11 is located in the middle region of the extending direction of the first strip-shaped portion 1, and the second portion 12 is located in the two end edge regions of the extending direction. This achieves the setting of an edge amorphous structure for the first semiconductor layer 100.

[0048] like Figure 6 and Figure 7 As shown, in some embodiments, for the strip-shaped first strip portion 1, the first portion 11 includes a strip-shaped middle portion extending along a first direction and strip-shaped edge portions disposed on both sides of the middle portion along a second direction. The lengths of the middle portion and the edge portions along the first direction can be the same. The crystallinity of the middle portion is greater than that of the edge portions, and the crystallinity of the edge portions can be the same as that of the second portion 12. That is, along the second direction, the first portion 11 is further divided into a middle portion and an edge portion, while the entire second portion 12 is an amorphous structure. In the second direction, not the entire area of ​​the first portion 11 is crystallized; only the middle portion is crystallized. The two sides of the middle portion and the second portion 12 are amorphous structures and are not subjected to laser crystallization. Since the first portion 11 has a crystalline structure and the second portion 12 has an amorphous structure, the overall crystallinity of the middle portion is greater than that of the edge portions and the second portion 12. This configuration ensures that the middle portion with a relatively high crystallinity does not include the stacked portion 15 where the first strip 1 is stacked on the second strip, thus providing better insulation between the first strip 1 and the second strip of different conductivity types in the stacked portion 15 and reducing leakage current.

[0049] Furthermore, in this embodiment, within the first strip 1, the width of the edge portion on one side of the middle portion along the second direction is less than or equal to 100 μm. This configuration maximizes the area of ​​the middle portion by minimizing the width of the edge portion, thereby reducing contact resistance and improving current collection capability.

[0050] like Figure 1As shown, in some possible implementations, along the second direction, the crystallinity of at least one first stripe 1 near the edge of the first surface is the same as the crystallinity of the second portion 12. With this configuration, for the strip-shaped first stripe 1, multiple first stripe 1 are arranged along the second direction. In this arrangement direction, the entire area of ​​at least one first stripe 1 near the edge of the first surface has the same crystallinity as the second portion 12. That is, at least one first stripe 1 near the edge is not laser-crystallized, while the remaining first stripe 1 only forms an amorphous second portion 12 at both ends of its extension direction, thus realizing the edge amorphous structure of the first semiconductor layer 100.

[0051] For example, in the second direction, the crystallization rate of the entire area of ​​the two strip portions 1 located on the two edges of the first surface is the same as that of the second portion 12, or near the edge of each first surface, two or three equal numbers of the first strip portions 1 are reserved with the same crystallization rate as the second portion 12.

[0052] In some embodiments, the width of the second portion 12 is 0.3mm to 12mm along the direction from the first portion 11 to the second portion 12 and perpendicular to the side length of the semiconductor substrate 6. That is, a 0.3mm to 12mm edge region is reserved around the first semiconductor layer 100 of the semiconductor substrate 6 without laser crystallization treatment. If the width of the second portion 12 is too wide, the area of ​​the first portion 11 with the crystallized structure of the entire solar cell will be small, resulting in a smaller reduction in series resistance and a larger loss during current collection. If the width of the second portion 12 is too small, on the one hand, the edge of the first semiconductor layer 100 is thinner due to the limitations of the coating process; on the other hand, the angle of laser irradiation at the edge of the solar cell will be larger, causing a deviation in the energy distribution within the laser spot, which may result in some areas having excessively high laser energy density and damaging the passivation of the first semiconductor layer 100 at the edge. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to the passivation, the width of the second portion 12 is selected to be 0.3mm to 12mm.

[0053] Furthermore, the width of the second portion 12 is 0.3mm to 3mm. This further increases the area of ​​the first portion 11 of the first semiconductor layer 100, reduces contact resistance, and improves battery efficiency. Specifically, the width of the second portion 12 can be 0.3mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, etc.

[0054] For example, for a first semiconductor layer 100 including a plurality of first strip portions 1, along the extension direction (first direction) of the first strip portions 1, the extension length of the second portions 12 at both ends of the first strip portions 1 is 1 mm, 1.2 mm, 1.5 mm, etc. Along the arrangement direction (second direction) of the plurality of first strip portions 1, the crystallinity of the two first strip portions 1 near the two side edges of the first surface is the same as the crystallinity of the second portions 12.

[0055] In some embodiments, when the first side of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, i.e., when the solar cell is a back-contact cell, the second semiconductor layer 2 may include amorphous silicon and / or nanocrystalline silicon. The second semiconductor layer 2 has a structure similar to the first semiconductor layer 100, except that the conductivity type is different. That is, the second semiconductor layer 2 also has a first portion located in the middle region of the first side and a second portion located in the edge region of the first side. The first portion of the second semiconductor layer 2 may be entirely laser-crystallized, or it may not be entirely laser-crystallized. Referring to the description of the first portion 11 of the first semiconductor layer 100 above, it will not be repeated here.

[0056] For example, taking a first semiconductor layer corresponding to the P-region and a second semiconductor layer corresponding to the N-region as an example, the first semiconductor layer may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked together, and the second semiconductor layer may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked together. Both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are disposed close to the semiconductor substrate. Of course, the conductivity types of the first semiconductor layer and the second semiconductor layer can be interchanged, which will not be elaborated further.

[0057] With this configuration, for the first and second semiconductor layers with different conductivity types disposed on the first side, both the first and second semiconductor layers can form heterojunction structures, resulting in a heterojunction back contact battery with both P-region and N-region heterojunction structures on the back side. This configuration offers advantages such as good passivation, high conversion efficiency, long lifespan, and low fabrication energy consumption. As long as an amorphous silicon layer and / or a nanocrystalline silicon layer are present, the heterojunction back contact battery can also be applied to the battery structure described in this application, where the edges are amorphous and the central region is crystalline, to improve battery efficiency.

[0058] like Figures 1-7As shown, in some embodiments, when the first side of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back contact cell, the second semiconductor layer 2 can be at least one of a polycrystalline silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer, and the first semiconductor layer 100 can be a heterojunction structure. When the second semiconductor layer 2 is a polycrystalline silicon layer, a tunneling passivation contact structure can be formed. The second semiconductor layer 2 and the first semiconductor layer 100 have different conductivity types.

[0059] For example, the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer stacked on the first surface. The tunneling oxide layer 21 is disposed close to the semiconductor substrate 6. Taking the second semiconductor layer 2 corresponding to the N-region and the first semiconductor layer 100 corresponding to the P-region as an example, the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22. The first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 stacked on the first surface. The intrinsic amorphous silicon layer 13 is disposed close to the semiconductor substrate 6. Of course, when the second semiconductor layer 2 corresponds to the P-region and the first semiconductor layer 100 corresponds to the N-region, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.

[0060] This configuration, by setting a second semiconductor layer 2 and a first semiconductor layer 100 with different conductivity types on the first surface, forms a hybrid back contact battery with both a tunneling passivation contact structure and a heterojunction structure on the back side. The first semiconductor layer 100 is a heterojunction structure. This battery combines the advantages of high conversion efficiency, good stability, and low Auger recombination of the tunneling passivation contact structure with the advantages of good passivation effect, high conversion efficiency, long lifespan, and low fabrication energy consumption of the heterojunction structure. As long as an amorphous silicon layer and / or a nanocrystalline silicon layer is present, the hybrid back contact battery can also be applied to the battery structure in this application where the edges are amorphous and the central region is crystalline, to improve battery efficiency. Of course, when the second semiconductor layer 2 is made of other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed. By selecting different materials for the second semiconductor layer 2, back contact batteries with different structures in the P-region and N-region can be formed.

[0061] like Figure 1 , Figures 4-7As shown, in some possible implementations, the first strip 1 has a stacked portion 15 superimposed on the second strip, and the first portion 11 does not include the stacked portion 15; and / or, the solar cell further includes a first transparent conductive layer 71 covering the first portion 11, the projection of the middle portion of the first portion 11 onto the first transparent conductive layer 71 being at least within the boundary of the first transparent conductive layer 71. With this configuration, by providing the first transparent conductive layer 71, the carrier transport capability of the first semiconductor layer 100 is improved, enabling good ohmic contact with the electrode and improving conductivity. The middle portion with a crystalline structure does not extend beyond the boundary of the first transparent conductive layer 71, thereby reducing contact resistance within the effective conductive area of ​​the first transparent conductive layer 71, improving conductivity, and increasing cell efficiency.

[0062] like Figures 5-7 As shown, in some embodiments, the solar cell further includes a second transparent conductive layer 72 and a third transparent conductive layer 73. The second transparent conductive layer 72 covers a portion of the stacked portion 15 and a portion of the second strip portion; the third transparent conductive layer 73 covers a portion of the second portion 12, mainly covering the position of the second portion 12 near the edge of the semiconductor substrate 6; wherein, a PN isolation region 10 is provided between adjacent first transparent conductive layers 71 and second transparent conductive layers 72; and edge isolation regions 3 are provided between the first transparent conductive layer 71 and the third transparent conductive layer 73 and between the second transparent conductive layer 72 and the third transparent conductive layer 73.

[0063] With the above technical solution, electrical insulation between the P-region and the N-region is achieved through the PN isolation region 10, and electrical insulation between the PN region located in the middle region and the dead region located in the edge region is achieved through the edge isolation region. It should be noted that the dead region may include a stack of a first semiconductor layer and a second semiconductor layer, with the first semiconductor layer stacked on the second semiconductor layer. The first semiconductor layer located in the dead region belongs to the edge region of the second part, and the third transparent conductive layer 73 is disposed on the first semiconductor layer located in the dead region. The projection of the middle part of the first strip is located within the boundary of the first transparent conductive layer. Therefore, the middle part will not enter the boundary of the edge isolation region and / or the boundary of the PN isolation region. Thus, the irradiation range of the laser will not enter the edge isolation region and the PN isolation region. Since the isolation region does not have a crystalline structure or has a low crystallinity, the electrical insulation effect of the isolation region is guaranteed.

[0064] For example, such as Figure 6 and Figure 7As shown, the first semiconductor layer 100 has a stacked portion 15 stacked on the second semiconductor layer 2 in the second direction. For example, when the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polycrystalline silicon layer 22, and the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps the second semiconductor layer 2 to form the stacked portion 15. In this case, the PN isolation region 10 spans part of the stacked portion 15 and part of the non-stacked portion of the first semiconductor layer 100. Figure 5 As shown, the edge isolation region 3 spans a portion of the stack of the first semiconductor layer 100 and the second semiconductor layer 2, as well as a portion of the second portion 12, specifically, spanning the sidewalls and a portion of the bottom wall of the recessed portion of the semiconductor substrate.

[0065] Based on the PN isolation region 10 and the edge isolation region 3, along the second direction, such as Figure 6 As shown, the distance between the boundary of the middle portion (i.e., the crystallized region) on the first semiconductor layer 100 and the boundary of the PN isolation region 10 is greater than or equal to zero; and / or, as Figure 5 As shown, along the first direction and / or the second direction, the distance between the boundary of the middle portion (i.e., the crystallized region) of the first portion 11 on the first semiconductor layer 100 and the boundary of the edge isolation region 3 is greater than or equal to zero. That is, the middle portion does not enter the boundary of the edge isolation region 3 and / or does not enter the boundary of the PN isolation region 10, so the irradiation range of the laser will not enter the edge isolation region 3 and the PN isolation region 10. Since the first semiconductor layer 100 located in the edge isolation region 3 and the PN isolation region 10 is still an amorphous structure or has a low crystallinity, the electrical insulation effect of the edge isolation region 3 and the PN isolation region 10 is guaranteed.

[0066] like Figures 5-7 As shown, the first transparent conductive layer 71, the second transparent conductive layer 72, and the third transparent conductive layer 73 can be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layers can be single-layer thin films or multilayer thin films.

[0067] like Figure 20As shown, in this embodiment, EL (Electroluminescent) testing of the solar cell is a method for detecting internal defects in the solar cell. In the image obtained from the EL test, the brightness of the first part 11, which has a relatively high crystallinity, is greater than the brightness of the second part 12, which has a relatively low crystallinity. Under the same conditions, the EL test on the solar cell shows that the brightness of the first part 11 is greater than that of the second part 12, indicating that the contact resistance of the first part 11 is smaller than that of the second part 12. When the solar cell is powered on for testing, the electroluminescence brightness of the first part 11, with its lower contact resistance, is greater, while the electroluminescence brightness of the second part 12 is lower. Figure 20 The image of solar cell B shows that it has a first part 11 in the middle region and a second part 12 in the edge region. The brightness of the first part 11 in the middle region is greater than that of the second part 12 in the edge region. Comparing this image with that of solar cell C, it can be seen that solar cell C does not have the first part 11 in the middle region. Therefore, the brightness of solar cell C is uniform across its entire surface, and its overall brightness is lower than that of solar cell B, indicating that solar cell C has a higher overall contact resistance.

[0068] like Figure 2 and Figure 3 As shown, in some possible implementations, the solar cell further includes a first grid electrode 4 extending along a first direction. The first grid electrode 4 is conductively disposed on a first portion 11 of the first semiconductor layer 100 and extends from the first portion 11 to a second portion 12, having a middle portion extending from the first portion 11 to the second portion 12. The first grid electrode 4 does not extend into the edge isolation region 3. The extending direction of the first grid electrode 4 is consistent with the extending direction of the first strip portion 1, and it can collect charge carriers from both the first portion 11 and a portion of the second portion 12 on the same first semiconductor layer 100. Therefore, the charge carrier collection capability of the first grid electrode 4 for the first semiconductor layer 100 can be improved.

[0069] For a solar cell having a second semiconductor layer 2, the solar cell further includes a second grid electrode 5 conductively disposed on the second semiconductor layer 2, the extension direction of the second grid electrode 5 being along a first direction and consistent with the extension direction of the second semiconductor layer 2. In the case of having a first transparent conductive layer 71 and a second transparent conductive layer 72, the first grid electrode 4 is disposed on the first transparent conductive layer 71, and the second grid electrode 5 is disposed on the second transparent conductive layer 72.

[0070] In some embodiments, the side of the semiconductor substrate with the amorphous semiconductor layer has a textured structure. The amorphous semiconductor layer and the textured structure are conformal. The textured structure has a light-trapping effect, increasing light collection, and also enables better contact with the electrode. When laser crystallization is performed on a first portion of the first semiconductor layer, the laser irradiates the textured structure of the first portion, reaching the crystallization temperature, causing a localized area of ​​the first portion to form a crystalline microcrystalline or nanocrystalline structure. Thus, the crystalline region has both an amorphous and a crystalline structure. The crystalline structure reduces contact resistance but also reduces the passivation effect, increasing the possibility of recombination, which is detrimental to photoelectric efficiency. Therefore, by forming a crystalline structure in a localized area of ​​a portion of the textured structure, the two factors of contact resistance and passivation effect can be balanced, thereby optimizing battery efficiency.

[0071] like Figure 5 and Figure 6 As shown, in some embodiments, the semiconductor substrate 6 includes a recessed portion on a first surface, the recessed portion including sidewalls and a bottom wall, the recessed portion being recessed relative to the remainder of the first surface toward a second surface, and a first portion 11 being located within the recessed portion. This configuration, where the recessed portion is formed by etching to the surface of the semiconductor substrate 6, typically has a textured structure. Placing the first portion 11, which is composed of amorphous silicon and nanocrystalline silicon, in the recessed portion increases the contact area of ​​the intermediate portion, which is beneficial for current collection.

[0072] This embodiment describes the structure of a solar cell from the perspective of the first semiconductor layer only. Figures 1-7 For example, the solar cell includes a semiconductor substrate 6 and a first semiconductor layer 100. The semiconductor substrate 6 has a first surface and a second surface facing each other. The first semiconductor layer 100 is disposed on the first surface and includes a central portion located in its central region and an edge portion located in the peripheral region of the central portion. The central portion includes amorphous silicon and nanocrystalline silicon, and the edge portion is amorphous silicon. The edge portion surrounds the central portion. It should be noted that the edge portion here does not refer to the edge of the semiconductor substrate 6; there is a certain distance between the edge portion of the first semiconductor layer 100 and the edge of the semiconductor substrate 6.

[0073] Because a crystalline structure is formed only in the central portion of the first semiconductor layer, this central portion contains both nanocrystalline silicon and amorphous silicon, while the edge portions of the first semiconductor layer surrounding the central portion remain uncrystallized, retaining their original amorphous silicon. This results in a higher overall crystallinity in the central portion of the first semiconductor layer compared to the edge portions. The nanocrystalline silicon in the central portion is formed by laser irradiation of the amorphous silicon. However, due to the non-uniformity of the laser beam across the entire surface and the uneven thickness of the first semiconductor layer, the laser can damage the passivation at the edges of the first semiconductor layer when it strikes them, increasing recombination at the edges. Therefore, this application avoids forming nanocrystalline silicon at the edges using laser irradiation, retaining the amorphous silicon at the edges of the first semiconductor layer. This ensures the passivation effect at the edges near the semiconductor substrate, reduces recombination at the edges, and results in a relatively high crystallinity in the central portion of the first semiconductor layer, reducing contact resistance. Thus, by setting a reasonable region with a crystalline structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized, improving the overall cell efficiency.

[0074] In some embodiments, the first semiconductor layer covers the entire surface of the first surface, with the edge portion forming an annular shape between the middle portion and the edge of the first surface. With this configuration, the entire first surface of the solar cell is covered by the first semiconductor layer, forming one side of a bifacial solar cell, which can serve as a P-region or an N-region. The first semiconductor layer on this side can form a heterojunction structure. As long as the first semiconductor layer of this application is present, the bifacial solar cell can also be adapted to the cell structure of this application, where the edges are amorphous silicon and the middle portion has both amorphous silicon and nanocrystalline silicon, to improve cell efficiency.

[0075] In some possible implementations, the solar cell further includes a third semiconductor layer disposed on the second surface. The third semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. This configuration forms a bifacial solar cell. The semiconductor layers on the first and second surfaces can be the same or different. As long as the first semiconductor layer as described in this application is present, the bifacial cell is suitable for the cell structure described in this application, where the edge portion is amorphous silicon and the middle portion has both amorphous silicon and nanocrystalline silicon, to improve cell efficiency.

[0076] by Figure 1 , Figure 2 and Figure 7Taking the structure shown as an example, in some embodiments, when a first semiconductor layer 100 is provided on the first surface, the solar cell also includes a second semiconductor layer 2 provided on the first surface. Both the first semiconductor layer 100 and the second semiconductor layer 2 are elongated strips extending along the first direction and are arranged adjacent to each other along the second direction. The first semiconductor layer 100 includes a stacked portion 15 stacked on the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the first direction and the second direction intersect therein, with the middle portion not including the stacked portion 15.

[0077] When the above technical solution is adopted, the elongated first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. The first semiconductor layer 100 includes a stacked portion 15 stacked on the second semiconductor layer 2, and the middle portion having amorphous silicon and nanocrystalline silicon does not include the stacked portion 15, that is, the stacked portion 15 is amorphous silicon. Therefore, the first semiconductor layer 100 and the second semiconductor layer 2 with different conductivity types have good insulation in the stacked portion 15, reducing leakage current.

[0078] like Figure 4 and Figure 6 As shown, in some possible implementations, the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, with the projection of the middle portion onto the semiconductor substrate 6 completely within the projection of the first transparent conductive layer 71 onto the semiconductor substrate 6. This configuration, by providing the first transparent conductive layer 71, improves the carrier transport capability of the first semiconductor layer 100, enabling it to form good ohmic contact with the electrodes, thus improving conductivity. Furthermore, since the middle portion containing amorphous silicon and nanocrystalline silicon does not extend beyond the boundary of the first transparent conductive layer 71, it reduces contact resistance within the effective conductive area of ​​the first transparent conductive layer 71, thereby improving conductivity and increasing cell efficiency.

[0079] like Figure 5 and Figure 6 As shown, in some possible implementations, along the first direction, there is a first spacing L1 between the boundary of the middle portion and the boundary of the first semiconductor layer 100; along the second direction, there is a second spacing L2 between the boundary of the middle portion and the boundary of the first semiconductor layer 100; wherein the first spacing L1 is greater than the second spacing L2. Since the portion of the first semiconductor layer 100 near the edge of the semiconductor substrate 6 has large defects, poor passivation effect, large leakage current, and severe recombination, the first spacing L1 between the middle portion and the boundary of the first semiconductor layer 100 is set relatively large to avoid edge defects. The second spacing L2 is not close to the edge of the semiconductor substrate 6, so it is sufficient that the middle portion containing amorphous silicon and nanocrystalline silicon does not include the stacked portion. The area of ​​the middle portion is increased as much as possible by reducing the second spacing L2 to reduce contact resistance and improve current collection capability.

[0080] In some possible implementations, the first spacing L1 is 0.2 mm to 12 mm, and / or the second spacing L2 is less than or equal to 100 μm. If the width of the first spacing L1 is too wide, the middle part of the solar cell is smaller, resulting in less reduction in series resistance and greater current collection losses. If the width of the first spacing L1 is too small, defects closer to the edge are larger, passivation effect is poor, recombination is greater, and leakage current is larger. Therefore, considering the reduction of the overall contact resistance of the solar cell and avoiding edge defects, the first spacing L1 is chosen to be 0.2 mm to 12 mm. If the second spacing L2 is too large, it will result in a smaller middle part and greater current collection losses. Therefore, the second spacing L2 is less than or equal to 100 μm.

[0081] like Figure 2 and Figure 3 As shown, in some possible implementations, the solar cell further includes a first grid electrode 4 disposed on the first semiconductor layer 100 and extending along a first direction, the first grid electrode 4 extending from above the middle portion to above the edge portion. The extending direction of the first grid electrode 4 is consistent with the extending direction of the first semiconductor layer 100, and it can collect charge carriers in both the middle and edge portions, thus improving the charge carrier collection capability of the first grid electrode 4 for the first semiconductor layer 100.

[0082] Furthermore, in this embodiment, along the second direction, the ratio of the width of the first gate electrode 4 to the width of the middle portion is 10% to 120%, specifically 10%, 30%, 50%, 80%, 100%, 120%, etc. The ratio of the width of the first gate electrode 4 to the width of the middle portion is selected based on the material and carrier transport capability of the first semiconductor layer 100. If the carrier transport capability of the first semiconductor layer 100 is weak, the ratio of the width of the first gate electrode 4 to the width of the middle portion is increased to increase the contact area between the first gate electrode 4 and the middle portion, reducing the contact resistance. Conversely, the ratio can be decreased to save electrode material while still satisfying current collection requirements.

[0083] For example, the width of the first gate electrode 4 can be 30 μm to 600 μm: specifically, when the first gate electrode 4 is prepared by screen printing, the width of the first gate electrode 4 is 30 μm to 80 μm; when the first gate electrode 4 is prepared by deposition methods such as electroplating, the width of the first gate electrode 4 is 100 μm to 600 μm. The width of the middle portion is 200 μm to 700 μm. A suitable width of the first gate electrode 4 is selected based on the width of the middle portion and the electrode preparation process.

[0084] Furthermore, in the case where the solar cell includes a first transparent conductive layer 71, the first grid electrode 4 extends along a first direction and is disposed on the first transparent conductive layer 71; along a second direction, the width of the first grid electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion. For example, the width of the first transparent conductive layer 71 is 120 μm to 800 μm, the width of the middle portion is 200 μm to 700 μm, and the ratio of the width of the first transparent conductive layer 71 to the width of the middle portion is 1.2 to 1.5. A suitable width of the first transparent conductive layer 71 is selected based on the width of the middle portion, and a suitable width of the first grid electrode 4 is selected based on the width of the middle portion, the width of the first transparent conductive layer 71, and the electrode fabrication process. With this configuration, the first grid electrode 4 can be disposed directly opposite the middle portion, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion, thereby improving the current collection capability.

[0085] Based on the solar cells described in any of the above embodiments, this invention also provides a photovoltaic module, including the solar cells described in any of the above embodiments.

[0086] Since the photovoltaic module uses the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the solar cell described above, and will not be described in detail here.

[0087] This invention also provides a method for manufacturing a solar cell, which can prepare such a solar cell. Figures 1-7 The solar cell described in any of the above embodiments, and the method for manufacturing the solar cell includes the following steps: Step S100: A semiconductor substrate 6 is provided, the semiconductor substrate 6 having a first side and a second side opposite to each other.

[0088] In step S200, a first semiconductor layer 100 is formed on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 includes a plurality of first strip portions 1 extending along a first direction. Each first strip portion 1 includes a first portion 11 and a second portion 12. The first portion 11 is located in the middle region of the extension direction of the first strip portion 1, and the second portion 12 is located in the edge regions at both ends of the extension direction of the first strip portion 1. The edge regions are adjacent to the edges of the first surface.

[0089] In step S300, the first part 11 is irradiated with a laser while the second part 12 is not irradiated, such that the crystallization rate of the first part 11 is greater than that of the second part 12. The first semiconductor layer 100 includes at least one of amorphous silicon and nanocrystalline silicon.

[0090] In the above technical solution, the first portion 11 in the middle region of the first semiconductor layer 100 is crystallized using a laser, thereby increasing the crystallinity. The second portion of the first semiconductor layer 100 located at both edges along the first direction is not irradiated by the laser, retaining its amorphous structure. Due to the non-uniformity of the laser beam and the uneven thickness of the first semiconductor layer 100, when the laser acts on the second portion 12 at the edge of the first semiconductor layer 100, it damages the passivation of the edge region, increasing recombination in the edge region. Therefore, this application does not form a crystallized structure at the edge using a laser, retaining the amorphous structure of the edge region of the first semiconductor layer 100, thus ensuring the passivation effect of the second portion 12 at the edge region and reducing recombination in the edge region. Furthermore, the laser crystallization of the first portion 11 in the middle region of the first semiconductor layer 100 reduces the contact resistance. Therefore, by reasonably controlling the laser irradiation area on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized, improving the overall cell efficiency.

[0091] Furthermore, the first surface has a first side and a second side arranged opposite to each other along a first direction. Therefore, step S300, irradiating the first portion 11 with a laser, specifically includes the following steps: Step S301: Use a laser to start irradiating at a position a first distance from the first side, and irradiate through the first part 11 in the first direction, and stop irradiating at a position a second distance from the second side.

[0092] With the above technical solution, the laser irradiates the first semiconductor layer along the direction from the first side to the second side. The starting point of the irradiation of the first part 11 is a first distance from the first side, and the ending point of the irradiation of the first part 11 is a second distance from the second side. Only the first part 11 of the first semiconductor layer is irradiated, and the laser irradiation stops in the second part 12 located at both edge regions along the first direction. The irradiation can be repeated multiple times along the first direction so that the area of ​​the first part perpendicular to the first direction is irradiated by the laser. In the width direction of the first semiconductor layer, there is a gap between the irradiation area of ​​the laser on the first semiconductor layer and the boundary of the width of the first semiconductor layer, so that the formed middle part does not enter the PN isolation region used to isolate the P-region and the N-region, ensuring the electrical insulation effect of the PN isolation region.

[0093] Furthermore, the first distance and / or the second distance is 0.2mm to 12mm. This is to allow for the unirradiated edge portion of the first semiconductor layer. If the edge portion is too wide, the central area of ​​the solar cell will be small, resulting in less reduction in series resistance and greater current collection losses. If the width of the edge portion of the first semiconductor layer is too small, on the one hand, due to limitations in the coating process, the first semiconductor layer at the edge is thinner; on the other hand, the laser irradiation angle at the edge of the solar cell will be larger, causing deviations in the energy distribution within the laser spot, potentially leading to excessively high laser energy density in some areas and damaging the passivation of the first semiconductor layer at the edge. Therefore, considering the reduction of the overall contact resistance of the solar cell and minimizing damage to the passivation, the first distance and / or the second distance is chosen to be 0.2mm to 12mm.

[0094] In some possible implementations, the first semiconductor layer includes an amorphous silicon layer. After the middle portion is irradiated with a laser, parts of the amorphous silicon layer crystallize to form nanocrystals. Using an amorphous silicon layer as the first semiconductor layer results in better passivation of the un-illuminated portions and improved insulation in the isolation region.

[0095] In some embodiments, the wavelength of the laser is 325nm~532nm, specifically, the wavelength of the laser can be 325nm, 450nm, 532nm, etc.; and / or, the energy density of the laser is 200mJ / cm². 2 ~6000mJ / cm 2 Specifically, the energy density of the laser can be 200 mJ / cm². 2 500mJ / cm 2 1000mJ / cm 2 2000mJ / cm 2 3000mJ / cm 2 5000mJ / cm 2 6000mJ / cm 2 The laser pulse width can be on the order of picoseconds to nanoseconds. By setting this wavelength range, the laser can be absorbed by the first semiconductor layer 100, which is beneficial for achieving crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high-temperature range will expand, and the temperature at the tip of the textured structure will be too high, thus affecting the passivation of the tip region of the textured structure. If the laser energy density is too low, the energy accumulation time will be too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, selecting a laser energy density within this range allows only the tip of the textured structure to reach a high temperature, achieving morphological changes and forming a crystalline structure.

[0096] like Figures 8-19As shown, this embodiment provides a specific fabrication process for a solar cell. Taking the fabrication of a hybrid back-contact cell with a tunneling passivation contact structure and a heterojunction structure on the back side as an example, the fabrication process of this back-contact cell is as follows: Step 1: As Figure 8 As shown, the silicon wafer is polished and cleaned. Specifically, the silicon wafer is put into a tank-type polishing and cleaning machine for polishing to remove the cutting damage layer of the silicon wafer. The polishing morphology of both sides is controlled by controlling the temperature, time and chemical concentration. The resulting silicon wafer is used as a semiconductor substrate 6. The semiconductor substrate 6 can be an n-type, p-type or intrinsic silicon substrate.

[0097] Step 2: As Figure 9 As shown, a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 are sequentially formed on the back surface of the semiconductor substrate 6, wherein the tunneling oxide layer 21 is a SiOx layer. The tunneling oxide layer 21 and the intrinsic polysilicon layer 23 can be formed using one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition. Alternatively, the tunneling oxide layer 21 can be generated by a high-temperature reaction between oxygen and the semiconductor substrate 6, or by a wet chemical method, such as the reaction of silicon with ozone or the oxidation reaction of silicon with nitric acid. The thickness of the tunneling oxide layer 21 is 1 nm to 4 nm, optionally 1.4 nm, and the thickness of the intrinsic polysilicon layer 23 is 30 nm to 250 nm, optionally 120 nm.

[0098] Step 3: As Figure 10 As shown, the intrinsic polycrystalline silicon layer 23 is doped to form an n-type doped polycrystalline silicon layer 22 by high-temperature diffusion, and a phosphorus-containing oxide layer, namely a phosphorus silicon glass layer 24, is generated. The doping concentration of the n-type doped polycrystalline silicon layer 22 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0099] Step 4: As Figure 11 As shown, the phosphorus silicate glass layer 24 formed after phosphorus diffusion is removed by HF solution.

[0100] Step 5: As Figure 12 As shown, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22. The silicon nitride mask layer 25 serves two purposes: firstly, it acts as a hydrogen source to provide hydrogen atoms at the interface between the crystalline silicon and the tunneling oxide layer 21, passivating dangling bonds, and also passivating some defects within the crystalline silicon. Secondly, it acts as a mask to protect the N-region film layer during subsequent P-region patterning.

[0101] Step 6: As Figure 13As shown, the P-region is patterned using laser technology. The laser ablates all P-region film layers down to the semiconductor substrate 6. The laser can be a 532nm laser, and the pulse width can be either nanosecond or picosecond. Optionally, a 532 picosecond laser is used.

[0102] Step 7: As Figure 14 As shown, the exposed semiconductor substrate 6 in the P-region is texturized using a wet etching process to obtain a textured structure, such as a pyramid structure. Then, the silicon nitride mask layer 25 is removed. The wet etching process serves two purposes: first, it removes the damaged layer from the laser-treated semiconductor substrate 6 in the P-region, performing interface cleaning; second, it removes the silicon nitride mask layer 25 deposited in the N-region.

[0103] Step 8: As Figure 15 As shown, an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the back surface of the entire semiconductor substrate 6 to form a p-region emitter. The thickness of the intrinsic amorphous silicon layer 13 is 2 nm to 20 nm, optionally 8 nm; the thickness of the p-type amorphous silicon layer 14 is 5 nm to 50 nm, optionally 15 nm. Simultaneously, a passivation layer 8 and an antireflection layer 9 are sequentially deposited on the front surface of the semiconductor substrate 6. The antireflection layer 9 is one or more of silicon nitride, silicon oxide, and silicon oxynitride layers, and the passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.

[0104] Step 9: As Figure 16 As shown, a laser process is used to pattern the N-region, removing the intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polycrystalline silicon layer 22, exposing the n-type doped polycrystalline silicon layer 22. An oxide layer is formed on the n-type doped polycrystalline silicon layer 22, which is subsequently removed by a wet etching process. The laser can be a 355nm or 532nm laser, with pulse widths selectable in the nanosecond or picosecond range; optionally, a 532 picosecond laser is used. The wet etching process can employ a chain-type equipment, with the semi-finished product facing upwards and protected by a water film. The back side contacts an HF solution to remove the oxide layer and the silicon nitride deposited around it.

[0105] Step 10: As Figure 16As shown, a laser process is used to irradiate the middle region of the p-type amorphous silicon layer 14 in the P-region, forming a first part 11 with a crystalline structure in the middle region of the p-type amorphous silicon layer 14. The portion of the p-type amorphous silicon layer 14 near the edge of the semiconductor substrate 6 is not irradiated by the laser, retaining its original amorphous structure and forming a second part 12. The laser can be a 355nm or 532nm laser, and the pulse width can be either nanosecond or picosecond; optionally, a 532 picosecond laser is used. Specifically, the pulsed laser spot moves along the extension direction of the p-type amorphous silicon layer 14. Ideally, the width of the laser treatment area is consistent with the width of the P-region (p-type amorphous silicon layer 14) to maximize the laser treatment area. Even if the laser treatment area extends beyond the P-region and reaches the isolation region, it will not affect the battery performance. However, considering production capacity, the laser treatment area should be minimized, and it is recommended that the laser treatment area not exceed the P-region. The laser treatment area avoids the edge of the semiconductor substrate 6 by 0.3mm to 3mm. Of the multiple p-type amorphous silicon layers 14, the two outermost p-type amorphous silicon layers 14, each approximately 1 mm wide, are not subjected to laser processing. The edges of the remaining p-type amorphous silicon layers 14, approximately 1 mm wide, are also not subjected to laser processing. It should be noted that the laser processes in steps nine and ten can be performed in the same step, without any specific order. To save laser processing time, the crystallization process is performed after the P-region patterning is completed using laser irradiation.

[0106] Step 11: As Figure 17 As shown, a transparent conductive layer 7 is deposited on the back surface of the semiconductor substrate 6. This layer can be one or more of the following: fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide, either in a stacked or monolayer configuration. Optionally, an indium tin oxide film layer can be used.

[0107] Step 12: As Figure 18 As shown, the transparent conductive layer 7 on the N-region and P-region is broken to form a PN isolation region. This allows the transparent conductive layer 7 to form a first transparent conductive layer 71 on the P-region and a second transparent conductive layer 72 on the N-region, achieving insulation between the P-region and the N-region. The transparent conductive layer 7 is broken at the edge of the semiconductor substrate 6 in both the N-region and P-region, forming a third transparent conductive layer at the edge. The PN isolation region located between the P-region and the N-region spans the overlapping area between the N-region and the P-region, as well as part of the p-region, to achieve better insulation.

[0108] Step 13: As Figure 19 As shown, a first gate electrode 4 and a second gate electrode 5 are deposited and formed on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region, respectively, wherein the two ends of the first gate electrode 4 extend to the following... Figure 1The second part 12 on both sides shown. The materials of the first gate electrode 4 and the second gate electrode 5 can be one or more combinations of silver, copper, and aluminum.

[0109] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0110] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate having opposing first and second surfaces; A first semiconductor layer is disposed on the first surface. The first semiconductor layer includes a plurality of first strip-shaped portions extending along a first direction. Each first strip-shaped portion includes a first part and a second part. The first part is located in the middle region of the extending direction of the first strip-shaped portion, and the second part is located in the edge regions at both ends of the extending direction of the first strip-shaped portion. The edge regions are adjacent to the edges of the first surface. The crystallinity of the first part is greater than that of the second part. The first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

2. The solar cell according to claim 1, characterized in that, The solar cell further includes a third semiconductor layer disposed on the second surface. The third semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. The third semiconductor layer has a different conductivity type than the first semiconductor layer.

3. The solar cell according to claim 1, characterized in that, The third semiconductor layer is a polycrystalline silicon layer. The semiconductor layer is arranged in a strip shape on the second surface, or the entire third semiconductor layer is arranged on the second surface. The third semiconductor layer includes a thicker portion arranged in a strip shape and a thinner portion other than the thicker portion.

4. The solar cell according to claim 1, characterized in that, The solar cell further includes a second semiconductor layer disposed on the first surface. The second semiconductor layer includes a plurality of second strip-shaped portions extending along a first direction. The first strip-shaped portions and the second strip-shaped portions are arranged alternately along a second direction. The first semiconductor layer and the second semiconductor layer have different conductivity types. The first direction and the second direction intersect.

5. The solar cell according to claim 4, characterized in that, Within the first strip-shaped portion, the first portion includes a middle portion extending in a strip shape along a first direction and strip-shaped edge portions disposed on both sides of the middle portion along a second direction, wherein the crystallization rate of the middle portion is greater than that of the edge portions.

6. The solar cell according to claim 5, characterized in that, Within the first strip, the width of the edge portion on one side of the middle portion along the second direction is less than or equal to 100 μm.

7. The solar cell according to claim 4, characterized in that, The second semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer.

8. The solar cell according to claim 4, characterized in that, Along the second direction, the crystallinity of at least one of the first strips near the edge of the first surface is the same as that of the second portion.

9. The solar cell according to claim 1, characterized in that, The contact resistance of the first part is less than that of the second part.

10. The solar cell according to claim 5, characterized in that, The first strip portion has a stacked portion superimposed on the second strip portion, wherein the first portion does not include the stacked portion; and / or, the solar cell further includes a first transparent conductive layer covering a portion of the first portion. The projection of the middle portion onto the first transparent conductive layer is at least within the boundary of the first transparent conductive layer.

11. The solar cell according to claim 10, characterized in that, It also includes a second transparent conductive layer and a third transparent conductive layer, wherein the second transparent conductive layer covers a portion of the stacked portion and a portion of the second strip portion; and the third transparent conductive layer covers a portion of the second portion. A PN isolation region exists between adjacent first and second transparent conductive layers; An edge isolation region is provided between the first transparent conductive layer and the third transparent conductive layer and / or between the second transparent conductive layer and the third transparent conductive layer.

12. The solar cell according to claim 1, characterized in that, In the image obtained from the EL test of the solar cell, the brightness of the first part is greater than that of the second part.

13. The solar cell according to claim 1, characterized in that, It also includes a first gate electrode extending along the first direction, the first gate electrode being conductively disposed on a first portion of the first semiconductor layer and extending from the first portion to the second portion.

14. The solar cell according to claim 1, characterized in that, Along the direction from the first portion to the second portion and perpendicular to the side length of the semiconductor substrate, the width of the second portion is 0.3mm to 12mm.

15. The solar cell according to claim 5, characterized in that, The semiconductor substrate includes a recessed portion on the first surface, the recessed portion being recessed toward the second surface relative to the remainder of the first surface, and the intermediate portion being located within the recessed portion.

16. A photovoltaic module, comprising a solar cell, characterized in that, The solar cell is the solar cell according to any one of claims 1-15.

17. A method for manufacturing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces; A first semiconductor layer is formed on the first surface. The first semiconductor layer includes a plurality of first strip portions extending along a first direction. Each first strip portion includes a first portion and a second portion. The first portion is located in the middle region of the extension direction of the first strip portion, and the second portion is located in the edge regions at both ends of the extension direction of the first strip portion. The edge regions are adjacent to the edges of the first surface. The first portion is irradiated with a laser, while the second portion is not irradiated, such that the crystallinity of the first portion is greater than that of the second portion, wherein the first semiconductor layer comprises at least one of amorphous silicon and nanocrystalline silicon.

18. The method for manufacturing a solar cell according to claim 17, characterized in that, The first surface has a first side and a second side disposed opposite to each other along a first direction; The use of laser irradiation on the first part includes: The laser is used to irradiate from a position at a first distance from the first side, and passes through the first part in a first direction, stopping at a position at a second distance from the second side.

19. The method for manufacturing a solar cell according to claim 18, characterized in that, The first distance and / or the second distance is 0.2mm to 12mm.

20. The method for manufacturing a solar cell according to claim 17, characterized in that, The first semiconductor layer includes an amorphous silicon layer. After the first portion is irradiated with the laser, a portion of the amorphous silicon layer crystallizes to form nanocrystals.

21. The method for manufacturing a solar cell according to claim 17, characterized in that, The wavelength of the laser is 325nm~532nm; And / or, the energy density of the laser is 200 mJ / cm². 2 ~6000mJ / cm 2 .

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