Pin nondestructive testing system and method based on near-field probe and phase-locked amplification

Abstract

The invention discloses a pin nondestructive testing system and method based on a near-field probe and phase-locked amplification, and relates to the technical field of pin detection, the system comprises a square wave generation module, a near-field probe device, a signal preceding stage channel, a frequency measurement phase-locked module based on combination of an FPGA and an ARM, a demodulation module based on combination of the FPGA and the ARM, a communication interface and an upper computer; the square wave generation module comprises a multi-pin microprocessor chip based on STM32 and a pin external connection line of the multi-pin microprocessor chip. According to the invention, rapid and accurate nondestructive testing can be carried out on the pins of the multi-pin microprocessor, the near-field probe device and the frequency measurement phase locking module are combined, local electromagnetic signals in the pin range are captured, signal changes corresponding to pin defects are accurately extracted from a complex electromagnetic environment, and calibration and positioning are carried out.

Description

Technical Field

[0001] This application relates to the field of pin inspection technology, and in particular to a pin non-destructive testing system and method based on a near-field probe and lock-in amplification. Background Technology

[0002] In the field of non-destructive testing (NDT) technology, with the development of electronic components towards high integration and miniaturization, the application of multi-pin, highly integrated chips (such as BGA and QFP packaged chips) is becoming increasingly widespread. The integrity of their pins directly determines the reliability of the chip and even the entire electronic device. Therefore, the demand for non-destructive testing of pin defects is becoming increasingly urgent. Currently, NDT technologies for chip pin defects mainly include optical inspection technology, ultrasonic inspection technology, and electromagnetic induction inspection technology. Among them, optical inspection technology (such as a chip pin visual inspection method disclosed in patent document CN115456945A) identifies pin appearance defects through image acquisition and processing. However, this technology can only detect visible defects on the pin surface (such as pin deformation and missing corners) and cannot identify hidden defects such as cold solder joints and micro-cracks inside the pin. Moreover, it is affected by the chip packaging structure, and the detection effect on some hidden pins (such as BGA pins) is poor. Ultrasonic inspection technology uses the propagation characteristics of ultrasonic waves to detect internal defects. However, its detection resolution is limited by the ultrasonic wavelength, making it difficult to accurately locate pin defects with small diameters in multi-pin microprocessors. Furthermore, the detection process requires close contact with the chip surface, which can easily damage the chip.

[0003] Electromagnetic induction testing technology has significant advantages in chip pin inspection due to its non-contact detection characteristics. Near-field probes, in particular, are increasingly being used for pin defect detection because they can collect localized weak electromagnetic signals. Existing electromagnetic compatibility (EMC) testing devices often use near-field probes to collect electromagnetic signals during chip operation to detect electromagnetic interference, but these devices primarily target EMC issues. Summary of the Invention

[0004] The main objective of this application is to propose a pin non-destructive testing system and method based on a near-field probe and lock-in amplification, so as to improve the accuracy of pin defect detection and achieve non-destructive testing.

[0005] To achieve the above objectives, one aspect of this application proposes a pin non-destructive testing system based on a near-field probe and phase-locked amplification. The system includes: a square wave generation module, a near-field probe device, a signal preamplifier channel, a frequency measurement phase-locked module based on FPGA and ARM, a demodulation module based on FPGA and ARM, a communication interface, and a host computer; wherein the square wave generation module includes a multi-pin microprocessor chip based on STM32 and its pin external connection lines. The square wave generation module is used to control each pin of the multi-pin microprocessor to output a square wave signal of a fixed frequency through online programming and to provide the external connection line of the pin to the subsequent circuit. The near-field probe device is used to scan the square wave signal generated by the external connection line of each pin point by point, and to sense the analog voltage signal. The signal preamp channel is used to convert the analog voltage signal output by the near-field probe device into a digital voltage signal; The frequency measurement phase-locked loop module is used to receive the digital voltage signal output from the signal preamp channel, determine the frequency of the input signal, and generate a discrete sine and cosine reference signal that is in phase and frequency with the input signal. The demodulation module is used to receive the discrete sine and cosine reference signal output by the frequency measurement phase-locked module and the digital voltage signal transmitted by the signal pre-stage channel, and to perform mixing and filtering operations through FPGA to calculate the amplitude and phase of the digital voltage signal transmitted by the signal pre-stage channel. The communication interface is used to realize data transmission between the demodulation module and the host computer; The host computer is used to set the frequency parameters of the square wave signal, the relevant parameters of the demodulation module, and visualize the detection data.

[0006] In some embodiments, the frequency measurement phase-locked loop module includes a prescaler, a counter, a phase detector, and a DDS module; The prescaler is used to divide the signal output from the signal preamp channel and output the divided signal to the counter and the phase detector. The counter is used to count the frequency-divided signal and calculate the frequency of the output signal of the pre-stage channel of the signal according to the pre-division coefficient, and output the calculated frequency to the DDS module and the communication interface respectively. The phase detector is used to measure the phase difference between the frequency-divided signal and the sine and cosine signals output by the DDS module, and feeds it back to the DDS module. The DDS module is used to receive the phase difference output by the phase detector and the frequency output by the counter, and generate the sine and cosine signals that are in phase and frequency with the reference signal, and output the sine and cosine signals to the phase detector and the demodulation module respectively.

[0007] In some embodiments, the demodulation module includes an input signal channel, a sine and cosine reference signal channel, a multiplier, a low-pass filter, and a cordic module; The multiplier is used to perform a product operation on the input signal and the sine and cosine reference signals to obtain two signals that are 90° out of phase and output them to the low-pass filter. The low-pass filter is used to filter out the second harmonic signal of the two product signals and retain the DC signals X and Y; The cordic module is used to perform cordic operations on the filtered DC signals X and Y to obtain the amplitude and phase of the input signal.

[0008] In some embodiments, the signal preamplifier channel includes a preamplifier, a low-pass filter, and an analog-to-digital converter.

[0009] In some embodiments, the communication interface is an Ethernet or USB 3.0 interface with a transmission rate equal to or greater than 100 Mbps.

[0010] To achieve the above objectives, another aspect of this application proposes a pin non-destructive testing method based on a near-field probe and lock-in amplification. This method is applied to the aforementioned pin non-destructive testing system based on a near-field probe and lock-in amplification, and includes the following steps: A square wave signal with a fixed frequency is output using a multi-pin microprocessor; The near-field probe device is used to scan the pin external connections of the multi-pin microprocessor and generate an induced voltage signal; The frequency measurement phase-locked loop module is used to obtain the preprocessed input signal and discrete sine and cosine reference signals based on the induced voltage signal; The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the corresponding demodulation result. The host computer determines whether there is a defect in the external connection line of the pin based on the demodulation result and the expected signal corresponding to the normal pin.

[0011] In some embodiments, the method of using a multi-pin microprocessor to output a square wave signal of a fixed frequency includes the following steps: A square wave signal with a fixed frequency is output using a multi-pin microprocessor. ; in, The square wave signal, The peak current within one cycle. For a square wave period, For duty cycle, It is a unit step function. It is an integer. For time; The Fourier series obtained from the decomposition of the square wave signal is: .

[0012] In some embodiments, the step of scanning the pin interconnects of the multi-pin microprocessor using a near-field probe device and generating an induced voltage signal includes the following steps: The near-field probe device scans the pin external connections of the multi-pin microprocessor and generates an induced voltage signal as follows: ; in, The induced voltage signal. The peak current within one cycle. The radius of the near-field probe device is given. For a square wave period, For duty cycle, The permeability of free space, It is an integer. For time; (0, a) represents the position coordinates of the pin of the external connection line, (0, b) represents the position coordinates of the end of the external connection line, and (p, 0) represents the position coordinates of the near-field probe device.

[0013] In some embodiments, the demodulation module performs demodulation processing based on the preprocessed input signal and discrete sine and cosine reference signals to calculate the corresponding demodulation result, including the following steps: The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the amplitude and phase of the preprocessed input signal as the demodulation result.

[0014] In some embodiments, the amplitude and phase of the preprocessed input signal are calculated through the following steps: The amplitude and phase of the preprocessed input signal are calculated according to the following formula; ; ; in, The amplitude of the preprocessed input signal. The phase of the preprocessed input signal. The phase of the square wave signal is... The phase of the sine and cosine reference signals.

[0015] The embodiments of this application include at least the following beneficial effects: This application provides a pin non-destructive testing system and method based on a near-field probe and phase-locked loop (PLL) amplification. The system includes a square wave generation module, a near-field probe device, a signal preamplifier channel, a frequency measurement PLL module based on FPGA and ARM, a demodulation module based on FPGA and ARM, a communication interface, and a host computer. The square wave generation module includes a multi-pin microprocessor chip based on STM32 and its pin external connections. This application enables rapid and accurate non-destructive testing of the pins of a multi-pin microprocessor. By combining the near-field probe device and the frequency measurement PLL module, it captures local electromagnetic signals within the pin range, accurately extracts signal changes corresponding to pin defects (such as cold solder joints or micro-cracks) from complex electromagnetic environments, and performs calibration and positioning. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a pin non-destructive testing system based on a near-field probe and lock-in amplifier provided in an embodiment of this application; Figure 2 Example signal diagrams of normal and defective pins provided in embodiments of this application; Figure 3 An example diagram of a frequency measurement phase-locked loop module based on a combination of FPGA and ARM provided in an embodiment of this application; Figure 4 An example diagram of a demodulation module based on a combination of FPGA and ARM provided for embodiments of this application; Figure 5 An example structural diagram of a pin non-destructive testing system based on a near-field probe and lock-in amplifier provided in this application embodiment; Figure 6 This is an example flowchart of a pin non-destructive testing method based on a near-field probe and lock-in amplification, provided for an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] Before providing a detailed description of the embodiments of this application, some related technologies involved in the embodiments of this application will be described first, as follows: Existing electromagnetic induction detection solutions are not specifically optimized for pin defect identification and typically lack effective signal amplification and processing techniques, making it difficult to extract the weak electromagnetic signal changes caused by pin defects.

[0021] In the field of weak signal extraction, lock-in amplification (LIA) technology has been applied to various detection scenarios due to its strong noise suppression capabilities. Existing weak signal detection systems extract weak signals submerged in noise using LIA amplifiers. However, these systems are mainly used in fields such as biomedicine, environmental monitoring, and materials analysis, and have not yet been fully integrated with near-field probe technology for non-destructive testing of chip pins. In particular, corresponding signal acquisition and analysis schemes have not been designed for the characteristics of multi-pin microprocessors, such as dense pins and susceptibility to crosstalk.

[0022] The purpose of this application is to overcome the shortcomings and deficiencies of existing non-destructive testing technologies in pin inspection of multi-pin microprocessors (such as BGA and QFP packaged chips), and to provide a non-destructive testing scheme for evaluating the pin integrity and quality reliability of multi-pin microprocessors, achieving non-contact, full defect coverage, and high-precision pin defect detection.

[0023] Reference Figure 1 This application provides a pin non-destructive testing system based on a near-field probe and lock-in amplification. The method may include, but is not limited to, steps S100 to S130, as follows: The system includes: a square wave generation module, a near-field probe device, a signal pre-stage channel, a frequency measurement phase-locked loop module based on FPGA and ARM, a demodulation module based on FPGA and ARM, a communication interface and a host computer; wherein, the square wave generation module includes a multi-pin microprocessor chip based on STM32 and its pin external connection lines. The square wave generation module is used to control each pin of the multi-pin microprocessor to output a square wave signal of a fixed frequency through online programming and to provide the external connection line of the pin to the subsequent circuit. The near-field probe device is used to scan the square wave signal generated by the external connection line of each pin point by point, and to sense the analog voltage signal. The signal preamp channel is used to convert the analog voltage signal output by the near-field probe device into a digital voltage signal; The frequency measurement phase-locked loop module is used to receive the digital voltage signal output from the signal preamp channel, determine the frequency of the input signal, and generate a discrete sine and cosine reference signal that is in phase and frequency with the input signal. The demodulation module is used to receive the discrete sine and cosine reference signal output by the frequency measurement phase-locked module and the digital voltage signal transmitted by the signal pre-stage channel, and to perform mixing and filtering operations through FPGA to calculate the amplitude and phase of the digital voltage signal transmitted by the signal pre-stage channel. The communication interface is used to realize data transmission between the demodulation module and the host computer; The host computer is used to set the frequency parameters of the square wave signal, the relevant parameters of the demodulation module, and visualize the detection data.

[0024] Optionally, the frequency measurement phase-locked loop module includes a prescaler, a counter, a phase detector, and a DDS module; The prescaler is used to divide the signal output from the signal preamp channel and output the divided signal to the counter and the phase detector. The counter is used to count the frequency-divided signal and calculate the frequency of the output signal of the pre-stage channel of the signal according to the pre-division coefficient, and output the calculated frequency to the DDS module and the communication interface respectively. The phase detector is used to measure the phase difference between the frequency-divided signal and the sine and cosine signals output by the DDS module, and feeds it back to the DDS module. The DDS module is used to receive the phase difference output by the phase detector and the frequency output by the counter, and generate the sine and cosine signals that are in phase and frequency with the reference signal, and output the sine and cosine signals to the phase detector and the demodulation module respectively.

[0025] Optionally, the demodulation module includes an input signal channel, a sine and cosine reference signal channel, a multiplier, a low-pass filter, and a cordic module; The multiplier is used to perform a product operation on the input signal and the sine and cosine reference signals to obtain two signals that are 90° out of phase and output them to the low-pass filter. The low-pass filter is used to filter out the second harmonic signal of the two product signals and retain the DC signals X and Y; The cordic module is used to perform cordic operations on the filtered DC signals X and Y to obtain the amplitude and phase of the input signal.

[0026] Optionally, the signal preamplifier channel includes a preamplifier, a low-pass filter, and an analog-to-digital converter.

[0027] Optionally, the communication interface adopts an Ethernet or USB 3.0 interface with a transmission rate equal to or greater than 100Mbps.

[0028] To achieve the above objectives, another aspect of this application proposes a pin non-destructive testing method based on a near-field probe and lock-in amplification. This method is applied to the aforementioned pin non-destructive testing system based on a near-field probe and lock-in amplification, and includes the following steps: A square wave signal with a fixed frequency is output using a multi-pin microprocessor; The near-field probe device is used to scan the pin external connections of the multi-pin microprocessor and generate an induced voltage signal; The frequency measurement phase-locked loop module is used to obtain the preprocessed input signal and discrete sine and cosine reference signals based on the induced voltage signal; The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the corresponding demodulation result. The host computer determines whether there is a defect in the external connection line of the pin based on the demodulation result and the expected signal corresponding to the normal pin.

[0029] Optionally, the step of using a multi-pin microprocessor to output a square wave signal at a fixed frequency includes the following steps: A square wave signal with a fixed frequency is output using a multi-pin microprocessor. ; in, The square wave signal, The peak current within one cycle. For a square wave period, For duty cycle, It is a unit step function. It is an integer. For time; The Fourier series obtained from the decomposition of the square wave signal is: .

[0030] Optionally, the step of using a near-field probe device to scan the pin external connections of the multi-pin microprocessor and generate an induced voltage signal includes the following steps: The near-field probe device scans the pin external connections of the multi-pin microprocessor and generates an induced voltage signal as follows: ; in, The induced voltage signal. The peak current within one cycle. The radius of the near-field probe device is given. For a square wave period, For duty cycle, The permeability of free space, It is an integer. For time; (0, a) represents the position coordinates of the pin of the external connection line, (0, b) represents the position coordinates of the end of the external connection line, and (p, 0) represents the position coordinates of the near-field probe device.

[0031] Optionally, the demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals to calculate the corresponding demodulation result, including the following steps: The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the amplitude and phase of the preprocessed input signal as the demodulation result.

[0032] Optionally, the amplitude and phase of the preprocessed input signal are calculated through the following steps: The amplitude and phase of the preprocessed input signal are calculated according to the following formula; ; ; in, The amplitude of the preprocessed input signal. The phase of the preprocessed input signal. The phase of the square wave signal is... The phase of the sine and cosine reference signals.

[0033] The following sections will provide a detailed description and explanation of some optional embodiments of this application, using specific application examples.

[0034] This embodiment relates to the field of pin non-destructive testing technology, specifically focusing on the application of non-destructive testing that uses a near-field probe as a signal acquisition element and combines it with lock-in amplification technology to extract and analyze weak signals. It is particularly suitable for pin defect (such as pin soldering failure, pin breakage, etc.) identification and quality assessment scenarios of multi-pin, highly integrated chips, directly serving the non-destructive testing needs for pin integrity in the production and testing process of such chips.

[0035] This embodiment provides a pin non-destructive testing system based on a near-field probe and phase-locked amplification. The system includes a square wave generation module, a near-field probe device, a signal preamplifier channel, a frequency measurement phase-locked module based on FPGA and ARM, a demodulation module based on FPGA and ARM, a communication interface, and a host computer. Wherein: The square wave generation module includes a multi-pin microprocessor based on STM32 and its pin external connections. It controls each pin of the microprocessor to output a square wave at a fixed frequency through in-system programming and provides external connections to output to subsequent circuits. The near-field probe device is used to scan the square wave signals generated by each external connection line point by point; The signal preamp channel is used to convert the analog voltage signal output by the near-field probe device into a digital signal; The frequency measurement phase-locked loop module based on FPGA and ARM is used to receive the digital signal output from the signal pre-stage channel, determine the frequency of the input signal, and generate discrete sine and cosine reference signals that are in phase with the input signal. The demodulation module based on FPGA and ARM is used to receive the discrete sine and cosine reference signals output by the frequency measurement phase-locked loop module and the digital voltage signals transmitted by the signal pre-stage channel. The FPGA is used to perform mixing and filtering operations to calculate the amplitude and phase of the digital voltage signals transmitted by the signal pre-stage channel. The communication interface adopts Ethernet or USB 3.0 interface for high-speed data transmission between the demodulation module and the host computer, with a transmission rate of not less than 100Mbps, to ensure the real-time data of multi-pin microprocessor batch detection; The host computer is used to set square wave frequency parameters, demodulation module parameters, and visualize detection data.

[0036] Furthermore: The signal preamplifier channel consists of a preamplifier, a low-pass filter, and an analog-to-digital converter, which is used to convert the analog voltage signal output by the near-field probe device into a digital signal. The frequency measurement phase-locked loop module based on FPGA and ARM integration includes a prescaler, a counter, a phase detector, and a DDS module, among which: The prescaler is used to divide the signal output from the preamp channel and output the divided signal to the counter and phase detector. The counter is used to count the frequency division signal and calculate the frequency of the output signal of the pre-stage channel based on the pre-division coefficient. The calculated signal frequency is output to the DDS module and the communication interface respectively. The phase detector is used to measure the phase difference between the frequency division signal and the sine and cosine signals output by the DDS module, and feeds it back to the DDS module; The DDS module is used to receive the phase difference output by the phase detector and the frequency output by the counter, and generate sine and cosine signals that are in phase and frequency with the reference signal. The sine and cosine signals are output to the phase detector and the subsequent demodulation module, respectively.

[0037] Furthermore: The demodulation module based on FPGA and ARM includes input and cosine reference signal channels, a multiplier, a low-pass filter, and a Cordic module, wherein: The multiplier is used to multiply the input signal with the sine and cosine reference signals to obtain two signals that are 90° out of phase and output them to the low-pass filter. A low-pass filter is used to filter out the second harmonic of the two product signals and retain the DC signals X and Y; The cordic module is used to perform cordic operations on filtered signals X and Y to obtain the amplitude and phase of the input signal.

[0038] A specific embodiment is as follows: Still refer to Figure 1 The system in this embodiment includes a square wave generation module 101, a near-field probe device 102, a signal pre-stage channel 103, a frequency measurement phase-locked loop module 107 based on FPGA and ARM, a demodulation module 108 based on FPGA and ARM, a communication interface 109, and a host computer 110.

[0039] The square wave generation module 101 consists of a multi-pin microprocessor based on STM32 and external circuits. The host computer 110 controls the square wave generation module 101 to output a square wave of a fixed frequency through the communication interface 109 and outputs it to the subsequent circuits through the external pins.

[0040] like Figure 2 As shown, 201 represents a signal that all pins of the microprocessor are free of defects; 202 represents a signal that the microprocessor has a defective pin, causing a certain channel in the middle to be unable to transmit a square wave. Figure 2 This is a schematic diagram of the data flow output from the square wave generation module 101 to the near-field probe device 102. Within the scanning range of the near-field probe, the corresponding pin is controlled by the program to output a square wave signal of a fixed frequency. For defective pins, it can be assumed that the signal output is abnormal, resulting in the inability to output a square wave. Figure 2 In the diagram, 201 represents the square wave signal output from a normal pin, 202 represents the output signal from multiple pins when a defective pin exists, and 203 represents the output signal from a defective pin.

[0041] Assuming the period of the square wave transmitted by the multi-pin microprocessor is T, and the duty cycle is D, the current value of the square wave jumps from 0 to [value missing] within one cycle. If we jump back to 0, the square wave can be represented as: Decomposing it into a Fourier series yields: .

[0042] The near-field probe device 102 generates an induced voltage based on the phenomenon of electromagnetic induction. Assuming A(0, a) is a pin of the multi-pin microprocessor, B(0, b) is the end of the external connection line, P(p, 0) is the location of the near-field probe device 102, and r is the radius of the near-field probe device 102, the induced voltage can be expressed as: .

[0043] The signal preamp channel 103 consists of a preamplifier 104, a low-pass filter 105, and an analog-to-digital converter 106, and is used to convert the analog voltage signal output by the near-field probe device 102 into a digital signal.

[0044] Figure 3 This is a frequency measurement phase-locked loop (PLL) module based on FPGA and ARM. This module forms a negative feedback loop to generate discrete sine and cosine signals that are in phase and frequency with the reference signal. The FPGA and ARM-based PLL module 107 includes a frequency measurement module 301 and a PLL module 304. The frequency measurement module 301 pre-divides the reference signal using a prescaler 302 to reduce frequency measurement errors. After counting the pre-dividered signal using a counter 303, it obtains the corresponding square wave frequency and outputs it to the DDS module 306 and the communication interface 109. The DDS module 306 generates two sine and cosine digital signals of the corresponding frequency based on the square wave frequency. One signal is returned to the phase detector 305 to perform a phase-locked loop with the pre-dividered reference signal, synchronizing the phase of the sine and cosine digital signals generated by the DDS with the reference signal. The other signal is output to the FPGA and ARM-based demodulation module 108 for demodulating the input signal. The phase of this sine and cosine digital signal can be controlled by a host computer 110 via the communication interface 109.

[0045] Figure 4This is a demodulation module based on FPGA and ARM. 401 is the signal channel, including an input signal channel and a reference signal channel. The demodulation module 108 also includes a multiplier 402, a low-pass filter 403, and a Cordic module 404. The input signal channel and the reference signal channel 401 are multiplied digitally by the multiplier 402 and then input to the low-pass filter 403. The time constant of the low-pass filter 403 should be appropriately selected according to the frequency of the reference signal, so that the data after low-pass filtering removes high-frequency signals and retains only the DC signal. The in-phase component X and quadrature component Y output from the low-pass filter are squared, square-rooted, and arctangented in the Cordic module 404 to obtain the signal amplitude R and phase difference. The is: , ,in The phase of the square wave signal. The phase of the reference signal can be controlled by the host computer 110.

[0046] For chip pins with defects (such as cold solder joints or micro-cracks), their current conduction characteristics will change, resulting in significant differences in the amplitude, phase, and other parameters of the current signal passing through the defective pin compared to the normal pin. The voltage signal collected by the near-field probe device 102 directly reflects the current change of the corresponding pin. After the demodulation module 108 demodulates and extracts the input voltage signal based on the preset reference signal, if the demodulation result does not match the expected signal characteristics corresponding to the normal pin, it can be determined that the pin at the current scanning position has a defect, thereby accurately locking the specific location of the defective pin.

[0047] The host computer 110 is built with QT and can communicate with the FPGA through the communication interface 109 to adjust the parameters of this embodiment in real time.

[0048] Another specific embodiment is as follows: Figure 5 The diagram shows the structural composition of the system in this embodiment. 501 is a square wave generation module, 502 is a near-field probe device, 503 is a signal pre-stage channel, 504 is a demodulation module based on FPGA and ARM, 505 is a DDS module based on FPGA and ARM, 506 is a communication interface, and 507 is a host computer.

[0049] In this embodiment, the DDS module 505 directly controls the square wave generation module 501 to generate a square wave signal with a set frequency. The DDS module 505 simultaneously outputs a reference signal corresponding to this frequency to the demodulation module for demodulating the input signal. The output of the demodulation module is transmitted to the host computer 507 via the communication interface 506; the host computer 507 can control the DDS module 505 through the communication interface 506 to adjust the frequency of its output signal.

[0050] Figure 6 The pin non-destructive testing method based on a near-field probe and lock-in amplification provided in this embodiment includes the following steps: The S100 multi-pin microprocessor outputs a fixed frequency signal, and the near-field probe device scans the external lines and generates an induced voltage. It should be further noted that, in some embodiments, the DDS module can be used in internal reference mode to directly control the output of a fixed frequency signal from a multi-pin microprocessor. S200 acquires the preprocessed input signal and discrete sine and cosine reference signals based on the induced voltage signal; It should be further noted that step S200 may include: S210, amplifying the induced voltage signal; S220, filtering the amplified signal to limit its frequency within the Nyquist frequency range; S230, performing analog-to-digital processing on the filtered signal to obtain a discrete input sampling signal. S300 performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the corresponding demodulation result. It should be further noted that, in some embodiments, a known frequency sine and cosine reference signal can be directly obtained through an internal reference mode and demodulated with the preprocessed input signal. The S400 determines the location of the defective pin based on the demodulation results.

[0051] Compared with traditional non-destructive testing techniques, this embodiment innovatively combines near-field detection technology and lock-in amplification technology. Based on the principle of electromagnetic induction, it realizes non-contact non-destructive testing. Compared with optical testing (which only measures surface defects) and ultrasonic testing (which is prone to damage upon contact), it can penetrate the packaging shield to detect hidden defects such as poor soldering and micro-cracks inside the pins, while fundamentally avoiding mechanical damage, making it suitable for the testing of highly integrated chips.

[0052] This embodiment relies on the weak signal detection function of lock-in amplification technology to extract the microvolt-level weak voltage signal output by the near-field probe from the background noise. It not only achieves accurate demodulation of weak defect signals, but also significantly improves the detection signal-to-noise ratio by 1-2 orders of magnitude. Even if the pin defect only causes a small current fluctuation, it can be clearly identified.

[0053] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0054] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer technical solutions than shown, or a combination of certain technical solutions, or different technical solutions.

[0055] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0056] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A pin non-destructive testing system based on a near-field probe and lock-in amplification, characterized in that, The system includes: a square wave generation module, a near-field probe device, a signal pre-stage channel, a frequency measurement phase-locked loop module based on FPGA and ARM, a demodulation module based on FPGA and ARM, a communication interface and a host computer; wherein, the square wave generation module includes a multi-pin microprocessor chip based on STM32 and its pin external connection lines. The square wave generation module is used to control each pin of the multi-pin microprocessor to output a square wave signal of a fixed frequency through online programming and to provide the external connection line of the pin to the subsequent circuit. The near-field probe device is used to scan the square wave signal generated by the external connection line of each pin point by point, and to sense the analog voltage signal. The signal preamp channel is used to convert the analog voltage signal output by the near-field probe device into a digital voltage signal; The frequency measurement phase-locked loop module is used to receive the digital voltage signal output from the signal preamp channel, determine the frequency of the input signal, and generate a discrete sine and cosine reference signal that is in phase and frequency with the input signal. The demodulation module is used to receive the discrete sine and cosine reference signal output by the frequency measurement phase-locked module and the digital voltage signal transmitted by the signal pre-stage channel, and to perform mixing and filtering operations through FPGA to calculate the amplitude and phase of the digital voltage signal transmitted by the signal pre-stage channel. The communication interface is used to realize data transmission between the demodulation module and the host computer; The host computer is used to set the frequency parameters of the square wave signal, the relevant parameters of the demodulation module, and visualize the detection data.

2. The pin non-destructive testing system based on a near-field probe and lock-in amplification according to claim 1, characterized in that, The frequency measurement phase-locked loop module includes a prescaler, a counter, a phase detector, and a DDS module; The prescaler is used to divide the signal output from the signal preamp channel and output the divided signal to the counter and the phase detector. The counter is used to count the frequency-divided signal and calculate the frequency of the output signal of the pre-stage channel of the signal according to the pre-division coefficient, and output the calculated frequency to the DDS module and the communication interface respectively. The phase detector is used to measure the phase difference between the frequency-divided signal and the sine and cosine signals output by the DDS module, and feeds it back to the DDS module. The DDS module is used to receive the phase difference output by the phase detector and the frequency output by the counter, and generate the sine and cosine signals that are in phase and frequency with the reference signal, and output the sine and cosine signals to the phase detector and the demodulation module respectively.

3. The pin non-destructive testing system based on a near-field probe and lock-in amplification according to claim 1, characterized in that, The demodulation module includes an input signal channel, a sine and cosine reference signal channel, a multiplier, a low-pass filter, and a Cordic module; The multiplier is used to perform a product operation on the input signal and the sine and cosine reference signals to obtain two signals that are 90° out of phase and output them to the low-pass filter. The low-pass filter is used to filter out the second harmonic signal of the two product signals and retain the DC signals X and Y; The cordic module is used to perform cordic operations on the filtered DC signals X and Y to obtain the amplitude and phase of the input signal.

4. The pin non-destructive testing system based on a near-field probe and lock-in amplification according to claim 1, characterized in that, The signal preamplifier channel includes a preamplifier, a low-pass filter, and an analog-to-digital converter.

5. A pin non-destructive testing system based on a near-field probe and lock-in amplification according to any one of claims 1 to 4, characterized in that, The communication interface uses an Ethernet or USB 3.0 interface with a transmission rate equal to or greater than 100Mbps.

6. A non-destructive testing method for pins based on a near-field probe and lock-in amplification, characterized in that, The method is applied to a pin non-destructive testing system based on a near-field probe and lock-in amplification as described in claim 1, and the method includes the following steps: A square wave signal with a fixed frequency is output using a multi-pin microprocessor; The near-field probe device is used to scan the pin external connections of the multi-pin microprocessor and generate an induced voltage signal; The frequency measurement phase-locked loop module is used to obtain the preprocessed input signal and discrete sine and cosine reference signals based on the induced voltage signal; The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the corresponding demodulation result. The host computer determines whether there is a defect in the external connection line of the pin based on the demodulation result and the expected signal corresponding to the normal pin.

7. The pin non-destructive testing method based on a near-field probe and lock-in amplification according to claim 6, characterized in that, The method of using a multi-pin microprocessor to output a square wave signal at a fixed frequency includes the following steps: A square wave signal with a fixed frequency is output using a multi-pin microprocessor. ； in, The square wave signal, The peak current within one cycle. For a square wave period, For duty cycle, It is a unit step function. It is an integer. For time; The Fourier series obtained from the decomposition of the square wave signal is: 。 8. The pin non-destructive testing method based on a near-field probe and lock-in amplification according to claim 6, characterized in that, The method of using a near-field probe device to scan the pin external connections of the multi-pin microprocessor and generate an induced voltage signal includes the following steps: The near-field probe device scans the pin external connections of the multi-pin microprocessor and generates an induced voltage signal as follows: ； in, The induced voltage signal. The peak current within one cycle. The radius of the near-field probe device is given. For a square wave period, For duty cycle, The permeability of free space, It is an integer. For time; (0, a) represents the position coordinates of the pin of the external connection line, (0, b) represents the position coordinates of the end of the external connection line, and (p, 0) represents the position coordinates of the near-field probe device.

9. A pin non-destructive testing method based on a near-field probe and lock-in amplification according to claim 6, characterized in that, The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals to calculate the corresponding demodulation result, including the following steps: The demodulation module performs demodulation processing on the preprocessed input signal and discrete sine and cosine reference signals, and calculates the amplitude and phase of the preprocessed input signal as the demodulation result.

10. A pin non-destructive testing method based on a near-field probe and lock-in amplification according to claim 9, characterized in that, The amplitude and phase of the preprocessed input signal are calculated through the following steps: The amplitude and phase of the preprocessed input signal are calculated according to the following formula; ； ； in, The amplitude of the preprocessed input signal. The phase of the preprocessed input signal. The phase of the square wave signal is... The phase of the sine and cosine reference signals.

Images