Photoelectric co-packaging structure and preparation method thereof

Abstract

The invention provides a photoelectric co-packaging structure and a preparation method thereof, relates to the technical field of photoelectric integration, and is designed for solving the problem that a photoelectric packaging structure formed after bonding of an optical engine and an electric chip has relatively large interface stress due to different thermal expansion coefficients of the optical engine and the electric chip. The photoelectric co-packaging structure comprises an optical chip and an electric chip which are connected in a bonding mode, the face, facing the optical chip, of the electric chip is provided with a center area and an edge area, the center area and the edge area are each provided with a plurality of supporting columns distributed in a scattered mode, and the interval between the supporting columns in the center area is smaller than the interval between the supporting columns in the edge area. According to the invention, the interface stress between the optical chip and the electric chip can be reduced.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic integration technology, and more specifically, to an optoelectronic co-packaging structure and its fabrication method. Background Technology

[0002] Optoelectronic co-packaging is an advanced optical communication technology. Its core idea is to highly integrate the optical engine and the electrical chip within the same package, replacing the discrete architecture of traditional pluggable optical modules. However, optical engines utilize a variety of materials, including indium phosphide, gallium arsenide, and lithium niobate. Indium phosphide has a coefficient of thermal expansion (CTE) of approximately 4.7 ppm / ℃, and lithium niobate has a CTE of approximately 0.5–1.5 ppm / ℃, both significantly different from the CTE of silicon (2.6 ppm / ℃), which is used as the electrical chip. This difference in CTE leads to interface stress issues, both during high-temperature annealing and the high-temperature operation of the chip. For example, when indium phosphide is bonded to silicon to form an optoelectronic co-packaging structure, the higher CTE of indium phosphide results in compressive stress on the silicon surface after heating. Conversely, when lithium niobate is bonded to silicon to form an optoelectronic co-packaging structure, the lower CTE of lithium niobate results in tensile stress on the silicon surface after heating. The presence of the aforementioned interfacial stress will lead to microcracks between the interfaces, which will not only cause structural instability, but also cause performance drift of optical devices and reduce transmission accuracy. Summary of the Invention

[0003] The first objective of this invention is to provide an optoelectronic co-packaging structure to solve the technical problem that the optoelectronic packaging structure formed after the bonding of the optical engine and the electrical chip has large interfacial stress due to the different thermal expansion coefficients of the two.

[0004] The optoelectronic co-packaging structure provided by the present invention includes an optical chip and an electrical chip bonded together. The side of the electrical chip facing the optical chip has a central region and an edge region. Both the central region and the edge region are provided with a plurality of dispersed support pillars. The spacing between the support pillars in the central region is smaller than the spacing between the support pillars in the edge region.

[0005] Furthermore, the diameter of the support column in the central region is larger than the diameter of the support column in the edge region.

[0006] Furthermore, the density of the support columns in the central region is 50-80%, and the density of the support columns in the edge region is 20-40%.

[0007] Furthermore, the diameter of the support column is between 2 and 30 μm, and the height of the support column is between 2 and 40 μm.

[0008] Furthermore, the optoelectronic co-packaging structure also includes an intermediate bonding layer, which is located between the optical chip and the electrical chip, and the intermediate bonding layer is filled between any two adjacent support pillars.

[0009] Furthermore, the coefficient of thermal expansion of the intermediate bonding layer is between 2 and 20 ppm / ℃.

[0010] Furthermore, each of the support columns has the same support height, and the depth of the interval between the support columns in the central region is less than the depth of the interval between the support columns in the edge region.

[0011] The beneficial effects of the optoelectronic co-packaging structure of this invention are: By arranging multiple dispersed support pillars on the side of the electronic chip facing the optical chip, with a higher density of support pillars in the central region and a lower density in the edge region, the following advantages are achieved: First, the electronic chip has sufficient rigidity in the central region, improving its support stability for the optical chip and ensuring the structural stability after bonding. Second, the low-density support pillars in the edge region provide deformation space, buffering thermal deformation stress. When the thermal expansion coefficient of the optical chip is greater than that of the electronic chip, the electronic chip experiences compressive stress. The larger spacing between the support pillars in the edge region buffers this compressive stress. During this process, the support pillars in the central region will generate outward expanding support force with the larger deformation of the optical chip. Conversely, when the thermal expansion coefficient of the optical chip is less than that of the electronic chip, the electronic chip experiences tensile stress. Similarly, the larger spacing between the support pillars in the edge region buffers this tensile stress. During this process, the support pillars in the central region will generate inward contracting support force with the larger deformation of the electronic chip. After the temperature returns to normal, the stress accumulated in the support pillars in the central and edge regions will be released.

[0012] Therefore, this optoelectronic co-packaging structure, by setting support pillars of varying densities on the side of the electronic chip facing the optical chip, utilizes the density gradient of the support pillars from the center to the edge to construct a heterogeneous bonding region for connection with the optical chip. This ensures the stability of the support for the optical chip while buffering the different deformation stresses caused by the different coefficients of thermal expansion between the optical and electronic chips, thereby reducing interfacial stress between them. Furthermore, this density gradient between the center and edge regions allows for a more gradual stress release, minimizing the impact of thermal stress.

[0013] The second objective of this invention is to provide a method for preparing an optoelectronic co-packaging structure, in order to solve the technical problem that the optoelectronic packaging structure formed after the bonding of the optical engine and the electrical chip has large interfacial stress due to the different thermal expansion coefficients of the two.

[0014] The method for preparing the optoelectronic co-packaging structure provided by the present invention is used to manufacture the above-mentioned optoelectronic co-packaging structure, comprising: A substrate is provided, and the substrate is patterned to form the electrical chip; Activating the bonding surface between the electrical chip and the optical chip; wherein the step of activating the bonding surface between the electrical chip and the optical chip includes: a first etching step, subjecting the bonding surface between the electrical chip and the optical chip to plasma bombardment; and a second etching step, subjecting the bonding surface between the electrical chip and the optical chip to free radical etching modification to form OH- groups on the bonding surface between the electrical chip and the optical chip. The optical chip and the electrical chip are bonded together.

[0015] Furthermore, in the first etching step, the process gas includes nitrogen, the upper electrode power is 200-400 W, the lower electrode power is 20-50 W, the process pressure is 6-15 mTorr, the nitrogen flow rate is 20-50 sccm, and the process time is 5-15 s.

[0016] Furthermore, in the second etching step, the process gas includes oxygen and water vapor, the upper electrode power is 150-300 W, the lower electrode power is 1-10 W, the process pressure is 5-10 mTorr, the water vapor flow rate is 30-60 sccm, and the oxygen flow rate is 15-30 sccm.

[0017] Furthermore, prior to the step of bonding the optical chip and the electrical chip, the method further includes: An organic adhesive layer is coated on the bonding surface of the electrical chip.

[0018] Furthermore, in the step of bonding the optical chip and the electrical chip, the process temperature is 175–185°C, the process pressure is 1.5–3 MPa, and the bonding time is 10–20 min.

[0019] The beneficial effects of the method for preparing the optoelectronic co-packaging structure of the present invention are: Before bonding the optical chip and the electronic chip, this preparation method first uses a first etching step to bombard the bonding surfaces of the electronic chip and the optical chip with plasma, which can break the chemical bonds on the bonding surfaces. Then, a second etching step is used to modify the bonding surfaces of the electronic chip and the optical chip with free radical etching, which can form OH- groups on the bonding surfaces. The large number of OH- groups suspended on the bonding surfaces can improve the bonding quality of the electronic chip and the optical chip, thereby ensuring the bonding effect. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 is a cross-sectional view of the optoelectronic co-packaging structure manufactured by the method for preparing the optoelectronic co-packaging structure according to an embodiment of the present invention at each process step; Figure 2 A schematic diagram of the forces acting on the optoelectronic co-packaging structure provided in this embodiment of the invention when the thermal expansion coefficient of the optical chip is greater than that of the electrical chip. Figure 3 A schematic diagram of the forces acting on the optoelectronic co-packaging structure provided in this embodiment of the invention when the thermal expansion coefficient of the optical chip is less than that of the electrical chip. Figure 4 is a schematic diagram of the distribution of support pillars in the edge region of the electronic chip of the optoelectronic co-packaging structure provided in the embodiment of the present invention; Figure 5 is a schematic diagram of the distribution of support pillars in the central region of the electronic chip in the optoelectronic co-packaging structure provided in the embodiment of the present invention; Figure 6 This is a flowchart illustrating the fabrication method of the optoelectronic co-packaging structure provided in an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures: 100 - Optical chip; 200 - Electrical chip; 300 - Intermediate bonding layer; 210 - Central area; 220 - Edge area; 230 - Supporting column; 201 - Substrate; 202 - Photoresist. Detailed Implementation

[0023] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0024] As shown in Figure 1(h), this embodiment provides an optoelectronic co-packaging structure, including an optical chip 100 and an electrical chip 200 bonded together. As shown in Figures 1(d) and (e), the side of the electrical chip 200 facing the optical chip 100 has a central region 210 and an edge region 220. Both the central region 210 and the edge region 220 are provided with a plurality of dispersed support pillars 230. The spacing between the support pillars 230 in the central region 210 is smaller than the spacing between the support pillars 230 in the edge region 220, that is, C1 < C2 in Figure 1(d).

[0025] By arranging multiple dispersed support pillars 230 on the side of the electrical chip 200 facing the optical chip 100, and making the support pillar density high in the central region 210 and low in the edge region 220, on the one hand, the electrical chip 200 can have sufficient rigidity in the central region 210, improving the support stability for the optical chip 100 and ensuring the structural stability after the optical chip 100 and the electrical chip 200 are bonded; on the other hand, the low-density arrangement of the support pillars 230 in the edge region 220 can provide deformation space and buffer thermal deformation stress. Specifically, when the thermal expansion coefficient of the optical chip 100 is greater than that of the electrical chip 200, such as... Figure 2 As shown, the electrical chip 200 is subjected to compressive stress (see...). Figure 2 In F1 of the image, the larger spacing between the support pillars 230 in the edge region 220 can buffer the aforementioned compressive stress. During this process, the support pillars 230 in the central region 210 will generate an outward expanding support force as the optical chip 100 undergoes a larger deformation (see F1 in the image). Figure 2 (N1 in the text); When the coefficient of thermal expansion of the optical chip 100 is less than that of the electrical chip 200, the electrical chip 200 is subjected to tensile stress (see N1 in the text). Figure 3 Similarly, the larger spacing between the support columns 230 in the edge region 220 can be used to buffer the tensile stress mentioned above. During this process, the support columns 230 in the central region 210 will generate an inward contraction support force due to the large deformation of the electrical chip 200 (see F2 in the image). Figure 3 (N2 in the middle). After the temperature returns to normal, the stress accumulated in the support column 230 in the central region 210 and the edge region 220 will be released.

[0026] Therefore, this optoelectronic co-packaging structure, by setting support pillars 230 of different densities on the side of the electrical chip 200 facing the optical chip 100, utilizes the density gradient of the support pillars 230 from the central region 210 to the edge region 220 to construct a heterogeneous bonding region for connection with the optical chip 100. This ensures the stability of the support for the optical chip 100 while also buffering the different deformation stresses caused by the different coefficients of thermal expansion between the optical chip 100 and the electrical chip 200, thereby reducing the interface stress between them. Furthermore, this density gradient setting between the central region 210 and the edge region 220 allows for a more gradual stress release, minimizing the impact of thermal stress.

[0027] It should be noted that in this embodiment, "central region 210" and "edge region 220" are only relative terms and do not mean that this application includes only one central region 210 and one edge region 220. In fact, the electronic chip 200 may have multiple regions from its center to its edge. Among them, the region closer to the center in each pair of adjacent regions can be called the central region 210, and the region closer to the edge can be called the edge region 220.

[0028] It should also be noted that, in this embodiment, from the top view of the electrical chip 200, the central region 210 and the edge region 220 can be arranged radially. Of course, it is also possible to simply place the edge region 220 on both sides of the central region 210.

[0029] In this embodiment, the electrical chip 200 can be made of silicon, and the optical chip 100 can be made of indium phosphide or lithium niobate. When the optical chip 100 is made of indium phosphide, its coefficient of thermal expansion is greater than that of silicon. Therefore, under thermal stress, the stress distribution of the optoelectronic co-packaging structure is as follows: Figure 2 As shown; when the optical chip 100 is made of lithium niobate, its coefficient of thermal expansion is less than that of silicon. Therefore, under thermal stress, the stress state of the optoelectronic co-packaging structure is as follows. Figure 3 As shown.

[0030] In this embodiment, as shown in Figures 5(a) and (b), the density of the support columns 230 in the central region 210 is 50-80%, and as shown in Figures 4(a) and (b), the density of the support columns 230 in the edge region 220 is 20-40%. That is, the area occupied by all the support columns 230 in the central region 210 accounts for 50-80% of the total area of ​​the central region 210; and the area occupied by all the support columns 230 in the edge region 220 accounts for 20-40% of the total area of ​​the edge region 220.

[0031] By limiting the density of the support columns 230 in the central region 210 to the above range, on the one hand, it can be avoided that the support columns 230 in the central region 210 are arranged too closely, resulting in insufficient deformation space around the support columns 230 in the central region 210, which would be unable to adapt to the deformation of the central structure caused by thermal stress. On the other hand, it can also be avoided that the support columns 230 in the central region 210 are arranged too loosely, resulting in insufficient support for the center of the optical chip 100, which would cause structural instability.

[0032] By limiting the density of the support pillars 230 in the edge region 220 to the above range, on the one hand, it can be avoided that the support pillars 230 in the edge region 220 are arranged too closely, resulting in insufficient deformation space around the support pillars 230 in the edge region 220, which would be unable to adapt to the edge structure deformation caused by thermal stress. On the other hand, it can also be avoided that the support pillars 230 in the edge region 220 are arranged too sparsely, resulting in insufficient support force on the edge of the optical chip 100, which would cause structural instability.

[0033] Please continue referring to Figure 1(d). The diameter of the support column 230 in the central region 210 is larger than the diameter of the support column 230 in the edge region 220. That is, D1 > D2 in Figure 1(d).

[0034] By making the support pillars 230 in the central region 210 thicker and the support pillars 230 in the edge region 220 thinner, on the one hand, the contact area between each support pillar 230 in the central region 210 and the optical chip 100 can be increased by increasing the diameter of the support pillars 230 in the central region 210, thereby improving the support stability of the optical chip 100. On the other hand, the contact area between each support pillar 230 in the edge region 220 and the optical chip 100 can be reduced by reducing the diameter of the support pillars 230 in the edge region 220, thereby providing a reliable buffering effect when subjected to thermal stress.

[0035] In this embodiment, the diameter of the support column 230 is between 2 and 30 μm. This arrangement not only ensures the support strength for the optical chip 100, but also provides deformation buffering when subjected to thermal stress.

[0036] Please refer to Figure 1(d) for further details. In this embodiment, the height H of the support column 230 is between 2 and 40 μm.

[0037] This design avoids two problems. First, it prevents the support column 230 from being too high, which would result in poor stability and structural instability in the resulting optoelectronic co-packaging structure. Second, it avoids the support column 230 from being too low, which would limit its deformation capacity and prevent it from effectively buffering deformation under thermal stress.

[0038] Please continue to refer to Figure 1(e). In this embodiment, each support column 230 has the same support height. The depth of the interval between the support columns 230 in the central region 210 is less than the depth of the interval between the support columns 230 in the edge region 220.

[0039] This configuration allows the spacing between two adjacent support pillars 230 on the side of the electrical chip 200 where the support pillars 230 are located to form a depth difference from the central region 210 to the edge region 220. By making the spacing depth between the support pillars 230 in the edge region 220 larger, the support pillars 230 in the edge region 220 can be more easily deformed under thermal stress. In addition, the support pillars 230 in the edge region 220 are thinner and have larger spacing, which can make the overall thermal stress of the optoelectronic co-packaging structure more uniform.

[0040] Please continue to refer to Figure 1(h). The optoelectronic co-packaging structure may also include an intermediate bonding layer 300. Specifically, the intermediate bonding layer 300 is located between the optical chip 100 and the electrical chip 200, and the intermediate bonding layer 300 is filled between any two adjacent support pillars 230.

[0041] The aforementioned intermediate bonding layer 300 can, on the one hand, increase the bonding quality between the optical chip 100 and the electrical chip 200. On the other hand, the intermediate bonding layer 300, located between two adjacent support pillars 230, can also fill the space between the support pillars 230. While ensuring the support strength of the electrical chip 200, the toughness of the intermediate bonding layer 300 can also buffer thermal stress.

[0042] It should be noted that, Figure 2 and Figure 3 To facilitate a clear description of the stress conditions under thermal stress, the intermediate joint layer 300 between two adjacent support columns 230 was concealed.

[0043] In this embodiment, the coefficient of thermal expansion of the intermediate bonding layer 300 is between 2 and 20 ppm / ℃.

[0044] By setting the coefficient of thermal expansion of the intermediate bonding layer 300 within the above parameter range, effective buffering of thermal expansion stress in different directions can be achieved.

[0045] Specifically, the organic adhesive layer can be an organosilicon-polyimide composite intermediate layer.

[0046] Furthermore, this embodiment also provides a method for preparing an optoelectronic co-packaging structure, used to manufacture the aforementioned optoelectronic co-packaging structure, such as... Figure 6 As shown, it includes: Step S100: As shown in (a)-(d) of Figure 1, a substrate 201 is provided and patterned to form an electrical chip 200.

[0047] Please refer to Figure 1(a) for further details. In this process, the substrate 201 of the electrical chip 200 used for optoelectronic co-packaging is prepared and the surface is cleaned to realize the preparation process for heterogeneous bonding.

[0048] Please refer to Figure 1(b) to see how, after completing the preparation and cleaning of substrate 201, photoresist 202 is applied to the upper surface of substrate 201.

[0049] Please continue to refer to Figure 1(c). This step is the patterning process of the substrate 201. Specifically, the photoresist 202 is patterned by arranging the required support pillars 230.

[0050] Please refer to Figure 1(d) for further details. In this step, the photoresist 202 is used as a mask to etch the substrate 201 to form support pillars 230 with a higher density, thicker diameter, and smaller spacing in the central region 210, and support pillars 230 with a lower density, thinner diameter, and larger spacing in the edge region 220.

[0051] Step S200: As shown in Figure 1(e), activate the bonding surface of the electrical chip 200 and the optical chip 100; wherein, the step of activating the bonding surface of the electrical chip 200 and the optical chip 100 includes: a first etching step, subjecting the bonding surface of the electrical chip 200 and the optical chip 100 to plasma bombardment; a second etching step, subjecting the bonding surface of the electrical chip 200 and the optical chip 100 to free radical etching modification to form OH- groups on the bonding surface of the electrical chip 200 and the optical chip 100.

[0052] Before bonding the optical chip 100 and the electrical chip 200, the preparation method first uses a first etching step to bombard the bonding surfaces of the electrical chip 200 and the optical chip 100 with plasma, which can break the chemical bonds on the bonding surfaces. Then, a second etching step is used to modify the bonding surfaces of the electrical chip 200 and the optical chip 100 with free radical etching, which can form OH- groups on the bonding surfaces. The large number of OH- groups suspended on the bonding surfaces can improve the bonding quality between the electrical chip 200 and the optical chip 100, thereby ensuring the bonding effect.

[0053] Specifically, in the first etching step mentioned above, the process gas includes nitrogen, the upper electrode power is 200-400 W, the lower electrode power is 20-50 W, the process pressure is 6-15 mTorr, the nitrogen flow rate is 20-50 sccm, and the process time is 5-15 s.

[0054] Through the first etching step described above, the chemical bonds on the bonding surfaces of the electrical chip 200 and the optical chip 100 can be broken, making the originally hydrophobic surface hydrophilic, greatly increasing the surface energy, and improving the interfacial adhesion, thereby improving the connection strength between the electrical chip 200 and the intermediate bonding layer 300 and between the optical chip 100 and the intermediate bonding layer 300, and ensuring the bonding quality of the optoelectronic co-packaging structure.

[0055] In the second etching step described above, the process gas includes oxygen and water vapor, the upper electrode power is 150-300 W, the lower electrode power is 1-10 W, the process pressure is 5-10 mTorr, the water vapor flow rate is 30-60 sccm, and the oxygen flow rate is 15-30 sccm.

[0056] In the second etching step, by setting the flow rate of water vapor to be greater than that of oxygen, a high proportion of OH- plasma can be formed to form a high density of OH- groups on the surfaces of the electrical chip 200 and the optical chip 100.

[0057] Step S300: Bond the optical chip 100 and the electrical chip 200.

[0058] Specifically, prior to the step of bonding the optical chip 100 and the electrical chip 200, as shown in FIG1(f), the method further includes coating an organic adhesive layer on the bonding surface of the electrical chip 200.

[0059] After forming a high density of OH- groups on the bonding surfaces of the electrical chip 200 and the optical chip 100, the surface energy of the bonding surfaces can be significantly increased. This makes it easier for the organic adhesive layer located between the electrical chip 200 and the optical chip 100 to wet the bonding surfaces of the electrical chip 200 and the optical chip 100. This not only improves the bonding strength, but also reduces the porosity of the bonding sites, thereby improving the toughness of the bonding sites.

[0060] After the organic adhesive layer is coated, as shown in Figure 1(g), the optical chip 100 and the electrical chip 200 are aligned and bonded together. The resulting optoelectronic co-package structure after bonding is shown in Figure 1(h).

[0061] Specifically, in the above-mentioned steps of bonding the optical chip 100 and the electrical chip 200, the process temperature is 175-185 ℃, the process pressure is 1.5-3 MPa, and the bonding time is 10-20 min.

[0062] By using the above process parameters to bond the optical chip 100 and the electrical chip 200, the organic adhesive layer can effectively bond the optical chip 100 and the electrical chip 200 together, thereby ensuring the bonding quality and high-temperature stability of the formed optoelectronic co-packaging structure.

[0063] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0064] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] In the above embodiments, descriptions of directions such as "up", "down", and "side" are based on the accompanying drawings.

[0066] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A photoelectric co-packaging structure, characterized in that, The device includes an optical chip (100) and an electrical chip (200) bonded together. The side of the electrical chip (200) facing the optical chip (100) has a central region (210) and an edge region (220). Both the central region (210) and the edge region (220) are provided with a plurality of dispersed support pillars (230). The spacing between the support pillars (230) in the central region (210) is smaller than the spacing between the support pillars (230) in the edge region (220).

2. The optoelectronic co-packaging structure according to claim 1, characterized in that, The diameter of the support column (230) in the central region (210) is greater than the diameter of the support column (230) in the edge region (220).

3. The optoelectronic co-packaging structure according to claim 1, characterized in that, The density of the support columns (230) in the central region (210) is 50-80%, and the density of the support columns (230) in the edge region (220) is 20-40%.

4. The optoelectronic co-packaging structure according to claim 1, characterized in that, The diameter of the support column (230) is between 2 and 30 μm, and the height of the support column (230) is between 2 and 40 μm.

5. The optoelectronic co-packaging structure according to claim 1, characterized in that, The optoelectronic co-packaging structure further includes an intermediate bonding layer (300), which is located between the optical chip (100) and the electrical chip (200), and the intermediate bonding layer (300) is filled between any two adjacent support pillars (230).

6. The optoelectronic co-packaging structure according to claim 5, characterized in that, The coefficient of thermal expansion of the intermediate bonding layer (300) is between 2 and 20 ppm / ℃.

7. The optoelectronic co-packaging structure according to claim 1, characterized in that, Each of the support columns (230) has the same support height, and the depth of the interval between the support columns (230) in the central region (210) is less than the depth of the interval between the support columns (230) in the edge region (220).

8. A method for fabricating an optoelectronic co-packaging structure, characterized in that, For manufacturing the optoelectronic co-packaging structure according to any one of claims 1-7, comprising: A substrate (201) is provided and the substrate (201) is patterned to form the electrical chip (200). Activating the bonding surfaces of the electrical chip (200) and the optical chip (100); wherein the step of activating the bonding surfaces of the electrical chip (200) and the optical chip (100) includes: a first etching step, subjecting the bonding surfaces of the electrical chip (200) and the optical chip (100) to plasma bombardment; and a second etching step, subjecting the bonding surfaces of the electrical chip (200) and the optical chip (100) to free radical etching modification to form OH- groups on the bonding surfaces of the electrical chip (200) and the optical chip (100); The optical chip (100) and the electrical chip (200) are bonded together.

9. The preparation method according to claim 8, characterized in that, In the first etching step, the process gas includes nitrogen, the upper electrode power is 200-400 W, the lower electrode power is 20-50 W, the process pressure is 6-15 mTorr, the nitrogen flow rate is 20-50 sccm, and the process time is 5-15 s.

10. The preparation method according to claim 8, characterized in that, In the second etching step, the process gas includes oxygen and water vapor, the upper electrode power is 150-300 W, the lower electrode power is 1-10 W, the process pressure is 5-10 mTorr, the water vapor flow rate is 30-60 sccm, and the oxygen flow rate is 15-30 sccm.

11. The preparation method according to claim 8, characterized in that, Before the step of bonding the optical chip (100) and the electrical chip (200), the method further includes: An organic adhesive layer is coated on the bonding surface of the electrical chip (200).

12. The preparation method according to claim 8, characterized in that, In the step of bonding the optical chip (100) and the electrical chip (200), the process temperature is 175-185 ℃, the process pressure is 1.5-3 MPa, and the bonding time is 10-20 min.

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