FPGA (Field Programmable Gate Array) multi-soft-core serial port communication online upgrading system and method for display screen

Abstract

The invention provides an FPGA multi-soft-core serial port communication online upgrading system for a display screen, and belongs to the technical field of hardware development, the system comprises an upper computer, the display screen and an FPGA board card, the FPGA board card comprises a plurality of soft cores and Brams used for processing data communication and online upgrading of an FPGA, and the number of the soft cores is larger than or equal to 3. When a large amount of data needs to be processed or a new function needs to be added to the FPGA, a new soft core can be continuously added. The multiple soft cores can process independent tasks at the same time, reusability and portability of an upgrade module are facilitated, the throughput of data of the whole system is improved, and the problem that a single soft core is poor in load capacity is solved.

Description

Technical Field

[0001] This invention belongs to the field of hardware development technology, specifically relating to an online upgrade system and method for FPGA multi-soft-core serial communication for display screens. Background Technology

[0002] FPGAs (Field-Programmable Gate Arrays) possess highly parallel processing capabilities, flexible programmability, and real-time signal processing capabilities, thus playing a crucial role in video processing and display applications. For reliability and product integrity reasons, the JTAG port used for FPGA chip upgrades is typically enclosed within the display casing. When performing software upgrades on FPGA chips on the hardware circuit boards of some displays, upgrading via JTAG requires disassembling the display casing each time, a cumbersome process.

[0003] In some situations, the JTAG interface is not suitable for security or convenience reasons. Serial ports, such as RS232, are used for program debugging and data monitoring, and are therefore generally external. Serial communication protocols are simple, data transmission is easy to implement, and it facilitates rapid program development and upgrades. Furthermore, almost all operating systems and programming languages ​​support serial communication, making cross-platform data transmission easy. Online FPGA upgrades via external serial ports allow for operation without restarting the device, reducing downtime. Upgrading FPGA firmware using an external serial port does not require opening the device casing, simplifying the process and improving the security and convenience of the upgrade.

[0004] Typically, FPGAs have a soft core for handling data reception, transmission, and other functions. Directly adding upgrade functionality to existing programs would further complicate the program and hinder future maintenance and debugging. Summary of the Invention

[0005] The purpose of this invention is to realize online upgrade of FPGA through an external serial port, and to use different soft cores to handle the online upgrade function, the reception and transmission of data through the IIC interface and GPIO interface, and other functions.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an FPGA multi-soft-core serial port communication online upgrade system for a display screen, the system comprising a host computer, a display screen and an FPGA board, the FPGA board comprising multiple soft cores and Brams for processing FPGA data communication and online upgrades, wherein the number of soft cores is greater than or equal to 3.

[0007] The FPGA multi-soft-core serial communication online upgrade system for display screens provided by this invention also has the following technical feature: the number of soft cores is three, namely soft core one, soft core two, and soft core three. Soft core one is configured to receive status data from the host computer and write it into the Bram, and to read FPGA status data from the Bram and send it to the host computer. Soft core two is configured to read status data from the host computer into the Bram and send it to the display screen via the GPIO interface, and to receive status data from the display screen via the IIC interface and store it in the Bram. Soft core three is a backup soft core used to handle other communication functions between the FPGA and the display screen. The host computer connects to soft core one via UART; soft core one connects to Bram on one side and Flash on the other via SPI; Bram connects to soft core one, soft core two, and soft core three; soft core two connects to the display screen via GPIO and IIC interfaces; soft core three connects to the display screen via other communication methods.

[0008] The FPGA multi-soft-core serial communication online upgrade system for display screen provided by this invention also has the following technical features: the host computer is a PC, which communicates with the soft core of the FPGA through a full-duplex RS232 interface; the baud rate of communication between the host computer and the FPGA is set to 230400, and the data format is 1 start bit, 1 stop bit, and 8 data bits; the serial communication parity bit is set to odd parity.

[0009] The host computer is configured to split the FGPA bin format upgrade file into 1024-byte packets and send them to the first soft core, as well as to send the host computer's status data to the first soft core.

[0010] The FPGA multi-soft-core serial communication online upgrade system for display screen provided by the present invention also has the following technical features: the FPGA clock frequency is 100MHz, and the Xilinx XC7K325T chip is used as the logic operation platform; the FPGA logic design is implemented on Vivado, and the software development of soft core one, soft core two and soft core three is implemented in the SDK environment.

[0011] The FPGA multi-soft-core serial communication online upgrade system for display screens provided by this invention also has the following technical feature: the host computer is configured with the following workflow: S1: Initialize the host computer software system; S2: Send serial port configuration commands via serial port to configure the FPGA serial port parameters to be consistent with the host computer serial port parameters. Then continuously check whether the serial port receives the "serial port configuration successful" ack sent by the FPGA. If it is successfully detected, proceed to S3; otherwise, repeat S2. S3: Send the start online upgrade command via serial port to tell the FPGA that it can enter the online upgrade process. Then continuously check whether the serial port receives the "ready for online upgrade" ack sent by the FPGA. If it is successfully detected, proceed to S4; otherwise, repeat S3. S4: Send the online upgrade data packet via serial port, then continuously check whether the serial port receives the "data packet write successful ack" sent by the FPGA. If it is successfully detected, determine that the upgrade data packet has been sent. Then determine whether all upgrade data packets have been sent. If all have been sent, proceed to S5; otherwise, repeat S4. S5: End online upgrade by sending an online upgrade end command via serial port.

[0012] The FPGA multi-soft-core serial communication online upgrade system for display screens provided by this invention also has the following technical feature: the soft core is configured with the following workflow: Step (1): Initialize the soft core peripheral and proceed to step (2); Step (2): When the serial port receives data, enter the serial port receive interrupt; verify the received serial port data to determine whether the currently received data is an online upgrade command or a data packet. If it is an online upgrade command or a data packet, proceed to step (3); otherwise, proceed to step (5). Step (3): Continue to judge the serial port data. If it is an "online upgrade data packet", perform frame header verification on the upgrade data packet, complete the reception of the online upgrade data packet, and then perform a check on all the data and proceed to step (4). If it is not an online upgrade data packet, proceed to step (6). Step (4): Perform read / write flash verification. Write the received data to the flash via the SPI bus, then read the data from the flash via the SPI bus. Compare each written data and read data using the Memcmp() function. If the comparison passes, end the current data packet reception and proceed to step (7). Step (5): Determine that the current serial port data is "host computer status data packet", perform frame header verification and S& verification on the host computer status data packet, write the host computer status data into Bram, then read the FGPA status data from Bram, perform S& verification on it, and then send the FGPA status data to the host computer every 500ms, and proceed to step (7). Step (6): Determine that the current instruction is an "online upgrade instruction packet", complete the upgrade instruction packet reception, reconfigure the serial port information, perform read and write flash test, start online upgrade, and proceed to step (7). Step (7): End the current data packet reception and determine whether all data packets have been received. If all data packets have been received, end the online upgrade; otherwise, proceed to step (2).

[0013] The FPGA multi-soft-core serial communication online upgrade system for display screens provided by this invention also has the following technical feature: the second soft core is configured with the following workflow: A. Initialize the second soft core, then proceed to B; B. Read the host computer status data from the Bram using the library functions provided in the SDK, perform a checksum verification on the read host computer status data, and then send the host computer status to the display screen via GPIO, proceeding to C; C. Communicate with the display screen via IIC to obtain the display screen status data, then perform a checksum verification on the display screen status data; obtain the FGPA status data and perform a data checksum verification, then write the FGPA status data and the display screen status data into the Bram, thus completing one data read / write cycle.

[0014] The FPGA multi-soft-core serial communication online upgrade system for display screens provided by this invention also has the following technical features, wherein the display screen is configured to operate as follows: Step I: Initialize the display program, then proceed to Step II; Step II: Read the status data sent by the FPGA from the host computer from the memory, display it on the screen, and proceed to Step III; Step 3: Obtain the display status and send it to the FPGA via IIC to end this program read / write operation.

[0015] Another objective of this invention is to provide an online upgrade method for FPGA multi-soft-core serial communication for display screens, the method being implemented based on the online upgrade system provided in any of the preceding claims.

[0016] Beneficial effects: This application provides an online upgrade system for FPGA multi-soft-core serial communication for displays. Firstly, it handles the online upgrade function by adding new soft cores. When a large amount of data needs to be processed or the FPGA needs new functionality, more soft cores can be added. Multiple soft cores can handle independent tasks simultaneously, which improves the reusability and portability of the upgrade module, increases the overall system data throughput, and solves the problem of poor single-soft-core load capacity. The provided method enables online firmware upgrades for FPGAs via serial port, offering advantages such as simple upgrade process and high versatility. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a structural block diagram of the system provided in the embodiments of the present invention. Figure 2 This is a flowchart of the host computer program implementation method provided in the embodiments of the present invention; Figure 3 This is a flowchart of the soft-core program implementation method provided in the embodiments of the present invention; Figure 4 This is a flowchart of the soft-core two-program implementation method provided in the embodiments of the present invention; Figure 5 This is a flowchart of the display screen program implementation method provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent changes or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the protection scope of the present invention.

[0020] In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the invention.

[0021] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0022] The terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art will understand the specific meaning of these terms in this invention based on the specific circumstances.

[0023] like Figure 1-5 As shown, this embodiment of the invention provides an FPGA multi-soft-core serial port communication online upgrade system for a display screen. The system includes a host computer, a display screen, and an FPGA board. The FPGA board includes multiple soft cores and Brams for processing FPGA data communication and online upgrades, wherein the number of soft cores is greater than or equal to 3.

[0024] In some embodiments, the number of soft cores is three, namely soft core one, soft core two, and soft core three. Soft core one is configured to receive status data from the host computer and write it into the Bram, and to read FPGA status data from the Bram and send it to the host computer. Soft core two is configured to read status data from the host computer into the Bram and send it to the display screen through the GPIO interface, and to receive status data from the display screen through the IIC interface and store it in the Bram. Soft core three is a spare soft core used to handle other communication functions between the FPGA and the display screen. The host computer is connected to soft core one through UART. Soft core one is connected to the Bram and to the Flash memory through SPI. The Bram connects soft core one and soft core two. Soft core two is connected to the display screen through the GPIO interface and the IIC interface. Soft core three is connected to the display screen through other communication methods.

[0025] In some embodiments, the host computer is a PC that communicates with the soft core of the FPGA via a full-duplex RS232 interface. The baud rate for communication between the host computer and the FPGA is set to 230400, using a data format of 1 start bit, 1 stop bit, and 8 data bits. The serial communication parity bit is set to odd parity. The host computer is configured to split the FPGA's bin format upgrade file into 1024-byte packets and send them to the soft core, as well as to send the host computer's status data to the soft core.

[0026] In some embodiments, the FPGA has a clock frequency of 100MHz and uses a Xilinx XC7K325T chip as the logic operating platform; the FPGA logic design is implemented on Vivado, and the software development of soft core one, soft core two and soft core three is implemented in the SDK environment.

[0027] In the above embodiment, the first soft core uses the MicroBlaze IP core, a 32-bit RISC architecture embedded soft core processor developed by Xilinx. The first soft core connects to the Bram and communicates with the host computer via a serial port. When not in online upgrade mode, the host computer and the first soft core exchange host computer status data and FPGA status data every 500ms. When performing an online upgrade operation, the first soft core stops exchanging status data with the host computer. It only receives online upgrade data or command packets sent via the serial port and responds to the commands.

[0028] The Bram is 4Kb in size, with addresses ranging from 0x00080000 to 0x00080FFF. It uses a true dual-port RAM mode, with both write and read widths set to 32 bits and a depth of 2048.

[0029] The second soft core also uses the MicroBlaze IP core, a 32-bit RISC architecture embedded soft core processor developed by Xilinx.

[0030] In some embodiments, the host computer is configured with the following workflow: S1: Initialize the host computer software system, including initializing the serial port configuration, setting the host computer's serial port baud rate to 230400, and setting the start bit, stop bit, data bit, and parity, etc.; then split the bin file used for online upgrade into several packages, each of which is 1024 bytes except for the last package. S2: Send serial port configuration commands via serial port to configure the FPGA serial port parameters to be consistent with the host computer serial port parameters. Then continuously check whether the serial port receives the "serial port configuration successful" ack sent by the FPGA. If it is successfully detected, proceed to S3; otherwise, repeat S2. S3: Send the start online upgrade command via serial port to tell the FPGA that it can enter the online upgrade process. Then continuously check whether the serial port receives the "ready for online upgrade" ack sent by the FPGA. If it is successfully detected, proceed to S4; otherwise, repeat S3. S4: Send the online upgrade data packet via serial port, then continuously check whether the serial port receives the "data packet write successful ack" sent by the FPGA. If it is successfully detected, determine that the upgrade data packet has been sent. Then determine whether all upgrade data packets have been sent. If all have been sent, proceed to S5; otherwise, repeat S4. S5: End online upgrade by sending an online upgrade end command via serial port.

[0031] In some embodiments, the soft core is configured to operate as follows: Step (1): Initialize the soft core peripheral, including initializing the timer, serial port, SPI, and interrupt system. Set the serial port baud rate of the soft core to 230400, and set the start bit, stop bit, data bit, and parity, etc.; set the serial port transmit interrupt and serial port receive interrupt; set the timer trigger interrupt to trigger the serial port transmit interrupt once every 500ms; set the SPI to work in four-wire mode, and proceed to step (2). Step (2): When the serial port receives data, enter the serial port receive interrupt; verify the received serial port data to determine whether the currently received data is an online upgrade command or a data packet. If it is an online upgrade command or a data packet, proceed to step (3); otherwise, proceed to step (5). Step (3): Continue to judge the serial port data. If it is an "online upgrade data packet", perform frame header verification on the upgrade data packet, complete the reception of the online upgrade data packet, and then perform a check on all the data and proceed to step (4). If it is not an online upgrade data packet, proceed to step (6). Step (4): Perform read / write flash verification. Write the received data to the flash via the SPI bus, then read the data from the flash via the SPI bus. Compare each written data and read data using the Memcmp() function. If the comparison passes, end the current data packet reception and proceed to step (7). Step (5): Determine that the current serial port data is "host computer status data packet", perform frame header verification and S& verification on the host computer status data packet, write the host computer status data into Bram, then read the FGPA status data from Bram, perform S& verification on it, and then send the FGPA status data to the host computer every 500ms, and proceed to step (7). Step (6): Determine that the current instruction is an "online upgrade instruction packet", complete the upgrade instruction packet reception, reconfigure the serial port information, perform read and write flash test, start online upgrade, and proceed to step (7). Step (7): End the current data packet reception and determine whether all data packets have been received. If all data packets have been received, end the online upgrade; otherwise, proceed to step (2).

[0032] In some embodiments, the second soft core is configured to operate as follows: A. Initialize the second soft core, initialize the GPIO port, enable the GPIO port; initialize IIC communication, set the IIC clock frequency to 100kHz, enable the IIC bus, and proceed to B. B. Read the host computer status data from the Bram using the library functions provided in the SDK, perform a checksum verification on the read host computer status data, and then send the host computer status to the display screen via GPIO, proceeding to C; C. Communicate with the display screen via IIC to obtain the display screen status data, then perform a checksum verification on the display screen status data; obtain the FGPA status data and perform a data checksum verification, then write the FGPA status data and the display screen status data into the Bram, thus completing one data read / write cycle.

[0033] In some embodiments, the display screen is configured to operate as follows: Step 1: Initialize the display program, initialize the GPIO port, enable the GPIO port; initialize IIC communication, set the IIC clock frequency to 100kHz, enable the IIC bus, and proceed to Step 2. Step II: Read the status data sent by the FPGA from the host computer from the memory, display it on the screen, and proceed to Step III; Step 3: Obtain the display status and send it to the FPGA via IIC to end this program read / write operation.

[0034] In some embodiments, an online upgrade method for FPGA multi-soft-core serial communication for display screens is provided, the method being implemented based on the online upgrade system provided in any of the foregoing embodiments.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the protection scope of the present invention.

Claims

1. An FPGA multi-soft-core serial communication online upgrade system for display screens, characterized in that, The system includes a host computer, a display screen, and an FPGA board. The FPGA board includes multiple soft cores and Brams for processing FPGA data communication and online upgrades, wherein the number of soft cores is greater than or equal to 3.

2. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 1, characterized in that, The number of soft cores is 3, namely soft core one, soft core two and soft core three. Soft core one is configured to receive status data from the host computer and write it into the Bram, and to read FPGA status data from the Bram and send it to the host computer. Soft core two is configured to read status data from the host computer into the Bram and send it to the display screen through the GPIO interface, and to receive status data from the display screen through the IIC interface and store it in the Bram. Soft core three is a backup soft core used to handle other communication functions between the FPGA and the display screen. The host computer connects to soft core one via UART; soft core one connects to Bram on one side and Flash on the other via SPI; Bram connects to soft core one, soft core two, and soft core three; soft core two connects to the display screen via GPIO and IIC interfaces; soft core three connects to the display screen via other communication methods.

3. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 2, characterized in that, The host computer is a PC, which communicates with the soft core of the FPGA via a full-duplex RS232 interface. The baud rate for communication between the host computer and the FPGA is set to 230400, and the data format is 1 start bit, 1 stop bit, and 8 data bits. The serial communication parity bit is set to odd parity. The host computer is configured to split the FGPA bin format upgrade file into 1024-byte packets and send them to the first soft core, as well as to send the host computer's status data to the first soft core.

4. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 2, characterized in that, The FPGA has a clock frequency of 100MHz and uses a Xilinx XC7K325T chip as its logic operating platform. The FPGA's logic design is implemented on Vivado, and the software development for soft core one, soft core two, and soft core three is implemented in the SDK environment.

5. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 2, characterized in that, The host computer is configured with the following workflow: S1: Initialize the host computer software system; S2: Send serial port configuration commands via serial port to configure the FPGA serial port parameters to be consistent with the host computer's serial port parameters. Then continuously check whether the serial port receives the "serial port configuration successful" ack sent by the FPGA. If it is successfully detected, proceed to S3. Otherwise, repeat S2; S3: Send the start online upgrade command via serial port to tell the FPGA that it can enter the online upgrade process. Then continuously check whether the serial port receives the "ready for online upgrade" ack sent by the FPGA. If it is successfully detected, proceed to S4; otherwise, repeat S3. S4: Send the online upgrade data packet via serial port, then continuously check whether the serial port receives the "data packet write successful ack" sent by the FPGA. If it is successfully detected, determine that the upgrade data packet has been sent. Then determine whether all upgrade data packets have been sent. If all have been sent, proceed to S5; otherwise, repeat S4. S5: End online upgrade by sending an online upgrade end command via serial port.

6. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 2, characterized in that, The soft core is configured to operate as follows: Step (1): Initialize the soft core peripheral and proceed to step (2); Step (2): When the serial port receives data, enter the serial port receive interrupt; verify the received serial port data to determine whether the currently received data is an online upgrade command or a data packet. If it is an online upgrade command or a data packet, proceed to step (3); otherwise, proceed to step (5). Step (3): Continue to judge the serial port data. If it is an "online upgrade data packet", perform frame header verification on the upgrade data packet, complete the reception of the online upgrade data packet, and then perform a check on all the data and proceed to step (4). If it is not an online upgrade data packet, proceed to step (6). Step (4): Perform read / write flash verification. Write the received data to the flash via the SPI bus, then read the data from the flash via the SPI bus. Compare each written data and read data using the Memcmp() function. If the comparison passes, end the current data packet reception and proceed to step (7). Step (5): Determine that the current serial port data is "host computer status data packet", perform frame header verification and S& verification on the host computer status data packet, write the host computer status data into Bram, then read the FGPA status data from Bram, perform S& verification on it, and then send the FGPA status data to the host computer every 500ms, and proceed to step (7). Step (6): Determine that the current instruction is "online upgrade instruction packet", complete the upgrade instruction packet reception, reconfigure the serial port information, perform read and write flash test, start online upgrade, and proceed to step (7); Step (7): End the current data packet reception and determine whether all data packets have been received. If all data packets have been received, end the online upgrade; otherwise, proceed to step (2).

7. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 2, characterized in that, The second soft core is configured to operate as follows: A. Initialize the second soft core, then proceed to B; B. Read the host computer status data from the Bram using the library functions provided in the SDK, perform a checksum verification on the read host computer status data, and then send the host computer status to the display screen via GPIO, proceeding to C; C. Communicate with the display screen via IIC to obtain the display screen status data, then perform a checksum verification on the display screen status data; obtain the FGPA status data and perform a data checksum verification, then write the FGPA status data and the display screen status data into the Bram, thus completing one data read / write cycle.

8. The FPGA multi-soft-core serial communication online upgrade system for display screens according to claim 2, characterized in that, The display screen is configured to operate as follows: Step I: Initialize the display program, then proceed to Step II; Step II: Read the status data sent by the FPGA from the host computer from the memory, display it on the screen, and proceed to Step III; Step 3: Obtain the display status and send it to the FPGA via IIC to end this program read / write operation.

9. A method for online upgrade of FPGA multi-soft-core serial communication for display screens, characterized in that, The method is implemented based on the online upgrade system provided in any one of claims 1-8.

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