Cache processing method and device, FPGA chip, electronic equipment and computer program product

Abstract

The invention provides a cache processing method and device, an FPGA chip, electronic equipment and a computer program product, and the method comprises the steps: determining whether access data is hit in a cache component of the FPGA chip or not according to an access address, and the cache component is divided into a high-frequency region and a low-frequency region; if the access data is hit, executing a corresponding cache processing strategy according to the high-frequency area or the low-frequency area to which the access data belongs; wherein the cache processing strategy is used for indicating that the elimination priority level of the high-frequency region is lower than the elimination priority level of the low-frequency region under a preset condition. According to the method, the designed structure is simple, and meanwhile the cache hit rate is high.

Description

Technical Field

[0001] This application relates to the field of cache technology, and in particular to a cache processing method, apparatus, FPGA chip, electronic device and computer program product. Background Technology

[0002] In modern computing systems, a cache is a high-speed storage component that stores programs and data for fast access. Caches typically reside between the processor and main memory, aiming to reduce the average time required for the processor to access data. The role of caches is particularly important in Field Programmable Gate Arrays (FPGAs), as FPGAs are commonly used for applications requiring high-speed data access and processing, such as network communication, image processing, and dataflow analysis. FPGA caches can efficiently store temporary data, reducing the number of accesses to slow external memory, thereby significantly improving the overall system performance.

[0003] However, due to limited resources on FPGAs, cache size is typically constrained and cannot store all potentially accessed data. Therefore, when the cache is full, an algorithm is needed to determine which data should be retained and which should be evicted to make room for new data. Currently, common cache eviction algorithms (or cache replacement algorithms) either have low cache hit rates or high cache hit rates, but these solutions are often complex to design and require software support.

[0004] Therefore, the relevant technologies cannot achieve a high cache hit rate while maintaining a simple design structure. Summary of the Invention

[0005] Exemplary embodiments of this application provide a cache processing method, apparatus, FPGA chip, electronic device, and computer program product to solve the problem that related technologies cannot achieve a high cache hit rate while maintaining a simple design structure.

[0006] In a first aspect, embodiments of this application provide a caching method, the method comprising:

[0007] Based on the access address, it is determined whether the accessed data is hit in the cache component, which is divided into a high-frequency area and a low-frequency area;

[0008] If the accessed data is hit, a corresponding caching strategy is executed based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone; wherein, the caching strategy is used to indicate that, under preset conditions, the eviction level of the high-frequency zone is lower than the eviction level of the low-frequency zone.

[0009] In one possible design, the caching component includes a cache, which is a multi-way set-associative cache, with one cache set corresponding to one configuration parameter;

[0010] Specifically, for each cache group of the cache component, the configuration parameter is used to determine the number of times the contents of the low-frequency cache blocks within the cache group are continuously evicted.

[0011] In one possible design, the caching strategy includes an eviction policy for high-frequency zones; the step of executing the corresponding caching strategy based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone includes:

[0012] When the accessed data is in the high-frequency zone of the corresponding first cache group, update the first least recently used (LRU) block information of the high-frequency zone of the first cache group, and output the accessed data; and / or,

[0013] When the accessed data is in the low-frequency zone of the first cache group, the contents of the cache block in the low-frequency zone of the first cache group where the accessed data is located are swapped with the contents of the cache block that has been evicted in the high-frequency zone of the first cache group, and the LRU block information of the first cache group is updated. The accessed data is then output. The LRU block information includes the first LRU block information of the high-frequency zone and the second LRU block information of the low-frequency zone. The cache block that has been evicted in the high-frequency zone of the first cache group is determined by executing the eviction policy for the high-frequency zone of the first cache group.

[0014] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0015] In one possible design, the method further includes:

[0016] When updating the first LRU block information of the high-frequency area of ​​the first cache group or updating the LRU block information of the first cache group, the configuration parameter corresponding to the first cache group is set to 0.

[0017] In one possible design, if the access data is not found, the access data is obtained by querying external memory;

[0018] Based on the access address and the access data, execute the corresponding caching strategy.

[0019] In one possible design, the content of the cache block includes an identifier indicating whether the cache block is valid, data bits, and a memory TAG value indicating the storage address; the execution of the corresponding caching strategy based on the access address and the access data includes:

[0020] Based on the access address, determine the group number of the corresponding second cache group and the first TAG value;

[0021] Read each cache block of the second cache group corresponding to the group number, and determine whether there are invalid cache blocks in the second cache group based on the identifier of each cache block in the second cache group;

[0022] If the second cache group contains invalid cache blocks, the accessed data and the corresponding first TAG value are overwritten to the first cache block, and the first LRU block information in the high-frequency zone or the second LRU block information in the low-frequency zone of the second cache group where the first cache block is located is updated. The identifier corresponding to the first cache block is also updated to indicate a valid identifier. The first cache block is determined from the invalid cache blocks in the second cache group, and the configuration parameters remain unchanged; and / or,

[0023] If there are no invalid cache blocks in the second cache group, then the second cache block of the second cache group is determined according to the configuration parameters and the number of times threshold. The access data and the corresponding first TAG value are overwritten to the second cache block, and the second LRU block information of the low-frequency zone of the second cache group where the second cache block is located is updated or the LRU block information of the second cache group is updated.

[0024] In one possible design, the caching strategy further includes a low-frequency region eviction policy; determining the second cache block of the second cache group based on the configuration parameters and the number of occurrences threshold includes:

[0025] When the configuration parameter is greater than or equal to the number of times threshold is reached, the eviction policy for the high-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the high-frequency region of the second cache group, and the eviction policy for the low-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the low-frequency region of the second cache group, and the content of the cache blocks evicted in the high-frequency region of the second cache group is overwritten with the content of the cache blocks evicted in the low-frequency region of the second cache group; wherein, the cache blocks evicted in the high-frequency region of the second cache group are used as the second cache blocks; and / or,

[0026] When the configuration parameter is less than the number of times threshold, the low-frequency area eviction policy for the second cache group is executed to determine the content of the cache blocks that are evicted in the low-frequency area of ​​the second cache group; wherein, the cache blocks that are evicted in the low-frequency area of ​​the second cache group are used as the second cache blocks.

[0027] In one possible design, the method further includes:

[0028] When the configuration parameter is greater than or equal to the number of accesses threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is set to 0, and the access data is output; and / or,

[0029] When the configuration parameter is less than the number of times threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is incremented by 1, and the access data is output.

[0030] In one possible design, the elimination strategy for the high-frequency region includes:

[0031] Based on the first LRU block information in the high-frequency zone, the contents of the evicted cache blocks are determined from the high-frequency zone.

[0032] In one possible design, the elimination strategy for the low-frequency region includes:

[0033] Based on the second LRU block information of the low-frequency region, the contents of the cache blocks that have been evicted are determined from the low-frequency region.

[0034] In one possible design, determining whether the accessed data is hit in the cache component based on the access address includes:

[0035] Based on the access address, determine the group number and second TAG value corresponding to the access address in the cache component;

[0036] Read each cache block of the cache group corresponding to the group number, and for a valid cache block, determine whether the accessed data has been hit by comparing the third TAG value and the second TAG value of the valid cache block.

[0037] Secondly, embodiments of this application provide a cache processing apparatus, the apparatus comprising:

[0038] The judgment module is used to determine whether the accessed data is hit in the cache component based on the access address. The cache component is divided into a high-frequency area and a low-frequency area.

[0039] The processing module is configured to execute a corresponding caching strategy based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone when the accessed data is hit; wherein the caching strategy is configured to indicate that, under preset conditions, the eviction level of the high-frequency zone is lower than the eviction level of the low-frequency zone.

[0040] Thirdly, embodiments of this application provide a field-programmable gate array (FPGA) chip, the FPGA chip including a cache component, the FPGA chip being used to execute the cache processing method as described in any of the first aspects.

[0041] In one possible design, the caching component is a Cache, which is a multi-way set-associative mapped Cache; each Cache set includes multiple Cache blocks, and each Cache set corresponds to a high-frequency region and a low-frequency region, with one high-frequency region corresponding to one first LRU information and one low-frequency region corresponding to one second LRU information. There are multiple Cache blocks in both the high-frequency region and the low-frequency region, and the content of each Cache block includes an identifier for indicating whether it is valid, data bits, and a TAG value.

[0042] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0043] Fourthly, embodiments of this application provide an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0044] The memory stores computer-executed instructions;

[0045] The processor executes computer execution instructions stored in the memory to implement the method as described in any of the first aspects.

[0046] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in any of the first aspects.

[0047] The caching processing method, apparatus, FPGA chip, electronic device, and computer program product provided in this embodiment first determine whether the accessed data is hit in the cache component based on the access address. The cache component is divided into a high-frequency zone and a low-frequency zone. Further, if the accessed data is hit, a corresponding caching processing strategy is executed according to whether the accessed data belongs to the high-frequency zone or the low-frequency zone. The caching processing strategy indicates that, under preset conditions, the eviction level of the high-frequency zone is lower than that of the low-frequency zone. Therefore, this application divides the cache component into high-frequency and low-frequency zones, and based on the design that the eviction level of the high-frequency zone is lower than that of the low-frequency zone, it achieves operations such as prioritizing the eviction of the low-frequency zone under preset conditions, allowing high-frequency data to be retained. This greatly protects high-frequency data, preventing it from being easily evicted, thus achieving a high hit rate. Simultaneously, the design structure is simple and requires no additional software intervention. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the high-speed cache storage system structure provided in an embodiment of this application;

[0050] Figure 2 This is a schematic diagram of group-associated mapping provided in an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of the cache structure corresponding to the cache processing method provided in the embodiments of this application;

[0052] Figure 4 This is a schematic diagram of the structure of a Block provided in an embodiment of this application;

[0053] Figure 5 A flowchart illustrating the caching method provided in this application embodiment;

[0054] Figure 6 A schematic flowchart of a caching method provided in another embodiment of this application;

[0055] Figure 7A schematic flowchart illustrating a caching method provided in another embodiment of this application;

[0056] Figure 8 A four-way PLRU binary tree diagram provided for embodiments of this application;

[0057] Figure 9 A schematic diagram illustrating an example of low-frequency content hits provided in an embodiment of this application;

[0058] Figure 10 A schematic diagram illustrating an example of high-frequency content hits provided in an embodiment of this application;

[0059] Figure 11 A schematic diagram illustrating an example of eliminating low-frequency content provided in an embodiment of this application;

[0060] Figure 12 A schematic diagram illustrating an example of eliminating frequently used content provided in an embodiment of this application;

[0061] Figure 13 This is a schematic diagram of the structure of the cache processing device provided in the embodiments of this application;

[0062] Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0063] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0064] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0065] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0066] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0067] To address the problems of related technologies, the technical concept of this application is to divide the cache into high-frequency and low-frequency areas based on pseudo-LRU. When the cache hits the low-frequency area, the hit low-frequency data will be swapped into the high-frequency area. When the cache misses and needs to be replaced, the low-frequency data will be replaced first, which greatly protects the high-frequency data and prevents the high-frequency data from being easily replaced, thus achieving a high hit rate. At the same time, the design structure is simple and does not require any additional software intervention.

[0068] The cache processing method, apparatus, cache component, and FPGA chip provided in this application are intended to solve the above-mentioned technical problems in related technologies.

[0069] First, let me explain the terms used in this application:

[0070] Least Frequently Used (LFU): Data that has been accessed the least in the past period is discarded.

[0071] Least Recently Used (LRU): Evicts data that has not been accessed for the longest time.

[0072] The caching method provided in this application can be applied to Figure 1 The diagram shows the architecture of a high-speed cache storage system. Figure 1As shown, this high-speed cache storage system includes a lookup table module and a cache module in the FPGA chip, as well as memory (e.g., external memory). The cache module utilizes the RAM resources in the FPGA, directly storing some entries from external memory in the cache. Typically, the cache's storage capacity is much smaller than that of the external memory. After data access is processed by the lookup table, the desired memory address is obtained. This address is first checked against the cache to see if it is mapped to the cache. If it is, it's called a "hits," and the entry is directly retrieved from the cache and returned. Otherwise, it's considered a "miss," requiring a lookup in memory. The retrieved information is returned and simultaneously updated in the cache. The ratio of "hits" to the total amount of data accessed within a certain period is called the "cache hit rate."

[0073] For example, to improve the hit rate, the cache uses a set-associative mapping (e.g., a cache with multi-way set-associative mapping), see [link to relevant documentation]. Figure 2 The diagram illustrates a set-associative mapping. The cache is divided into m sets, each containing n cache blocks. Figure 2 The diagram shows two cache sets, each with two cache blocks (i.e., two-way cache per set, one for high-frequency cache and one for low-frequency cache), with each block being 16 bytes in size. A location in main memory corresponds to a specific cache set and can store any cache block within that set. The main memory block number I is mapped to the cache set number modulo I modulo the number of cache sets m. The number of cache blocks n in each set is called the cache way count.

[0074] For example, the positions of data 0-15 in main memory correspond to cache group 1. That is, bytes 0-15 in main memory are mapped to cache group 1, bytes 16-31 are mapped to cache group 2, bytes 32-47 are mapped to cache group 1, bytes 48-63 are mapped to cache group 2, and so on, with a cycle length of 2 16 bytes.

[0075] The specific application scenario of this application can be implemented based on an n-way set-associative cache structure, and the implemented cache structure is as follows: Figure 3 As shown. Combined with Figure 1As shown, the external memory address is provided by the cache front-end module, such as the lookup table module. The external memory address is parsed to determine which group it is mapped to, and then all cache blocks (hereinafter referred to as "Block") are searched in parallel within that group. The tag memory (TAG) values ​​storing the address are compared to determine if a matching Block exists. If a match exists, it's a "cache hit," the data in that Block is output, and the LRU block information is updated. If no match exists, it's a "cache miss," and the search continues in external memory. The search result is returned to the cache, and during cache write-back, a replacement algorithm (referring to the corresponding cache handling strategy) is executed to determine which Block the new data should be written to, and the LRU block information is updated. This structure can be implemented using RAM resources in the FPGA (chip).

[0076] The structure of a Block is as follows: Figure 4 As shown, it includes a Valid bit (i.e., a valid bit, 1 bit), a TAG bit (a flag used to distinguish blocks from different paths within the same group), and a DATA bit (used to store the DDR address entry corresponding to this block's data). The Valid bit indicates whether the block's data is valid. When the block is empty (i.e., not filled with data), the Valid bit is 0; otherwise, it is 1. When comparing for a cache hit, only blocks with Valid set to 1 need to be compared, improving processing efficiency. The TAG is used to determine if a block in the matched cache group stores data that matches the processor's desired data. This is typically the high-order bits of the memory address (here referring to the access address), and the bit width is determined based on the actual situation. DATA stores the actual data, which comes from external memory. When a "hits" occur, the DATA in the cache is directly retrieved as the output result. Given that the DATA bit width is usually relatively wide, DATA can also be placed in other locations on the FPGA, such as by creating a separate DATA area. This embodiment does not specifically limit this.

[0077] Figure 3 The LRU block shown is used to record the relative access status (here referring to access status) of the Blocks within the group, and is used to guide (or indicate) the replacement rules (here referring to replacement strategy) of the replacement algorithm. In the embodiments of this application, each Cache group contains two LRU blocks, which are used to maintain the high-frequency area and the low-frequency area respectively. That is, one Cache group corresponds to one high-frequency area and one low-frequency area, one high-frequency area corresponds to one LRU information, and one low-frequency area corresponds to one LRU information.

[0078] Figure 3The parameter n shown (here referring to the configuration parameter) is used to avoid high-frequency area retention. After the low-frequency area is continuously replaced (here referring to being eliminated) m times, the next step is to replace the high-frequency area content and then insert the eliminated high-frequency area content into the low-frequency area.

[0079] In this embodiment, the caching method can be applied to FPGA chips, or other chips configured with the aforementioned caching components, which will not be elaborated further here. Taking an FPGA chip as an example, the FPGA chip's caching components are divided into high-frequency and low-frequency areas. Under normal circumstances, the replacement level of the high-frequency area is lower than that of the low-frequency area, greatly protecting high-frequency data and preventing it from being easily replaced. For example, in a certain access pattern, some high-frequency data exists over a long period, but some burst data appears within a short period, causing this high-frequency data to not be accessed. Traditional pseudo-LRU schemes (which are only applicable to LRU-friendly data and fail especially during data cyclic access) only focus on the access pattern within this short period and replace the high-frequency data. However, this embodiment, through operations such as prioritizing the replacement of low-frequency data under certain conditions, allows high-frequency data to be retained. In other words, this embodiment can handle not only LRU-friendly data but also LFU-friendly data.

[0080] Therefore, the structure designed in this application is simple, requires no additional software intervention, and has a high hit rate.

[0081] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0082] Figure 5 This is a flowchart illustrating a caching method provided in an embodiment of this application. The caching method may include:

[0083] S501. Based on the access address, determine whether the accessed data is hit in the cache component. The cache component is divided into a high-frequency area and a low-frequency area.

[0084] S502. If the accessed data is hit, then according to the high-frequency zone or the low-frequency zone to which the accessed data belongs, the corresponding caching strategy is executed; wherein, the caching strategy is used to indicate that, under preset conditions, the elimination level of the high-frequency zone is lower than the elimination level of the low-frequency zone; and / or, if the accessed data is not hit, then the accessed data is obtained by querying the external memory, and the corresponding caching strategy is executed according to the access address and the accessed data.

[0085] In this embodiment, the execution entity can be a cache processing device, which can be deployed on an FPGA chip, without any specific limitation.

[0086] The caching strategy is used to indicate that, under preset conditions, data in the low-frequency region should be prioritized for eviction. For example, under preset conditions, the eviction level of the high-frequency region is lower than that of the low-frequency region. Here, the eviction level may include eviction weight or eviction priority, and the specific form of the eviction level is not limited here. For instance, the caching strategy is used to indicate that, under preset conditions, the eviction weight of the high-frequency region is lower than that of the low-frequency region; or, the caching strategy is used to indicate that, under preset conditions, the eviction priority of the high-frequency region is lower than that of the low-frequency region.

[0087] Specifically, address access can be divided into two states: "hit" and "miss", which can be further divided into the following 5 scenarios:

[0088] 1) Targeting the hit scenario

[0089] Scenario a. If a low-frequency region is hit, select a high-frequency data point according to the high-frequency region's elimination rule and swap it with the hit low-frequency data. Then update the LRU block information of the high-frequency region (i.e., the high-frequency region LRU block information) and the LRU block information of the low-frequency region (i.e., the low-frequency region LRU block information).

[0090] Scenario b. If the high-frequency region is hit, only the LRU information of the high-frequency region needs to be updated.

[0091] 2) For scenarios where a shot is missed

[0092] Scenario c. If there is a vacancy, insert the data directly into that vacancy, updating either the high-frequency LRU or low-frequency LRU information; priority is given to inserting into vacancy slots in the high-frequency region. That is: within the corresponding cache set, if an invalid block exists (i.e., a block with a Valid value of 0), the access data read from external memory (here referring to new data used for caching) is written to that block. If an invalid block exists in the high-frequency region, the new data is preferentially written to that invalid block in the high-frequency region, and the high-frequency LRU information is updated. If the new data is written to an invalid block in the low-frequency region, the low-frequency LRU information is updated.

[0093] Scenario d. If the group is full (i.e. there is no block with Valid=0), then according to the low-frequency area eviction rule (here referring to the low-frequency area eviction strategy), one data is evicted, then new data is inserted and the low-frequency area LRU information is updated.

[0094] Scenario e. To avoid the problem of high-frequency content lingering, set parameter n (here referring to the configuration parameter, which will not be elaborated below). After the low-frequency region has been continuously replaced m times (i.e. the number of times threshold, which will not be elaborated below), the next time is to replace the high-frequency content, and then insert the replaced high-frequency content into the low-frequency region.

[0095] The caching method provided in this application divides the cache component into a high-frequency area and a low-frequency area. Based on the design, the high-frequency area has a lower priority for eviction than the low-frequency area. This allows high-frequency data to be retained by prioritizing the eviction of low-frequency data under certain conditions, thus greatly protecting high-frequency data and preventing it from being easily evicted. This results in a high hit rate. At the same time, the design is simple and does not require any additional software intervention.

[0096] In one possible design, determining whether the accessed data is hit in the cache component based on the access address includes:

[0097] Based on the access address, determine the group number and second TAG value corresponding to the access address in the cache component;

[0098] Read each cache block of the cache group corresponding to the group number, and for a valid cache block, determine whether the accessed data has been hit by comparing the third TAG value and the second TAG value of the valid cache block.

[0099] In this embodiment, determining whether the accessed data has been hit in the cache component based on the access address can be achieved through the following process:

[0100] The system receives the access address from the preceding module, parses it to obtain the cache set number and the corresponding TAG value (which can be used as the second TAG value). Typically, the lower bits of the address are used as the set number index, and the higher bits are used as the TAG. All blocks in the cache set are read, and blocks with a Valid value of 1 are probed. The TAG value of these blocks (the third TAG value) is compared to the target TAG value (determined by parsing the access address, such as the second TAG value). If a matching block exists, a "hash" occurs; otherwise, new data is read from external memory. This eliminates the need to probe blocks with a Valid value of 0, thus improving processing efficiency.

[0101] In one possible design, the caching component includes a cache, which is a multi-way set-associative cache, with one cache set corresponding to one configuration parameter;

[0102] Specifically, for each cache group of the cache component, the configuration parameter is used to indicate the number of times the contents of the cache blocks in the low-frequency area within the cache group are continuously evicted.

[0103] In this embodiment, configuration parameters are used to avoid high-frequency content lingering. After the low-frequency content has been replaced m times consecutively, the next replacement will be of the high-frequency content, which will then be inserted into the low-frequency content. This improves the elimination level of the high-frequency content. When the configuration parameters are less than the number of replacements threshold (i.e., under preset conditions), low-frequency content is eliminated first.

[0104] In one possible design, the caching strategy includes an eviction policy for high-frequency zones; the step of executing the corresponding caching strategy based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone includes:

[0105] When the accessed data is in the high-frequency zone of the corresponding first cache group, update the first least recently used (LRU) block information of the high-frequency zone of the first cache group, and output the accessed data; and / or,

[0106] When the accessed data is in the low-frequency zone of the first cache group, the contents of the cache block in the low-frequency zone of the first cache group where the accessed data is located are swapped with the contents of the cache block that has been evicted in the high-frequency zone of the first cache group, and the LRU block information of the first cache group is updated. The accessed data is then output. The LRU block information includes the first LRU block information of the high-frequency zone and the second LRU block information of the low-frequency zone. The cache block that has been evicted in the high-frequency zone of the first cache group is determined by executing the eviction policy for the high-frequency zone of the first cache group.

[0107] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0108] In this embodiment, for a hit scenario, it checks whether the hit Block (here referring to the Block of the first Cache group) is in the high-frequency zone. If the hit Block is in the high-frequency zone, the high-frequency zone LRU block information (here referring to the first LRU block information of the high-frequency zone, which will not be repeated below) is updated, and the DATA value of the Block is read and output.

[0109] If the hit block is in the low-frequency region, then according to the high-frequency region LRU block information, select a high-frequency data and swap it with the hit data, update the high-frequency region LRU block information and the low-frequency region LRU block information (here referring to the second LRU block information in the low-frequency region, which will not be repeated below), and read the DATA value of the hit block and output it.

[0110] In one possible design, the method further includes:

[0111] When updating the first LRU block information of the high-frequency area of ​​the first cache group or updating the LRU block information of the first cache group, the configuration parameter corresponding to the first cache group is set to 0.

[0112] Specifically, the step of executing a corresponding caching strategy based on whether the accessed data belongs to a high-frequency or low-frequency zone includes:

[0113] When the accessed data is in the high-frequency zone of the corresponding first cache group, update the first least recently used LRU block information of the high-frequency zone of the first cache group, set the configuration parameter corresponding to the first cache group to 0, and output the accessed data; and / or,

[0114] When the accessed data is in the low-frequency zone of the first cache group, the contents of the cache block in the low-frequency zone of the first cache group where the accessed data is located are swapped with the contents of the cache block that has been evicted in the high-frequency zone of the first cache group, and the LRU block information of the first cache group is updated. The configuration parameters corresponding to the first cache group are set to 0, and the accessed data is output. The LRU block information includes the first LRU block information in the high-frequency zone and the second LRU block information in the low-frequency zone. The cache block that has been evicted in the high-frequency zone of the first cache group is determined by executing the eviction policy for the high-frequency zone of the first cache group.

[0115] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0116] Therefore, by using configuration parameters, when a hit occurs, the configuration parameters corresponding to the group are set to 0 at the same time as updating the LRU block information, or before or after updating the LRU block information. This interrupts the scenario where low-frequency areas are continuously eliminated, meaning that the configuration parameters need to be accumulated from 0 again, continuing the strategy of prioritizing the elimination of low-frequency content, thereby preserving high-frequency areas to a great extent.

[0117] In this embodiment, for the hit scenario, it is checked whether the hit Block is in the high-frequency zone. If so, the high-frequency zone LRU block information is updated, the parameter n is set to 0, and the DATA value of the Block is read and output.

[0118] If the hit block is in the low-frequency region, then according to the high-frequency region LRU block information, select a high-frequency data and swap it with the hit data, update the high-frequency region LRU block information and the low-frequency region LRU block information, set the parameter n to 0, and read the DATA value of the hit block and output it.

[0119] For example, see Figure 6 As shown, Figure 6 A flowchart illustrating a caching method provided in another embodiment of this application, namely... Figure 6 This diagram illustrates the process when an access address is "hit" in the cache. Specifically:

[0120] Receive the access address from the preceding module;

[0121] Parse the access address to determine the cache group number and TAG value;

[0122] Read the data of the corresponding cache group, that is, read all blocks of the cache group;

[0123] If Valid=1, compare whether the TAG value is equal to the target value (i.e., the target TAG value);

[0124] If a matching TAG value exists, determine whether the high-frequency region has been hit; if no matching TAG value exists, query the external register.

[0125] If a high-frequency region is hit, update the high-frequency LRU (i.e., the LRU block information of the high-frequency region or the LRU block information of the high-frequency region), set the parameter n to 0, read the DATA value of the hit block and output it;

[0126] If a low-frequency region is hit, the high-frequency data is selected and swapped with the hit data (referring to the data of the hit block) according to the high-frequency LRU, the high-frequency LRU and the low-frequency LRU (i.e., the LRU block information of the low-frequency region or the LRU block information of the low-frequency region) are updated, the parameter n is set to 0, the DATA value of the hit block is read and output.

[0127] Therefore, based on the pseudo-LRU, the cache is divided into high-frequency and low-frequency areas. When a cache hit occurs in the low-frequency area, the hit data is swapped into the high-frequency area, updating both the high-frequency and low-frequency LRUs, and resetting the parameter n to 0. This updates the high-frequency data and prevents high-frequency content from being retained. When a cache hit occurs in the high-frequency area, the high-frequency LRU is updated, and the parameter n is set to 0, further increasing the likelihood that high-frequency content will be retained. This ensures a high hit rate.

[0128] In one possible design, the content of the cache block includes an identifier indicating whether the cache block is valid, data bits, and a memory TAG value indicating the storage address; the execution of the corresponding caching strategy based on the access address and the access data includes:

[0129] Based on the access address, determine the group number of the corresponding second cache group and the first TAG value;

[0130] Read each cache block of the second cache group corresponding to the group number, and determine whether there are invalid cache blocks in the second cache group based on the identifier of each cache block in the second cache group;

[0131] If the second cache group contains invalid cache blocks, the accessed data and the corresponding first TAG value are overwritten to the first cache block, and the first LRU block information in the high-frequency zone or the second LRU block information in the low-frequency zone of the second cache group where the first cache block is located is updated. The identifier corresponding to the first cache block is also updated to indicate a valid identifier. The first cache block is determined from the invalid cache blocks in the second cache group, and the configuration parameters remain unchanged; and / or,

[0132] If there are no invalid cache blocks in the second cache group, then the second cache block of the second cache group is determined according to the configuration parameters and the number of times threshold. The access data and the corresponding first TAG value are overwritten to the second cache block, and the second LRU block information of the low-frequency zone of the second cache group where the second cache block is located is updated or the LRU block information of the second cache group is updated.

[0133] In this embodiment, in the event of a cache miss, a replacement algorithm will be executed when writing back to the cache to determine which block the new data should be written to and to update the LRU block information.

[0134] Specifically, it receives the access address and DATA value (the DATA value is stored in the data bits) from the external memory. The access address here is the same as the access address input by the previous module. The address is parsed to obtain the Cache group number (here referring to the second Cache group; in one scenario, if the access addresses are the same, the identifier of the second Cache group (e.g., the group number) is the same as or similar to the identifier of the first Cache group) and the TAG value (here referring to the first TAG value). Read all blocks in the cache group and check if there is a block with Valid=0. If there is a block with Valid=0, write a new TAG value (the first TAG value) and DATA value (the DATA value corresponding to the access address) directly, and set Valid to 1. Prioritize writing to the high-frequency zone (for example, if there is only one block with Valid=0, use that block as the first cache block; if there are multiple blocks with Valid=0, and one of them is in the high-frequency zone, select the high-frequency zone cache block as the first cache block). Update the LRU block information of the corresponding zone (for example, if the first cache block is in the high-frequency zone, update the high-frequency zone LRU block information; if the first cache block is in the low-frequency zone, update the low-frequency zone LRU block information). The parameter n remains unchanged.

[0135] If no block has a Valid value of 0, then it is determined whether parameter n is greater than or equal to the set threshold (i.e., the number of times threshold). Then, the corresponding caching strategy is used to determine the second cache block. The new TAG value (referring to the first TAG value) and DATA value (referring to the DATA value corresponding to the access address) are written into the second cache block, and the LRU block information of the corresponding area is updated (for example, if the second cache block is in the high-frequency area, the LRU block information in the cache group is updated, that is, the LRU block information in the high-frequency area (referring to the first LRU block information) and the LRU block information in the low-frequency area (referring to the second LRU block information) in the cache group (referring to the second cache group) are updated; if the second cache block is in the low-frequency area, the LRU block information in the low-frequency area is updated) and parameter n is updated.

[0136] Therefore, when a cache miss occurs and data needs to be replaced, low-frequency data is prioritized for elimination. In order to avoid high-frequency data being retained, the system determines whether to replace high-frequency data with low-frequency data based on the parameter n. This ensures that low-frequency data is not eliminated indiscriminately when the preset conditions are not met, thus guaranteeing the effectiveness and timeliness of cache processing.

[0137] In one possible design, the caching strategy further includes a low-frequency region eviction policy; determining the second cache block of the second cache group based on the configuration parameters and the number of occurrences threshold includes:

[0138] When the configuration parameter is greater than or equal to the number of times threshold is reached, the eviction policy for the high-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the high-frequency region of the second cache group, and the eviction policy for the low-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the low-frequency region of the second cache group, and the content of the cache blocks evicted in the high-frequency region of the second cache group is overwritten with the content of the cache blocks evicted in the low-frequency region of the second cache group; wherein, the cache blocks evicted in the high-frequency region of the second cache group are used as the second cache blocks; and / or,

[0139] When the configuration parameter is less than the number of times threshold, the low-frequency area eviction policy for the second cache group is executed to determine the content of the cache blocks that are evicted in the low-frequency area of ​​the second cache group; wherein, the cache blocks that are evicted in the low-frequency area of ​​the second cache group are used as the second cache blocks.

[0140] In this embodiment, it is determined whether parameter n is greater than or equal to a set threshold (here, the number of accesses threshold). If so, the high-frequency region's eviction policy is used to determine the content of cache blocks evicted in the high-frequency region, and the LRU block information for both the high-frequency and low-frequency regions is updated. If parameter n is less than the set threshold, the low-frequency region's eviction policy is used to determine the content of cache blocks evicted in the low-frequency region, and the LRU block information for the low-frequency region is updated. Therefore, by using configuration parameters, even in the event of a cache miss, parameter n can still be updated, thereby improving the hit rate of subsequent accesses.

[0141] In one possible design, the method further includes:

[0142] When the configuration parameter is greater than or equal to the number of accesses threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is set to 0, and the access data is output; and / or,

[0143] When the configuration parameter is less than the number of times threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is incremented by 1, and the access data is output.

[0144] In one possible design, the elimination strategy for the high-frequency region includes:

[0145] Based on the first LRU block information in the high-frequency zone, the contents of the evicted cache blocks are determined from the high-frequency zone.

[0146] In one possible design, the elimination strategy for the low-frequency region includes:

[0147] Based on the second LRU block information of the low-frequency region, the contents of the cache blocks that have been evicted are determined from the low-frequency region.

[0148] In this implementation, if parameter n is greater than or equal to the set threshold, high-frequency data is selected for replacement based on the high-frequency LRU block information (this replacement includes elimination), low-frequency data is selected for replacement based on the low-frequency LRU block information, and the new DATA and TAG are overwritten in the replaced block. The selected high-frequency data is overwritten in the position of the eliminated low-frequency data, the high-frequency LRU block information and the low-frequency LRU block information are updated, parameter n is set to 0, and the DATA value is output.

[0149] If parameter n is less than the set threshold, then the low-frequency area data is selected for replacement based on the low-frequency area LRU block information, and the new DATA and TAG are overwritten to the replaced block. The low-frequency area LRU block information is updated, parameter n is incremented by 1, and the DATA value is output.

[0150] For example, see Figure 7 As shown, Figure 7 A flowchart illustrating a caching method provided in another embodiment of this application, namely... Figure 7 This diagram illustrates the process when an access address is "missed" in the cache. Specifically:

[0151] External memory returns data and access address;

[0152] Determine the Cache group number and TAG value based on the address (here referring to the access address);

[0153] Read the data of the corresponding cache group, that is, read all blocks of the cache group;

[0154] Check if Valid = 0 exists;

[0155] If Valid=0 exists, select (high frequency priority) empty slot for insertion, update DATA, update high frequency / low frequency LRU (update the LRU block information of the region to which the insertion is performed), parameter n, and output DATA;

[0156] If Valid=0 does not exist, check if parameter n is greater than or equal to the threshold (i.e., the number of times threshold);

[0157] If parameter n is greater than or equal to the threshold, select replacement data according to the high-frequency LRU, update DATA, update the high-frequency LRU and low-frequency LRU (because a replacement block needs to be selected in the low-frequency region to carry the replacement data selected from the high-frequency region, the LRU block information in the low-frequency region also needs to be updated), parameter n, and output DATA;

[0158] If parameter n is less than the threshold, select replacement data according to the low-frequency LRU, update DATA, update the low-frequency LRU and parameter n, and output DATA.

[0159] The LRU block is used to record the relative access status of blocks within the group. It is updated when a cache hit occurs or data is written back, and is used to guide which block should be evicted during write-back replacement. The specific update and eviction logic can adopt the traditional pseudo-LRU algorithm (PLRU) or its various improvements, such as the modified pseudo-LRU algorithm (MPLRU). No specific limitation is made here.

[0160] The following section uses PLRU as an example to explain cache processing in detail.

[0161] Example 1 (Handling when a cache "cache hit")

[0162] First, it's essential to understand the update and replacement logic of PLRU. The PLRU algorithm uses a binary tree structure to simulate the LRU mechanism, avoiding the need for counters and comparators. See also... Figure 8 As shown, Figure 8 This is a four-way PLRU binary tree graph, where the LRU value has a total of 3 bits and is stored in one LRU block:

[0163] The 0th bit represents Current AB / CD, indicating that the current path should be selected as A / B or C / D.

[0164] The first bit represents the A / B bit, indicating whether Block A or B is currently selected;

[0165] The second bit represents the C / D bit, indicating whether Block C or D is currently selected;

[0166] These bits are updated according to the current state after data access occurs. Initially, the LRU block is 000, and the update method of these 3 bits is shown in Table 1.

[0167] Table 1 PLRU Update Logic

[0168]

[0169] Specifically:

[0170] 1) If data accesses "Block A" or "Block B", the Current AB / CD bit is set to 1; if accessing "Block C" or "Block D", the Current AB / CD bit is set to 0.

[0171] 2) If data accesses “Block A”, the A / B bits are set to 1; if “Block B” is accessed, the A / B bits are set to 0; when accessing “Block A” or “Block B”, the C / D bits remain unchanged.

[0172] 3) If data accesses “Block C”, the C / D bit is set to 1; if “Block D” is accessed, the C / D bit is set to 0; when accessing “Block C” or “Block D”, the A / B bit remains unchanged.

[0173] In other words, the update method for each bit in a binary tree structure can be summarized as follows: if a memory access operation falls on the left branch of a bit, then that bit is set to 1; if a memory access operation falls on the right branch of a bit, then that bit is set to 0. Based on this idea, a PLRU can be extended to 8-way, 16-way, etc., or it can be degenerated into 2-way.

[0174] Table 2 shows the PLRU eviction logic or eviction strategy (i.e., PLRU algorithm eviction rules), where * indicates that the bit does not need to be considered. That is:

[0175] Table 2 PLRU Algorithm Elimination Rules

[0176]

[0177] Specifically:

[0178] When Current AB / CD is 0 and A / B is 0, it means that "Block A" has not been accessed recently and should be evicted. When Current AB / CD is 1 and C / D is 0, it means that "Block C" has not been accessed recently and should be evicted. The other cases are similar and will not be elaborated here.

[0179] In this embodiment, it is assumed that an 8-way cache is set, with 4 ways in the high-frequency area and 4 ways in the low-frequency area, and the threshold parameter n is set to 2. In the initial state, a certain cache group is filled with data 1, 2, 3, 4, 5, 6, 7, 8.

[0180] The following is a combination of Tables 1 and 2:

[0181] like Figure 9 As shown, Figure 9A schematic diagram of an example of hitting low-frequency content is shown; when accessing data 5, a "hit" occurs, hitting low-frequency data 5. Based on Table 2, data 1 is selected to replace it according to the LRU block information 000 in the high-frequency area. Then, data 5 and data 1 are swapped. Based on Table 1, the high-frequency area LRU information is updated to 110, the low-frequency area LRU is updated to 110, and parameter n is reset to 0.

[0182] like Figure 10 As shown, Figure 10 The diagram illustrates an example of a high-frequency content hit; when accessing data 2 results in a "hit", hitting high-frequency data 2, the LRU information of the high-frequency area is updated to 100 according to the update rule (e.g., based on Table 1), and parameter n is reset to 0.

[0183] Example 2 (Handling when a cache "miss")

[0184] The settings in this embodiment (such as the update logic and replacement logic of PLRU) are the same as in Embodiment 1, and will not be repeated here.

[0185] like Figure 11 As shown, Figure 11 A schematic diagram illustrating an example of eliminating low-frequency content is shown; when accessing data 9 results in a "miss", the probe parameter n is 0, and the low-frequency content is eliminated. Based on Table 2, data 5 is selected for elimination and data 9 is inserted according to the LRU information 000 of the low-frequency area. Based on Table 1, the LRU information of the low-frequency area is updated to 110, and the parameter n is incremented by 1.

[0186] like Figure 12 As shown, Figure 12 The diagram illustrates an example of eliminating high-frequency content. Assume parameter n is 2, meaning low-frequency data has already been eliminated twice consecutively. Accessing data 9 results in a "miss," and parameter n is checked and found to be 2, satisfying the set threshold. High-frequency data needs to be eliminated. Based on Table 2, data 1 is selected for elimination according to the high-frequency LRU information 000, and data 9 is inserted. Then, based on Table 1, the high-frequency LRU value is changed to 110. The eliminated high-frequency data 1 is inserted into the low-frequency region. Based on Table 2, according to the low-frequency LRU information 000, the position of data 5 is inserted. Based on Table 1, the low-frequency LRU is updated to 110, and parameter n is reset to 0.

[0187] For example, a check for data cycle access failure:

[0188] Suppose there is a cache that can store 4 data items, and a dataset containing 5 data items, labeled A to E.

[0189] Set up 2 high-frequency zones + 2 low-frequency zones.

[0190] Now, access these data items repeatedly in a specific order:

[0191] 1. Initial access to A, B, C, D: High-frequency LRU state: 0, Low-frequency LRU state: 0;

[0192] Cache status: A, B, C, D;

[0193] 2. Next, access E. According to the algorithm's elimination criteria, C in the low-frequency zone is eliminated, and the low-frequency LRU status is 1.

[0194] Cache states: A, B, E, D;

[0195] 3. Next, access A, hit the high-frequency region A, high-frequency LRU status: 1;

[0196] Cache states: A, B, E, D;

[0197] 4. Next, accessing B, hitting the high-frequency region B, high-frequency LRU status: 0;

[0198] Cache states: A, B, E, D;

[0199] 5. ...

[0200] Therefore, this application implements a replacement algorithm that is simple in structure, hardware-friendly, and has a high hit rate, which can solve the problem of data loop access failure and is not limited to LRU-friendly data.

[0201] This application applies to pseudo-LRU replacement algorithms for FPGAs, but is not limited to using PLRU as the basic algorithm. Various improved versions of PLRU and other non-pseudo-LRU algorithms can also be used as the basic algorithm of this application.

[0202] Specifically, based on the pseudo-LRU strategy, the cache is divided into high-frequency and low-frequency areas. When a cache hit occurs in the low-frequency area, the hit data is swapped into the high-frequency area; when a cache miss occurs and replacement is needed, low-frequency data is evicted first. This approach adjusts the pseudo-LRU strategy rather than introducing a completely new replacement method. Since the pseudo-LRU strategy has proven effective for most applications in practice, and the corresponding pseudo-LRU algorithm has relatively low hardware implementation costs, this application retains these advantages of the pseudo-LRU strategy to the greatest extent possible.

[0203] Therefore, by partitioning high-frequency and low-frequency data and using the parameter 'n', high-frequency data is protected to a great extent, preventing it from being easily discarded. For example, in a certain access pattern, some high-frequency data may exist over a long period, but then some bursts of data may occur within a short period, causing these high-frequency data to remain unaccessed. Traditional pseudo-LRU schemes only focus on the access pattern within this short period and replace the high-frequency data. However, the technical solution of this application, through the operation of prioritizing the elimination of low-frequency areas and swapping high and low-frequency areas, allows high-frequency data to be retained. In other words, the technical solution of this application can handle not only LRU-friendly data but also LFU-friendly data. Since the technical solution of this application uses a pseudo-LRU algorithm as its basic algorithm, it is more suitable for FPGA implementation and does not require any software intervention.

[0204] To implement the aforementioned cache processing method, this embodiment provides a cache processing device, see [link to documentation]. Figure 13 , Figure 13 This is a schematic diagram of the structure of a cache processing device provided in an embodiment of this application; the cache processing device is applied to an FPGA chip and includes: a judgment module 1301 and a processing module 1302;

[0205] The judgment module 1301 is used to determine whether the accessed data is hit in the cache component based on the access address. The cache component is divided into a high-frequency area and a low-frequency area.

[0206] Processing module 1302 is configured to, upon encountering accessed data, execute a corresponding caching strategy based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone; wherein the caching strategy is configured to indicate, under preset conditions, that the eviction level of the high-frequency zone is lower than the eviction level of the low-frequency zone; and / or,

[0207] The processing module 1302 is used to obtain the access data by querying the external memory when the access data is not hit, and to execute the corresponding caching processing strategy according to the access address and the access data.

[0208] In this embodiment, the judgment module 1301 and the processing module 1302 are used to determine whether the accessed data is hit in the cache component based on the access address. The cache component is divided into a high-frequency zone and a low-frequency zone. Further, if the accessed data is hit, a corresponding cache processing strategy is executed according to whether the accessed data belongs to the high-frequency zone or the low-frequency zone. The cache processing strategy is used to indicate that, under preset conditions, the eviction level of the high-frequency zone is lower than that of the low-frequency zone. Therefore, this application divides the cache component into a high-frequency zone and a low-frequency zone, and based on the design that the eviction level of the high-frequency zone is lower than that of the low-frequency zone, it realizes that by prioritizing the eviction of the low-frequency zone under preset conditions, high-frequency data can still be retained, which greatly protects high-frequency data and prevents it from being easily evicted, thus achieving a high hit rate. At the same time, the design structure is simple and does not require any additional software intervention.

[0209] The cache processing device provided in this embodiment can be used to execute the technical solution of the above-described cache processing method embodiment. Its implementation principle and technical effect are similar, and will not be described again here.

[0210] In one possible design, the caching component includes a cache, which is a multi-way set-associative cache, with one cache set corresponding to one configuration parameter;

[0211] Specifically, for each cache group of the cache component, the configuration parameter is used to determine the number of times the contents of the low-frequency cache blocks within the cache group are continuously evicted.

[0212] In one possible design, the cache processing strategy includes an eviction policy for high-frequency areas; the processing module 1302 is specifically used for:

[0213] When the accessed data is in the high-frequency zone of the corresponding first cache group, update the first least recently used (LRU) block information of the high-frequency zone of the first cache group, and output the accessed data; and / or,

[0214] When the accessed data is in the low-frequency zone of the first cache group, the contents of the cache block in the low-frequency zone of the first cache group where the accessed data is located are swapped with the contents of the cache block that has been evicted in the high-frequency zone of the first cache group, and the LRU block information of the first cache group is updated. The accessed data is then output. The LRU block information includes the first LRU block information of the high-frequency zone and the second LRU block information of the low-frequency zone. The cache block that has been evicted in the high-frequency zone of the first cache group is determined by executing the eviction policy for the high-frequency zone of the first cache group.

[0215] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0216] In one possible design, the device further includes: an update module; the update module is configured to set the configuration parameters corresponding to the first cache group to 0 when updating the first LRU block information of the high-frequency area of ​​the first cache group or updating the LRU block information of the first cache group.

[0217] In one possible design, the content of the cache block includes a memory TAG value indicating whether the cache block is valid, data bits, and storage address; the processing module 1302 is specifically used for:

[0218] Based on the access address, determine the group number of the corresponding second cache group and the first TAG value;

[0219] Read each cache block of the second cache group corresponding to the group number, and determine whether there are invalid cache blocks in the second cache group based on the identifier of each cache block in the second cache group;

[0220] If the second cache group contains invalid cache blocks, the accessed data and the corresponding first TAG value are overwritten to the first cache block, and the first LRU block information in the high-frequency zone or the second LRU block information in the low-frequency zone of the second cache group where the first cache block is located is updated. The identifier corresponding to the first cache block is also updated to indicate a valid identifier. The first cache block is determined from the invalid cache blocks in the second cache group, and the configuration parameters remain unchanged; and / or,

[0221] If there are no invalid cache blocks in the second cache group, then the second cache block of the second cache group is determined according to the configuration parameters and the number of times threshold. The access data and the corresponding first TAG value are overwritten to the second cache block, and the second LRU block information of the low-frequency zone of the second cache group where the second cache block is located is updated or the LRU block information of the second cache group is updated.

[0222] In one possible design, the caching strategy further includes an eviction policy for low-frequency areas; the processing module 1302 is specifically used for:

[0223] When the configuration parameter is greater than or equal to the number of times threshold is reached, the eviction policy for the high-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the high-frequency region of the second cache group, and the eviction policy for the low-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the low-frequency region of the second cache group, and the content of the cache blocks evicted in the high-frequency region of the second cache group is overwritten with the content of the cache blocks evicted in the low-frequency region of the second cache group; wherein, the cache blocks evicted in the high-frequency region of the second cache group are used as the second cache blocks; and / or,

[0224] When the configuration parameter is less than the number of times threshold, the low-frequency area eviction policy for the second cache group is executed to determine the content of the cache blocks that are evicted in the low-frequency area of ​​the second cache group; wherein, the cache blocks that are evicted in the low-frequency area of ​​the second cache group are used as the second cache blocks.

[0225] In one possible design, the processing module 1302 is further configured to:

[0226] When the configuration parameter is greater than or equal to the number of accesses threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is set to 0, and the access data is output; and / or,

[0227] When the configuration parameter is less than the number of times threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is incremented by 1, and the access data is output.

[0228] In one possible design, the processing module 1302 is specifically used for:

[0229] Based on the first LRU block information in the high-frequency zone, the contents of the evicted cache blocks are determined from the high-frequency zone.

[0230] In one possible design, the processing module 1302 is specifically used for:

[0231] Based on the second LRU block information of the low-frequency region, the contents of the cache blocks that have been evicted are determined from the low-frequency region.

[0232] In one possible design, the judgment module 1301 is specifically used for:

[0233] Based on the access address, determine the group number and second TAG value corresponding to the access address in the cache component;

[0234] Read each cache block of the cache group corresponding to the group number, and for a valid cache block, determine whether the accessed data has been hit by comparing the third TAG value and the second TAG value of the valid cache block.

[0235] To implement the above-mentioned caching method, this embodiment provides a caching component, combined with... Figure 1-12 As shown, the cache component includes a high-frequency region and a low-frequency region; the cache component is used to perform the cache processing method described in any one of the first aspects.

[0236] In one possible design, the caching component is a Cache, which is a multi-way set-associative mapped Cache; each Cache set includes multiple Cache blocks, and each Cache set corresponds to a high-frequency region and a low-frequency region, with one high-frequency region corresponding to one first LRU information and one low-frequency region corresponding to one second LRU information. There are multiple Cache blocks in both the high-frequency region and the low-frequency region, and the content of each Cache block includes an identifier for indicating whether it is valid, data bits, and a TAG value.

[0237] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0238] The caching component provided in this embodiment can be used to implement the technical solutions of the above method embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0239] To implement the above-described caching method, this embodiment provides a field-programmable gate array (FPGA) chip, which includes the aforementioned caching component and is used to execute the caching method as described in any of the first aspects.

[0240] In one possible design, the caching component is a Cache, which is a multi-way set-associative mapped Cache; each Cache set includes multiple Cache blocks, and each Cache set corresponds to a high-frequency region and a low-frequency region, with one high-frequency region corresponding to one first LRU information and one low-frequency region corresponding to one second LRU information. There are multiple Cache blocks in both the high-frequency region and the low-frequency region, and the content of each Cache block includes an identifier for indicating whether it is valid, data bits, and a TAG value.

[0241] The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

[0242] The FPGA chip provided in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0243] To implement the methods of the above embodiments, this embodiment provides an electronic device. Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 14 As shown, the electronic device of this embodiment includes: a processor 1401 and a memory 1402 communicatively connected to the processor; wherein, the memory 1402 is used to store computer execution instructions; the processor 1401 is used to execute the computer execution instructions stored in the memory to implement the various steps performed in the above embodiment. For details, please refer to the relevant descriptions in the foregoing method embodiments.

[0244] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0245] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0246] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms. Additionally, the functional modules in the various embodiments of this application may be integrated into one processing unit, or each module may exist physically separately, or two or more modules may be integrated into one unit. The above-mentioned modular units can be implemented in hardware or in the form of hardware plus software functional units.

[0247] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods of the various embodiments of this application. It should be understood that the processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0248] The memory may include high-speed RAM, and may also include non-volatile memory (NVM), such as at least one disk drive, and may also be a USB flash drive, external hard drive, read-only memory, disk, or optical disc. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses in the accompanying drawings are not limited to a single bus or a single type of bus. The aforementioned storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, disk, or optical disc. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0249] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0250] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0251] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A caching method, characterized in that, The method includes: Based on the access address, it is determined whether the accessed data is hit in the cache component, which is divided into a high-frequency area and a low-frequency area; If the accessed data is hit, a corresponding caching strategy is executed based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone; wherein, the caching strategy is used to indicate that, under preset conditions, the eviction level of the high-frequency zone is lower than the eviction level of the low-frequency zone.

2. The method according to claim 1, characterized in that, The caching component includes a cache, which is a multi-way set-associative cache, with one cache set corresponding to one configuration parameter; Specifically, for each cache group of the cache component, the configuration parameter is used to indicate the number of times the contents of the cache blocks in the low-frequency area within the cache group are continuously evicted.

3. The method according to claim 2, characterized in that, The caching strategy includes an eviction policy for high-frequency zones; the step of executing the corresponding caching strategy based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone includes: When the accessed data is in the high-frequency zone of the corresponding first cache group, update the first least recently used (LRU) block information of the high-frequency zone of the first cache group, and output the accessed data; and / or, When the accessed data is in the low-frequency zone of the first cache group, the contents of the cache block in the low-frequency zone of the first cache group where the accessed data is located are swapped with the contents of the cache block that has been evicted in the high-frequency zone of the first cache group, and the LRU block information of the first cache group is updated. The accessed data is then output. The LRU block information includes the first LRU block information of the high-frequency zone and the second LRU block information of the low-frequency zone. The cache block that has been evicted in the high-frequency zone of the first cache group is determined by executing the eviction policy for the high-frequency zone of the first cache group. The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

4. The method according to claim 3, characterized in that, The method further includes: When updating the first LRU block information of the high-frequency area of ​​the first cache group or updating the LRU block information of the first cache group, the configuration parameter corresponding to the first cache group is set to 0.

5. The method according to claim 2, characterized in that, The method further includes: If the access data is not found, the access data is obtained by querying external memory; Based on the access address and the access data, execute the corresponding caching strategy.

6. The method according to claim 5, characterized in that, The contents of the cache block include a flag, data bits, and a memory TAG value indicating whether the cache block is valid; The step of executing a corresponding caching strategy based on the access address and the access data includes: Based on the access address, determine the group number of the corresponding second cache group and the first TAG value; Read each cache block of the second cache group corresponding to the group number, and determine whether there are invalid cache blocks in the second cache group based on the identifier of each cache block in the second cache group; If the second cache group contains invalid cache blocks, the accessed data and the corresponding first TAG value are overwritten to the first cache block, and the first LRU block information in the high-frequency zone or the second LRU block information in the low-frequency zone of the second cache group where the first cache block is located is updated. The identifier corresponding to the first cache block is also updated to indicate a valid identifier. The first cache block is determined from the invalid cache blocks in the second cache group, and the configuration parameters remain unchanged; and / or, If there are no invalid cache blocks in the second cache group, then the second cache block of the second cache group is determined according to the configuration parameters and the number of times threshold. The access data and the corresponding first TAG value are overwritten to the second cache block, and the second LRU block information of the low-frequency zone of the second cache group where the second cache block is located is updated or the LRU block information of the second cache group is updated.

7. The method according to claim 6, characterized in that, The caching strategy also includes a low-frequency area eviction policy; determining the second cache block of the second cache group based on the configuration parameters and the number of occurrences threshold includes: When the configuration parameter is greater than or equal to the number of times threshold is reached, the eviction policy for the high-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the high-frequency region of the second cache group, and the eviction policy for the low-frequency region of the second cache group is executed to determine the content of the cache blocks evicted in the low-frequency region of the second cache group, and the content of the cache blocks evicted in the high-frequency region of the second cache group is overwritten with the content of the cache blocks evicted in the low-frequency region of the second cache group; wherein, the cache blocks evicted in the high-frequency region of the second cache group are used as the second cache blocks; and / or, When the configuration parameter is less than the number of times threshold, the low-frequency area eviction policy for the second cache group is executed to determine the content of the cache blocks that are evicted in the low-frequency area of ​​the second cache group; wherein, the cache blocks that are evicted in the low-frequency area of ​​the second cache group are used as the second cache blocks.

8. The method according to claim 6 or 7, characterized in that, The method further includes: When the configuration parameter is greater than or equal to the number of accesses threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is set to 0, and the access data is output; and / or, When the configuration parameter is less than the number of times threshold, after determining the content of the second cache block, the configuration parameter corresponding to the second cache group is incremented by 1, and the access data is output.

9. The method according to claim 3 or 7, characterized in that, The elimination strategy for the high-frequency region includes: Based on the first LRU block information in the high-frequency zone, the contents of the evicted cache blocks are determined from the high-frequency zone.

10. The method according to claim 7, characterized in that, The elimination strategy for the low-frequency region includes: Based on the second LRU block information of the low-frequency region, the contents of the cache blocks that have been evicted are determined from the low-frequency region.

11. The method according to claim 1 or 2, characterized in that, The step of determining whether the accessed data is found in the cache component based on the access address includes: Based on the access address, determine the group number and second TAG value corresponding to the access address in the cache component; Read each cache block of the cache group corresponding to the group number, and for a valid cache block, determine whether the accessed data has been hit by comparing the third TAG value and the second TAG value of the valid cache block.

12. A cache processing device, characterized in that, The device includes: The judgment module is used to determine whether the accessed data is hit in the cache component based on the access address. The cache component is divided into a high-frequency area and a low-frequency area. The processing module is configured to execute a corresponding caching strategy based on whether the accessed data belongs to the high-frequency zone or the low-frequency zone when the accessed data is hit; wherein the caching strategy is configured to indicate that, under preset conditions, the eviction level of the high-frequency zone is lower than the eviction level of the low-frequency zone.

13. A field-programmable gate array (FPGA) chip, characterized in that, The FPGA chip includes a cache component, and the FPGA chip is used to perform the cache processing method as described in any one of claims 1-11.

14. The FPGA chip according to claim 13, characterized in that, The caching component is a Cache, and the Cache is a multi-way set-associative mapping Cache; each Cache group includes multiple Cache blocks, and each Cache group corresponds to a high-frequency zone and a low-frequency zone respectively. A high-frequency zone corresponds to a first LRU information, and a low-frequency zone corresponds to a second LRU information. There are multiple Cache blocks in the high-frequency zone and multiple Cache blocks in the low-frequency zone. The content of the Cache block includes an identifier for indicating whether it is valid, data bits, and a TAG value. The first LRU block information is used to record the access status of cache blocks in the high-frequency area of ​​the corresponding cache group, and the second LRU block information is used to record the access status of cache blocks in the low-frequency area of ​​the corresponding cache group. The access status is used to determine the cache processing strategy to be executed during the next access.

15. An electronic device comprising: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the cache processing method as described in any one of claims 1-11.

16. A computer program product comprising a computer program that, when executed by a processor, implements the cache processing method of any one of claims 1-11.

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