CXL memory controller, operating method thereof, and CXL memory device

Abstract

A compute fast link (CXL) memory controller includes a data conversion device that receives a failure bitmap and converts the failure bitmap into error correction code (ECC) pre-decode information in symbol units, a read-only memory (ROM) that stores the ECC pre-decode information, and an error correction code (ECC) engine that transmits the error correction code (ECC) pre-decode information to the read-only memory (ROM) that transmits the error correction code (ECC) pre-decode information to the read-only memory (ROM). The error correction code (ECC) engine performs a decoding operation based on the ECC pre-decoding information. The ECC pre-decoding information includes address information indicating an address at which an error occurs, error symbol position information indicating one or more symbols at which an error occurs among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.

Description

Technical Field

[0001] The apparatus, devices, and methods consistent with this disclosure relate to computation fast link (CXL) memory controllers, and more specifically, to CXL memory controllers including data conversion means for converting failed bitmaps, methods of operation thereof, and CXL memory devices. Background Technology

[0002] Devices configured to process data can perform various operations by accessing memory. For example, a device can process data read from memory or write processed data to memory. Due to the performance and functionality required by the system, it can include various devices that communicate with each other via links providing high bandwidth and low latency. The memory included in the system can be shared and accessed by two or more devices. Therefore, the performance of the system can depend on the efficiency of communication between devices, the time spent accessing memory, and the operating speed of each device. Summary of the Invention

[0003] One aspect is to provide a computational fast link (CXL) memory controller, a method for operating the CXL memory controller, and a CXL memory device, wherein the CXL memory controller includes a data conversion device capable of converting a failure bitmap in error correction code (ECC) units or symbol units.

[0004] According to one or more embodiments, a Computational Fast Link (CXL) memory controller is provided, the CXL memory controller comprising: a data conversion device that receives a failure bitmap and converts the failure bitmap into error correction code (ECC) pre-decoding information in symbol units; a read-only memory (ROM) that stores the ECC pre-decoding information; and an ECC engine that performs a decoding operation based on the ECC pre-decoding information. The ECC pre-decoding information includes: address information indicating an address where an error has occurred, error symbol location information indicating at least one symbol among a plurality of symbols corresponding to the address where an error has occurred, and error type information indicating the error type of the at least one symbol.

[0005] According to another aspect of one or more embodiments, a method for operating a computation fast link (CXL) memory controller is provided, the method comprising: receiving a failure bitmap; converting the failure bitmap into error correction code (ECC) pre-decoding information in symbol units; storing the ECC pre-decoding information in a read-only memory (ROM); and performing a decoding operation based on the ECC pre-decoding information. The ECC pre-decoding information includes: address information indicating an address where an error has occurred, error symbol location information indicating at least one symbol among a plurality of symbols corresponding to the address where an error has occurred, and error type information indicating the type of error of the at least one symbol.

[0006] According to another aspect of one or more embodiments, a Computational Fast Link (CXL) memory device is provided, the CXL memory device including a CXL memory and a CXL memory controller, the CXL memory including a first chip and a second chip, the CXL memory controller including: a data conversion device that receives a failure bitmap including error information of each of the first chip and the second chip, and converts the failure bitmap into error correction code (ECC) pre-decoding information in symbol units; a read-only memory (ROM) storing the ECC pre-decoding information; and an ECC engine that receives an access request and performs ECC decoding based on the ECC pre-decoding information when the target address of the access request corresponds to address information. The ECC pre-decoding information includes: address information indicating the address where an error occurred, error symbol location information indicating at least one symbol among a plurality of symbols corresponding to the address where an error occurred, and error type information indicating the error type of the at least one symbol. Attached Figure Description

[0007] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A This is a diagram illustrating an example of an electronic die sorting (EDS) device; Figure 1B This is a diagram showing an example of a failure bitmap; Figure 1C It is a block diagram of a memory system; Figure 2A This is a diagram illustrating an example of a data conversion apparatus according to an embodiment; Figure 2B This is a diagram illustrating an example of error-correcting code (ECC) pre-decoding information according to an embodiment; Figure 3 This is a block diagram of a computing system including a storage system according to an embodiment; Figure 4 This is a block diagram illustrating elements in a computing system according to an embodiment; Figure 5 This is a diagram illustrating an example of a compute fast link (CXL) memory controller according to an embodiment; Figure 6 This is a diagram illustrating an example of ECC pre-decoding information stored in the read-only memory (ROM) of the CXL memory controller according to an embodiment; Figure 7 This is a flowchart illustrating an operation method of a data conversion apparatus according to an embodiment; Figure 8 This is a block diagram of a computing system according to an embodiment; Figure 9 This is a block diagram of a computing system according to an embodiment; Figure 10 This is a block diagram of a computing system according to an embodiment; and Figure 11 This is a block diagram of a data center according to an embodiment. Detailed Implementation

[0008] Various embodiments will be described in detail below with reference to the accompanying drawings. In the following description, although terms such as “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, a “first” element, component, region, layer, or portion described below may be referred to as a “second” element, component, region, layer, or portion.

[0009] Figure 1A This is a diagram illustrating an example of an electronic die sorting (EDS) device, and Figure 1B This is a diagram showing an example of a failure bitmap.

[0010] refer to Figure 1AThe EDS device 10 can perform EDS tests. EDS tests may include at least one test for selecting defective chips (defective chips) from a plurality of chips on a wafer. For example, EDS tests may include electrical testing (ET), wafer burn-in (WBI) testing, pre-laser hot (PLH) testing, and pre-laser cold (PLC) testing. In electrical testing (ET), parameters of the DC voltage and current characteristics of each device (e.g., transistors, resistors, capacitors, diodes, etc.) used in the operation of the chip are tested, and the operability of each device is determined accordingly. In wafer burn-in (WBI) testing, a predetermined temperature may be applied to the wafer, and then AC and DC voltages may be applied to the wafer to detect defective chips. Pre-laser hot (PLH) and pre-laser cold (PLC) testing are used to determine whether each device operates normally at high and low temperatures before laser repair is performed using fuses, or before laser repair is performed by connecting repairable chips to columns or rows with remaining cells.

[0011] EDS device 10 can generate a failure bitmap and store the failure bitmap as failure bitmap information. (See reference) Figure 1B A failure bitmap can be information indicating how many failure bits exist in each of multiple chips on a wafer. For example, refer to... Figure 1B The EDS device 10 can determine the grade based on the number of failure bits detected from each chip and can generate a failure bit map indicating the grade of each chip. Even after laser repair, the EDS device 10 can determine to discard at least one chip containing failure bits of a specific grade or higher. That is, while the EDS device 10 can improve yield and product reliability by performing repair after pre-detecting defective chips, it may be unrelated to the utilization of defective chips containing failure bits.

[0012] Figure 1C This is a block diagram of memory system 1.

[0013] refer to Figure 1CThe memory system 1 may include a memory controller 20 and a memory device 30. The memory system 1 may be referred to as a storage device. In some embodiments, the memory system 1 may refer to an integrated circuit, electronic device or system, smartphone, tablet PC, computer, server, workstation, portable communication terminal, personal digital assistant (PDA), portable multimedia player (PMP), other suitable computing devices, virtual machines, or virtual computing devices thereof. In some embodiments, the memory system 1 may include components of a computing system, such as a graphics card. According to some embodiments, the memory system 1 may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a low-load DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small-size DIMM (SODIMM), etc.

[0014] The memory device 30 may include a memory cell array comprising a plurality of memory cells. The memory cell array may include a plurality of word lines and a plurality of bit lines, and a plurality of memory cells formed at the intersections between the word lines and bit lines. The memory cells of the memory cell array may include volatile memory cells (e.g., dynamic random access memory (DRAM) cells, static RAM (SRAM) cells, etc.), non-volatile memory cells (e.g., flash memory cells, resistive RAM (ReRAM) cells, phase-change RAM (PRAM) cells, magnetic RAM (MRAM) cells), or another type of memory cell.

[0015] In some embodiments, the memory system 1 may be implemented as a memory built into or detachably attached to an electronic device. For example, the memory system 1 may be implemented in various types such as: embedded universal flash memory (UFS) memory device, embedded multimedia card (eMMC), solid-state drive (SSD), UFS memory card, compact flash memory (CF) memory card, secure digital (SD) memory card, micro secure digital (Micro-SD) memory card, mini secure digital (Mini-SD) memory card, extreme digital (xD) memory card, or memory stick.

[0016] The memory controller 20 can respond to write / read requests from the host to read data stored in the memory device 30, or control the memory device 30 to write data into the memory device 30. Specifically, the memory controller 20 can provide the memory device 30 with the address ADDR, the command CMD, and the control signal CTRL, and control the write, read, and erase operations on the memory device 30. Data DATA to be stored in the memory device 30 and data DATA read from the memory device 30 can be transferred between the memory controller 20 and the memory device 30.

[0017] The memory controller 20 may include a decoder 100. The decoder 100 may use error-correcting codes (ECC) to decode data read from the memory device 30. The decoder 100 performs decoding and corrects errors in the read data. That is, the decoder 100 can correct data read from the memory cell array of the memory device 30.

[0018] According to an embodiment, when a failure bit exceeding ECC performance is detected during runtime, decoder 100 can perform post-packaging repair (PPR). For example, when a column or row including a redundant unit is retained in the chip from which the failure bit was detected, decoder 100 can disconnect from the unit where the failure bit occurred and connect to the redundant unit to perform repair.

[0019] According to an embodiment, decoder 100 can enter a decoding mode that does not use the corresponding chip. For example, when the number of failure bits exceeding the ECC performance is detected from a specific chip, decoder 100 can determine not to use the corresponding chip. That is, when a chip outside the ECC performance range is detected, decoder 100 simply does not use the corresponding chip to maintain data reliability, but the determination not to use the corresponding chip is unrelated to the utilization of defective chips including failure bits.

[0020] Figure 2A This is a diagram illustrating an example of a data conversion apparatus 200 according to an embodiment, and Figure 2B This is a diagram illustrating an example of ECC pre-decoding information according to an embodiment.

[0021] refer to Figure 2A The data conversion device 200 can receive a failure bitmap and convert it into ECC pre-decoding information. The failure bitmap can correspond to the information mentioned above. Figure 1B The failure bitmap is described. According to embodiments, the failure bitmap can have various units. For example, in some embodiments, the failure bitmap can have a single bit unit, can have an 8-bit unit for repair, or can have address units, column units, or row units.

[0022] ECC pre-decoding information may include information for ECC decoding performed by the ECC engine. Specifically, ECC pre-decoding information may include address information, error symbol location information, and / or error type information.

[0023] The ECC engine can be based on Reed-Solomon codes. The codewords of the Reed-Solomon code can be decoded based on the location of the erroneous symbol and the error value. Therefore, the data conversion device 200 can convert the received failure bitmap into information about the location of the erroneous symbol for each address for decoding the Reed-Solomon code. That is, the data conversion device 200 can convert the failure bitmap on an ECC processing unit or a symbol unit. Here, the information about the location of the erroneous symbol can be a set of multiple bits. In embodiments, the number of bits can be a predefined number. For example, each bit can indicate which symbol at a specific address has an error.

[0024] In an embodiment, the ECC pre-decoding information may also include information about the error type. For example, the error type may correspond to one of a first error type, a second error type, and a third error type, where the first error type indicates a defect in a single symbol at a specific address, the second error type indicates a defect in a specific row at a specific address, and the third error type indicates a defect in a specific column at a specific address.

[0025] In an embodiment, the value of the first error type, where only one symbol in a particular address is faulty, can be "01". Here, the bits in the error symbol location information can indicate the symbol in a particular address where the error occurred. For example, when the bits of the error symbol location information are "10000000", it can be identified that the error occurred in the first symbol in a particular address.

[0026] like Figure 2B As shown, the value of the second error type, where an error occurs in at least two symbols at a specific address and these at least two symbols correspond to the same row, can be "10". Here, the bits in the error symbol location information can indicate the symbol at the specific address where the error occurred. For example, in the case of error symbol location information "11000000", it can indicate that the error occurred in the first and second symbols.

[0027] An error occurring in at least two symbols at a specific address, and the value for a third error type corresponding to these two symbols in the same column, can be "11". Here, the bits in the error symbol location information can indicate the symbol at the specific address where the error occurred. For example, in the case of error symbol location information "10001000", it could indicate that the error occurred in the first and fifth symbols. ECC engines based on Reed-Solomon codes can improve error correction performance simply by identifying the location of the erroneous symbol for a specific address.

[0028] According to an embodiment, the data conversion device 200 can be implemented in Figure 1A In the EDS device 10. When the data conversion device 200 is implemented in the EDS device 10, the EDS device 10 may include communication circuitry for uploading ECC pre-decoding information to a server (not shown).

[0029] According to an embodiment, the data conversion device 200 can be implemented in a memory controller (not shown). For example, in an embodiment, the data conversion device 200 can be implemented in a CXL controller included in a CXL memory device.

[0030] Figure 3 This is a block diagram of a computing system 300 including a storage system according to an embodiment.

[0031] refer to Figure 3 The computing system 300 may include a host 301, multiple memory devices 302a and 302b, a compute fast link CXL storage 310, and a CXL memory 320.

[0032] In some embodiments, the computing system 300 may be included in a user device (such as a PC, laptop computer, server, media player, digital camera, etc.) or an automotive device (such as a navigation system, black box, vehicle electronics, etc.). In some embodiments, the computing system 300 may include a mobile system, such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, and / or Internet of Things (IoT) device.

[0033] The host 301 can control the overall operation of the computing system 300. In some embodiments, the host 301 can be one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc. In some embodiments, the host 301 may include a single-core processor or a multi-core processor.

[0034] Multiple memory devices 302a and 302b can be used as main memory or system memory in computing system 300. In some embodiments, the multiple memory devices 302a and 302b may each include a DRAM device and may have a dual in-line memory module (DIMM) form factor. However, embodiments are not limited thereto, and in some embodiments, the multiple memory devices 302a and 302b may include non-volatile memory, such as flash memory, PRAM, RRAM, MRAM, etc.

[0035] Multiple memory devices 302a and 302b can communicate directly with host 301 via a Double Data Rate (DDR) interface. In one embodiment, host 301 may include a memory controller configured to control the multiple memory devices 302a and 302b. However, embodiments are not limited thereto, and in some embodiments, the multiple memory devices 302a and 302b may communicate with host 302 via various interfaces.

[0036] CXL storage 310 may include a CXL storage controller 311 and a non-volatile memory (NVM). The CXL storage controller 311 may, under control from the host 301, store data in the NVM or transfer data stored in the NVM to the host 301. In some embodiments, the NVM may be NAND flash memory, but embodiments are not limited thereto.

[0037] CXL memory 320 may include a CXL memory controller 321 and a buffer memory BFM. The CXL memory controller 321 may, under control from the host 301, store data in the buffer memory BFM or transfer data stored in the buffer memory BFM to the host 301. In some embodiments, the buffer memory BFM may include DRAM, but embodiments are not limited thereto.

[0038] In this embodiment, host 301, CXL storage 310, and CXL memory 320 can be configured to share the same interface. For example, host 301, CXL storage 310, and CXL memory 320 can communicate with each other via the CXL interface IF_CXL. In this embodiment, the CXL interface IF_CXL can represent a low-latency, high-bandwidth link that enables various connections between accelerators, memory devices, or various electronic devices by supporting input / output protocol consistency, memory access, and dynamic protocol multiplexing.

[0039] In an embodiment, the CXL storage controller 311 can manage data stored in the non-volatile memory (NVM) using mapping data. The mapping data may include information about the relationship between logical block addresses managed by the host 301 and physical block addresses of the NVM.

[0040] In one embodiment, CXL storage 310 may not include additional buffer memory for storing or managing mapping data. In this case, buffer memory for storing or managing mapping data within CXL storage 320 may be used. In another embodiment, at least some areas of CXL storage 320 may be used as buffer memory for CXL storage 310. In this case, the mapping table managed by CXL storage controller 311 of CXL storage 310 may be stored in CXL storage 320. For example, at least some areas of CXL storage 320 may be allocated by host 301 as buffer memory (exclusive areas of CXL storage 310) for CXL storage 310.

[0041] In this embodiment, CXL storage 310 can access CXL memory 320 via the CXL interface IF_CXL. For example, CXL storage 310 can store or read a mapping table from an allocation area in CXL memory 320. CXL memory 320 can, under control from CXL storage 310, store data (e.g., mapping data) in buffer memory BFM or transfer data (e.g., mapping data) stored in buffer memory BFM to CXL storage 310.

[0042] The CXL storage controller 311 of the CXL storage 310 can communicate with the host 301 and the CXL memory 320 (i.e., the buffer memory) via the CXL interface IF_CXL. In other words, the CXL storage controller 311 of the CXL storage 310 can communicate with the host 301 and the CXL memory 320 via the same type of interface or a common interface, and can use some areas of the CXL memory 320 as a buffer memory.

[0043] In the following text, for ease of description, it is assumed that host 301, CXL storage 310, and CXL memory 320 communicate with each other via the CXL interface IF_CXL. However, the embodiments are not limited to this, and in some embodiments, host 301, CXL storage 310, and CXL memory 320 may communicate with each other based on various computing interfaces such as the GEB-Z protocol, NVLink protocol, Accelerator Cache Coherent Interconnect (CCIX) protocol, Open Coherent Accelerator Processor Interface (CAPI) protocol, etc.

[0044] Figure 4This is a block diagram illustrating the components in a computing system 300 according to an embodiment. In detail, Figure 4 It is shown in detail Figure 3 A block diagram of the components of the computing system 300. (See reference.) Figure 3 describe Figure 4 Furthermore, for the sake of brevity, redundant descriptions can be omitted.

[0045] refer to Figure 4 The computing system 300 may include a CXL switch SW_CXL, a host 301, a CXL storage 310, and a CXL memory 320.

[0046] The CXL switch SW_CXL can be included in the CXL interface IF_CXL. The CXL switch SW_CXL can be configured to relay communication between host 301, CXL storage 310, and CXL memory 320. For example, when host 301 and CXL storage 310 communicate with each other, the CXL switch SW_CXL can be configured to relay information such as requests, data, responses, or signals from host 301 or CXL storage 310 to CXL storage 310 or host 301. Similarly, when host 301 and CXL memory 320 communicate with each other, the CXL switch SW_CXL can be configured to relay information such as requests, data, responses, or signals from host 301 or CXL memory 320 to CXL memory 320 or host 301. When CXL storage 310 and CXL memory 320 communicate with each other, the CXL switch SW_CXL can be configured to transmit information such as requests, data, responses, or signals from CXL storage 310 and CXL memory 320 to CXL memory 320 or CXL storage 310. Host 301 may include CXL host interface circuitry (CXL_HI / F circuitry) 301a. CXL host interface circuitry 301a can communicate with CXL storage 310 or CXL memory 320 via CXL switch SW_CXL.

[0047] CXL storage 310 may include CXL storage controller 311 and non-volatile memory NVM. CXL storage controller 311 may include CXL storage interface circuitry (CXL_S I / F circuitry) 311a, processor 311b, RAM 311c, flash translation layer (FTL) 311d, error correction code (ECC) engine 311e, and NAND interface circuitry 311f.

[0048] The CXL storage interface circuit 311a can be connected to the CXL switch SW_CXL. The CXL storage interface circuit 311a can communicate with the host 301 or the CXL memory 320 via the CXL switch SW_CXL.

[0049] The processor 311b can be configured to control the overall operation of the CXL memory controller 311. The RAM 311c can be used as the working memory or buffer memory of the CXL memory controller 311.

[0050] The FTL 311d can perform various management operations to efficiently utilize the non-volatile memory (NVM). For example, the FTL 311d can perform address translation between logical block addresses managed by the host 301 and physical block addresses used in the NVM based on mapping data (or a mapping table). The FTL 311d can perform bad block management operations on the NVM. The FTL 311d can perform wear leveling operations on the NVM. The FTL 311d can perform garbage collection operations on the NVM.

[0051] In this embodiment, the FTL 311d can be implemented based on software, hardware, firmware, or a combination thereof. When the FTL 311d is implemented as software or firmware, the program code associated with the FTL 311d can be stored in RAM 311c and can be driven by processor 311b. When the FTL 311d is implemented as hardware, the hardware elements forming the various management operations described above can be implemented in the CXL memory controller 311.

[0052] The ECC engine 311e can perform error detection and correction on data stored in non-volatile memory (NVM). For example, the ECC engine 311e can generate parity bits for user data UD to be stored in the NVM, and the generated parity bits can be stored together with the user data UD in the NVM. When reading user data UD from the NVM, the ECC engine 311e can detect and correct errors in the user data UD by using the parity bits read together with the user data UD from the NVM.

[0053] NAND interface circuitry 311f can control non-volatile memory (NVM), allowing data to be stored in or read from the NVM. In embodiments, NAND interface circuitry 311f can be implemented conforming to standards such as a toggle interface or ONFI. For example, the NVM may include multiple NAND flash memory devices, and when NAND interface circuitry 311f is implemented based on a toggle interface, it can communicate with multiple flash memory devices via multiple channels. Multiple NAND flash memory devices can be connected to multiple channels via a multi-channel / multiplexed architecture.

[0054] The non-volatile memory (NVM) can store or output user data UD according to control from the CXL memory controller 311. The non-volatile memory (NVM) can also store or output mapping data MD according to control from the CXL memory controller 311. In an embodiment, the mapping data MD stored in the non-volatile memory (NVM) may include mapping information corresponding to the entire user data UD stored in the non-volatile memory (NVM). The mapping data MD stored in the non-volatile memory (NVM) may be stored in the CXL memory 320 during the initialization operation of the CXL memory 310.

[0055] CXL memory 320 may include CXL memory controller 321 and buffer memory BFM. CXL memory controller 321 may include CXL memory interface circuit (CXL_MI / F circuit) 321a, processor 321b, memory manager 321c and buffer memory interface circuit 321d.

[0056] The CXL memory interface circuit 321a can be connected to the CXL switch SW_CXL. The CXL memory interface circuit 321a can communicate with the host 301 or the CXL storage 310 via the CXL switch SW_CXL.

[0057] Processor 321b can be configured to control the overall operation of CXL memory controller 321. Memory manager 321c can be configured to manage buffer memory (BFM). For example, memory manager 321c can be configured to translate memory addresses (e.g., logical or virtual addresses) accessed by host 301 or CXL memory 310 into physical addresses related to buffer memory (BFM). In embodiments, memory addresses can be addresses used to manage storage regions of CXL memory 320, and can be logical or virtual addresses specified and managed by host 301.

[0058] The buffer memory interface circuit 321d can control the buffer memory BFM, allowing data to be stored in or read from the buffer memory BFM. In embodiments, the buffer memory interface circuit 321d can be implemented to conform to standards such as DDR interface, LPDDR interface, etc.

[0059] The buffer memory (BFM) can store or output stored data according to control from the CXL memory controller 321. In an embodiment, the buffer memory (BFM) can be implemented to store mapping data (MD) used in the CXL memory 310. The mapping data (MD) can be transferred from the CXL memory 310 to the CXL memory 320 during the initialization operation of the computing system 300 or the CXL memory 310.

[0060] As described above, CXL storage 310 can store mapping data MD used to manage non-volatile memory (NVM) in CXL storage 320 connected to it via CXL switch SW_CXL (or CXL interface IF_CXL). Subsequently, when CXL storage 310 performs a read operation based on a request from host 301, CXL storage 310 can read at least some mapping data MD from CXL storage 320 via CXL switch SW_CXL (or CXL interface IF_CXL), and can perform a read operation based on the read mapping data MD. In some embodiments, when CXL storage 310 performs a write operation based on a request from host 301, CXL storage 310 can perform a write operation on the non-volatile memory (NVM) and update the mapping data MD. Here, the updated mapping data MD can be primarily stored in the RAM 311c of the CXL storage controller 311, and the mapping data MD stored in the RAM 311c can be transferred to the buffer memory BFM of the CXL memory 320 via the CXL switch SW_CXL (or CXL interface IF_CXL) to update the mapping data MD stored in the buffer memory BFM.

[0061] In an embodiment, at least some areas in the buffer memory BFM of the CXL memory 320 can be allocated as dedicated areas of the CXL memory 310, and the remaining areas can be used as areas accessible to the host 301.

[0062] In this embodiment, host 301 and CXL storage 310 can communicate with each other via CXL.io, which serves as an input / output protocol. CXL.io can have a non-consistent input / output protocol based on Fast Peripheral Component Interconnect (PCIe). Host 301 and CXL storage 310 can exchange user data or various information with each other using CXL.io.

[0063] In this embodiment, CXL storage 310 and CXL memory 320 can communicate with each other via CXL.mem, which is a memory access protocol. CXL.mem can be a memory access protocol that supports memory access. CXL storage 310 can access some areas of CXL memory 320 (e.g., the area storing mapped data MD or a dedicated area of ​​CXL storage 310) by using CXL.mem.

[0064] In this embodiment, host 301 and CXL memory 320 can communicate with each other using CXL.mem, which is a memory access protocol. Host 301 can access the remaining areas of CXL memory 320 (e.g., areas other than the area storing mapped data MD or areas other than the dedicated area of ​​CXL memory 310) by using CXL.mem.

[0065] The access types mentioned above (CXL.io, CXL.mem, etc.) are examples, and the implementation is not limited to the examples mentioned above.

[0066] In embodiments, CXL storage 310 and CXL memory 320 can be mounted in a physical port (e.g., a PCIe physical port) via a CXL interface. In embodiments, CXL storage 310 and CXL memory 320 can be implemented based on E1.S, E1.L, E3.S, E3.L, and / or PCIe AIC (CEM) form factors. In some embodiments, CXL storage 310 and CXL memory 320 can be implemented based on U.2 form factor, M2 form factor, and / or other various types of PCIe-based form factors and / or other various types of small form factors. CXL storage 310 and CXL memory 320 can support hot-plug functionality, allowing attachment to or removal from a physical port. References are made below. Figure 9 Describe the hot-swap function in detail.

[0067] Figure 5 This is a diagram illustrating an example of a CXL memory controller 500 according to an embodiment, and Figure 6 This is a diagram illustrating an example of ECC pre-decoding information stored in the ROM 520 of the CXL memory controller 500.

[0068] refer to Figure 5 The CXL memory controller 500 may include a data conversion device 510, a ROM 520, and an ECC engine 530. In an embodiment, Figure 5 The CXL memory controller 500 can correspond to Figure 3 and Figure 4 The CXL memory controller 321.

[0069] According to an embodiment, the data conversion device 510 can receive a failure bitmap. In some embodiments, the failure bitmap can be received from a server (not shown). In some embodiments, the failure bitmap can be received by the data conversion device 510 implemented in the CXL memory controller 500, and the failure bitmap can represent information about chips included in the CXL memory (e.g., Figure 3 and Figure 4 The bitmap information is from the buffer memory (BFM), not from the failure bitmap of the overall chip on the wafer.

[0070] The data conversion device 510 can convert the failure bitmap into ECC pre-decoding information and store the ECC pre-decoding information in ROM 520. The data conversion device 510 can convert the failure bitmap by ECC processing unit or symbol unit. Here, the information about the location of the error symbol can be a set of bits. In embodiments, the bits can be predefined. For example, each bit can indicate which symbol at a specific address has an error.

[0071] According to an embodiment, the data conversion device 510 can convert at least some of a plurality of erroneous symbols into ECC pre-decoding information based on a failure bitmap. For example, when the data conversion device 510 converts all symbols, including those with errors in at least one bit, into ECC pre-decoding information based on the failure bitmap and stores the ECC pre-decoding information in the ROM 520, the capacity of the ROM 520 may be insufficient. Therefore, the data conversion device 510 can convert the ECC pre-decoding information based on a threshold number. For example, in an embodiment, the threshold number can be 2. In this case, the data conversion device 510 can convert only symbols with errors in at least two bits into ECC pre-decoding information based on the failure bitmap.

[0072] According to an embodiment, the data conversion device 510 can generate and store data in a CXL memory (e.g., Figure 3 and Figure 4 The buffer memory (BFM) matches the ECC pre-decoding information 600. For example, refer to... Figure 5 and Figure 6 The data conversion device 510 can map error symbol location information to each chip in the CXL memory (e.g., 10 chips forming a memory rank) for a specific address. In an embodiment, each chip forming the CXL memory can be a DDR5x4 chip. A DDR5x4 chip can include four DQ pins for outputting data. The output from each DQ pin includes 16 bits, so a DDR5x4 chip can output 64 bits. As mentioned above, since a symbol has 8 bits, the 64-bit output can correspond to 8 symbols. Therefore, each DDR5x4 chip can map 8 symbols to 8 bits to indicate which symbol has an error. For example, ECC pre-decoding information 600 can combine error symbol location information from each of the first chip (Chip 0) to the tenth chip (Chip 9) corresponding to a specific address. For a specific address, which symbol in the chip has an error can be identified by using 8 bits from each chip, and the magnitude of the error symbol location information for a specific address in the CXL memory can be 80 bits. However, the number of chips forming the CXL memory, the size of the error symbol location information, etc., are not limited to this and can vary depending on the ECC unit, symbol size, codeword size, etc.

[0073] ECC engine 530 can perform ECC decoding based on ECC pre-decoding information stored in ROM 520. For example, ECC engine 530 can perform decoding based on Reed-Solomon codes. According to an embodiment, ECC engine 530 can detect errors during operation. For example, ECC engine 530 can receive access requests (e.g., access requests from a host), and when the target address of the access request corresponds to the address information in the ECC pre-decoding information, it performs ECC decoding based on the ECC pre-decoding information. For example, due to retention degradation in DRAM over time, errors may occur at addresses other than those stored in ROM 520. ECC engine 530 can determine whether the address where the error occurred corresponds to an address in the ECC pre-decoding information. When the address where the error occurred does not correspond to multiple addresses in the ECC pre-decoding information, ECC engine 530 can update ROM 520. Here, ECC engine 530 can add a new address to match the format of the ECC pre-decoding information in ROM 520.

[0074] Figure 7 This is a flowchart illustrating an operation method of a data conversion apparatus according to an embodiment.

[0075] refer to Figure 7 In operation S710, the data conversion device (e.g., Figure 2A Data conversion device 200 and / or Figure 5 The data conversion device 510 can receive a failure bitmap. The failure bitmap can include information about error bits of multiple chips on the wafer. The failure bitmap can have a single bit unit, can have an 8-bit unit for repair, or can have address units, column units, or row units.

[0076] In operation of S720, the data conversion device can generate error symbol location information. For example, the data conversion device can identify which symbol among symbols for a specific address corresponds to the location where an error has occurred, and generate error symbol location information based on the identified symbol. For example, the first chip among multiple chips may have an error at a first address. The data conversion device can identify multiple symbols corresponding to the first address. For example, one symbol can be configured for every 8 bits. The data conversion device can identify which symbol has an error in ECC units or symbol units. In Reed-Solomon code decoding, which symbol has an error (e.g., error location) is identified, and which bit among the bits forming the erroneous symbol is the error bit (e.g., error magnitude) is identified. Based on the error symbol location information, additional errors can be corrected by a decoding method that corrects additional erroneous symbols (e.g., erasure decoding). Identifying which symbol has the erroneous bit is advantageous, and error correction performance can be improved even without information about which bit in the corresponding symbol has an error. For example, when a symbol is identified as having an error (e.g., an error location), the corresponding symbol can be called an erasure symbol, and when no symbol is identified as having an error, it is called an error symbol. The storage of the failure bitmap corresponds to the marking of the erasure symbol. In the case of a Reed-Solomon code with a correction capability of 2, up to two error symbols can be corrected, and in the case of an erasure symbol, up to four symbols can be corrected. In some embodiments, when two erasure symbols are present, one error symbol can be corrected. Therefore, errors can be further corrected using error symbol location information, and error correction performance can be improved.

[0077] The data conversion device can identify which of a plurality of symbols (e.g., 8 symbols corresponding to the first address) has an error based on information about the first chip in the failure bitmap, and can generate error symbol location information. The error symbol location information can include 8 bits, each indicating whether an error has occurred in a symbol in a corresponding sequence. For example, the error symbol location information can be assumed to be "10101010". In this case, the error symbol location information can indicate that an error has occurred in the first, third, fifth, and seventh symbols among the 8 symbols corresponding to the first address. In another example, the error symbol location information can be assumed to be "10000000". In this case, the error symbol location information can indicate that an error has occurred in the first symbol among the 8 symbols corresponding to the first address.

[0078] In operation S730, the data conversion device can generate error type information based on the error symbol location information. For example, in the case of the error symbol location information "10000000", the data conversion device can generate error type information "01", which indicates that only one symbol in the symbols of the first address has an error. In another example, it can be assumed that the error symbol location information is "11000000". In this case, the error symbol location information can indicate that the error occurs in the first and second symbols among the eight symbols corresponding to the first address. When the first and second symbols of the first address have the same row address, the data conversion device can generate error type information "10" indicating a row defect. In the case of the error symbol location information "10101010", when the first, third, fifth, and seventh symbols among the eight symbols corresponding to the first address have the same column address, error type information "11" indicating a column defect can be generated.

[0079] In operation S740, ECC pre-decoding information can be generated by combining a specific address, error symbol location, and error type information. For example, the data conversion device can generate ECC pre-decoding information by combining a first address, error symbol location information indicating at least one symbol among the symbols corresponding to the first address that has an error, and error type information indicating the type of at least one symbol that has an error. According to some embodiments, the data conversion device can generate ECC pre-decoding information regarding multiple chips included in the CXL memory. For example, the data conversion device can combine error symbol location information indicating the error symbol among the symbols corresponding to addresses in each of the multiple chips.

[0080] Figure 8 This is a block diagram of a computing system 800 according to an embodiment. In the following text, for ease of description and brevity, detailed descriptions of the elements provided in the above embodiments are omitted.

[0081] refer to Figure 8 The computing system 800 may include a host 801, multiple memory devices 802a and 802b, a CXL switch SW_CXL, multiple CXL storage devices 810_1 to 810_m, and multiple CXL storage devices 820_1 to 820_n.

[0082] The host 801 can be directly connected to multiple memory devices 802a and 802b. The host 801, multiple CXL storage devices 810_1 to 810_m and multiple CXL storage devices 820_1 to 820_n can be connected to the CXL switch SW_CXL and can communicate with each other via the CXL switch SW_CXL.

[0083] In this embodiment, host 801 can manage multiple CXL storage devices 810_1 to 810_m as a storage cluster and multiple CXL storage devices 820_1 to 820_n as a memory cluster. Host 801 can allocate specific areas of the memory cluster to a storage cluster as dedicated areas (i.e., areas used to store mapped data of the storage cluster). In some embodiments, host 801 can allocate areas from the multiple CXL storage devices 820_1 to 820_n to the multiple CXL storage devices 810_1 to 810_m as dedicated areas respectively.

[0084] Figure 9 This is a block diagram of a computing system 900 according to an embodiment. In the following text, for ease of description and brevity, detailed descriptions of the elements provided in the above embodiments are omitted.

[0085] refer to Figure 9 The computing system 900 may include a host 901, multiple memory devices 902a and 902b, a CXL switch SW_CXL, multiple CXL storage devices 910_1, 910_2 and 910_3, and multiple CXL storage devices 920_1, 920_2 and 920_3.

[0086] The host 901 can be directly connected to multiple memory devices 902a and 902b. The host 901, multiple CXL memories 910_1 and 910_2, and multiple CXL memories 920_1 and 920_2 can be connected to the CXL switch SW_CXL and can communicate with each other via the CXL switch SW_CXL. Similar to the above description, some areas of CXL memories 920_1 and 920_2 can be allocated as dedicated areas for CXL memories 910_1 and 910_2.

[0087] In some embodiments, during the operation of the computing system 900, CXL storage 910_1 and 910_2 or CXL memory 920_1 and 920_2 may be partially released from or removed from the CXL switch SW_CXL (hot-removal). In some embodiments, during the operation of the computing system 900, CXL storage 910_3 or CXL memory 920_3 may be connected to or added to the CXL switch SW_CXL (hot-add). In this case, the host 901 can re-perform memory allocation by performing an initialization operation on the devices connected to the CXL switch SW_CXL via a reset operation or a hot-plug operation. That is, CXL storage and CXL memory can support hot-plugging functionality, and the storage capacity and memory capacity of the computing system can be expanded through various connections.

[0088] Figure 10 This is a block diagram of a computing system 1000 according to an embodiment. In the following text, for ease of description and brevity, detailed descriptions of the elements provided in the above embodiments are omitted.

[0089] refer to Figure 10 The computing system 1000 may include a first CPU 1110, a second CPU 1120, a GPU 1130, an NPU 1140, a CXL switch SW_CXL, a CXL storage 1210, a CXL memory 1220, a PCIe device 1310, and an accelerator (CXL device) 1320.

[0090] The first CPU 1110, the second CPU 1120, the GPU 1130, the NPU 1140, the CXL storage 1210, the CXL memory 1220, the PCIe device 1310, and the accelerator (CXL device) 1320 can be connected to the CXL switch SW_CXL and can communicate with each other via the CXL switch SW_CXL.

[0091] In this embodiment, each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may be as described above. Figures 1A to 9 The described host can be directly connected to a separate storage device.

[0092] In the embodiment, CXL storage 1210 and CXL memory 1220 can respectively correspond to the above reference. Figures 1A to 8 The CXL storage and CXL memory are described, and at least a portion of the CXL memory 1220 can be allocated as a dedicated area of ​​the CXL storage 1210 by one or more of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140. That is, the CXL storage 1210 and the CXL memory 1220 can be used as storage space STR of the computing system 1000.

[0093] In an embodiment, the CXL switch SW_CXL can be connected to a PCIe device 1310 or an accelerator (CXL device) 1320 configured to support various functions, and the PCIe device 1310 or the accelerator 1320 can communicate with each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140, or can access the storage space STR, including the CXL storage 1210 and the CX memory 1220, via the CXL switch SW_CXL.

[0094] In this embodiment, the CXL switch SW_CXL can be connected to an external network or infrastructure and can communicate with an external server via the external network or infrastructure.

[0095] Figure 11 This is a block diagram of a data center 2000 according to an embodiment. The data center 2000 may include a computing system according to an embodiment. In the following text, for ease of description and brevity, detailed descriptions of the elements provided in the above embodiments are omitted.

[0096] refer to Figure 11 Data center 2000 is a facility that collects various types of data and provides services, and may be referred to as a data storage center. Data center 2000 may be a system for operating search engines and databases, and may be a computing system used in companies such as banks or government organizations. Data center 2000 may include multiple application servers, including first application server 2110 to m-th application server 21m0. Data center 2000 may include multiple storage servers, including first storage server 2210 to n-th storage server 22n0. According to embodiments, the number of application servers and the number of storage servers may be selected differently, and in embodiments, the number of application servers may differ from the number of storage servers.

[0097] The structure of the first storage server 2210 is described below. Each of the application servers 2110 to 21m0 and each of the storage servers 2210 to 22n0 may have similar structures to each other, and the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 may communicate with each other via network NT.

[0098] The first storage server 2210 may include a processor 2211, a memory 2212, a switch 2213, a storage device 2215, a CXL memory 2214, and a network interface card (NIC) 2216. The processor 2211 can control the overall operation of the first storage server 2210 and can access the memory 2212 to execute instructions loaded on the memory 2212 or process data. Examples of the memory 2212 may include double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), DIMM, Optane DIMM, and / or non-volatile DIMM (NVMDIMM). The processor 2211 and the memory 2212 may be directly connected to each other, and the number of processors 2211 and the number of memories 2212 included in the storage server 2210 may be selected differently.

[0099] In an embodiment, processor 2211 and memory 2212 may provide a processor-memory pair. In an embodiment, the number of processors 2211 may differ from the number of memories 2212. Processor 2211 may include a single-core processor or a multi-core processor. The above description of storage server 2210 can be similarly applied to each of application servers 2110 to 21m0.

[0100] Switch 2213 can be configured to relay or route communication among various components included in the first storage server 2210. In an embodiment, switch 2213 may include the components referenced above. Figures 1A to 10 The description refers to the CXL switch SW_CXL. In other words, switch 2213 can be implemented based on the CXL protocol.

[0101] CXL memory 2214 can be connected to switch 2213. In embodiments, CXL memory 2214 can be used as a memory expander for processor 2211. In some embodiments, CXL memory 2214 can be allocated as exclusive memory or buffer memory for storage device 2215, as referenced above. Figures 1A to 10 As stated above.

[0102] Storage device 2215 may include CXL interface circuitry CXL_IF, controller CTRL, and NAND flash memory. Storage device 2215 may store or output stored data according to a request from processor 2211. In embodiments, storage device 2215 may include the above-referenced... Figures 1A to 10 The described CXL memory. In an embodiment, storage device 2215 may be allocated at least a portion of the area of ​​CXL memory 2214 as a dedicated area, similar to the referenced... Figures 1A to 10 The description provided allows for the use of a dedicated area as a buffer memory (i.e., the mapped data is stored in CXL memory 2214).

[0103] According to an embodiment, the application servers 2210 to 21m0 may omit the storage device 2215. In some embodiments, the storage server 2210 may include at least one storage device 2215. According to an embodiment, the number of storage devices 2215 included in the storage server 2210 may be selected differently.

[0104] The NIC 2216 can be connected to the CXL switch SW_CXL. The NIC 2216 can communicate with other storage servers 2220 to 22n0 or other application servers 2110 to 21m0 via the network NT.

[0105] In this embodiment, NIC 2216 may include a network interface card, a network adapter, etc. NIC 2216 can be connected to a network NT via a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. NIC 2216 may include internal memory, a digital signal processor (DSP), a host bus interface, etc., and can be connected to processor 2211 and / or switch 2213 via the host bus interface. In this embodiment, NIC 2216 may be integrated with at least one of processor 2211, switch 2213, and storage device 2215.

[0106] In this embodiment, the network NT can be implemented via Fibre Channel (FC), Ethernet, etc. Here, FC is a medium used to transmit data at relatively high speeds and can utilize optical switches that provide high performance / high availability. Depending on the access type of the network NT, the storage servers can be provided as file storage, block storage, or object storage, respectively.

[0107] In embodiments, the network NT may include a storage-specific network, such as a storage area network (SAN). For example, the SAN may include an FC-SAN that can use an FC network and can be implemented according to the FC protocol (FCP). Alternatively, the SAN may include an IP-SAN that can use a Transmission Control Protocol / Internet Protocol (TCP / IP) network and can be implemented according to a Small Computer System Interface (SCSI) protocol over TCP / IP or Internet SCSI (iSCSI). In embodiments, the network NT may include a general-purpose network such as a TCP / IP network. For example, the network NT may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and Network Attached Non-Volatile Memory (NVMe) (NVMe-of).

[0108] In this embodiment, at least one of application servers 2110 to 21m0 can store data requested by a user or client in one of storage servers 2210 to 22n0 via network NT. At least one of application servers 2110 to 21m0 can obtain data requested by a user or client from one of storage servers 2210 to 22n0 via network NT. For example, at least one of application servers 2110 to 21m0 can be implemented as a web server, a database management system (DBMS), etc.

[0109] In this embodiment, at least one of application servers 2110 to 21m0 can access, via network NT, a memory, CXL memory, or storage device included in another application server, or can access via network NT, a memory, CXL memory, or storage device included in storage servers 2210 to 22n0. Thus, at least one of application servers 2110 to 21m0 can perform various operations on data stored in other application servers and / or storage servers. For example, at least one of application servers 2110 to 21m0 can execute instructions for moving or copying data between different application servers and / or storage servers. Here, data can be moved directly or via the storage server's memory or CXL memory from the storage server's storage device to the application server's memory or CXL memory. For security or privacy, data moved over the network can be encrypted.

[0110] In an embodiment, a storage device included in at least one of application servers 2110 to 21m0 and storage servers 2210 to 22n0 can receive allocations of CXL memory included in at least one of application servers 2110 to 21m0 and storage servers 2210 to 22n0 as a dedicated area, and the storage device can use the dedicated area as a buffer memory (i.e., storing mapped data). For example, storage device 2215 included in storage server 2210 can receive allocations of CXL memory included in another storage server (e.g., 22m0) and can access the CXL memory included in the other storage server (e.g., 22m0) via switch 2213 and NIC 2216. In this case, the mapped data of storage device 2215 of the first storage server 2210 can be stored in the CXL memory of the other storage server 22m0. That is, the storage devices and CXL memory of the data center according to the present invention can be connected and implemented in various ways.

[0111] Although various embodiments have been specifically shown and described with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A CXL memory controller, wherein, CXL stands for Compute Fast Link, and the CXL memory controller includes: A data conversion device receives a failure bitmap and converts the failure bitmap into ECC pre-decoding information in symbol units, wherein ECC stands for Error Correction Code. ROM, wherein the ROM stores the ECC pre-decoding information, wherein ROM is a read-only memory; and The ECC engine performs decoding operations based on the ECC pre-decoding information. The ECC pre-decoding information includes: address information indicating the address where the error occurred, error symbol location information indicating at least one symbol among multiple symbols corresponding to the address where the error occurred, and error type information indicating the error type of the at least one symbol.

2. The CXL memory controller according to claim 1, wherein, The failure bitmap includes error information for each of the first and second chips in the CXL memory that are connected to the CXL memory controller, and The error symbol location information includes first error symbol location information and second error symbol location information. The first error symbol location information indicates at least one symbol that has an error in a first address of the first chip, and the second error symbol location information indicates at least one symbol that has an error in a second address of the second chip.

3. The CXL memory controller according to claim 1, wherein, The ECC engine performs the decoding operation based on Reed-Solomon codes.

4. The CXL memory controller according to claim 1, wherein, The error symbol location information includes multiple bits, and the number of these multiple bits is the same as the number of the multiple symbols. The data conversion device is configured to change the bit corresponding to the symbol in which the error occurred among the plurality of symbols to logic high.

5. The CXL memory controller according to claim 1, wherein, The error type information includes one of a first error type, a second error type, and a third error type, wherein the first error type indicates that only one of the plurality of symbols corresponding to the address has an error; The second error type indicates that at least two of the plurality of symbols corresponding to the address have an error and that the at least two symbols have the same row address; The third error type indicates that at least two of the plurality of symbols corresponding to the address have an error and that the at least two symbols have the same column address.

6. The CXL memory controller according to claim 1, wherein, The ECC engine receives an access request, and when the target address of the access request corresponds to the address information, it performs ECC decoding based on the ECC pre-decoding information.

7. The CXL memory controller according to claim 1, wherein, The data conversion device is configured to: Identify the erroneous symbol from the plurality of symbols corresponding to the address, and The error symbol location information is generated, which indicates that among the identified symbols, there are symbols with more than a threshold number of error bits.

8. An operation method for a CXL memory controller, wherein, CXL stands for Computational Fast Link, and the operation method includes: Receive failure bitmap; The failure bitmap is converted into ECC pre-decoding information in symbol units, where ECC stands for error correction code; The ECC pre-decoding information is stored in ROM, where ROM is a read-only memory; and Decoding operations are performed based on the ECC pre-decoding information. The ECC pre-decoding information includes: address information indicating the address where the error occurred, error symbol location information indicating at least one symbol among multiple symbols corresponding to the address where the error occurred, and error type information indicating the error type of the at least one symbol.

9. The operating method according to claim 8, wherein, The failure bitmap includes error information for each of the first and second chips in the CXL memory that are connected to the CXL memory controller, and The error symbol location information includes first error symbol location information and second error symbol location information. The first error symbol location information indicates at least one symbol that has an error in the first address of the first chip, and the second error symbol location information indicates at least one symbol that has an error in the second address of the second chip.

10. The operating method according to claim 8, wherein, The ECC engine performs the decoding operation based on Reed-Solomon codes.

11. The operating method according to claim 8, wherein, The error symbol location information includes multiple bits, and the number of the multiple bits is the same as the number of the multiple symbols; The conversion includes changing the bit corresponding to the symbol that caused the error among the plurality of symbols to logic high.

12. The operating method according to claim 8, wherein, The error type information includes information indicating one of a first error type, a second error type, and a third error type, wherein the first error type indicates that only one of the plurality of symbols corresponding to the address has an error; The second error type indicates that at least two of the plurality of symbols corresponding to the address have an error and that the at least two symbols have the same row address; The third error type indicates that at least two of the plurality of symbols corresponding to the address have an error and that the at least two symbols have the same column address.

13. The operating method according to claim 8, wherein, Performing the decoding operation includes: Access requests are received by the ECC engine; When the target address of the access request corresponds to the address information, ECC decoding is performed based on the ECC pre-decoding information.

14. The operating method according to claim 8, wherein, The conversion includes: Identify the erroneous symbol from the plurality of symbols corresponding to the address; and The error symbol location information is generated, which indicates that among the identified symbols, there are symbols with more than a threshold number of error bits.

15. A CXL memory device, wherein, CXL stands for Compute Fast Link, and the CXL memory device includes: CXL memory, the CXL memory comprising a first chip and a second chip; and CXL memory controller, the CXL memory controller comprising: A data conversion device receives a failure bitmap including error information from each of the first chip and the second chip, and converts the failure bitmap into ECC pre-decoding information in symbol units, where ECC stands for Error Correction Code. ROM, wherein the ROM stores the ECC pre-decoding information, wherein ROM is a read-only memory, and The ECC engine receives access requests and, when the target address of the access request corresponds to address information, performs ECC decoding based on the ECC pre-decoding information. The ECC pre-decoding information includes: address information indicating the address where the error occurred, error symbol location information indicating at least one symbol among a plurality of symbols corresponding to the address where the error occurred, and error type information indicating the error type of the at least one symbol.

16. The CXL memory device according to claim 15, wherein, The error symbol location information includes first error symbol location information and second error symbol location information. The first error symbol location information indicates at least one symbol that has an error in a first address of the first chip, and the second error symbol location information indicates at least one symbol that has an error in a second address of the second chip.

17. The CXL memory device according to claim 15, wherein, The ECC engine performs the ECC decoding based on Reed-Solomon codes.

18. The CXL memory device according to claim 15, wherein, The error symbol location information includes multiple bits, and the number of the multiple bits is the same as the number of the multiple symbols. The data conversion device is configured to change the bit corresponding to the symbol in which the error occurred among the plurality of symbols to logic high.

19. The CXL memory device according to claim 15, wherein, The error type information includes information indicating one of a first error type, a second error type, and a third error type, wherein the first error type indicates that only one of the plurality of symbols corresponding to the address has an error; The second error type indicates that at least two of the plurality of symbols corresponding to the address have an error and that the at least two symbols have the same row address; The third error type indicates that at least two of the plurality of symbols corresponding to the address have an error and that the at least two symbols have the same column address.

20. The CXL memory device according to claim 15, wherein, The data conversion device is configured to: Identify the erroneous symbol from the plurality of symbols corresponding to the address, and The error symbol location information is generated, which indicates that among the identified symbols, there are symbols with more than a threshold number of error bits.

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