Access control method of memory, memory and electronic equipment

Abstract

The embodiment of the invention provides an access control method of a memory, the memory and electronic equipment, and relates to the technical field of memories. The memory supports read interruption, and the access control method of the memory comprises the steps that when a target event is detected and it is determined that the memory is prefetched, an invalid prefetch interruption request is generated, and the target event is used for indicating a missed event needing to be read during bus access; on the basis of the invalid prefetch interruption request, under the condition that the memory interface time sequence constraint is met, the read operation corresponding to prefetch is terminated; and initiating a read request of a new address corresponding to the target event to the memory. According to the method, the memory access performance of the processor can be improved.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory access control method, a memory, and an electronic device. Background Technology

[0002] The memory access latency is much higher than the processor execution speed, which makes the memory access speed a constraint on the processor's execution efficiency.

[0003] In related technologies, prefetching improves the processor's memory access performance. However, in scenarios such as instruction branching, the prefetched data or instructions are invalid, and the next read operation on the memory can only be performed after the prefetching is completed. Summary of the Invention

[0004] This application provides a memory access control method, a memory, and an electronic device to improve the performance of processor accessing memory.

[0005] In a first aspect, this application provides a memory access control method that supports read interruption. The method includes: when a target event is detected and it is determined that the memory is in the process of prefetching, generating an invalid prefetch interruption request, wherein the target event is used to indicate that a required read has been missed during bus access; based on the invalid prefetch interruption request, terminating the read operation corresponding to the prefetch while satisfying the memory interface timing constraints; and initiating a read request for the new address corresponding to the target event in the memory.

[0006] In one possible embodiment, terminating the read operation corresponding to the prefetch, provided that the memory interface timing constraints are met, includes: configuring to immediately terminate the read operation or to terminate the read operation after waiting for a preset number of clock cycles, based on the memory interface timing constraints.

[0007] In one possible embodiment, configuring to immediately terminate a read operation or wait for a preset number of clock cycles to terminate a read operation based on the memory's interface timing constraints includes: detecting the progress of the read operation, the progress including the number of clock cycles elapsed during the read operation; if the number of clock cycles elapsed during the read operation is greater than or equal to a threshold, configuring to wait for a preset number of clock cycles to terminate the read operation based on the memory's interface timing constraints; or, if the number of clock cycles elapsed during the read operation is less than a threshold, configuring to immediately terminate the read operation based on the memory's interface timing constraints.

[0008] In one possible embodiment, the prefetch is an instruction prefetch, and the target event indicates an event that occurs during data bus access where the data cache is missed and the prefetched address is also missed.

[0009] In one possible embodiment, the data cache and the instruction cache are connected via a cache interconnect bus; the memory access control method further includes: determining whether the new address corresponding to the target event hits the instruction cache; if it does, reading the data accessed by the data bus from the instruction cache.

[0010] In one possible embodiment, the prefetch is an instruction prefetch, and the target event indicates an instruction cache miss event that occurs during instruction bus access.

[0011] In one possible embodiment, the instruction cache and the data cache are connected via a cache interconnect bus; the memory access control method further includes: determining whether the new address corresponding to the target event hits the data cache; if it does, then reading the instruction accessed by the instruction bus from the data cache.

[0012] Secondly, this application provides a memory that supports read interruption. Specifically, the memory is used to: perform prefetching; during the prefetching process, based on an invalid prefetch interruption request, terminate the read operation corresponding to the prefetching if the memory interface timing constraints are met. The invalid prefetch interruption request is generated when a target event is detected and it is determined that the memory is performing prefetching. The target event is used to indicate that an event has occurred during bus access where the required read was not hit.

[0013] In one possible embodiment, the memory includes a memory array, an invalid prefetch determination module, and an invalid prefetch interruption module; the memory array is used to store program instructions and data; the invalid prefetch determination module is connected to the memory array and is used to generate an invalid prefetch interruption request when a target event is detected and it is determined that the memory is performing a prefetch; the invalid prefetch interruption module is connected to the invalid prefetch determination module and is used to terminate the read operation corresponding to the prefetch based on the invalid prefetch interruption request, provided that the memory interface timing constraints are met; and to initiate a read request for the new address corresponding to the target event in the memory.

[0014] Thirdly, this application provides an electronic device, including a processor and a memory as described in the second aspect, which is communicatively connected to the processor.

[0015] In this embodiment, when a target event is detected, indicating a missed read during bus access, and it is determined that the memory is currently prefetching, the ongoing prefetch can be identified as an invalid prefetch, thereby accurately generating an invalid prefetch interruption request. By terminating the read operation corresponding to the prefetch based on the invalid prefetch interruption request, while satisfying memory interface timing constraints, the memory can support read interruption while meeting these constraints. This allows for early termination of invalid prefetching without waiting for it to complete, reducing latency. By initiating a read request for the new address corresponding to the target event, the memory can quickly respond to the next read request. Therefore, this embodiment improves the performance of processor accessing memory. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 This is a schematic diagram illustrating the memory access control method, memory, and electronic device according to embodiments of this application applied to a mobile terminal scenario.

[0018] Figure 2 This is a schematic diagram of the system architecture of flash memory in related technologies.

[0019] Figure 3 This is a schematic diagram of the pre-fetched data.

[0020] Figure 4 This is a diagram illustrating a branch jump scenario for an instruction.

[0021] Figure 5 This is a diagram illustrating data access that occurs during instruction prefetching.

[0022] Figure 6 This is a schematic diagram illustrating repeated access to flash memory for both instruction and data access.

[0023] Figure 7 This is a flowchart illustrating a memory access control method according to an embodiment of this application.

[0024] Figure 8 This is a schematic diagram of a memory access control method according to an embodiment of this application.

[0025] Figure 9 This is a schematic diagram of the system architecture of a memory according to an embodiment of this application.

[0026] Figure 10 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application.

[0027] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0030] The memory access control method, memory, and electronic device of this application can be applied to scenarios such as mobile terminals and embedded systems.

[0031] For mobile terminal scenarios, Figure 1 This is a schematic diagram illustrating the memory access control method, memory, and electronic device according to embodiments of this application applied to a mobile terminal scenario.

[0032] like Figure 1 As shown, user 1 interacts with mobile terminal 2 via touchscreen, buttons, or voice commands. For example, application 3 installed on mobile terminal 2 responds to the user's trigger command by having processor 4 access memory 5, read instructions and data from memory 5, and execute them to implement the functions of application 3. Processor 4 and memory 5 are integrated into mobile terminal 2.

[0033] For embedded system scenarios, industrial control equipment based on embedded systems responds to user-triggered industrial control functions by having its processor read relevant instructions and data from memory and execute them to realize industrial control functions.

[0034] Not limited to the above scenarios, since the processor's clock frequency is much higher than the memory's clock frequency, the slower memory access speed becomes a factor that limits the processor's execution efficiency. Figure 1In the example, memory 5 is flash memory (flash), and the following explanation will also use flash memory as an example. Flash memory is a non-volatile memory that is widely used in various chips and electronic devices.

[0035] Figure 2 This is a schematic diagram of the system architecture of flash memory in related technologies. Figure 2 The system employs an architecture that separates data access from instruction access. The data access interface of the flash memory allows the processor to read data from the flash memory via the data bus. The instruction access interface of the flash memory allows the processor to read instructions from the flash memory via the instruction bus. The flash interface controller manages the actual physical access to the memory array. The flash memory array is used to physically store the actual data and instructions. Data read by the processor from the flash memory can be stored in the data cache, and read instructions can be stored in the instruction cache. Both the data cache and the instruction cache can include corresponding caches and buffers. For instruction prefetching, the instruction cache can also include an instruction prefetch buffer. Figure 2 In the memory array, W0 (word0) to W3 (word3) are arranged sequentially to represent a cache line. A cache line is a fixed-length contiguous block of data and is the smallest unit of data transfer between the cache (such as the instruction cache or data cache) and the flash memory. It is usually 16 bytes (4 words). One cache line usually corresponds to one instruction or one data item.

[0036] The following technologies are used to improve the performance of processor accessing flash memory.

[0037] In related technology 1, the bandwidth of flash memory can be increased by expanding the physical interface, allowing the processor to read more bits of data or instructions each time it accesses the flash memory, thereby improving the processor's performance in accessing the flash memory.

[0038] In related technology 2, a data access and instruction access separation architecture is adopted, providing independent buses and interfaces for data access and instruction access. On the one hand, this reduces frequent jumps between reading data and reading instructions from flash memory; on the other hand, it avoids concurrent access conflicts that can occur when data and instruction access are performed synchronously. Based on this data access and instruction access separation architecture, the processor can concurrently access data and instructions in flash memory, thereby improving the processor's flash memory access performance.

[0039] In related technology 3, when the processor is not accessing the flash memory (i.e., the flash memory is in an idle period), prefetching allows the flash memory to read subsequent data or instructions in advance, reducing the time the processor spends waiting for subsequent data or instructions and thus improving the processor's performance in accessing the flash memory. Since the processor typically executes instructions sequentially, prefetching instructions is more efficient. However, processor data access is usually random, so prefetching data is less efficient. The following explanation will use instruction prefetching as an example. Of course, in some cases, the memory can predict data access and thus prefetch data as well.

[0040] Figure 3 This is a schematic diagram for pre-fetching. (For example...) Figure 3 As shown, the bus interface is the communication channel between the processor and the flash memory. Figure 3 The bus interface and its corresponding bus support a 32-bit width, meaning 4 bytes are transferred at a time. Taking instruction prefetching as an example, when the processor reads instruction X from flash memory, if instruction X is stored in the instruction cache via instruction prefetching, the processor reads instruction X directly from the instruction cache. However, if instruction X is not stored in the instruction cache, the processor needs to read instruction X from the flash memory array. Reading instruction X from the instruction cache is faster and has better performance than reading instruction X from the memory array.

[0041] The aforementioned technologies can improve processor performance when accessing flash memory to some extent. However, they still have drawbacks:

[0042] In branch jump scenarios, the instruction being prefetched from flash memory is invalid. Furthermore, due to flash memory timing constraints, flash memory needs to wait for this invalid prefetch to complete before initiating a new instruction access. Each prefetch, for example, involves reading a cache line. Because flash memory waits for invalid prefetches to complete, flash memory access performance is reduced, and processor flash memory access performance needs improvement.

[0043] Specifically, Figure 4 This is a diagram illustrating a branching jump scenario in an instruction. For example... Figure 4 As shown, the processor's clock frequency is 180MHz. The bus command signal indicates that the processor is requesting a read instruction, the bus ready signal indicates whether the processor is ready to receive data, the flash address signal indicates the address to be sent to the flash memory, the flash clock signal is the internal clock of the flash memory, and the flash output is the data returned by the flash memory.

[0044] exist Figure 4In the second clock cycle, the processor initiates a read instruction for address A via the bus. The bus command signal is valid, and the flash memory address signal outputs address A. From the second to the third clock cycle, the bus ready signal is valid, meaning the bus is in a data transfer ready state. In the third clock cycle, the flash memory clock signal generates a pulse, triggering internal address decoding and data reading in the flash memory. Starting from the second clock cycle, after a 30ns access delay, the flash memory outputs the instruction corresponding to address A.

[0045] exist Figure 4 In the eighth clock cycle, the instruction prefetch for reading address A+16 is initiated in advance, and the flash memory address signal outputs address A+16. Starting from the ninth clock cycle, after a 30ns access delay, the flash memory outputs the instruction corresponding to address A+16.

[0046] In the ninth clock cycle, the processor initiates an instruction to read address B via the bus. Address B is not the starting address of the next cache line after address A, meaning a branch jump occurs in the ninth clock cycle.

[0047] The bus command signal becomes valid again, and the flash address signal outputs address B. The instruction to read address B is executed only after the prefetch of address A+16 is completed. The prefetch of address A+16, which begins in the ninth clock cycle, is an invalid prefetch. This invalid prefetch causes a 30ns access delay.

[0048] A is a specific address in the flash memory. A is specifically the starting address of a cache line. A+16 can be understood as the starting address of the next cache line after address A.

[0049] Figure 5 This diagram illustrates data access during instruction prefetching. Generally, processor data access requests are real-time needs and affect instruction execution. For example... Figure 5 As shown, when data access to address B occurs during the instruction prefetching process at address A+16, the data access at address B needs to be executed after the instruction prefetching at address A+16 is completed. This causes a delay in data access to address B, thus affecting the processor's performance in accessing flash memory.

[0050] Figure 6 This diagram illustrates the repeated access to flash memory by instruction and data access. After compilation, a program can be divided into instruction and data segments. There are cases where the same cache line contains both data and instruction segments. In this case, if an architecture that separates data and instruction access is adopted, the same address may be accessed repeatedly because both the data and instruction segments in the same cache line are accessed.

[0051] The memory access control method, memory, and electronic device provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0052] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0053] Figure 7 This is a flowchart illustrating a memory access control method according to an embodiment of this application. The method can be applied to a memory that has access control functionality.

[0054] like Figure 7 As shown, the memory access control method includes steps S110 to S130. This memory supports read interruption.

[0055] S110. When a target event is detected and it is determined that the memory is in the process of prefetching, an invalid prefetch interruption request is generated.

[0056] The target event is used to indicate an event that a required read was missed during a bus access.

[0057] When memory is prefetching, it sends the prefetched instructions or data to the corresponding cache. Since cache access is faster than memory access, the processor can read data or instructions from the cache more efficiently. When a target event is detected, indicating that a bus access to the cache failed and memory is prefetching, it means the data or instructions prefetched by memory do not match the data or instructions accessed by the bus, and the prefetching is invalid. In this case, an invalid prefetch interruption request can be generated for subsequent invalid prefetch interruptions.

[0058] S120. Based on an invalid prefetch interruption request, terminate the read operation corresponding to the prefetch if the memory interface timing constraints are met.

[0059] Memory interface timing can be understood as the time constraints that must be met between the memory's address, data, and control signals. Meeting the memory interface timing requirements can effectively terminate the read operation corresponding to the prefetch. It should be noted that memory support for read interruption can be understood as supporting read interruption while meeting the memory interface timing constraints.

[0060] For example, when the memory is currently prefetching, the memory read enable signal is at an active level. Based on an invalid prefetch interruption request, and provided that the memory interface timing constraints are met, the read operation corresponding to the prefetch can be terminated by controlling the memory read enable signal to be adjusted from an active level to an invalid level.

[0061] S130: Initiate a read request to the memory for the new address corresponding to the target event.

[0062] When a target event is detected, the new address corresponding to the target event can be obtained through the program counter. When the target event indicates bus access, the new address corresponding to the target event can be obtained. By adjusting the read enable signal of the control memory from an invalid level to an active level, the read request for the new address corresponding to the target event can be executed.

[0063] In this embodiment, when a target event is detected, indicating a missed read during bus access, and it is determined that the memory is performing a prefetch, the ongoing prefetch can be identified as an invalid prefetch, thereby accurately generating an invalid prefetch interruption request. By terminating the read operation corresponding to the prefetch based on the invalid prefetch interruption request, while satisfying memory interface timing constraints, the memory can support read interruption while meeting these constraints. This allows for early termination of invalid prefetching without waiting for it to complete, reducing latency. By initiating a read request for the new address corresponding to the target event, the memory can quickly respond to the next read request. Therefore, this embodiment improves the performance of processor accessing memory.

[0064] For example, the read operation corresponding to the termination of prefetching and the read request for the new address corresponding to the target event in the memory can be executed synchronously, and the memory can respond quickly to the next read request synchronously with the read operation corresponding to the termination of prefetching.

[0065] In one possible embodiment, as described in the above embodiments, when a target event is detected and it is determined that the memory is prefetching, the read operation corresponding to the prefetch is invalid, and the data or instructions read through the prefetch read operation may be incorrect. Therefore, the data or instructions read through the prefetch read operation can be discarded instead of being sent to the cache. This avoids invalidation of cache resources and improves cache resource utilization.

[0066] Figure 8 This is a schematic diagram of a memory access control method according to an embodiment of this application.

[0067] like Figure 8 As shown, in the second clock cycle, the processor initiates a read instruction for address A via the bus. The bus command signal is valid, and the flash memory address signal outputs address A. From the second to the third clock cycle, the bus ready signal is valid, meaning the bus is in a data transfer ready state. In the third clock cycle, the flash memory clock signal generates a pulse, triggering internal address decoding and data reading in the flash memory. Starting from the second clock cycle, after a 30ns access delay, the flash memory outputs the instruction corresponding to address A.

[0068] exist Figure 8 In the eighth clock cycle, the instruction prefetch for reading address A+16 is initiated ahead of schedule. The bus command signal and bus ready signal become valid again. The flash address signal outputs address A+16.

[0069] In the ninth clock cycle, the processor initiates a read instruction for address B via the bus. Address B is not the starting address of the next cache line after address A; that is, a branch jump occurs in the ninth clock cycle. The bus command signal and the bus ready signal remain active again.

[0070] By executing the memory access control method of this application embodiment, if a target event is detected in the ninth clock cycle and the memory is prefetching, the read operation corresponding to the prefetch can be terminated and a read request for the new address corresponding to the target event can be initiated to the memory. Figure 8 In the example, the target event is the event that the address B is missed during bus access. The memory is performing an instruction prefetch at address A+16, and the read request for the new address corresponding to the target event is the read request for address B.

[0071] The memory access control method in this application detects a target event triggering an address switch, causing the flash memory address signal to switch to address B in the ninth clock cycle. That is, the read request for the new address corresponding to the target event begins execution from the ninth clock cycle. This allows for the early termination of the instruction prefetch for address A+16. It eliminates the need to wait for the 30ns delay required for the invalid prefetch of address A+16 to complete, thus reducing the latency of the invalid prefetch.

[0072] In one possible embodiment, step S120, terminating the read operation corresponding to the prefetch when the memory interface timing constraints are met, includes: configuring to immediately terminate the read operation or to terminate the read operation after waiting for a preset number of clock cycles, according to the memory interface timing constraints.

[0073] For example, the timing for terminating a read operation with invalid prefetch time can be configured via a configuration register. For instance, the configuration register indicates the configured delay clock cycle number Y. Y is an integer greater than or equal to 0; Y = 0 indicates immediate termination of the read operation.

[0074] For example, relevant personnel can write or modify the delay clock cycle number Y in the configuration register.

[0075] For example, the above Figure 8 An example of configuring to immediately terminate a read operation.

[0076] In this embodiment, the timing of interrupting invalid prefetches can be flexibly configured to adapt to different scenario requirements. For example, different processors and flash memory have different access latencies and bus bandwidths. If the access latency and bus bandwidth utilization caused by an invalid prefetch are significant, the read operation can be terminated immediately. If the access latency and bus bandwidth utilization caused by an invalid prefetch are minor, the read operation can be terminated after waiting for a preset number of clock cycles.

[0077] In one possible embodiment, configuring to immediately terminate a read operation or wait for a preset number of clock cycles to terminate a read operation based on the memory's interface timing constraints includes: detecting the progress of the read operation, the progress including the number of clock cycles elapsed during the read operation; if the number of clock cycles elapsed during the read operation is greater than or equal to a threshold, configuring to wait for a preset number of clock cycles to terminate the read operation based on the memory's interface timing constraints; or, if the number of clock cycles elapsed during the read operation is less than a threshold, configuring to immediately terminate the read operation based on the memory's interface timing constraints.

[0078] For example, when a read operation is initiated (e.g., at the moment the bus sends the address signal), a dedicated counter (synchronized with the processor's clock frequency) is triggered to start incrementing to detect the progress of the read operation.

[0079] The threshold can be determined based on the number of clock cycles of the delay for a single prefetch operation. For example, if the delay for a single prefetch operation is 5 cycles, the threshold can be set to 4.

[0080] If the clock cycles elapsed during a read operation are less than a threshold, it indicates that the read operation has just begun. In this case, the sunk cost of interrupting the read operation is low, and the resource waste is minimal. Conversely, if the clock cycles elapsed during a read operation are greater than or equal to the threshold, it indicates that the read operation may have already been largely completed. In this case, the sunk cost of interrupting the read operation is high, but the resource waste is still relatively low. Therefore, in this embodiment, by configuring the interruption timing of the read operation based on its progress, the resource waste from interrupting the read operation can be reduced.

[0081] In one possible embodiment, the prefetch is an instruction prefetch, and the target event indicates an event that occurs during data bus access where the data cache is missed and the prefetched address is also missed.

[0082] When accessing the data bus, the data cache is not hit and the prefetched address is also not hit. That is, when accessing the data bus, the data access address does not hit the data cache with higher access speed and the data access address is different from the prefetched address.

[0083] Prefetching refers to instruction prefetching. When a target event occurs during data bus access, indicating a data cache miss and a miss at the prefetched address, it means that data access occurs before instruction prefetching is complete. In this embodiment, without waiting for instruction prefetching to complete, invalid instruction prefetching can be terminated while satisfying memory interface timing constraints, and a read request corresponding to the data access can be initiated to the memory. This allows the memory to quickly respond to data accesses with higher real-time requirements and higher priority, thereby improving the processor's memory access performance.

[0084] In one possible embodiment, the data cache and instruction cache are connected via a cache communication bus. The memory access control method further includes: determining whether the new address corresponding to the target event hits the instruction cache; if so, reading the data accessed by the data bus from the instruction cache.

[0085] For example, real-time requirements are higher for data bus access; for instance, the priority of data bus access can be set higher than that of instruction bus access. When the data cache and instruction cache are connected via a cache communication bus, if both data bus and instruction bus access occur simultaneously, the memory can prioritize the data bus access.

[0086] In this embodiment, the data cache and instruction cache are connected via a cache interconnect bus, enabling bidirectional access between the two caches. For example, data bus access can access the instruction cache. If a data bus access misses both the data cache and the prefetched address, it can further determine whether the new address corresponding to the target event hits the instruction cache, allowing data bus access to the instruction cache via the cache interconnect bus. If a hit occurs, the data accessed via the data bus can be directly read from the faster instruction cache, eliminating the need to repeatedly access the instruction cache via the instruction bus. This improves the processor's memory access performance.

[0087] In one possible embodiment, the prefetch is an instruction prefetch, and the target event indicates an instruction cache miss event that occurs during instruction bus access.

[0088] When prefetching is instruction prefetching, and the instructions obtained through instruction prefetching are stored in the prefetch instruction cache, and the instruction cache includes the prefetch instruction cache, a cache miss occurs when accessing the instruction bus. This means that when accessing the data bus, the instruction access address does not hit the instruction cache with higher access speed, and the instruction access address is different from the prefetch address.

[0089] Prefetching refers to instruction prefetching. When a target event indicates a cache miss during instruction bus access, it means that an instruction branch jump occurs before instruction prefetching is complete. In this embodiment, without waiting for instruction prefetching to complete, invalid instruction prefetching can be terminated while meeting memory interface timing constraints, and a read request for the new address corresponding to the target event can be initiated to the memory. This allows the memory to respond quickly to branch instructions, improving processor memory access performance.

[0090] In one possible embodiment, the instruction cache and data cache are connected via a cache communication bus. The memory access control method further includes: determining whether the new address corresponding to the target event hits the data cache; if so, reading the instruction accessed by the instruction bus from the data cache.

[0091] In this embodiment, the data cache and instruction cache are connected via a cache interconnect bus, enabling bidirectional access between the two caches. For example, instruction bus access can access the data cache. If an instruction bus access misses the instruction cache, it can further determine whether the new address corresponding to the target event hits the data cache, allowing instruction bus access to the data cache via the cache interconnect bus. If a hit occurs, the instruction accessed by the instruction bus can be directly read from the faster data cache, eliminating the need to repeatedly access the data cache via the data bus. This improves the processor's memory access performance.

[0092] This application embodiment also provides a memory that supports read interruption. Specifically, the memory is used to: perform prefetching; and during the prefetching process, based on an invalid prefetch interruption request, terminate the read operation corresponding to the prefetch if the memory interface timing constraints are met.

[0093] An invalid prefetch interruption request is generated when a target event is detected and it is determined that memory is in the process of prefetching. The target event is used to indicate that a required read has been missed during bus access.

[0094] Figure 9 This is a schematic diagram of the system architecture of a memory according to an embodiment of this application. Figure 9 The memory shown includes a storage array, an invalid prefetch detection module, and an invalid prefetch interruption module. Figure 9 Let's continue with the example of flash memory.

[0095] Storage arrays are used to store program instructions and data.

[0096] The invalid prefetching detection module is connected to the storage array and is used to generate an invalid prefetching interruption request when a target event is detected and it is determined that the memory is in the process of prefetching.

[0097] The invalid prefetch interruption module is connected to the invalid prefetch judgment module. It is used to terminate the read operation corresponding to the prefetch based on the invalid prefetch interruption request, provided that the memory interface timing constraints are met; and to initiate a read request for the new address corresponding to the target event in the memory.

[0098] The memory in this application embodiment has the same specific technical features as the memory access control method in the above embodiments, and its implementation principle and technical effect are similar. For related explanations, please refer to the relevant content of the memory access control method in the above embodiments, which will not be repeated here.

[0099] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 10 As shown, this application embodiment provides an electronic device including a processor 201 and a memory 202. Optionally, the device further includes a communication component 203. The processor 201, memory 202, and communication component 203 are connected via a bus 204.

[0100] Electronic devices can include mobile terminals, industrial control equipment, etc.

[0101] In the specific implementation process, the memory 202 stores code and data, and the processor 201 runs the code stored in the memory 202.

[0102] The specific implementation process of processor 201 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0103] In the above Figure 10 In the illustrated embodiments, it should be understood that the processor 201 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0104] The memory 202 may include flash memory, high-speed RAM memory, and may also include non-volatile memory (NVM).

[0105] Bus 204 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Bus 204 can be divided into address bus, data bus, control bus, etc. For ease of illustration, the bus 204 in the accompanying drawings of this application is not limited to only one bus or one type of bus.

[0106] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0107] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0108] It should be understood that the division of units / modules in the above embodiments is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, integrated into another system, or some features may be ignored or not executed.

[0109] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0110] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0111] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as flash memory, USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0112] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0113] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0114] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A memory access control method, characterized in that, The memory supports read interruption, and the method includes: When a target event is detected and it is determined that the memory is in the process of prefetching, an invalid prefetch interruption request is generated. The target event is used to indicate that a missed read event has occurred during bus access. Based on the invalid prefetch interruption request, the read operation corresponding to the prefetch is terminated if the memory interface timing constraints are met. Initiate a read request to the memory for the new address corresponding to the target event.

2. The method according to claim 1, characterized in that, The step of terminating the read operation corresponding to the prefetch when the memory interface timing constraints are met includes: Based on the interface timing constraints of the memory, the read operation can be terminated immediately or terminated after waiting for a preset number of clock cycles.

3. The method according to claim 2, characterized in that, The step of configuring the read operation to be terminated immediately or after waiting for a preset number of clock cycles, based on the interface timing constraints of the memory, includes: The operation progress of the read operation is detected, and the operation progress includes the number of clock cycles experienced by the read operation; If the number of clock cycles experienced by the read operation is greater than or equal to a threshold, the read operation is configured to terminate after waiting for a preset number of clock cycles, based on the memory's interface timing constraints; or, if the number of clock cycles experienced by the read operation is less than the threshold, the read operation is configured to terminate immediately, based on the memory's interface timing constraints.

4. The method according to any one of claims 1-3, characterized in that, The prefetch is an instruction prefetch, and the target event indicates an event that occurs during data bus access where the data cache is not hit and the prefetched address is not hit.

5. The method according to claim 4, characterized in that, The data cache and instruction cache are connected via a cache interconnection bus; the method further includes: Determine whether the new address corresponding to the target event hits the instruction cache; if it does, read the data accessed by the data bus from the instruction cache.

6. The method according to any one of claims 1-3, characterized in that, The prefetch is instruction prefetch, and the target event indicates an instruction cache miss event that occurs during instruction bus access.

7. The method according to claim 6, characterized in that, The instruction cache and data cache are connected via a cache interconnection bus; the method further includes: Determine whether the new address corresponding to the target event hits the data cache; if it does, read the instruction accessed by the instruction bus from the data cache.

8. A memory, characterized in that, The memory supports read interruption, and the memory is specifically used for: Perform prefetching; During the prefetching process, based on an invalid prefetch interruption request, the read operation corresponding to the prefetch is terminated if the memory interface timing constraints are met. The invalid prefetch interruption request is generated when a target event is detected and it is determined that the memory is in the process of prefetching. The target event is used to indicate that a missed read event has occurred during bus access.

9. The memory according to claim 8, characterized in that, The memory includes a storage array, an invalid prefetch judgment module, and an invalid prefetch interruption module; The storage array is used to store program instructions and data; The invalid prefetch determination module is connected to the storage array and is used to generate the invalid prefetch interruption request when the target event is detected and it is determined that the memory is in the process of prefetching. The invalid prefetch interruption module is connected to the invalid prefetch judgment module and is used to terminate the read operation corresponding to the prefetch based on the invalid prefetch interruption request, provided that the memory interface timing constraints are met. And initiate a read request to the memory for the new address corresponding to the target event.

10. An electronic device, characterized in that, It includes a processor and a memory as described in claim 8 or 9 that is communicatively connected to the processor.

Images