Method for generating conductive area of circuit board

Abstract

The invention discloses a circuit board conductive area generation method, and relates to the technical field of circuit board design, and the method comprises the steps: recognizing a target circuit board of a to-be-generated conductive area, obtaining original design data, extracting via hole parameter characteristics, and obtaining parameter data according to the via hole parameter characteristics; based on the parameter data, determining a via hole cluster of the target circuit board, determining a first via hole, a distribution density and a correction coefficient of the distribution density according to cluster characteristics of the via hole cluster, and calculating an alpha value of the via hole cluster to construct an initial boundary of the via hole cluster; and performing iterative optimization on the initial boundary by using the multi-objective optimization model, outputting a final boundary, and generating a conductive region. The technical problems that manual circuit board design is high in complexity, low in efficiency and unstable in result and automatic design is not optimized are solved, and the technical effects that efficiency and intelligence are achieved, the workload is reduced, the period is shortened, the characteristics of high consistency, high debuggeability and the like are achieved, multiple processes and product lines can be adapted, and enterprise requirements are met are achieved.

Description

Technical Field

[0001] This application relates to the field of circuit board design technology, and in particular to a method for generating conductive areas on a circuit board. Background Technology

[0002] In related technologies, circuit board design can rely on designers' rich experience to carry out manual design, such as manually planning the distribution, shape, connection method and spacing of copper foil to optimize electrical performance, enhance heat dissipation, improve anti-interference and ensure manufacturability; or it can rely on pre-set design rules, such as the minimum size, maximum number and spacing of vias, for automated design.

[0003] However, in related technologies, manual design is slow and inefficient due to the complexity of circuit boards, making it difficult to meet the needs of rapid iteration and high-efficiency production in the modern electronics industry. Furthermore, differences in the experience levels of different designers may lead to significant variations in the layout of conductive areas, making it difficult to guarantee the consistency and stability of the design results, thus affecting the overall reliability of the circuit board performance. On the other hand, automated design often fails to fully consider the mutual influence between vias and the optimization of the overall layout, which may lead to problems such as signal interference and uneven heat dissipation in practical applications, and urgently needs improvement. Summary of the Invention

[0004] This application provides a method for generating conductive areas on a circuit board, which at least solves the problems in related technologies. Manually designing circuit boards is slow and inefficient due to increased complexity, making it difficult to meet the needs of the modern electronics industry. Furthermore, the design results vary greatly among experienced personnel, leading to unstable results and affecting performance reliability. Automated design does not fully consider the impact of vias and layout optimization, resulting in problems such as signal interference and uneven heat dissipation in the actual application of conductive areas.

[0005] This application provides a method for generating a conductive region on a circuit board, comprising the following steps: identifying a target circuit board for which a conductive region is to be generated, obtaining the original design data of the target circuit board, and extracting at least one via parameter feature of the target circuit board from the original design data, so as to obtain parameter data of at least some vias based on the at least one via parameter feature; determining a via cluster of the target circuit board based on the parameter data, and determining a first via, a distribution density, and a correction coefficient of the distribution density in the via cluster according to the cluster features of the via cluster, and calculating the alpha value of the via cluster based on the aperture value of the first via, the distribution density, and the correction coefficient, so as to construct an initial boundary of the via cluster based on the alpha value and the cluster features; inputting the initial boundary into a pre-constructed multi-objective optimization model, iteratively optimizing the initial boundary to output the final boundary of the conductive region to be generated, and generating the conductive region of the target circuit board according to the final boundary.

[0006] This application also provides an apparatus for generating conductive regions on a circuit board, comprising: a first generation module, configured to identify a target circuit board for which conductive regions are to be generated, obtain original design data of the target circuit board, and extract at least one via parameter feature of the target circuit board from the original design data, so as to obtain parameter data of at least some vias based on the at least one via parameter feature; a first construction module, configured to determine a via cluster of the target circuit board based on the parameter data, and determine a first via, a distribution density, and a correction coefficient of the distribution density in the via cluster according to the cluster features of the via cluster, and calculate the alpha value of the via cluster based on the aperture value of the first via, the distribution density, and the correction coefficient, so as to construct an initial boundary of the via cluster based on the alpha value and the cluster features; and a second generation module, configured to input the initial boundary into a pre-constructed multi-objective optimization model, perform iterative optimization on the initial boundary to output the final boundary of the conductive regions to be generated, and generate the conductive regions of the target circuit board according to the final boundary.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described methods for generating conductive areas on a circuit board.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described methods for generating conductive areas on a circuit board.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described methods for generating conductive regions on a circuit board.

[0010] This application allows for the acquisition of the original design data of the target circuit board from which the conductive area to be generated, extraction of corresponding via parameter features, and thus obtaining parameter data for at least some vias. This enables the determination of via clusters, and the calculation of alpha values ​​based on the first vias meeting certain aperture conditions, their distribution density, and corresponding correction coefficients. This constructs an initial boundary, which is then iteratively optimized using a pre-built multi-objective optimization model to output the final boundary of the conductive area to be generated, thereby generating the conductive area of ​​the target circuit board. Therefore, it addresses the challenges of manual circuit board design, which suffers from increased complexity leading to slower drawing speeds and lower efficiency, failing to meet the demands of the modern electronics industry. Furthermore, it addresses the significant design discrepancies among experienced personnel, resulting in unstable outcomes and impacting performance reliability. It also addresses the issue of automated design failing to adequately consider via influence and layout optimization, leading to signal interference and uneven heat dissipation in practical applications of the conductive area. This approach achieves high efficiency and intelligence, significantly reducing manual workload and shortening the design cycle. It offers high consistency, strong debuggability, and good scalability, supports custom rules, and allows for dynamic maintenance. It enables rapid adaptation to different process and product line requirements, aligning with enterprise needs. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating a method for generating conductive regions on a circuit board, as provided in this application embodiment; Figure 2 This is a flowchart illustrating the determination of via clusters on a printed circuit board according to one embodiment of this application; Figure 3 This is a flowchart illustrating the construction of an initial boundary according to an embodiment of this application; Figure 4 This is a flowchart for calculating the area of ​​the minimum bounding rectangle according to an embodiment of this application; Figure 5 A flowchart illustrating the calculation of the PSO (Particle Swarm Optimization) algorithm according to an embodiment of this application; Figure 6 This is a block diagram illustrating the final boundary generated according to an embodiment of this application; Figure 7 This is a flowchart illustrating the working principle of a method for generating conductive regions on a circuit board according to an embodiment of this application; Figure 8 This is a block diagram of a circuit board conductive region generation apparatus provided according to an embodiment of this application.

[0013] Figure label: Among them, 10 is a device for generating conductive areas on a circuit board; 100 is a first generation module; 200 is a first construction module; and 300 is a second generation module. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The embodiments of this application provide a method for generating conductive regions on a circuit board. The method is described in detail below in conjunction with the execution flow of the method for generating conductive regions on a circuit board.

[0018] Specifically, Figure 1 This is a flowchart of a method for generating conductive areas on a circuit board according to an embodiment of this application.

[0019] like Figure 1 As shown, the method for generating the conductive area of ​​the circuit board includes the following steps: In step S101, the target circuit board for which the conductive area is to be generated is identified to obtain the original design data of the target circuit board, and at least one via parameter feature of the target circuit board is extracted from the original design data to obtain parameter data of at least some vias based on at least one via parameter feature.

[0020] It is understood that, in the embodiments of this application, the target circuit board can be understood as a specific circuit board for analysis or processing, which may include, but is not limited to, printed circuit boards, flexible circuit boards, rigid-flex boards, ceramic circuit boards, metal-based circuit boards, etc., and this application does not impose specific limitations.

[0021] The original design data may include, but is not limited to, circuit layout, component positions, trace widths, and stack-up structures, and this application does not impose specific limitations.

[0022] Via parameter characteristics may include, but are not limited to, the geometric parameters of the via, such as center coordinates, aperture, and wall thickness, etc., which are not specifically limited in this application; network attribute characteristics, such as the network name (e.g., 3.3 volt power supply voltage, ground / ground terminal, USB (Universal Serial Bus) signal), signal type (high speed, power, ground, etc., which are not specifically limited in this application); spatial distribution characteristics, such as the distance between different vias, etc., which can be set by those skilled in the art according to the actual situation, and are not specifically limited in this application.

[0023] As one possible approach, embodiments of this application can first identify the target circuit board for which conductive areas are to be generated and obtain the original design data of the target circuit board. Then, using the original design data, the via parameter features of the target circuit board can be extracted, and the parameter data of at least some vias can be obtained based on the via parameter features.

[0024] For example, in this application embodiment, the original design data of the printed circuit board can be read by calling the API (Application Programming Interface) interface between the printed circuit board and the EDA (Electronic Design Automation) tool, and the via parameter characteristics such as center coordinates, hole diameter, hole wall thickness, network name, signal type, and distance between different vias can be extracted. In this way, the center coordinates (x, y), hole diameter d, hole wall thickness t, network name, signal type, and distance between different vias of each via can be obtained.

[0025] In step S102, based on the parameter data, the via cluster of the target circuit board is determined, and the first via, distribution density, and correction coefficient of the distribution density in the via cluster that meet the preset aperture condition are determined according to the cluster characteristics of the via cluster. Based on the aperture value, distribution density, and correction coefficient of the first via, the alpha value of the via cluster is calculated, so as to construct the initial boundary of the via cluster based on the alpha value and the cluster characteristics.

[0026] It is understood that the preset aperture condition can be interpreted as selecting the via with the largest aperture in each via cluster. The specific setting can be made by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0027] The distribution density in this embodiment can be calculated based on the number of vias in the via cluster and the area of ​​the minimum circumscribed rectangle. The calculation formula can be, but is not limited to, expressed as: , in, For the number of vias, Let be the area of ​​the minimum bounding rectangle of the cluster. The average distribution density of the cluster, in units of: .

[0028] Furthermore, in this embodiment, the corresponding correction coefficient can be determined based on the distribution density. The higher the distribution density, the larger the correction coefficient value. Generally, the value is 0.1-0.3, and this application does not impose specific limitations, thereby avoiding excessive shrinkage of the boundary of dense vias.

[0029] Furthermore, in embodiments of this application, the alpha value can be calculated based on the aperture value, distribution density, and correction coefficient of the first via. The calculation formula can be, but is not limited to, expressed as: , in, The aperture value of the first via, in mm, is the aperture value of the largest via in the via cluster, ensuring that the boundary can cover the edge of the largest via; For correction factor, This is the alpha value.

[0030] It should be noted that in the embodiments of this application, the alpha value is a key parameter for controlling the initial boundary shape: if the alpha value is too small, the boundary will be too fragmented, such as jagged edges or depressions, and a closed copper layer cannot be formed; while if the alpha value is too large, the boundary will be excessively expanded, wasting wiring space.

[0031] For example, in an embodiment of this application, if the maximum aperture value within a certain via cluster is... , , ,but ,Pick Based on this, the alpha value can be calculated. .

[0032] In some embodiments, the present application embodiments can determine the via cluster of the target circuit board based on parameter data. Then, the present application embodiments can determine the first via that meets the preset aperture condition, the distribution density, and the correction coefficient of the distribution density in the via cluster based on the via cluster, thereby calculating the corresponding alpha value, and combining the alpha value with the cluster characteristics to construct the initial boundary of the via cluster.

[0033] Optionally, in one embodiment of this application, determining the via cluster of the target circuit board based on parameter data includes: determining the signal type value, center coordinate value, aperture value, and wall thickness value of the corresponding via based on the parameter data; calculating the distance value between different vias with the same signal type value based on the signal type value, center coordinate value, aperture value, and wall thickness value; and, in response to a distance value being less than a preset threshold, dividing the vias corresponding to the distance value into the same via cluster to determine the via cluster.

[0034] In some embodiments, the via clusters of a target circuit board can be determined based on parameter data.

[0035] For example, in the embodiments of this application, the content of the printed circuit board via cluster is determined as follows: Figure 2 As shown, the main contents include: Step S201: Analyze the original design data of the printed circuit board.

[0036] Step S202: Call the EDA tool API interface to extract via parameter features.

[0037] Step S203: Obtain the parameter data of the via.

[0038] In the embodiments of this application, the parameter data may include, but is not limited to, center coordinate values, aperture values, aperture wall thickness values, network names, signal type values, etc., and this application does not impose specific limitations.

[0039] Step S204: Calculate the preset threshold of the clustering parameters of the DBSCAN algorithm.

[0040] In this embodiment of the application, a preset threshold for the DBSCAN (Density-Based Spatial Clustering of Applications with Noise) algorithm can be calculated, and its calculation formula can be, but is not limited to, expressed as: , in, Indicates the preset threshold. The average aperture (usually 0.5-2 mm, but this application does not impose a specific limit). The parameter is typically 3-5, but this application does not impose any specific restrictions.

[0041] In addition, the preset threshold can be set by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0042] Step S205: Execute the DBSCAN algorithm.

[0043] In this embodiment, the via cluster is expanded by randomly selecting core points and searching for neighboring vias.

[0044] It can be understood that, for vias with the same signal type value, the embodiments of this application can divide vias with a distance value less than a preset threshold into the same via cluster.

[0045] In this application embodiment, if the via cluster is invalid, it can be handled according to... readjust the method And re-clustering, this application does not impose specific restrictions.

[0046] Step S206: Obtain cluster characteristics based on parameter data.

[0047] The cluster characteristics may include, but are not limited to, the number of vias, distribution density, average aperture, geometric center, cluster number, signal type, etc., as well as the center coordinates, aperture, wall thickness, and network name of each via in the cluster. This application does not impose specific restrictions.

[0048] Step S207: Check for the existence of isolated vias.

[0049] In this embodiment of the application, if there is a via with a distance value greater than or equal to the distance threshold, it is determined that there is an isolated via, and step S208 is executed; otherwise, step S209 is executed.

[0050] Step S208: Merge isolated vias into the nearest via cluster.

[0051] Step S209: Output via cluster.

[0052] In this embodiment, the corresponding via cluster can be obtained according to the signal type value, and the number of vias, average aperture and geometric center of each cluster can be calculated. The extracted data is stored in a structured table as shown in Table 1. Table 1 is a schematic table of via clusters provided according to an embodiment of this application.

[0053] Table 1

[0054] In addition, this application embodiment also supports users to manually select and divide via clusters through the interface. The specific settings can be made by those skilled in the art according to the actual situation, and this application does not impose any specific limitations.

[0055] This application embodiment determines the signal type value, center coordinate value, aperture value, and wall thickness value of the corresponding via through parameter data, thereby calculating the distance value between different vias with the same signal type value, and determining the via cluster in response to the distance value being less than a preset threshold. This can accurately identify associated vias and lay a solid foundation for subsequent layout optimization and improvement of circuit board performance.

[0056] Optionally, in one embodiment of this application, the initial boundary of the via cluster is constructed based on the alpha value and cluster characteristics, including: collecting the initial edge points of all vias in the via cluster based on the cluster characteristics; preprocessing the initial edge points to obtain edge points that meet preset processing conditions; performing triangulation based on the edge points to generate target triangles with the edge points as vertices; and constructing the initial boundary in response to the edge values ​​of the target triangle being greater than or equal to the alpha value.

[0057] It is understood that the preset processing conditions may include, but are not limited to, deduplication conditions and expansion conditions, and can be set by those skilled in the art according to the actual situation. This application does not impose specific restrictions.

[0058] In some embodiments, this application can use cluster features to collect the initial edge points of all vias in the via cluster, and preprocess the initial edge points to obtain edge points that meet preset processing conditions. Then, by performing triangulation, a target triangle with the edge points as vertices is generated, and in response to the edge value of the target triangle being greater than the alpha value, an initial boundary is constructed.

[0059] For example, the content of constructing the initial boundary in the embodiments of this application is as follows: Figure 3 As shown, the main content is as follows: Step S301: Collect initial edge points.

[0060] In this embodiment of the application, each via can be... , Let be the diameter, where Number the vias, with the center of each via as the origin, and follow the sequence. Eight initial edge points are selected at intervals. The coordinate parameters of the initial edge points can be: the radius of the via. ;angle ,in, Then, a coordinate system transformation is performed to obtain the coordinates in the global coordinate system, which can be, but is not limited to, identified as: , , For example, for diameter , ,center The coordinates of the 8 initial edge points of the via are: .

[0061] Step S302: Preprocess the initial edge points to obtain edge points that meet the preset processing conditions.

[0062] In this embodiment, when the spacing between adjacent vias is too small, initial edge points may overlap (distance ≤ 0.01mm). In this case, this embodiment can perform deduplication and filtering. The main steps are as follows: First, calculate the Euclidean distance of all initial edge points. If the distance between two points is ≤ 0.01mm, retain one of the points. Then, remove edge points that exceed the effective area of ​​the printed circuit board (such as points less than 0.5mm from the board edge) to prevent subsequent boundaries from exceeding the design range, thereby obtaining a deduplicated set of initial edge points. ,in, The total number of points is usually the number of vias × 8, but this application does not impose a specific limit.

[0063] Furthermore, in the embodiments of this application, when performing Deloni triangulation, since Deloni triangulation is an algorithm that transforms a discrete set of points into a non-overlapping triangular mesh, its characteristic is to maximize the minimum angle. To avoid the formation of elongated triangles and to provide a stable topological structure for subsequent boundary extraction, the initial edge point set can be expanded. This avoids incomplete triangles when edge points are located at the triangulation edge. The expansion can be as follows: in the initial edge point set... Four virtual points (coordinates of vertices extending 5mm outward from the minimum bounding rectangle of the cluster) are added to the outer perimeter to form an expanded point set. This allows us to obtain edge points that meet the preset processing conditions.

[0064] Step S303: Calculate the alpha value.

[0065] The embodiments of this application can be implemented according to... The alpha value is calculated in this way.

[0066] Step S304: Perform triangulation and output the target triangle.

[0067] In this embodiment, a convex hull computation library or a generic geometry library can be used to implement Deloni triangulation and output a list of initial target triangles. ,in, Let be the total number of target triangles, and each initial target triangle is composed of . The initial target triangle is composed of three edge points. After deleting the initial target triangle containing virtual points (to avoid the boundary being affected by virtual points), a list of target triangles consisting only of edge points is obtained. And the edge values ​​of each target triangle in T' are calculated using Euclidean distance, which can be expressed as: .

[0068] It should be noted that the Convex Hull Computation Library is an open-source computational geometry library focused on efficiently constructing the convex hull of multidimensional datasets. It also supports geometric computation tasks such as Deloni triangulation. Its core algorithm is to quickly divide the point set through a divide-and-conquer strategy and gradually expand the convex hull boundary. On the other hand, the Generic Geometry Library focuses on solving geometric problems. This library defines geometric concepts, primitives (such as points, lines, polygons, etc., which are not specifically limited in this application) and algorithms (such as intersection, union, distance calculation, etc., which are not specifically limited in this application), and supports spatial analysis and geometric operations.

[0069] Step S305: Filter target triangles whose edge values ​​are greater than or equal to the alpha value.

[0070] In this embodiment, edges with edge values ​​greater than or equal to the alpha value can be retained, while edges with edge values ​​less than the alpha value can be deleted. This allows for the retention of only continuous edges that can surround the via cluster, eliminating short edges formed by localized density of vias and avoiding boundary depressions.

[0071] Step S306: Construct a closed boundary.

[0072] In this embodiment, the retained edges are sorted according to the vertex connection relationship to form a continuous polygonal outline. If there are broken line segments on the outline edge, they are completed by the minimum distance connection method, that is, the two endpoints with the closest distance are connected to ensure that the boundary is closed.

[0073] Step S307: Construct the initial boundary.

[0074] In this embodiment, an initial boundary can be constructed based on a closed boundary, and its vertex coordinate set can be represented as follows: .

[0075] The embodiments of this application can first collect the initial edge points of all vias in the via cluster, and obtain edge points that meet the preset processing conditions through preprocessing. Then, triangulation is performed to generate target triangles with edge points as vertices. In response to the edge value of the target triangle being greater than or equal to the alpha value, the initial boundary is constructed, which can effectively improve the accuracy and rationality of via cluster boundary determination.

[0076] Optionally, in one embodiment of this application, before inputting the initial boundary into a pre-built multi-objective optimization model, the method further includes: determining whether the initial boundary satisfies preset constraints; if the initial boundary satisfies the preset constraints, then allowing the initial boundary to be input into the multi-objective optimization model; if the initial boundary does not satisfy the preset constraints, then calculating a second alpha value to generate an initial boundary that satisfies the preset constraints using the second alpha value, and allowing the initial boundary that satisfies the preset constraints to be input into the multi-objective optimization model.

[0077] In some embodiments, before inputting the initial boundary into a pre-built multi-objective optimization model, it can first determine whether the initial boundary meets the preset constraints. If it does, the input is allowed; otherwise, the second alpha value is recalculated, and the second alpha value is used to generate an initial boundary that meets the preset constraints. Then, the initial boundary that meets the preset constraints is allowed to be input into the multi-objective optimization model.

[0078] The preset constraints can be understood as the design rules of the circuit board, such as the design rules of the printed circuit board, which may include, but are not limited to, electrical rules, process rules, layout rules, etc. This application does not impose specific restrictions.

[0079] The electrical rules may include connection constraints, insulation spacing rules, and impedance continuity rules, etc., and this application does not impose specific limitations.

[0080] The connection constraint can be understood as follows: the conductive area, i.e. the copper foil, must completely cover the pad area of ​​the via, and the distance between the boundary and the edge of the via is greater than or equal to 1.2 × the radius of the via. The specific setting can be made by those skilled in the art according to the actual situation. This application does not impose specific restrictions, thereby ensuring the continuity of the current path and avoiding open circuits caused by etching deviations.

[0081] The insulation spacing rule can be understood as the minimum spacing between the boundaries of different network copper layers being greater than or equal to the safe distance. (in, The setting can be based on the highest signal voltage level: 0.1mm for below 5V, 0.2mm for 12-48V, and 50% above the IPC-2221 (Generic Standard on Printed Board Design) standard for high-voltage signals. The specific setting can be made by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0082] The impedance continuity rule can be understood as the radius of curvature at the corner of the copper foil boundary being greater than or equal to 0.5 mm, thereby avoiding impedance abrupt changes at right angles for high-speed signals. The specific rules can be set by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0083] The process rules may include, but are not limited to, minimum copper strip width rules, copper strip distance rules, and solder mask opening rules, etc., but this application does not impose specific restrictions.

[0084] The minimum copper strip width rule can be understood as the copper strip width at any position on the boundary being greater than or equal to 0.2 mm, thereby ensuring the feasibility of the etching process and avoiding over-etching of fine copper strips. The specific setting can be made by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0085] The rule for the distance between the copper foil and the board edge can be understood as the distance between the boundary and the physical edge of the printed circuit board being greater than or equal to 1mm, thereby avoiding the exposure of the copper foil during board edge processing. The specific setting can be made by those skilled in the art according to the actual situation, and this application does not impose specific restrictions.

[0086] The rule for opening a window in the solder mask can be understood as the area within 0.1mm outward from the copper skin boundary being the solder mask opening area, which is not allowed to be covered by the solder mask layer. The specific setting can be made by those skilled in the art according to the actual situation, and this application does not impose specific restrictions.

[0087] The layout rules may include, but are not limited to, routing channel avoidance rules, device package avoidance rules, and heat dissipation no-displacement rules, etc., and this application does not impose specific restrictions.

[0088] The routing channel avoidance rule can be understood as the distance between the copper edge and the preset routing channel being ≥2 × the routing line width. For example, a 5mil line width corresponds to a 10mil avoidance distance. The specific rules can be set by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0089] The device packaging clearance rule can be understood as the distance between the copper edge and the device pad being ≥0.3mm, thereby avoiding bridging during soldering. The specific rules can be set by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0090] The rule of heat dissipation no-displacement zone can be understood as follows: if there are thermally sensitive devices (such as capacitors, sensors, etc., which are not specifically restricted in this application) near the via cluster, the copper edge must maintain a distance of ≥1mm from the device. The specific setting can be made by those skilled in the art according to the actual situation, and this application does not impose specific restrictions.

[0091] It should be noted that the embodiments of this application support the following personalized rule requirements for different target circuit board designs: a user interface is provided for custom rule bases, allowing the import of enterprise standard rule files (such as JSON format (JavaScript Object Notation, etc., which are not specifically limited in this application), or manual modification of rule parameters (such as adjusting the minimum copper width to 0.15mm to adapt to high-density board designs, which are not specifically limited in this application); and when multiple rules conflict (such as reducing the copper area may lead to insufficient copper width, which is not specifically limited in this application), rule priorities can be set (such as electrical rules > process rules > layout rules, which are not specifically limited in this application), prioritizing higher-priority rules during the optimization process. Specific settings can be made by those skilled in the art according to actual conditions, and are not specifically limited in this application.

[0092] For example, embodiments of this application may perform the following rule verification on the initial boundary: (1) Connection reliability check: In this embodiment, the minimum distance between the boundary and the edge of the via can be calculated by traversing all vias. If there is a via with a distance < 1.2 × via radius, the boundary will be automatically shifted outward by 0.05 mm and rechecked until all are satisfied.

[0093] (2) Minimum copper width check: In this application embodiment, the initial boundary can be sampled in a grid (one point is taken every 0.1mm), and the normal distance (copper width) between adjacent sampling points can be calculated. If there is a region with a width < 0.2mm, the boundary recessed part of the region is deleted (the convex contour is retained).

[0094] (3) Plate edge distance check: In this embodiment of the application, if the distance between the boundary and the plate edge is <1mm, the boundary will be shrunk by 0.5mm towards the center of the cluster to ensure that the safe distance is met.

[0095] Other rules can also be verified, and the specific rules can be set by those skilled in the art according to the actual situation. This application does not impose any specific restrictions.

[0096] Furthermore, if the preset constraints are still not met after three adjustments in this embodiment, the alpha value is recalculated (e.g., increasing the alpha value by 0.2 mm, etc., which is not specifically limited in this application), and the initial boundary is regenerated until the preset constraints are met. The initial boundary that meets the preset constraints is then allowed to be input into the multi-objective optimization model.

[0097] This application embodiment can determine whether the initial boundary meets preset constraints before inputting it into the multi-objective optimization model. If it does not meet the constraints, a second alpha value is calculated to generate an initial boundary that meets the preset constraints. This allows the initial boundary that meets the preset constraints to be input into the multi-objective optimization model, thereby ensuring the quality of the initial boundary input into the multi-objective optimization model and avoiding deviations in optimization results due to substandard initial boundaries. This can effectively improve optimization efficiency and accuracy, and ensure that the subsequent design of the conductive area of ​​the circuit board can more accurately achieve multi-objective optimization while meeting various constraints, thus improving the reliability and practicality of the overall design scheme.

[0098] Optionally, in one embodiment of this application, before inputting the initial boundary into the pre-constructed multi-objective optimization model, the method further includes: calculating the impedance coefficient weight corresponding to the impedance deviation sub-model, the heat dissipation coefficient weight corresponding to the thermal resistance coefficient sub-model, and the space coefficient weight corresponding to the space utilization sub-model in the multi-objective optimization model based on the signal type value of the via cluster; determining the characteristic impedance value of the via cluster under the action of the corresponding signal based on the signal type value, so as to construct the impedance deviation sub-model based on the characteristic impedance value; constructing the thermal resistance coefficient sub-model based on the power consumption of the via cluster; constructing the space utilization sub-model based on the area of ​​the minimum bounding rectangle of the via cluster; and constructing the multi-objective optimization model based on the impedance deviation sub-model, impedance coefficient weight, thermal resistance coefficient sub-model, heat dissipation coefficient weight, space utilization sub-model, and space coefficient weight.

[0099] It is understood that, in the embodiments of this application, the signal type value can be a high-speed signal (such as PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate Synchronous Dynamic Random Access Memory), etc., which are not specifically limited in this application), a power supply signal (such as 5-volt power supply voltage, which are not specifically limited in this application), a ground signal (such as ground wire / grounding terminal, which are not specifically limited in this application), etc., which are not specifically limited in this application.

[0100] Furthermore, in the embodiment of this application, when the signal type is a high-speed signal, the characteristic impedance is calculated as follows: (This can be achieved by matching the copper foil thickness with the reference plane spacing; this application does not impose specific limitations); current carrying capacity greater than or equal to 0.5A (meeting signal path current requirements); heat dissipation coefficient weight. (Lower priority); Impedance coefficient weight (Higher priority); Spatial coefficient weight .

[0101] When the signal type is a power signal, the characteristic impedance is calculated as follows: (DC low impedance); Current carrying capacity greater than or equal to 2A (calculated based on device power consumption); Heat dissipation coefficient weighting (Higher priority); Impedance coefficient weight (Higher priority); Spatial coefficient weight .

[0102] When the signal type is ground signal, the characteristic impedance is calculated as follows: Current carrying capacity greater than or equal to 1A; heat dissipation coefficient weighting (Balancing shielding and heat dissipation); Impedance coefficient weighting (Higher priority); Spatial coefficient weight .

[0103] This can be understood as follows: In order to achieve differentiated optimization, the impedance coefficient weights of the impedance deviation sub-model in the multi-objective optimization model can be adjusted according to the signal type value. The heat dissipation coefficient weights corresponding to the thermal resistance coefficient sub-model Spatial coefficient weights corresponding to the spatial utilization sub-model This makes the optimization direction more in line with actual needs. The relationship table of different signal types and weight coefficients is shown in Table 2. Table 2 is a relationship table of different signal types and weight coefficients provided according to an embodiment of this application.

[0104] Table 2

[0105] In some embodiments, before inputting the initial boundary into the pre-constructed multi-objective optimization model, the embodiments of this application can first calculate the impedance coefficient weight corresponding to the impedance deviation sub-model, the heat dissipation coefficient weight corresponding to the thermal resistance coefficient sub-model, and the space coefficient weight corresponding to the space utilization sub-model in the multi-objective optimization model based on the signal type value of the via cluster. Then, by constructing the impedance deviation sub-model, the thermal resistance coefficient sub-model, and the space utilization sub-model, and combining the impedance coefficient weight, the heat dissipation coefficient weight, and the space coefficient weight, a multi-objective optimization model is constructed. The expression of the multi-objective optimization model can be, but is not limited to, expressed as: , in, This is the impedance deviation rate (signal integrity index), i.e., the impedance deviation sub-model, in Ω; This refers to the thermal resistance coefficient (a performance indicator for heat dissipation), i.e., the thermal resistance coefficient sub-model. This refers to the space utilization loss rate (layout efficiency index), i.e., the space utilization sub-model. Weights for impedance coefficients; Weighted by the heat dissipation coefficient; For spatial coefficient weights, and satisfying , , , Adjust dynamically based on the signal type value.

[0106] Furthermore, in the embodiments of this application, when the signal type is a high-speed signal, the impedance deviation sub-model can ensure signal integrity through impedance matching, and its expression can be, but is not limited to, expressed as: , in, The target characteristic impedance (e.g., 50Ω); The actual impedance under the current copper foil boundary can be calculated using electromagnetic simulation tools (such as high-frequency structure simulators). The main calculation steps are: ① Establishing a three-dimensional model of the copper foil (thickness t is set according to the current carrying capacity, and the reference plane is the adjacent ground plane); ② Setting the simulation frequency (equal to the signal operating frequency); ③ Extracting the port impedance value. Other methods may also be used, and the specific settings can be made by those skilled in the art according to the actual situation. This application does not impose any specific restrictions.

[0107] When the signal type is a power signal or a ground signal, the target characteristic impedance is... At this point, the expression for the impedance deviation can be, but is not limited to, expressed as: , That is, the embodiments of this application measure impedance directly.

[0108] The thermal resistance coefficient sub-model can reflect the heat dissipation capacity of the copper foil; the smaller the value, the better the heat dissipation performance. Its expression can be, but is not limited to, as follows: , in, The total power consumption of the via cluster (can be determined based on device parameters, and this application does not impose specific limitations), in W; The temperature rise under the current copper boundary was calculated using thermal simulation tools. The main calculations included: ① defining the heat source; ② setting the ambient temperature (25℃) and heat dissipation boundary conditions; ③ simulating the temperature difference between the via area and the environment. Other methods may also be used, and the specific settings can be made by those skilled in the art according to the actual situation. This application does not impose any specific restrictions.

[0109] The space utilization sub-model measures the space occupancy of the conductive area relative to the target circuit board, i.e., the copper foil relative to the printed circuit board. Its expression can be, but is not limited to, as follows: , in, The area enclosed by the current copper area boundary (calculated using the polygon area formula): ); The area of ​​the minimum bounding rectangle of the via cluster (reference area).

[0110] in, The smaller the value, the closer the copper area is to the reference area, and the higher the space utilization rate.

[0111] Before inputting the initial boundary into the multi-objective optimization model, this embodiment first calculates the impedance coefficient weight corresponding to the impedance deviation sub-model, the heat dissipation coefficient weight corresponding to the thermal resistance coefficient sub-model, and the space coefficient weight corresponding to the space utilization sub-model in the multi-objective optimization model. By combining the impedance deviation sub-model, the thermal resistance coefficient sub-model, and the space utilization sub-model, a corresponding multi-objective optimization model is constructed. This fully considers the characteristics of via clusters in terms of electrical, heat dissipation, and space utilization, making the constructed multi-objective optimization model more in line with actual needs. This effectively improves the comprehensiveness and accuracy of via cluster layout optimization, providing reliable support for generating high-quality circuit board conductive area designs.

[0112] Optionally, in one embodiment of this application, before constructing the space utilization sub-model based on the area of ​​the minimum bounding rectangle of the via cluster, the method further includes: determining the abscissa, ordinate, and second aperture value of each via in the via cluster based on cluster features; sorting the abscissa and ordinate values ​​respectively to obtain sorted abscissa and ordinate values; extracting the coordinate boundary values ​​from the sorted abscissa and ordinate values ​​respectively to obtain the first abscissa boundary value, the second abscissa boundary value, the first ordinate boundary value, and the second ordinate boundary value; obtaining the four vertex values ​​of the minimum bounding rectangle of the via cluster based on the first abscissa boundary value, the second abscissa boundary value, the first ordinate boundary value, the second ordinate boundary value, and the second aperture value, and constructing the minimum bounding rectangle using the four vertex values; and calculating the area of ​​the minimum bounding rectangle based on the four vertices.

[0113] In some embodiments, the calculation of the area of ​​the minimum bounding rectangle in this application is as follows: Figure 4 As shown, the main content is as follows: Step S401: Determine the x-coordinate value and second aperture value of each via in the via cluster, and sort them to obtain the sorted x-coordinate values.

[0114] In this embodiment, the x-coordinate value of the center coordinate of each via in the via cluster can be retrieved cyclically. and the corresponding second aperture value Add to list ,right In Sort the data in ascending order to obtain the sorted x-coordinate values, which can be represented as: .

[0115] Step S402: Determine the ordinate value and second aperture value of each via in the via cluster, and sort them to obtain the sorted ordinate values.

[0116] Similarly, in this embodiment, the ordinate value of the center coordinate of the cluster via is obtained cyclically. and the corresponding second aperture value Add to list ,right In Sort the data in ascending order to obtain the sorted ordinate values, which can be represented as: .

[0117] Step S403: Determine the values ​​of the four vertices of the minimum bounding rectangle.

[0118] Among them, the minimum bounding rectangle The leftmost boundary of the direction can be represented as: The rightmost boundary can be represented as ; The lowest boundary of the direction can be represented as: The uppermost boundary can be represented as .

[0119] Step S404: Calculate the area of ​​the smallest bounding rectangle.

[0120] The formula for calculating the area of ​​the minimum bounding rectangle can be, but is not limited to, expressed as: , Before constructing the space utilization sub-model, this application embodiment can first determine the x-coordinate, y-coordinate, and second aperture value of each via in the via cluster, and obtain the sorted coordinate values ​​by sorting them. Then, the four vertex values ​​of the minimum bounding rectangle are extracted to construct the minimum bounding rectangle and calculate its area. This can accurately quantify the space occupancy of the via cluster, providing a reliable data foundation for constructing the space utilization sub-model, making the model more closely match the actual layout, effectively improving the accuracy of space utilization optimization for the via cluster, helping to plan space more rationally in circuit board design, improving the scientificity and rationality of the overall layout, and ensuring the performance and stability of the circuit board.

[0121] In step S103, the initial boundary is input into the pre-built multi-objective optimization model, and the initial boundary is iteratively optimized to output the final boundary of the conductive area to be generated, and the conductive area of ​​the target circuit board is generated according to the final boundary.

[0122] As one possible implementation method, embodiments of this application can input the initial boundary into a pre-built multi-objective optimization model, and then iteratively optimize the initial boundary to output the final boundary of the conductive region to be generated, and generate the conductive region of the target circuit board based on the final boundary.

[0123] Optionally, in one embodiment of this application, iterative optimization of the initial boundary to output the final boundary of the conductive region to be generated includes: obtaining a coordinate set of coordinates of all vertices in the initial boundary; constructing coordinate constraints of the coordinate set based on the vertex values ​​of the vertices of the minimum bounding rectangle; randomly generating an initial particle population based on the initial boundary and coordinate constraints; updating the initial coordinate values ​​of each initial particle in the initial particle population according to a preset update condition to obtain the updated particle coordinate values, and calculating the fitness of the updated particle based on the coordinate values; and determining the final boundary based on the fitness, in response to the iterative optimization of the initial boundary satisfying a preset iteration termination condition.

[0124] It is understood that the embodiments of this application may use the PSO algorithm to iteratively optimize the initial boundary in order to balance the three objectives of signal integrity, heat dissipation performance and space utilization.

[0125] In some embodiments, this application can obtain a coordinate set of all vertices in the initial boundary, and construct coordinate constraints of the coordinate set based on the vertex values ​​of the vertices of the minimum bounding rectangle. Then, an initial particle population is randomly generated, and the initial coordinate values ​​of each initial particle in the initial particle population are updated according to a preset update condition to obtain the updated particle coordinate values. The individual extreme values ​​and global extreme values ​​of the multi-objective optimization model are recalculated to obtain the first volume extreme value and the first global extreme value. In response to the iterative optimization of the initial boundary satisfying the preset iteration termination condition, the final boundary is determined.

[0126] The preset update condition can be understood as the update condition for the particle's velocity and position; the preset iteration termination condition can be that the number of iterations reaches T, or that in 10 consecutive iterations... The fitness change is ≤0.01, and the specific setting can be made by those skilled in the art according to the actual situation. This application does not impose any specific restrictions.

[0127] For example, in combination Figure 5 As shown, the embodiments of this application have made adaptive improvements to the PSO algorithm, and the specific steps are as follows: Step S501: Obtain the coordinate set.

[0128] In this embodiment, the vertex coordinates of the polygon in the initial boundary can be used as optimization variables. Let the initial boundary be... For polygons, the optimization variable is... The set of coordinates of vertices can be, but is not limited to, represented as: , where the coordinates of each vertex It is a continuous variable.

[0129] Step S502: Construct coordinate constraints.

[0130] In this embodiment of the application, to avoid the boundary from exceeding a reasonable range during the optimization process, constraints are imposed on the coordinates of each vertex, which can be, but are not limited to, expressed as: , , in, Subtract a certain value, such as 2mm, from the coordinates of the leftmost boundary of the smallest bounding rectangle. Add a certain value, such as 2mm, to the coordinates of the rightmost boundary of the smallest bounding rectangle. Subtract a certain value, such as 2mm, from the coordinates of the bottom boundary of the smallest bounding rectangle. Add a certain value, such as 2mm, to the coordinates of the uppermost boundary of the smallest bounding rectangle. This certain value can be set by those skilled in the art according to the actual situation, and this application does not impose specific limitations.

[0131] In this embodiment, coordinate constraints are constructed to ensure that the initial boundary can only be adjusted within a limited range around the via cluster, thus avoiding excessive deviation from the target via.

[0132] Step S503: Parameter settings for the PSO algorithm.

[0133] It is understood that in the embodiments of this application, the parameters of the PSO algorithm directly affect the optimization efficiency and convergence. For the irregular copper foil planning scenario, the parameter settings are shown in Table 3. The specific settings can be set by those skilled in the art according to the actual situation, and this application does not impose specific limitations. Table 3 is a parameter setting table of the PSO algorithm provided according to an embodiment of this application.

[0134] Table 3

[0135] Step S504: Randomly generate the initial particle population.

[0136] The embodiments of this application can be randomly generated. Given a set of particles (boundary scheme), where the coordinates of each particle satisfy the coordinate constraints described above, calculate the fitness of each particle. Record: Individual optimal position : No. The coordinates corresponding to the current optimal fitness of each particle; the global optimal position. : The coordinates corresponding to the optimal fitness among all particles.

[0137] Step S505: Speed ​​and position update.

[0138] In this embodiment, the particle's velocity and position can be updated according to the following formula, which can be, but is not limited to, expressed as: , , in, The particle's current velocity; For the updated speed (which needs to be limited to) (within the range) , Use random numbers between 0 and 1 to increase the randomness of the search; This represents the particle's current position. The updated position (satisfying coordinate constraints); Inertial weights; Cognitive factors; As a social factor; This represents the individual extreme value, i.e., the optimal position of the particle. The global extremum is the optimal position of all particles globally.

[0139] Step S506: Constraint Repair Mechanism.

[0140] In this application, the embodiments may be located in the updated position. Coordinate constraints are not met (e.g.) ,or, In the case of [missing information], a rebound correction method should be used for adjustment: (1) If ,but That is, as the particle bounces off the left boundary and rebounds to the right, the velocity component in the corresponding direction is reversed. This prevents particles from repeatedly going beyond the boundary.

[0141] (2) If ,but That is, when a particle exceeds the left boundary and bounces to the right, it simultaneously reverses the velocity component in the corresponding direction. This prevents particles from repeatedly going beyond the boundary.

[0142] Step S507: Calculate the fitness of the updated particles.

[0143] Step S508: Determine whether the preset iteration termination condition is met.

[0144] In this embodiment of the application, the preset iteration termination condition can be that the number of iterations reaches 100; or that in 10 consecutive iterations... If the fitness change is ≤0.01, and this condition is reached, the preset iteration termination condition is satisfied, and step S509 is executed; otherwise, step S503 is executed.

[0145] Step S509: Determine the final boundary.

[0146] This application embodiment can first obtain the coordinate set of the initial boundary vertices, construct coordinate constraints with the minimum bounding rectangle vertex value, randomly generate an initial particle population, update the particle coordinates and calculate the fitness according to preset conditions, and finally determine the final boundary in response to the preset iteration termination condition. By using particle swarm optimization and coordinate constraints, the optimal boundary can be searched efficiently under complex conditions, effectively improving the globality and accuracy of boundary optimization, making the finally determined conductive area boundary more in line with actual needs, and ensuring the rationality and performance stability of the conductive area layout of the circuit board.

[0147] Optionally, in one embodiment of this application, determining the final boundary based on fitness in response to the iterative optimization of the initial boundary satisfying a preset iteration termination condition includes: calculating the initial individual extreme value and the initial global extreme value of the multi-objective optimization model based on the initial coordinate values; updating the coordinate set based on fitness in response to the update result of the initial individual extreme value, or the update result of the initial global extreme value, to obtain the updated coordinate set; and determining the final boundary based on the updated coordinate set in response to the iterative optimization of the initial boundary satisfying the preset iteration termination condition.

[0148] In some embodiments, the present application embodiments can calculate the initial individual extreme value and the initial global extreme value of the multi-objective optimization model based on the initial coordinate values. In response to the update result of the initial individual extreme value or the update result of the initial global extreme value, the coordinate set is updated to obtain the updated coordinate set. In response to the iterative optimization of the initial boundary satisfying the preset iteration termination condition, the final boundary is determined.

[0149] For example, embodiments of this application can calculate the fitness of the updated particles. :like The fitness level is then updated. This is the current position; if The fitness level is then updated. Given the current position, and if the preset iteration termination condition is met, output... The corresponding boundary is taken as the optimal boundary, thus obtaining the final boundary.

[0150] It should be noted that, in this embodiment of the application, the corner angle can be calculated for all vertices of the final boundary. If the angle is <= 90° (right angle or acute angle), then the angle bisector of the corner is taken, and the distance from the boundary vertex is taken as the reference angle. Using the center and radius Subtract 0.5mm to draw a circle, and replace the corner with the arc that intersects it, regenerating a smooth boundary, thus determining the final boundary, as shown below. Figure 6 As shown, in this embodiment of the application, the angle of vertex A is an acute angle. In this case, this embodiment of the application can calculate the angle bisector of angle A, and take a distance of from vertex A on the angle bisector. Point O, with point O as the center, and... Draw a circle with a radius minus 0.5 mm. Replace the original boundary with the arcs intersecting the two sides of angle A to generate a smooth boundary, thus determining the final boundary. Vertex B is similar to vertex A, and will not be elaborated further here. Other methods can also be used to generate the final boundary, and the specific settings can be made by those skilled in the art according to the actual situation. This application does not impose specific limitations.

[0151] This application embodiment calculates the initial individual and global extrema of the multi-objective optimization model using initial coordinate values, and updates the coordinate set in response to the update results. When the preset iteration termination condition is met, the final boundary is determined. By using the extrema to guide the dynamic update of the coordinate set, the optimal boundary can be searched more accurately, effectively balancing various indicators in multi-objective optimization, improving the convergence and accuracy of boundary optimization, and ensuring that the final boundary of the conductive area reaches the comprehensive optimality in terms of electrical performance, space utilization, and other aspects, thereby enhancing the scientificity and reliability of circuit board design.

[0152] Optionally, in one embodiment of this application, after generating the conductive area of ​​the target circuit board according to the final boundary, the method further includes: detecting whether the target circuit board meets the preset verification conditions; if the target circuit board does not meet the preset verification conditions, generating an adjustment instruction for the multi-objective optimization model according to the preset verification conditions, and controlling the multi-objective optimization model to adjust according to the adjustment instruction, so as to determine the final boundary of the target circuit board according to the adjusted multi-objective optimization model.

[0153] It is understood that the preset verification conditions may include, but are not limited to, verification of signal integrity, heat dissipation performance, layout efficiency indicators, electrical rules, process rules, layout rules, visual verification, etc. The specific conditions can be set by those skilled in the art according to the actual situation, and this application does not impose any specific restrictions.

[0154] In some embodiments, after generating the conductive area of ​​the target circuit board according to the final boundary, this application embodiment can detect whether the target circuit board meets the preset verification conditions. If the target circuit board does not meet the preset verification conditions, an adjustment instruction for the multi-objective optimization model is generated according to the preset verification conditions, and the weights of the multi-objective optimization model are adjusted according to the adjustment instruction. Then, the final boundary of the target circuit board is determined according to the adjusted multi-objective optimization model.

[0155] The weights may include, but are not limited to, impedance coefficient weights, heat dissipation coefficient weights, and space coefficient weights; this application does not impose specific limitations on these.

[0156] For example, in this application embodiment, a conductive region, such as a copper foil, is created on a specified layer based on the final boundary. The logical binding relationship can be: establishing a dynamic link between the generated copper foil and the target via or via functional cluster. When any associated via is moved, deleted, or its attributes are changed, the final boundary is updated in real time, and the generated conductive region is verified in multiple dimensions to see if it meets preset verification conditions. For example, the reliability of the connection between the copper foil and the via (no open circuit) and the compliance of the spacing between copper foils of different networks are verified by using a DRC (Design Rule Check) tool; the reflection coefficient of the high-speed signal path is simulated using a high-frequency structure simulator (≤-15dB is acceptable, confirming signal integrity); the temperature rise of the power supply via area is simulated using electronic heat dissipation simulation software (≤25℃ under rated current is acceptable, indicating qualified heat dissipation performance), etc. This application does not impose specific limitations.

[0157] Furthermore, embodiments of this application can overlay copper boundaries, via clusters, wiring channels, device packages, etc., in the printed circuit board design interface, and use color to mark non-compliant areas (e.g., red indicates insufficient spacing, yellow indicates that the copper is too narrow, etc., this application does not impose specific limitations), supporting engineers to manually confirm or trigger secondary optimization, etc. The specific settings can be made by those skilled in the art according to the actual situation, and this application does not impose specific limitations.

[0158] Furthermore, in embodiments of this application, if the preset verification conditions are not met, adjustment instructions for the multi-objective optimization model can be generated specifically based on the specific verification results, and the model can be readjusted until the preset verification conditions are met.

[0159] After generating the conductive area of ​​the target circuit board based on the final boundary, this embodiment of the application can detect whether the target circuit board meets the preset verification conditions. If not, the multi-objective optimization model is adjusted to determine the final boundary of the target circuit board. The model parameters are flexibly adjusted according to the actual verification results, so that the final boundary continuously adapts to the actual needs, effectively improving the fault tolerance and adaptability of the circuit board design, avoiding performance failure due to initial design deviations, ensuring that the conductive area design has better comprehensive performance in electrical, heat dissipation and other aspects, and enhancing the overall performance and reliability of the circuit board.

[0160] The working principle of the method for generating conductive areas on a circuit board proposed in this application will be described below with reference to a specific embodiment.

[0161] in, Figure 7 This is a flowchart illustrating the working principle of a method for generating conductive regions on a circuit board according to an embodiment of this application.

[0162] Step S701: Identify the printed circuit board for which the conductive area to be generated is located.

[0163] Step S702: Obtain the original design data of the printed circuit board.

[0164] Step S703: Execute the DBSCAN algorithm to determine whether the via cluster is valid.

[0165] If it is effective, proceed to step S705; otherwise, proceed to step S704.

[0166] Step S704: Adjust the distance threshold.

[0167] Step S705: Check for the existence of isolated vias.

[0168] If it exists, proceed to step S706; otherwise, proceed to step S707.

[0169] Step S706: Merge isolated vias into the nearest via cluster.

[0170] Step S707: Output via cluster.

[0171] Step S708: Calculate the alpha value In this embodiment, the alpha value can be calculated according to the formula shown above.

[0172] Step S709: Generate initial boundaries.

[0173] In this embodiment, the initial boundary can be generated based on the alpha value.

[0174] Step S710: Determine whether the initial boundary satisfies the preset constraint conditions.

[0175] The preset constraints may include, but are not limited to, electrical rules, process rules, layout rules, etc., and this application does not impose specific restrictions.

[0176] Furthermore, in this embodiment of the application, step S711 may be executed if the condition is not met; otherwise, step S712 may be executed.

[0177] Step S711: Recalculate the alpha value.

[0178] Step S712: Construct a multi-objective optimization model.

[0179] The multi-objective optimization model constructed in the embodiments of this application may include, but is not limited to, impedance deviation sub-model, thermal resistance coefficient sub-model, space utilization sub-model, etc., and this application does not impose specific limitations.

[0180] Step S713: Determine the final boundary based on the PSO algorithm and the multi-objective optimization model.

[0181] In this embodiment, an initial boundary that meets preset constraints can be input into a pre-constructed multi-objective optimization model, and the PSO algorithm can be used to iteratively optimize the initial boundary until the preset iteration termination condition is met.

[0182] Step S714: Determine whether the preset iteration termination condition is met.

[0183] The preset iteration termination condition can be that the number of iterations reaches T, or that the iteration terminates within 10 consecutive iterations. The fitness change is ≤0.01, and this application does not impose specific restrictions.

[0184] Furthermore, in this embodiment of the application, step S716 is executed if the conditions are met; otherwise, step S715 is executed.

[0185] Step S715: Adjust the parameters of the PSO algorithm.

[0186] Step S716: Determine the final boundary.

[0187] Step S717: Determine whether the preset verification conditions are met.

[0188] If the condition is not met, proceed to step S718; otherwise, proceed to step S719.

[0189] Step S718: Adjust the weights of the multi-objective optimization model.

[0190] In this embodiment of the application, adjustment instructions for the multi-objective optimization model can be generated in a targeted manner based on the verification results, and the weights of the multi-objective optimization model can be adjusted according to the adjustment instructions.

[0191] Step S719: Generate the design file for the printed circuit board.

[0192] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0193] The method for generating conductive areas on a circuit board according to the embodiments of this application can obtain the original design data of the target circuit board for which the conductive area is to be generated, extract the corresponding via parameter features, and then obtain the parameter data of at least some vias to determine the via cluster. Based on the first via that meets certain aperture conditions, the distribution density, and the corresponding correction coefficient, the alpha value is calculated to construct the initial boundary. Then, the initial boundary is iteratively optimized according to the pre-built multi-objective optimization model to output the final boundary of the conductive area to be generated, thereby generating the conductive area of ​​the target circuit board. Therefore, it can solve the problems of slow and inefficient drawing due to increased complexity in manual circuit board design, which makes it difficult to meet the needs of the modern electronics industry. Furthermore, the design differences between experienced personnel are large, resulting in unstable results and affecting performance reliability. Automated design does not fully consider the influence of vias and layout optimization, leading to signal interference and uneven heat dissipation in the actual application of conductive areas. This method achieves high efficiency and intelligence, significantly reduces manual workload, shortens the design cycle, and has high consistency, strong debuggability, good scalability, supports custom rules, and can be dynamically maintained. It can quickly adapt to the needs of different processes and product lines and meet the technical effects required by enterprises.

[0194] Embodiments of this application also provide an apparatus for generating conductive regions on a circuit board.

[0195] Figure 8 This is a block diagram of a circuit board conductive region generation apparatus provided according to an embodiment of this application.

[0196] like Figure 8 As shown, the device 10 for generating the conductive area of ​​the circuit board includes: a first generation module 100, a first construction module 200, and a second generation module 300.

[0197] The first generation module 100 is used to identify the target circuit board for which the conductive area to be generated is to obtain the original design data of the target circuit board, and extract at least one via parameter feature of the target circuit board from the original design data, so as to obtain parameter data of at least some vias based on at least one via parameter feature.

[0198] The first construction module 200 is used to determine the via cluster of the target circuit board based on parameter data, and determine the first via, distribution density and correction coefficient of the distribution density in the via cluster that meet the preset aperture conditions according to the cluster characteristics of the via cluster. Based on the aperture value, distribution density and correction coefficient of the first via, the alpha value of the via cluster is calculated, so as to construct the initial boundary of the via cluster based on the alpha value and the cluster characteristics.

[0199] The second generation module 300 is used to input the initial boundary into a pre-built multi-objective optimization model, iteratively optimize the initial boundary to output the final boundary of the conductive region to be generated, and generate the conductive region of the target circuit board based on the final boundary.

[0200] Optionally, in one embodiment of this application, the first construction module 200 includes: a first determining unit, a first calculating unit, and a second determining unit.

[0201] The first determining unit is used to determine the signal type value, center coordinate value, hole diameter value and hole wall thickness value of the corresponding via based on the parameter data.

[0202] The first calculation unit is used to calculate the distance between different vias with the same signal type value, based on the signal type value, center coordinate value, aperture value, and aperture wall thickness value.

[0203] The second determining unit is used to divide the vias corresponding to the distance values ​​into the same via cluster in response to the distance value being less than a preset threshold, so as to determine the via cluster.

[0204] Optionally, in one embodiment of this application, it further includes: a first computing module, a second building module, a third building module, a fourth building module, and a fifth building module.

[0205] The first calculation module is used to calculate the impedance coefficient weights corresponding to the impedance deviation sub-model, the heat dissipation coefficient weights corresponding to the thermal resistance coefficient sub-model, and the space coefficient weights corresponding to the space utilization sub-model in the multi-objective optimization model based on the signal type values ​​of the via cluster before inputting the initial boundary into the pre-built multi-objective optimization model.

[0206] The second construction module is used to determine the characteristic impedance value of the via cluster under the action of the corresponding signal based on the signal type value, so as to construct an impedance deviation sub-model based on the characteristic impedance value.

[0207] The third building block is used to construct a thermal resistance coefficient sub-model based on the power consumption of the via cluster.

[0208] The fourth building module is used to construct a space utilization sub-model based on the area of ​​the minimum bounding rectangle of the via cluster.

[0209] The fifth module is used to construct a multi-objective optimization model based on the impedance deviation sub-model, impedance coefficient weight, thermal resistance coefficient sub-model, heat dissipation coefficient weight, space utilization sub-model, and space coefficient weight.

[0210] Optionally, in one embodiment of this application, it further includes: a first determining module, a sorting module, an extraction module, a sixth constructing module, and a second calculation module.

[0211] The first determining module is used to determine the abscissa, ordinate, and second aperture value of each via in the via cluster based on cluster characteristics before constructing the space utilization sub-model based on the area of ​​the minimum bounding rectangle of the via cluster.

[0212] The sorting module is used to sort the x-coordinate values ​​and y-coordinate values ​​respectively to obtain the sorted x-coordinate values ​​and y-coordinate values.

[0213] The extraction module is used to extract the coordinate boundary values ​​from the sorted horizontal and vertical coordinate values ​​respectively, so as to obtain the first horizontal coordinate boundary value, the second horizontal coordinate boundary value, the first vertical coordinate boundary value, and the second vertical coordinate boundary value.

[0214] The sixth construction module is used to obtain the four vertex values ​​of the minimum bounding rectangle of the via cluster based on the first horizontal coordinate boundary value, the second horizontal coordinate boundary value, the first vertical coordinate boundary value, the second vertical coordinate boundary value, and the second aperture value, and to construct the minimum bounding rectangle using the four vertex values.

[0215] The second calculation module is used to calculate the area of ​​the smallest bounding rectangle based on the four vertices.

[0216] Optionally, in one embodiment of this application, the second generation module 300 includes: an acquisition unit, a first construction unit, a first generation unit, a first update unit, and a third determination unit.

[0217] The acquisition unit is used to acquire the coordinate set of all vertices in the initial boundary.

[0218] The first building unit is used to construct coordinate constraints for the coordinate set based on the vertex values ​​of the vertices of the minimum bounding rectangle.

[0219] The first generation unit is used to randomly generate an initial particle population based on the initial boundary and coordinate constraints.

[0220] The update unit is used to update the initial coordinate values ​​of each initial particle in the initial particle population according to preset update conditions, so as to obtain the updated coordinate values ​​of the particles, and calculate the fitness of the updated particles based on the coordinate values.

[0221] The third determining unit is used to determine the final boundary based on fitness and in response to the iterative optimization of the initial boundary satisfying a preset iteration termination condition.

[0222] Optionally, in one embodiment of this application, the third determining unit includes: a calculation subunit, an update subunit, and a determining subunit.

[0223] The computational subunit is used to calculate the initial individual extrema and the initial global extrema of the multi-objective optimization model based on the initial coordinate values.

[0224] Update the sub-unit to update the coordinate set based on fitness, in response to the update result of the initial individual extremum, or the update result of the initial global extremum, to obtain the updated coordinate set.

[0225] Determine the sub-element, which is used to determine the final boundary based on the updated coordinate set and in response to the iterative optimization of the initial boundary satisfying the preset iteration termination condition.

[0226] Optionally, in one embodiment of this application, the first construction module 200 includes: a collection unit, a second generation unit, a third generation unit, and a second construction unit.

[0227] The acquisition unit is used to acquire the initial edge points of all vias in the via cluster based on cluster characteristics.

[0228] The second generation unit is used to preprocess the initial edge points to obtain edge points that meet the preset processing conditions.

[0229] The third generation unit is used to perform triangulation based on edge points to generate target triangles with edge points as vertices.

[0230] The second building unit is used to construct the initial boundary in response to the edge value of the target triangle being greater than or equal to the alpha value.

[0231] Optionally, in one embodiment of this application, it further includes: a judgment module, a first input module, and a second input module.

[0232] The judgment module is used to determine whether the initial boundary satisfies the preset constraints before inputting the initial boundary into the pre-built multi-objective optimization model.

[0233] The first input module is used to allow the initial boundary to be input into the multi-objective optimization model when the initial boundary meets the preset constraints.

[0234] The second input module is used to calculate the second alpha value when the initial boundary does not meet the preset constraints, so as to generate an initial boundary that meets the preset constraints using the second alpha value, and allow the initial boundary that meets the preset constraints to be input into the multi-objective optimization model.

[0235] Optionally, in one embodiment of this application, it further includes: a detection module and a second determination module. The detection module is used to detect whether the target circuit board meets the preset verification conditions after generating the conductive area of ​​the target circuit board according to the final boundary.

[0236] The second determining module is used to generate adjustment instructions for the multi-objective optimization model according to the preset verification conditions when the target circuit board is detected to not meet the preset verification conditions, and to control the multi-objective optimization model to adjust according to the adjustment instructions, so as to determine the final boundary of the target circuit board based on the adjusted multi-objective optimization model.

[0237] For a description of the features in the embodiment corresponding to the apparatus for generating conductive areas on a circuit board, please refer to the relevant description in the embodiment corresponding to the method for generating conductive areas on a circuit board, which will not be repeated here.

[0238] The circuit board conductive area generation device proposed in this application can obtain the original design data of the target circuit board to which the conductive area is to be generated, extract the corresponding via parameter features, and then obtain the parameter data of at least some vias, thereby determining the via cluster. Based on the first vias that meet certain aperture conditions, the distribution density, and the corresponding correction coefficient, the alpha value is calculated, and an initial boundary is constructed. Then, the initial boundary is iteratively optimized according to a pre-built multi-objective optimization model, thereby outputting the final boundary of the conductive area to be generated, and thus generating the conductive area of ​​the target circuit board. Therefore, it can solve the problems of slow and inefficient drawing due to increased complexity in manual circuit board design, which makes it difficult to meet the needs of the modern electronics industry. Furthermore, the design results vary greatly among experienced personnel, leading to unstable results and affecting performance reliability. Automated design does not fully consider the influence of vias and layout optimization, resulting in signal interference and uneven heat dissipation in the actual application of conductive areas. This device achieves high efficiency and intelligence, significantly reduces manual workload, shortens the design cycle, and has high consistency, strong debuggability, good scalability, supports custom rules, and can be dynamically maintained. It can quickly adapt to the needs of different processes and product lines and meet the technical effects required by enterprises.

[0239] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the method for generating conductive areas on a circuit board.

[0240] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the method for generating conductive areas on a circuit board.

[0241] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0242] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the method for generating conductive areas on a circuit board.

[0243] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the method for generating conductive areas on a circuit board.

[0244] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0245] The method for generating conductive regions on a circuit board provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for generating conductive regions on a circuit board, characterized in that, Includes the following steps: Identify the target circuit board for which conductive areas are to be generated, obtain the original design data of the target circuit board, and extract at least one via parameter feature of the target circuit board from the original design data, so as to obtain parameter data of at least some vias based on the at least one via parameter feature. Based on the parameter data, the via cluster of the target circuit board is determined, and the first via that meets the preset aperture condition, the distribution density, and the correction coefficient of the distribution density are determined according to the cluster characteristics of the via cluster. Based on the aperture value of the first via, the distribution density, and the correction coefficient, the alpha value of the via cluster is calculated, so as to construct the initial boundary of the via cluster based on the alpha value and the cluster characteristics. The initial boundary is input into a pre-built multi-objective optimization model, and the initial boundary is iteratively optimized to output the final boundary of the conductive region to be generated, and the conductive region of the target circuit board is generated according to the final boundary. The formula for calculating the alpha value is as follows: ， in, The diameter of the first through hole, in mm; The correction coefficient is... The alpha value is given.

2. The method according to claim 1, characterized in that, Determining the via cluster of the target circuit board based on the parameter data includes: Based on the parameter data, determine the signal type value, center coordinate value, aperture value, and hole wall thickness value of the corresponding via. Based on the signal type value, the center coordinate value, the aperture value, and the aperture wall thickness value, calculate the distance between different vias with the same signal type value; In response to the distance value being less than a preset threshold, the vias corresponding to the distance value are divided into the same via cluster to determine the via cluster.

3. The method according to claim 1, characterized in that, Before inputting the initial boundary into the pre-built multi-objective optimization model, the following steps are also included: Based on the signal type value of the via cluster, calculate the impedance coefficient weight corresponding to the impedance deviation sub-model, the heat dissipation coefficient weight corresponding to the thermal resistance coefficient sub-model, and the space coefficient weight corresponding to the space utilization sub-model in the multi-objective optimization model. Based on the signal type value, the characteristic impedance value of the via cluster under the corresponding signal is determined, so as to construct the impedance deviation sub-model according to the characteristic impedance value; Based on the power consumption of the via cluster, a sub-model of the thermal resistance coefficient is constructed; Based on the area of ​​the minimum bounding rectangle of the via cluster, the space utilization sub-model is constructed; The multi-objective optimization model is constructed based on the impedance deviation sub-model, the impedance coefficient weight, the thermal resistance coefficient sub-model, the heat dissipation coefficient weight, the space utilization sub-model, and the space coefficient weight.

4. The method according to claim 3, characterized in that, Before constructing the space utilization sub-model based on the area of ​​the minimum bounding rectangle of the via cluster, the method further includes: Based on the cluster characteristics, the abscissa value, ordinate value, and second aperture value of each via in the via cluster are determined. The x-coordinate values ​​and y-coordinate values ​​are sorted respectively to obtain sorted x-coordinate values ​​and y-coordinate values; Extract the coordinate boundary values ​​from the sorted x-coordinate and y-coordinate values ​​respectively to obtain the first x-coordinate boundary value, the second x-coordinate boundary value, the first y-coordinate boundary value, and the second y-coordinate boundary value; Based on the first horizontal coordinate boundary value, the second horizontal coordinate boundary value, the first vertical coordinate boundary value, the second vertical coordinate boundary value, and the second aperture value, the four vertex values ​​of the minimum bounding rectangle of the via cluster are obtained, and the minimum bounding rectangle is constructed using the four vertex values. Calculate the area of ​​the minimum bounding rectangle based on the four vertices.

5. The method according to claim 4, characterized in that, The iterative optimization of the initial boundary to output the final boundary of the conductive region to be generated includes: Obtain the coordinate set of all vertices in the initial boundary; Based on the vertex values ​​of the vertices of the minimum bounding rectangle, construct the coordinate constraints of the coordinate set; Based on the initial boundary and the coordinate constraints, an initial particle population is randomly generated; The initial coordinates of each initial particle in the initial particle population are updated according to the preset update conditions to obtain the updated coordinates of the particles, and the fitness of the updated particles is calculated based on the coordinates. Based on the fitness, the iterative optimization in response to the initial boundary satisfies a preset iteration termination condition to determine the final boundary.

6. The method according to claim 5, characterized in that, The step of determining the final boundary based on the fitness, in response to the initial boundary, by satisfying a preset iteration termination condition, includes: Based on the initial coordinate values, calculate the initial individual extreme values ​​and the initial global extreme values ​​of the multi-objective optimization model; Based on the fitness, in response to the update result of the initial individual extreme value, or the update result of the initial global extreme value, the coordinate set is updated to obtain the updated coordinate set; Based on the updated coordinate set, the final boundary is determined in response to the iterative optimization of the initial boundary satisfying a preset iteration termination condition.

7. The method according to claim 1, characterized in that, The initial boundary of the via cluster, constructed based on the alpha value and the cluster characteristics, includes: Based on the cluster characteristics, the initial edge points of all vias in the via cluster are collected; The initial edge points are preprocessed to obtain edge points that meet preset processing conditions; Based on the edge points, triangulation is performed to generate target triangles with the edge points as vertices; The initial boundary is constructed in response to the edge value of the target triangle being greater than or equal to the alpha value.

8. The method according to claim 1, characterized in that, Before inputting the initial boundary into the pre-built multi-objective optimization model, the following steps are also included: Determine whether the initial boundary satisfies the preset constraint conditions; If the initial boundary satisfies the preset constraint, then the initial boundary can be input into the multi-objective optimization model; If the initial boundary does not satisfy the preset constraint, a second alpha value is calculated to generate an initial boundary that satisfies the preset constraint, and the initial boundary that satisfies the preset constraint is allowed to be input into the multi-objective optimization model.

9. The method according to claim 1, characterized in that, After generating the conductive region of the target circuit board based on the final boundary, the process further includes: Detect whether the target circuit board meets the preset verification conditions; If the target circuit board is found to not meet the preset verification conditions, an adjustment instruction for the multi-objective optimization model is generated according to the preset verification conditions, and the multi-objective optimization model is controlled to be adjusted according to the adjustment instruction, so as to determine the final boundary of the target circuit board based on the adjusted multi-objective optimization model.

10. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the method for generating conductive areas on a circuit board as described in any one of claims 1-9.

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