Gate driving unit, gate driving circuit, driving method and display panel
By dynamically controlling the connection state of the storage module during the high-level overlap period, the pre-charge failure problem of the gate drive circuit is solved, ensuring the pixel charging rate and display stability under high refresh rate display.
Patent Information
- Application Number
- CN202511922935.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-03-03
AI Technical Summary
Under high duty cycle clock signals, the pre-charge failure of the gate drive circuit causes the bootstrap capacitor to fail to charge with sufficient voltage, resulting in insufficient pull-up node potential and affecting display quality.
By changing the connection state of the storage module during the high-level overlap period, the charging sustaining module establishes a potential difference across the storage module, ensuring effective pre-charging of the bootstrap capacitor and providing stable driving conditions during the output phase.
It improves the precharge failure problem under high duty cycle clock signals and enhances the pixel charging rate and display stability under high refresh rate displays.
Smart Images
Figure CN121600873A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display driving technology, specifically relating to a gate driving unit, a gate driving circuit, a driving method, and a display panel. Background Technology
[0002] With the popularization of high refresh rate display technology, the effective charging time per line has been greatly compressed; in order to improve the charging rate, the clock signal duty cycle is usually increased to extend the effective charging time.
[0003] When the clock duty cycle exceeds 50%, the clock signal used for precharging will overlap with the current row drive clock signal at a high level. During this overlap period, the gate drive circuit of the relevant technology will have the problem of failure to precharge the bootstrap capacitor. However, in the formal output stage of the row, since the bootstrap capacitor fails to charge with sufficient voltage, the pull-up node potential is insufficient, which makes the output transistor unable to conduct stably, ultimately leading to gate signal output failure or abnormality, which seriously affects the display quality.
[0004] It is evident that improving the precharge failure of the gate drive circuit under high duty cycle clock signals is an urgent problem to be solved. Summary of the Invention
[0005] This application provides a gate driving unit, a gate driving circuit, a driving method, and a display panel. By changing the connection state of the memory module during the high-level overlap period, this application can improve the pre-charge failure problem of high duty cycle clock signals and improve the pixel charging rate and display stability under high refresh rate display.
[0006] In a first aspect, this application provides a gate driving unit, the gate driving unit comprising: a pre-charge module configured to be connected to a pre-charge signal terminal and a pull-up node, for pre-charging the pull-up node in response to a pre-charge signal output from the pre-charge signal terminal; an output module configured to be connected to the pull-up node and a clock signal terminal, for outputting a gate driving signal according to the potential of the pull-up node and a driving clock signal output from the clock signal terminal; wherein the rising edge of the pre-charge signal is located before the rising edge of the driving clock signal, and the pre-charge signal and the driving clock signal have a high-level overlap period; a storage module, a first terminal of the storage module being connected to the pull-up node; and a charge sustaining module configured to be connected to a second terminal of the storage module and a driving output terminal of the output module, for establishing a potential difference across the storage module by changing the connection state of the second terminal of the storage module during the high-level overlap period.
[0007] Optionally, the charging sustaining module includes: a first switching submodule configured to be connected to the precharge signal terminal, the clock signal terminal, and the second terminal of the storage module, for connecting the second terminal of the storage module to a low-level terminal during the phase when the precharge signal is at an active level and the driving clock signal is at an inactive level; a timing control submodule configured to be connected to the clock signal terminal, for generating a switching control signal during a high-level overlap period and after a preset duration when the driving clock signal becomes active; and a second switching submodule configured to be connected to the second terminal of the storage module, the driving output terminal of the output module, and the output terminal of the timing control submodule, for switching the second terminal of the storage module to be connected to the driving output terminal of the output module under the action of the switching control signal.
[0008] Optionally, the first switching submodule includes: a first transistor, the control terminal of which is connected to the clock signal terminal, and a first terminal of which is connected to a second terminal of the storage module; and a second transistor, the control terminal of which is connected to the precharge signal terminal, and a first terminal of which is connected to a second terminal of the first transistor, and a second terminal of which is grounded; wherein the turn-on voltages of the first transistor and the second transistor are opposite.
[0009] Optionally, the timing control submodule includes: a diode, the anode of which is connected to the clock signal terminal, and the cathode of which serves as the output terminal of the timing control submodule; a resistor, the first terminal of which is connected to the clock signal terminal; a first capacitor, the first terminal of which is connected to the second terminal of the resistor, and the second terminal of which is connected to a low-level terminal; and a second capacitor, the first terminal of which is connected to the first terminal of the first capacitor, and the second terminal of which is connected to the cathode of the diode.
[0010] Optionally, the second switching submodule includes: a third transistor, the control terminal of the third transistor being connected to the output terminal of the timing control submodule, the first terminal of the third transistor being connected to the second terminal of the storage module, and the second terminal of the third transistor being connected to the drive output terminal of the output module.
[0011] Optionally, the pre-charge module includes: a fourth transistor, the control terminal of the fourth transistor being connected to the pre-charge signal terminal, the first terminal of the fourth transistor being connected to a high-level terminal, and the second terminal of the fourth transistor being connected to the pull-up node.
[0012] Optionally, the output module includes: a fifth transistor, the control terminal of which is connected to the pull-up node, the first terminal of which is connected to the clock signal terminal, and the second terminal of which serves as the drive output terminal of the output module; and a sixth transistor, the control terminal of which is connected to the pull-up node, the first terminal of which is connected to the clock signal terminal, and the second terminal of which serves as the stage transmission output terminal of the output module.
[0013] Secondly, this application provides a gate driving circuit, which includes N cascaded gate driving units; wherein the stage output terminal of the ni-th stage gate driving unit is used as the precharge signal terminal of the n-th stage gate driving unit; i is a positive integer.
[0014] Thirdly, this application provides a driving method applied to a gate driving unit. The driving method includes: in a pre-charge phase, a pre-charge module pre-charges a pull-up node according to a received pre-charge signal; in a high-level overlap phase, a charging maintenance module controls the connection state of the second end of the memory module to establish and maintain a potential difference between the two ends of the memory module and the driving output module; and in an output phase, an output module outputs a driving clock signal as a gate driving signal.
[0015] Optionally, the charging sustaining module includes a first switching submodule, a timing control submodule, and a second switching submodule. The charging sustaining module controls the connection state of the second terminal of the storage module and establishes and maintains a potential difference between the two ends of the storage module and the drive output module. This includes: during the phase when the pre-charge signal is at an active level and the drive clock signal is at an inactive level, the first switching submodule connects the second terminal of the storage module to a low-level terminal; during the high-level overlap period and after a preset duration when the drive clock signal becomes active, the timing control submodule generates a switching control signal; under the action of the switching control signal, the second switching submodule switches the second terminal of the storage module to be connected to the drive output terminal of the output module.
[0016] Fourthly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; and the non-display area includes a gate driving circuit, wherein the drive output terminal of the gate driving circuit is electrically connected to at least one scan line.
[0017] The technical solutions provided in this application have at least the following beneficial effects: This application utilizes a charging sustaining module to dynamically control the connection state of the second terminal of the storage module during the high-level overlap period, actively establishing an effective potential difference across the storage module. This solves the pre-charge failure problem caused by clock signal overlap, ensuring not only successful pre-charge of the storage module but also providing stable driving conditions for the output module in the subsequent output stage, guaranteeing reliable output of the gate drive signal. Therefore, by changing the connection state of the storage module during the high-level overlap period, this application can improve the pre-charge failure problem under high duty cycle clock signals, enhancing pixel charging rate and display stability under high refresh rate displays. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0019] Figure 1 The diagram shown is a schematic of the driving architecture of a display panel provided in an embodiment of this application.
[0020] Figure 2 The diagram shown is a circuit schematic of a gate drive unit in related technologies.
[0021] Figure 3 The diagram shown is a driving timing diagram provided in an embodiment of this application.
[0022] Figure 4 The diagram shown is another driving timing diagram provided in an embodiment of this application.
[0023] Figure 5 The diagram shown is a schematic diagram of a gate driving unit provided in an embodiment of this application.
[0024] Figure 6 The diagram shown is a structural schematic of another gate driving unit provided in an embodiment of this application.
[0025] Figure 7 The diagram shown is a circuit schematic of a gate driving unit provided in an embodiment of this application.
[0026] Figure 8 The diagram shown is another driving timing diagram provided in an embodiment of this application.
[0027] Figure 9 The diagram shown is a schematic representation of the conduction state of a transistor according to an embodiment of this application.
[0028] Figure 10The diagram shown is a schematic diagram of the conduction state of another transistor provided in an embodiment of this application.
[0029] Figure 11 The figure shown is a node voltage timing diagram provided in an embodiment of this application.
[0030] Figure 12 The diagram shown is a schematic diagram of the conduction state of another transistor provided in an embodiment of this application.
[0031] Figure 13 The diagram shown is a flowchart of a driving method provided in an embodiment of this application.
[0032] Explanation of reference numerals in the attached figures: 100. Gate driving unit; 110. Pre-charge module; 120. Output module; 130. Storage module; 140. Charge sustaining module; 141. First switching submodule; 142. Timing control submodule; 143. Second switching submodule; 150. Pull-down module; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; Cbt, bootstrap capacitor; C1, first capacitor; C2, second capacitor; R, resistor; D, diode; PU, pull-up node; FK, precharge signal terminal; Fout, stage output terminal; Gout, drive output terminal; CK, clock signal terminal; TK, pull-down signal terminal; VSS, low-level terminal; VGH, high-level terminal. Detailed Implementation
[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.
[0034] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.
[0035] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.
[0036] In conventional liquid crystal displays (LCDs), to improve pixel charging efficiency and reduce the timing design burden of the gate driver on array (GOA) circuit, a single-row, single-drive architecture is often used, such as... Figure 1 The 8CK (8 Clock) drive architecture is shown.
[0037] The inventors of this application have discovered that the circuit diagram of only the gate drive unit displaying the core logic is as follows: Figure 2 As shown, the design includes a fourth transistor T4 as a pre-charge transistor, a fifth transistor T5 and a sixth transistor T6 as output transistors, a seventh transistor T7 as a pull-down transistor, and a bootstrap capacitor Cbt. In this design, the GOA cells of the current row are typically pre-charged using clock signals from several rows preceding the current row to establish drive capability in advance. For example, the clock signals from the first four rows (CK1-CK4) are often used as the pre-charge enable signals for subsequent rows. It should be noted that this specification uses an 8CK drive and the first four rows of pre-charge as an example, but the number of clocks and the number of pre-charge rows in actual applications can be adjusted according to design requirements. For example, in 6CK, 10CK, and other drive architectures, the number of pre-charge rows can also correspond to the first 3 rows, the first 5 rows, etc. The numbers shown in the figure are only examples and do not constitute a limitation on the actual solution.
[0038] In this traditional architecture, when the clock duty cycle (CK duty) is less than or equal to 50%, the high-level periods of each clock signal are staggered in timing, and the pre-charging and formal output stages can be seamlessly connected. However, with the widespread adoption of high refresh rate display technology, the effective charging time available for each row of pixels has been significantly compressed. To improve the charging rate, extending the high-level time of the clock signal within one cycle, i.e., increasing the CK duty cycle, has become a direct and effective engineering approach. However, when the clock duty cycle is increased to above 50%, this architecture exposes inherent timing defects: taking the charging stage of the Nth row (e.g., the fifth row) as an example, as... Figure 3 As shown, the high-level period of its corresponding driving clock CK5 will overlap with the high-level period of the fourth-line clock CK1 (i.e., Fn-4) used for pre-charging of this line, and both will be at a high-level voltage V. GH At this point, the potential of the gate output node Gn is also pulled up to near V. GHThis causes the voltage across the bootstrap capacitor Cbt to be close to V. GH The effective potential difference that can be established at its two ends is close to zero, causing pre-charging to fail.
[0039] Subsequently, when entering the stage where the Nth line (the fifth line) should be output normally, such as Figure 4 As shown, CK1 goes low, but the bootstrap capacitor Cbt fails to charge effectively, and its stored voltage is insufficient to maintain the potential of the pull-up node PU. The voltage at PU drops to near zero, causing the gate-source voltage Vgs of the fifth transistor T5 and the sixth transistor T6 to be less than or equal to zero. As a result, the fifth transistor T5 and the sixth transistor T6 are turned off or in an unstable state, ultimately leading to no output or abnormal output of the gate signal Gn for that row, and the scan fails to start.
[0040] To improve the precharge failure problem under high duty cycle clock signals, this application provides a gate drive unit, specifically including the following embodiments: Figure 5 The diagram shown is a structural schematic of a gate driving unit 100 provided in an embodiment of this application. The gate driving unit 100 in this embodiment is a unit of a gate driving circuit. That is to say, for a gate driving circuit, there are N gate driving units 100. However, for a gate driving unit 100, there are at least a pull-up node PU, a stage transmission output terminal Fout, and a drive output terminal Gout.
[0041] like Figure 5 As shown, the gate drive unit 100 also includes a pre-charge module 110, configured to be connected to the pre-charge signal terminal FK and the pull-up node PU, for pre-charging the pull-up node PU in response to the pre-charge signal output by the pre-charge signal terminal FK. It should be noted that the pre-charge signal terminal FK in this embodiment is an environmental feature, which can be the stage output terminal Fout or the drive output terminal Gout of the preceding gate drive unit 100 (e.g., the ni-th stage gate drive unit 100); the pre-charge module 110 in this embodiment pre-charges the pull-up node PU when it receives a valid pre-charge signal.
[0042] In this embodiment, the gate driving unit 100 further includes an output module 120, which is configured to be connected to the pull-up node PU and the clock signal terminal CK, and is used to output a gate driving signal according to the potential of the pull-up node PU and the driving clock signal output by the clock signal terminal CK; wherein the rising edge of the precharge signal is located before the rising edge of the driving clock signal, and the precharge signal and the driving clock signal have a high-level overlap period.
[0043] It should be noted that the rising edge of the precharge signal preceding the rising edge of the drive clock signal indicates that the high-level activation timing of the precharge signal is earlier than that of the drive clock signal. When the duty cycle of the drive clock signal is greater than 50%, there will be periods where the high levels of the precharge signal and the drive clock signal overlap. These overlapping periods are as follows: Figure 3 The shaded area in the diagram represents the turn-on and turn-off of the output module 120, which controls the potential of the pull-up node PU. When the potential on the pull-up node PU is high, the output module 120 is turned on, and the high level of the drive clock signal is used as the gate drive signal and output through the drive output terminal Gout. Optionally, the output module 120 can also use the high level of the drive clock signal as the stage transmission signal and output through the stage transmission output terminal Fout.
[0044] In this embodiment, the gate driving unit 100 further includes a storage module 130, the first end of which is connected to the pull-up node PU. Specifically, the storage module 130 can be a bootstrap capacitor Cbt, and the connection of the first end of the storage module 130 to the pull-up node PU means that the upper plate of the bootstrap capacitor Cbt is directly connected to the pull-up node PU. In this embodiment, the storage module 130 can store charge during the pre-charging phase and raise the potential of the pull-up node PU during the output phase through capacitive coupling (i.e., bootstrap effect) to ensure that the output transistor in the output module 120 is fully turned on.
[0045] In this embodiment, the gate driving unit 100 further includes a charge sustaining module 140, which is configured to be connected to the second terminal of the storage module 130 and the drive output terminal Gout of the output module 120, and is used to establish a potential difference across the storage module 130 by changing the connection state of the second terminal of the storage module 130 during the high-level overlap period.
[0046] Specifically, in this embodiment, one end of the charge sustaining module 140 is connected to the second end (i.e., the lower plate) of the bootstrap capacitor Cbt, and the other end of the charge sustaining module 140 is connected to the drive output terminal Gout. Its specific function is to dynamically control the connection path of the lower plate of the bootstrap capacitor Cbt during the high-level overlap period, so that there is an effective potential difference between the two ends of the bootstrap capacitor Cbt during the high-level overlap period. This not only meets the need for effective pre-charging of the bootstrap capacitor Cbt, so that the pull-up node PU has sufficient turn-on voltage, but also enhances the voltage on the pull-up node PU through the bootstrap effect during the output stage, so that the output transistor in the output module 120 can be fully turned on.
[0047] Therefore, based on the timing relationship between the precharge signal and the drive clock signal, this application divides the working cycle of the gate drive unit 100 into a precharge stage, a high-level overlap stage, and an output stage. The specific working principle is as follows: (1) During the pre-charge phase, the pre-charge signal is at an active level (e.g., high level), while the drive clock signal is at an inactive level (e.g., low level). The pre-charge module 110 turns on in response to the active pre-charge signal, transmitting the high potential from the high-level terminal VGH to the pull-up node PU, thereby completing the initial charging of the pull-up node PU. At this time, although the pull-up node PU is charged to a high potential and the output module 120 turns on, the output module 120 does not output the gate drive signal because the drive clock signal is low, and the drive output terminal Gout remains at a low potential.
[0048] (2) High-level overlap phase: As the drive clock signal jumps to an effective level (high level), the high-level overlap period begins, during which the pre-charge signal and the drive clock signal are simultaneously effective. In conventional circuits, this overlap would directly cause the gate output terminal potential to be pulled up, thereby causing the potential difference across the bootstrap capacitor Cbt to disappear. However, in this embodiment, the charge sustaining module 140 dynamically controls the connection state of the second terminal of the storage module 130 during the high-level overlap period, thereby establishing an effective potential difference across the storage module 130 (bootstrap capacitor Cbt). The establishment of this potential difference indicates that the storage module 130 has stored enough charge, thus laying the energy foundation for the subsequent output phase.
[0049] (3) Output stage: When the precharge signal becomes invalid (low level), the drive clock signal may still be valid, entering the stable output stage; since an effective potential difference has been established at both ends of the storage module 130 during the high-level overlap stage, the potential of the pull-up node PU can be maintained or even further increased through the bootstrap effect of the storage module 130, providing a stable and sufficient drive voltage (i.e., gate-source voltage Vgs) for the output module 120. Therefore, the output module 120 can stably and completely output the gate drive signal to the gate output terminal according to the high potential of the pull-up node PU and the valid drive clock signal, thereby reliably opening the corresponding pixel row.
[0050] This application solves the pre-charge failure problem caused by clock signal overlap by dynamically controlling the connection state of the second terminal of the storage module 130 during the high-level overlap period through the charge sustaining module 140, actively establishing an effective potential difference across the storage module 130. This not only ensures successful pre-charge of the storage module 130 but also provides stable driving conditions for the output module 120 in the subsequent output stage, guaranteeing reliable output of the gate drive signal. Therefore, the gate drive unit 100 of this application can improve the pre-charge failure problem under high duty cycle clock signals by changing the connection state of the storage module 130 during the high-level overlap period, thereby improving the pixel charging rate and display stability under high refresh rate displays.
[0051] Figure 6The diagram shown is a structural schematic of another gate driving unit 100 provided in an embodiment of this application. Figure 6 As shown, the gate drive unit 100 also includes a pull-down module 150, which is configured to be connected to the pull-up node PU and the pull-down signal terminal TK, and is used to pull down the voltage of the pull-up node PU to a low level under the action of the pull-down control signal output by the pull-down signal terminal TK.
[0052] It should be noted that after the gate drive unit 100 completes a line scan output, or during its non-selected idle phase, the potential of the pull-up node PU needs to be reset to a low level to prevent circuit mis-triggering and reduce power consumption. Here, in this embodiment, the potential of the pull-up node PU is reset to a low level through the pull-down module 150. The specific working principle is as follows: when the pull-down control signal becomes an effective level (e.g., high level), the pull-down module 150 is turned on, forming a low-impedance discharge path from the pull-up node PU to the low-level terminal VSS, which quickly releases the charge remaining on the pull-up node PU and forces the voltage down to a low level.
[0053] In one embodiment, the charging sustaining module 140 includes a first switching submodule 141, configured to be connected to the precharge signal terminal FK, the clock signal terminal CK, and the second terminal of the storage module 130. This submodule connects the second terminal of the storage module 130 to a low-level terminal VSS when the precharge signal is at an active level and the driving clock signal is at an inactive level. Specifically, the charging sustaining module 140 receives a precharge signal from the precharge signal terminal FK and a driving clock signal from the clock signal terminal CK. When the precharge signal is at an active level (e.g., high level) and the driving clock signal is at an inactive level (e.g., low level), it establishes an effective electrical path within itself, connecting the second terminal of the storage module 130 to a constant low-level terminal VSS, thereby establishing an effective voltage difference across the two ends of the storage module 130 and satisfying the charging requirements of the storage module 130.
[0054] In one embodiment, the charging sustaining module 140 further includes a timing control submodule 142, configured to be connected to the clock signal terminal CK, for generating a switching control signal during a high-level overlap period and after a preset duration when the driving clock signal transitions to an effective level. Specifically, the timing control submodule 142 is activated when the high-level overlap period begins and the driving clock signal transitions from an ineffective level to an effective level. However, the timing control submodule 142 does not immediately output a signal, but instead initiates an internal timing or delay mechanism. Only after the driving clock signal transitions to an effective level for a preset duration will it generate an effective switching control signal from its output terminal. This switching control signal is used to control the on / off state of the second switching submodule 143.
[0055] In one embodiment, the charging sustaining module 140 further includes a second switching submodule 143, configured to be connected to the second terminal of the storage module 130, the drive output terminal Gout of the output module 120, and the output terminal of the timing control submodule 142. Under the action of a switching control signal, the second terminal of the storage module 130 is switched to be connected to the drive output terminal Gout of the output module 120. Specifically, the second switching submodule 143 is in a conducting state when and only when a valid switching control signal arrives, switching the connection between the second terminal of the storage module 130 and the low-level terminal VSS to an electrical connection with the drive output terminal Gout, thereby providing a conduction path for establishing a further effective voltage difference across the two terminals of the storage module 130.
[0056] Therefore, this embodiment achieves the purpose of changing the connection state of the second end of the storage module 130 during the high-level overlap period through the coordinated work of the first switching submodule 141, the timing control submodule 142, and the second switching submodule 143. This solves the pre-charge failure problem under high duty cycle, ensures the stability of the gate drive signal in the subsequent output stage, and enables the entire gate drive unit 100 to reliably work under the drive conditions required for high refresh rate.
[0057] Figure 7 The diagram shown is a circuit schematic of a gate driving unit 100 provided in an embodiment of this application. Figure 7 As shown, the first switching submodule 141 of this embodiment includes a first transistor T1 and a second transistor T2; the control terminal of the first transistor T1 is connected to the clock signal terminal CK, and the first terminal of the first transistor T1 is connected to the second terminal of the storage module 130; the control terminal of the second transistor T2 is connected to the precharge signal terminal FK, the first terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the second terminal of the second transistor T2 is grounded; wherein, the turn-on voltages of the first transistor T1 and the second transistor T2 are opposite; specifically, the first transistor T1 in this embodiment is a P-type MOS transistor, that is, the turn-on voltage is low level; the second transistor T2 in this embodiment is an N-type MOS transistor, that is, the turn-on voltage is high level.
[0058] like Figure 7 As shown, the timing control submodule 142 includes a diode D, a resistor R, a first capacitor C1, and a second capacitor C2; the anode of the diode D is connected to the clock signal terminal CK, and the cathode of the diode D serves as the output terminal of the timing control submodule 142; the first terminal of the resistor R is connected to the clock signal terminal CK; the first terminal of the first capacitor C1 is connected to the second terminal of the resistor R, and the second terminal of the first capacitor C1 is connected to the low-level terminal VSS; the first terminal of the second capacitor C2 is connected to the first terminal of the first capacitor C1, and the second terminal of the second capacitor C2 is connected to the cathode of the diode D.
[0059] In this embodiment, the second switching submodule 143 includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the output terminal of the timing control submodule 142, the first terminal of the third transistor T3 is connected to the second terminal of the storage module 130, and the second terminal of the third transistor T3 is connected to the drive output terminal Gout of the output module 120.
[0060] In one embodiment, the pre-charge module 110 includes: a fourth transistor T4, the control terminal of the fourth transistor T4 being connected to the pre-charge signal terminal FK, the first terminal of the fourth transistor T4 being connected to the high-level terminal VGH, and the second terminal of the fourth transistor T4 being connected to the pull-up node PU.
[0061] In one embodiment, the output module 120 includes a fifth transistor T5 and a sixth transistor T6; the control terminal of the fifth transistor T5 is connected to the pull-up node PU, the first terminal of the fifth transistor T5 is connected to the clock signal terminal CK, and the second terminal of the fifth transistor T5 serves as the drive output terminal Gout of the output module 120; the control terminal of the sixth transistor T6 is connected to the pull-up node PU, the first terminal of the sixth transistor T6 is connected to the clock signal terminal CK, and the second terminal of the sixth transistor T6 serves as the stage transmission output terminal Fout of the output module 120.
[0062] In one embodiment, the pull-down module 150 includes a seventh transistor T7, the control terminal of the seventh transistor T7 is connected to the pull-down signal terminal TK, the first terminal of the seventh transistor T7 is connected to the pull-up node PU, and the second terminal of the seventh transistor T7 is connected to the low-level terminal VSS.
[0063] This combination Figure 3 , Figure 4 and Figure 8 The timing diagram, taking the pre-charge process in the fifth row as an example, uses CK1 as the pre-charge signal and CK5 as the drive clock signal to explain in detail the working principle of the circuit structure of the gate drive unit 100 in this embodiment: (1) Pre-charging stage: such as Figure 8 The shaded area shown indicates that during this stage, the pre-charge signal CK1 is high and the drive clock signal CK5 is low. The conduction states of each transistor are as follows: Figure 9 As shown: First, since the precharge signal CK1 is high, the fourth transistor T4 is turned on. The high potential output by the high-level terminal VGH is written to the pull-up node PU through the fourth transistor T4, so that the pull-up node PU is charged to a high potential.
[0064] Secondly, since the precharge signal CK1 is high, the second transistor T2 is turned on; at the same time, the drive clock signal CK5 is low, causing the first transistor T1 to also turn on. Therefore, the lower plate of the bootstrap capacitor Cbt (i.e., node A) is connected to the low-level terminal VSS through the turned-on first transistor T1 and second transistor T2.
[0065] Then, since the drive clock signal CK5 is low at this time, the timing control submodule 142 is not started, and its output potential is low, so the third transistor T3 is cut off.
[0066] At this point, a Vt connection is formed across the bootstrap capacitor Cbt. PU - V A = V GH - V SS The initial effective potential difference completes the critical charging of the bootstrap capacitor Cbt; V PU This indicates the voltage at the pull-up node PU, V. A This represents the voltage at node A. Simultaneously, the high-potential pull-up node PU turns on the fifth transistor T5 and the sixth transistor T6. However, since the drive clock signal CK5 is low at this time, both the drive output Gout and the stage output Fout output a low level.
[0067] Therefore, the technical effect achieved during the pre-charging phase is that a voltage Vt has been successfully established across the bootstrap capacitor Cbt before the drive clock signal CK5 becomes effective, i.e., before the high level of the drive clock signal arrives. GH -V SS The potential difference causes the bootstrap capacitor Cbt to store charge and provides the conditions for the output transistor to conduct.
[0068] (2) High-level overlap phase: such as Figure 3 As shown in the shaded area, during this stage, the pre-charge signal CK1 remains high, while the drive clock signal CK5 transitions from low to high, entering a high-level overlap period. The conduction states of each transistor are as follows: Figure 10 As shown: The instant the drive clock signal CK5 transitions from low to high, current rapidly charges the second capacitor C2 through diode D, causing the output potential (i.e., point Q) of the timing control submodule 142 to quickly rise to approximately V. GH - V th (V) th (This is the forward voltage drop of diode D), and this potential is sufficient to initially turn on the third transistor T3.
[0069] Meanwhile, the high potential of the driving clock signal CK5 charges the first capacitor C1 through resistor R, causing the potential of node K to rise slowly. When the potential of point K exceeds V... thAt this time, diode D is cut off. Subsequently, due to the bootstrap effect of the second capacitor C2, the potential at point Q is further raised to approximately 2 × V. GH -V th The high level provides a strong and stable turn-on voltage for the third transistor T3; during this stage, the voltage timing of point K, point Q, and CK5 is as follows: Figure 11 As shown.
[0070] It should be noted that in the initial stage of high-level overlap, although the high level of the drive clock signal CK5 causes the first transistor T1 to tend to turn off, the high potential at point Q has already turned on the third transistor T3, thus switching the lower plate of the bootstrap capacitor Cbt from being connected to the low-level terminal VSS through the turned-on first transistor T1 and second transistor T2 to being directly connected to the drive output terminal Gout. At this time, since the fifth transistor T5 is already turned on, the potential of the drive output terminal Gout is in the process of rising from low to high level; when the potential of the lower plate of the bootstrap capacitor Cbt rises with the drive output terminal Gout, the potential of its upper plate (i.e., the pull-up node PU) is bootstrap raised through capacitive coupling. Finally, the potential of the pull-up node PU is locked at approximately 2 × V. GH - V SS The extremely high level ensures that the fifth transistor T5 and the sixth transistor T6 are strongly turned on, driving the output terminal Gout and the stage transmission output terminal Fout to output a complete high level; at the same time, the extremely high pull-up node PU potential makes the gate-source voltage Vgs of the fourth transistor T4 become negative, the fourth transistor T4 is turned off, cutting off the direct connection with the pre-charge signal CK1 and avoiding signal interference.
[0071] Therefore, during the high-level overlap period, the delayed start of the timing control submodule 142 and the precise switching of the second switching submodule 143 not only prevent the disappearance of the potential difference of the bootstrap capacitor Cbt, but also use the bootstrap effect to significantly raise and lock the potential of the pull-up node PU, creating conditions for stable output.
[0072] (3) Output stage: such as Figure 4 The shaded area is shown in the diagram. During this stage, the pre-charge signal CK1 goes low, while the drive clock signal CK5 remains high. The conduction states of each transistor are as follows: Figure 12 As shown: Because the precharge signal CK1 goes low, the fourth transistor T4 is turned off, and because the pull-up node PU potential is still maintained at a high level (i.e., 2×V) by the bootstrap effect. GH -V SSWith the fifth transistor T5 and the sixth transistor T6 continuously conducting, the high level of the drive clock signal CK5 is transmitted to the drive output terminal Gout and the stage transmission output terminal Fout respectively through the fully conducting fifth transistor T5 and sixth transistor T6, outputting a stable and complete high-level gate drive signal, successfully turning on the pixel in that row.
[0073] In summary, this embodiment ensures that during the high-level overlap period, the RC delay network composed of resistor R and first capacitor C1 ensures that the third transistor T3 only conducts after the initial establishment of the pull-up node PU potential. Diode D and second capacitor C2 are used to raise the potential of the switching control signal, causing the third transistor T3 to act as a strong switch, switching the lower plate of bootstrap capacitor Cbt from the low-level terminal VSS to the drive output terminal Gout. This operation transforms the interference during the overlap period into an opportunity to improve the circuit's driving capability, ultimately bootslinging the pull-up node PU potential to a stable level far higher than the power supply voltage. Therefore, this circuit solves the problems of pre-charge failure and output instability caused by signal overlap under high clock duty cycles, achieving stable driving with a CK duty cycle greater than 50%, and significantly improving the effective charging time and charging rate of each row of pixels in a high refresh rate display panel.
[0074] In one embodiment, this application provides a gate driving circuit, which includes N cascaded gate driving units of the above embodiments; wherein the stage output terminal of the ni-th stage gate driving unit is used as the precharge signal terminal of the n-th stage gate driving unit; i is a positive integer.
[0075] Figure 13 The diagram shown is a flowchart of a driving method provided in an embodiment of this application; as follows: Figure 13 As shown, the driving method of this embodiment is applied to the gate driving circuit shown in the above embodiment, and specifically includes the following steps: Step S100: In the pre-charging stage, the pre-charging module pre-charges the pull-up node according to the received pre-charging signal.
[0076] Step S200: During the high-level overlap phase, the connection state of the second end of the storage module is controlled by the charging sustaining module, and a potential difference is established and maintained between the two ends of the storage module to drive the output module.
[0077] Step S300: In the output stage, the drive clock signal is output as the gate drive signal through the output module.
[0078] In one embodiment, the charging sustaining module includes a first switching submodule, a timing control submodule, and a second switching submodule. The charging sustaining module controls the connection state of the second terminal of the storage module and establishes and maintains a potential difference between the two ends of the storage module and the drive output module. This includes: during the stage when the pre-charge signal is at an active level and the drive clock signal is at an inactive level, the first switching submodule connects the second terminal of the storage module to a low-level terminal; during the high-level overlap period and after a preset duration when the drive clock signal becomes active, the timing control submodule generates a switching control signal; under the action of the switching control signal, the second switching submodule switches the second terminal of the storage module to be connected to the drive output terminal of the output module.
[0079] It should be noted that the working principle of the driving method in this embodiment is the same as that of the gate driving unit described above, and will not be repeated here.
[0080] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes the gate driving circuit described in the above embodiment, and the drive output terminal of the gate driving circuit is electrically connected to at least one scan line.
[0081] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0082] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0083] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.
Claims
1. A gate driving unit, characterized in that, The gate driving unit includes: The pre-charge module is configured to connect to the pre-charge signal terminal and the pull-up node, and is used to pre-charge the pull-up node in response to the pre-charge signal output by the pre-charge signal terminal. An output module is configured to be connected to the pull-up node and the clock signal terminal, and is used to output a gate drive signal according to the potential of the pull-up node and the drive clock signal output by the clock signal terminal; wherein the rising edge of the precharge signal is located before the rising edge of the drive clock signal, and the precharge signal and the drive clock signal have a high-level overlap period. Storage module, the first end of which is connected to the pull-up node; A charging sustaining module is configured to be connected to the second terminal of the storage module and the drive output terminal of the output module, and is used to establish a potential difference across the storage module by changing the connection state of the second terminal of the storage module during the high-level overlap period.
2. The gate driving unit according to claim 1, characterized in that, The charge sustaining module includes: The first switching submodule is configured to be connected to the precharge signal terminal, the clock signal terminal and the second terminal of the storage module, and is used to connect the second terminal of the storage module to the low-level terminal during the stage when the precharge signal is at an active level and the drive clock signal is at an inactive level. The timing control submodule is configured to be connected to the clock signal terminal and to generate a switching control signal during a high-level overlapping period and after a preset duration when the driving clock signal becomes an effective level. The second switching submodule is configured to be connected to the second end of the storage module, the drive output end of the output module, and the output end of the timing control submodule, and is used to switch the second end of the storage module to be connected to the drive output end of the output module under the action of the switching control signal.
3. The gate driving unit according to claim 2, characterized in that, The first switching submodule includes: A first transistor, wherein the control terminal of the first transistor is connected to the clock signal terminal, and the first terminal of the first transistor is connected to the second terminal of the memory module; The second transistor has a control terminal connected to the precharge signal terminal, a first terminal connected to the second terminal of the first transistor, and a second terminal grounded. The turn-on voltages of the first transistor and the second transistor are opposite.
4. The gate driving unit according to claim 2, characterized in that, The timing control submodule includes: A diode, wherein the anode of the diode is connected to the clock signal terminal, and the cathode of the diode serves as the output terminal of the timing control submodule; A resistor, the first end of which is connected to the clock signal terminal; A first capacitor, wherein a first terminal of the first capacitor is connected to a second terminal of the resistor, and the second terminal of the first capacitor is connected to a low-level terminal; The second capacitor has its first terminal connected to the first terminal of the first capacitor, and its second terminal connected to the cathode of the diode.
5. The gate driving unit according to claim 2, characterized in that, The second switching submodule includes: The third transistor has its control terminal connected to the output terminal of the timing control submodule, its first terminal connected to the second terminal of the storage module, and its second terminal connected to the drive output terminal of the output module.
6. The gate driving unit according to any one of claims 1-5, characterized in that, The pre-charge module includes: a fourth transistor, the control terminal of the fourth transistor being connected to the pre-charge signal terminal, the first terminal of the fourth transistor being connected to the high-level terminal, and the second terminal of the fourth transistor being connected to the pull-up node; Or / and, the output module includes: a fifth transistor, the control terminal of which is connected to the pull-up node, the first terminal of which is connected to the clock signal terminal, and the second terminal of which serves as the drive output terminal of the output module. The sixth transistor has its control terminal connected to the pull-up node, its first terminal connected to the clock signal terminal, and its second terminal serving as the stage output terminal of the output module.
7. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units as described in any one of claims 1-6; wherein the stage output terminal of the ni-th gate driving unit is used as the precharge signal terminal of the n-th gate driving unit; i is a positive integer.
8. A driving method, characterized in that, Applied to the gate driving unit according to any one of claims 1-6, the driving method includes: During the pre-charging phase, the pre-charging module pre-charges the pull-up node based on the received pre-charging signal. During the high-level overlap phase, the connection state of the second end of the storage module is controlled by the charging sustaining module, and a potential difference is established and maintained between the two ends of the storage module to drive the output module. During the output phase, the drive clock signal is output as the gate drive signal through the output module.
9. The driving method according to claim 8, characterized in that, The charging sustaining module includes a first switching submodule, a timing control submodule, and a second switching submodule. The charging sustaining module controls the connection state of the second terminal of the storage module, establishing and maintaining a potential difference across the storage module to drive the output module, including: During the phase when the precharge signal is at an active level and the drive clock signal is at an inactive level, the second terminal of the storage module is connected to the low-level terminal through the first switching submodule; During the high-level overlapping period and after a preset duration when the driving clock signal becomes active, a switching control signal is generated by the timing control submodule. Under the action of the switching control signal, the second switching submodule switches the second end of the storage module to be connected to the drive output end of the output module.
10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit of claim 7, wherein the driving output terminal of the gate driving circuit is electrically connected to at least one scan line.