NAND memory reading circuit
By combining a pre-charge circuit, NAND memory, ping-pong discharge path, comparator circuit, and output circuit, the high power consumption problem during NAND memory read operation is solved, achieving power consumption reduction and energy efficiency improvement.
Patent Information
- Application Number
- CN202411151769.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2026-03-03
AI Technical Summary
Traditional NAND memory read solutions consume a lot of power during continuous read operations, and are particularly energy inefficient in in-memory computing scenarios.
By employing a combination of a pre-charge circuit, NAND memory, ping-pong discharge path, comparator circuit, register circuit, and output circuit, and through the coordination of SL and BL voltages, high-low current switching is achieved, thereby reducing the power consumption of the memory array.
Reduce memory array power consumption by 50% during continuous reads, maximize the use of charge on the BL, and reduce additional voltage consumption.
Smart Images
Figure CN121601004A_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to the field of data interaction technology, and in particular to a NAND memory read circuit. [Background Technology]
[0002] In traditional NAND memory read / write schemes, such as Figure 1 As shown, reading from a voltage-type sensitive amplifier requires charging the memory block (BL) to a high level, then discharging the charge on BL through a memory cell, and finally reading the voltage on BL to obtain the result. This process is repeated to read the stored content from different memory cells. However, for scenarios such as in-memory computation, continuous read operations are required for MAC calculations, which significantly increases the power consumption of the read process. Therefore, it is urgent to reduce the power consumption during the read process to improve the energy efficiency of the computation. [Summary of the Invention]
[0003] This invention provides a NAND memory read circuit, which aims to solve the technical problems of large current consumption during the NAND memory read process in related technologies.
[0004] In a first aspect, embodiments of the present invention provide a NAND memory read circuit, comprising:
[0005] Precharge circuit, NAND memory, ping-pong discharge path, comparator circuit, register circuit and output circuit;
[0006] The pre-charge circuit is connected to the BL of the NAND memory and is used to pre-charge the NAND memory to a first high voltage or a first low voltage.
[0007] The NAND memory is used to read the first voltage signal of the pre-charge circuit and the second voltage signal of the ping-pong discharge circuit corresponding to the current cycle, and to control the entire circuit to enter the charging state or the discharging state according to the first voltage signal and the second voltage signal.
[0008] The ping-pong discharge path is connected to the SL of the NAND memory and is used to switch between a second high voltage and a second low voltage according to a first voltage signal read from the NAND memory.
[0009] The comparison circuit is connected to the BL of the NAND memory and the register circuit, and is used to compare the first voltage signal stored in the NAND memory with the reference voltage value and output the comparison result.
[0010] The register circuit is connected between the comparator circuit and the output circuit, and is used to store the second voltage signal corresponding to the previous cycle.
[0011] The output circuit is connected to the register circuit and the comparison circuit, and is used to output a corresponding output signal based on the comparison result and the second voltage signal.
[0012] In one embodiment, optionally, the circuit further includes:
[0013] A switching circuit, connected between the precharge circuit and the NAND memory, is used to control the on / off state of the circuit between the precharge circuit and the NAND memory.
[0014] In one embodiment, the pre-charge circuit may optionally include a NOT gate, a first PMOS transistor, and a first NMOS transistor;
[0015] The input terminal of the NOT gate is connected to the output control voltage, and the output terminal is connected to the first gate of the first PMOS transistor and the second gate of the first NMOS transistor.
[0016] The first source of the first PMOS transistor is connected to a first high voltage, and the first drain of the first PMOS transistor is connected to one end of the switching circuit.
[0017] The second drain of the first NMOS transistor is connected to a first low voltage, and the second source of the first NMOS transistor is connected to one end of the switching circuit.
[0018] In one embodiment, optionally, the comparison circuit includes a comparator, wherein the positive input of the comparator is connected to the pre-charge circuit, the negative input of the comparator is connected to a reference voltage, and the output of the comparator is connected to the register circuit.
[0019] In one embodiment, optionally, the register circuit includes a register, wherein the input of the register is connected to the comparator circuit, the output of the register is connected to the input of the output circuit, and the enable terminal of the register is connected to the output of the output circuit.
[0020] In one embodiment, optionally, the output circuit includes an XOR gate, the first input of which is connected to the output of the comparator circuit, the second input of which is connected to the output of the register, and the output of which is connected to the enable terminal of the register.
[0021] In one embodiment, optionally, the ping-pong discharge path includes a second PMOS transistor and a second NMOS transistor;
[0022] The third drain of the second PMOS transistor is connected to the SL of the NAND memory, the third source of the second PMOS transistor is connected to the second high voltage, and the third gate of the second PMOS transistor is connected to the output control voltage.
[0023] The fourth source of the second NMOS transistor is connected to the SL of the NAND memory, the fourth drain of the second NMOS transistor is connected to the second low voltage, and the fourth gate of the second NMOS transistor is connected to the output control voltage.
[0024] In one embodiment, optionally, when entering the charging state for the first time, the BL of the NAND memory is connected to the first high voltage, and the SL of the NAND memory is connected to the second low voltage.
[0025] In one embodiment, optionally, when the NAND memory reads a large current, it enters a discharge state. If the BL of the NAND memory was connected to the first high voltage during the previous cycle read, the BL of the NAND memory is switched to the first low voltage, and the SL of the NAND memory is switched to the second high voltage.
[0026] If the BL of the NAND memory was connected to the first low voltage during the previous read cycle, the BL of the NAND memory is switched to the first high voltage, and the SL of the NAND memory is switched to the second low voltage.
[0027] In one embodiment, optionally, when the NAND memory reads a small current, the BL connection of the NAND memory remains unchanged, and the SL connection of the NAND memory remains unchanged.
[0028] The NAND flash memory read circuit of this invention includes: a precharge circuit, a NAND flash memory, a ping-pong discharge path, a comparator circuit, a register circuit, and an output circuit. The precharge circuit is connected to the BL of the NAND flash memory and is used to precharge the NAND flash memory to a first high voltage or a first low voltage. The NAND flash memory is used to read the first voltage signal of the precharge circuit and the second voltage signal of the ping-pong discharge path corresponding to the current cycle, and to control the entire circuit to enter a charging state or a discharging state based on the first and second voltage signals. The ping-pong discharge path is connected to the SL of the NAND flash memory and is used to switch between a second high voltage and a second low voltage based on the first voltage signal read from the NAND flash memory. The comparator circuit is connected to the BL of the NAND flash memory and the register circuit, and is used to compare the first voltage signal stored in the NAND flash memory with a reference voltage value and output a comparison result. The register circuit is connected between the comparator circuit and the output circuit and is used to store the second voltage signal corresponding to the previous cycle. The output circuit is connected to the register circuit and the comparator circuit and is used to output a corresponding output signal based on the comparison result and the second voltage signal. In this invention, by adding a ping-pong discharge path, a register circuit, a comparison circuit, and an output circuit, the storage result can be read by using high and low currents during continuous reading through the coordination of SL and BL voltages. This can reduce the power consumption of the memory array by 50%, thereby maximizing the utilization of the charge on BL and reducing additional replenishment consumption, as well as reducing the voltage required for pre-charging. [Attached Image Description]
[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 A schematic block diagram of an instrumentation amplifier circuit for a resistive sensor is shown in the related art.
[0031] Figure 2 A schematic diagram of a NAND memory read circuit according to an embodiment of the present invention is shown.
[0032] Figure 3 A schematic diagram of a NAND memory read circuit according to another embodiment of the present invention is shown.
[0033] Figure 4 A schematic diagram of the specific structure of a NAND memory read circuit according to an embodiment of the present invention is shown.
Detailed Implementation Methods
[0034] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0035] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0036] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0037] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0038] Please see Figure 2 , Figure 2 A schematic block diagram of a NAND memory read circuit according to an embodiment of the present invention is shown. This NAND memory read circuit is used to solve technical problems such as high current consumption during NAND memory read operations in related technologies.
[0039] like Figure 2 As shown, a NAND memory read circuit according to an embodiment of the present invention includes:
[0040] The circuit consists of: 1. Precharge circuit; 2. NAND memory; 3. Ping-pong discharge path; 4. Comparison circuit; 6. Register circuit; and 5. Output circuit.
[0041] The pre-charge circuit 1 is connected to the BL of the NAND memory and is used to pre-charge the NAND memory to a first high voltage or a first low voltage.
[0042] The NAND memory 2 is used to read the first voltage signal of the pre-charge circuit and the second voltage signal of the ping-pong discharge circuit corresponding to the current cycle, and to control the entire circuit to enter the charging state or the discharging state according to the first voltage signal and the second voltage signal.
[0043] The ping-pong discharge path 3 is connected to the SL of the NAND memory and is used to switch between a second high voltage and a second low voltage according to a first voltage signal read from the NAND memory.
[0044] The comparison circuit 4 is connected to the BL of the NAND memory and the register circuit, and is used to compare the first voltage signal stored in the NAND memory with the reference voltage value and output the comparison result.
[0045] The register circuit 6 is connected between the comparator circuit and the output circuit, and is used to store the second voltage signal corresponding to the previous cycle.
[0046] The output circuit 5 is connected to the register circuit and the comparison circuit, and is used to output a corresponding output signal according to the comparison result and the second voltage signal.
[0047] like Figure 3 As shown, in one embodiment, optionally, the circuit further includes:
[0048] The switching circuit 7 is connected between the precharge circuit 1 and the NAND memory 2, and is used to control the on / off state of the circuit between the precharge circuit 1 and the NAND memory 2.
[0049] like Figure 4 As shown, in one embodiment, optionally, the pre-charge circuit 1 includes a NOT gate, a first PMOS transistor, and a first NMOS transistor;
[0050] The input terminal of the NOT gate is connected to the output control voltage, and the output terminal is connected to the first gate of the first PMOS transistor and the second gate of the first NMOS transistor.
[0051] The first source of the first PMOS transistor is connected to a first high voltage, and the first drain of the first PMOS transistor is connected to one end of the switching circuit.
[0052] The second drain of the first NMOS transistor is connected to a first low voltage, and the second source of the first NMOS transistor is connected to one end of the switching circuit.
[0053] In one embodiment, optionally, the comparison circuit 4 includes a comparator, wherein the positive input terminal of the comparator is connected to the pre-charge circuit, the negative input terminal of the comparator is connected to the reference voltage, and the output terminal of the comparator is connected to the register circuit.
[0054] In one embodiment, optionally, the register circuit 6 includes a register, wherein the input terminal of the register is connected to the comparator circuit, the output terminal of the register is connected to the input terminal of the output circuit, and the enable terminal of the register is connected to the output terminal of the output circuit.
[0055] In one embodiment, optionally, the output circuit 5 includes an XOR gate, the first input of which is connected to the output of the comparator circuit, the second input of which is connected to the output of the register, and the output of which is connected to the enable terminal of the register.
[0056] In one embodiment, optionally, the ping-pong discharge path 3 includes a second PMOS transistor and a second NMOS transistor;
[0057] The third drain of the second PMOS transistor is connected to the SL of the NAND memory, the third source of the second PMOS transistor is connected to the second high voltage, and the third gate of the second PMOS transistor is connected to the output control voltage.
[0058] The fourth source of the second NMOS transistor is connected to the SL of the NAND memory, the fourth drain of the second NMOS transistor is connected to the second low voltage, and the fourth gate of the second NMOS transistor is connected to the output control voltage.
[0059] In one embodiment, optionally, when entering the charging state for the first time, the BL of the NAND memory is connected to the first high voltage, and the SL of the NAND memory is connected to the second low voltage.
[0060] In one embodiment, optionally, when the NAND memory reads a large current, it enters a discharge state. If the BL of the NAND memory was connected to the first high voltage during the previous cycle read, the BL of the NAND memory is switched to the first low voltage, and the SL of the NAND memory is switched to the second high voltage.
[0061] If the BL of the NAND memory was connected to the first low voltage during the previous read cycle, the BL of the NAND memory is switched to the first high voltage, and the SL of the NAND memory is switched to the second low voltage.
[0062] In one embodiment, optionally, when the NAND memory reads a small current, the BL connection of the NAND memory remains unchanged, and the SL connection of the NAND memory remains unchanged.
[0063] like Figure 4As shown, the NAND memory read circuit operates as follows: First, initialization is performed, the register is stored as 1, and BL is pre-charged to the first high voltage VBL_H. The reference voltage VREF can be the midpoint between VBL_H and VBL_L. In the first cycle, a target WL is selected, i.e., data is read from the target WL. Thus, input is obtained from the target WL, all other WLs are open, and BL leaks to SL. If the selected target WL stores a value of 1 (vth is small), the BL voltage is close to VSL_L, the comparator outputs 0, and the XORed output OUT is 1, which is the read result. The register is then updated to 0. In the second cycle, BL is pre-charged to VBL_L (requiring less power), a target WL is selected, input is obtained from the target WL, all other WLs are open, and BL leaks to SL, which is connected to VSL_H. If the selected target WL stores a value of 0 (vth is large), the BL voltage drops less, the comparator outputs 0, and the XORed output is 0. In other words, when a value of 1 is read (high current), the pre-charge circuit connected to BL will switch the pre-charge voltage, and the discharge voltage connected to SL will also switch, ensuring that the minimum charge can be pre-charged in the next cycle. When a value of 0 is read (low current), the directions of BL and SL do not change, which is consistent with the traditional structure.
[0064] It should be noted that the circuit function of the NAND memory read circuit provided in this embodiment is mainly realized through the circuit connection relationship between various circuit modules, and does not depend on the program module in a particular circuit module. Furthermore, the various circuit modules in the NAND memory read circuit can be implemented using analog circuits or digital circuits, and for circuit modules that can be programmed, their module functions can be implemented using program modules provided by existing technologies.
[0065] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0066] It should be understood that although the terms "first," "second," etc., may be used to describe the setting units in the embodiments of the present invention, these setting units should not be limited to these terms. These terms are only used to distinguish the setting units from each other. For example, without departing from the scope of the embodiments of the present invention, the first setting unit may also be referred to as the second setting unit, and similarly, the second setting unit may also be referred to as the first setting unit.
[0067] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."
[0068] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between systems or units may be electrical, mechanical, or other forms.
[0069] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.
[0070] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A NAND memory read circuit, characterized in that, include: Precharge circuit, NAND memory, ping-pong discharge path, comparator circuit, register circuit and output circuit; The pre-charge circuit is connected to the BL of the NAND memory and is used to pre-charge the NAND memory to a first high voltage or a first low voltage. The NAND memory is used to read the first voltage signal of the pre-charge circuit and the second voltage signal of the ping-pong discharge circuit corresponding to the current cycle, and to control the entire circuit to enter the charging state or the discharging state according to the first voltage signal and the second voltage signal. The ping-pong discharge path is connected to the SL of the NAND memory and is used to switch between a second high voltage and a second low voltage according to a first voltage signal read from the NAND memory. The comparison circuit is connected to the BL of the NAND memory and the register circuit, and is used to compare the first voltage signal stored in the NAND memory with the reference voltage value and output the comparison result. The register circuit is connected between the comparator circuit and the output circuit, and is used to store the second voltage signal corresponding to the previous cycle. The output circuit is connected to the register circuit and the comparison circuit, and is used to output a corresponding output signal based on the comparison result and the second voltage signal.
2. The NAND memory read circuit according to claim 1, characterized in that, The circuit also includes: A switching circuit, connected between the precharge circuit and the NAND memory, is used to control the on / off state of the circuit between the precharge circuit and the NAND memory.
3. The NAND memory read circuit according to claim 2, characterized in that, The pre-charge circuit includes a NOT gate, a first PMOS transistor, and a first NMOS transistor; The input terminal of the NOT gate is connected to the output control voltage, and the output terminal is connected to the first gate of the first PMOS transistor and the second gate of the first NMOS transistor. The first source of the first PMOS transistor is connected to a first high voltage, and the first drain of the first PMOS transistor is connected to one end of the switching circuit. The second drain of the first NMOS transistor is connected to a first low voltage, and the second source of the first NMOS transistor is connected to one end of the switching circuit.
4. The NAND memory read circuit according to claim 1, characterized in that, The comparison circuit includes a comparator, wherein the positive input terminal of the comparator is connected to the pre-charge circuit, the negative input terminal of the comparator is connected to the reference voltage, and the output terminal of the comparator is connected to the register circuit.
5. The NAND memory read circuit according to claim 1, characterized in that, The register circuit includes a register, wherein the input terminal of the register is connected to the comparator circuit, the output terminal of the register is connected to the input terminal of the output circuit, and the enable terminal of the register is connected to the output terminal of the output circuit.
6. The NAND memory read circuit according to claim 1, characterized in that, The output circuit includes an XOR gate, the first input of which is connected to the output of the comparator circuit, the second input of which is connected to the output of the register, and the output of which is connected to the enable terminal of the register.
7. The NAND memory read circuit according to claim 1, characterized in that, The ping-pong discharge path includes a second PMOS transistor and a second NMOS transistor; The third drain of the second PMOS transistor is connected to the SL of the NAND memory, the third source of the second PMOS transistor is connected to the second high voltage, and the third gate of the second PMOS transistor is connected to the output control voltage. The fourth source of the second NMOS transistor is connected to the SL of the NAND memory, the fourth drain of the second NMOS transistor is connected to the second low voltage, and the fourth gate of the second NMOS transistor is connected to the output control voltage.
8. The NAND memory read circuit according to claim 1, characterized in that, When the NAND flash memory first enters the charging state, its BL is connected to the first high voltage, and its SL is connected to the second low voltage.
9. The NAND memory read circuit according to claim 8, characterized in that, When the NAND memory reads a large current, it enters a discharge state. If the BL of the NAND memory was connected to the first high voltage during the previous cycle, the BL of the NAND memory is switched to the first low voltage, and the SL of the NAND memory is switched to the second high voltage. If the BL of the NAND memory was connected to the first low voltage during the previous read cycle, the BL of the NAND memory is switched to the first high voltage, and the SL of the NAND memory is switched to the second low voltage.
10. The NAND memory read circuit according to claim 9, characterized in that, When the NAND memory reads a small current, the BL connection of the NAND memory remains unchanged, and the SL connection of the NAND memory remains unchanged.