Novel long-wavelength vertical plane emitting laser

Abstract

The invention discloses a novel long-wavelength vertical plane emitting laser, which relates to the technical field of lasers and comprises a substrate, a bottom GaAs-based DBR (Distributed Bragg Reflector), a first Van der Waals buffer layer, a long-wavelength resonant cavity, a second Van der Waals buffer layer and a top GaAs-based DBR which are sequentially arranged from bottom to top, the first Van der Waals buffer layer and the second Van der Waals buffer layer are both graphene. The technical bottleneck limited by a material system is broken through, heterogeneous integration of the bottom GaAs-based DBR, the long-wavelength resonant cavity and the top GaAs-based DBR is achieved through the two Van der Waals buffer layers, then the purpose of monolithic integration of the high-performance long-wavelength active area and the high-performance GaAs-based DBR reflector is achieved, a new way is opened up for mass production of the high-performance and low-cost long-wavelength VCSEL, and the large-scale production of the high-performance and low-cost long-wavelength VCSEL is achieved. The method has great significance in the fields of optical communication, sensing and the like.

Description

Technical Field

[0001] This invention relates to the field of laser technology, and in particular to a novel long-wavelength vertical-plane emitting laser. Background Technology

[0002] A Vertical Cavity Surface Emitting Laser (VCSEL) is a semiconductor device that emits laser light perpendicular to the substrate surface. It is characterized by its small size, high beam quality, and array integration capabilities, and is widely used in optical communication, facial recognition, and laser sensing. According to common wavelength standards in the optoelectronic industry, VCSELs can be divided into short-wavelength VCSELs and long-wavelength VCSELs. Short-wavelength VCSELs typically refer to the 650-1100nm band and are mainly based on GaAs / AlGaAs materials. Long-wavelength VCSELs typically refer to the 1200-1650nm band and are mainly based on InP / InGaAsP or InGaAsP / InAlGaAs materials.

[0003] Due to differences in material systems, manufacturing processes, and performance requirements, long-wavelength VCSELs face a fundamental bottleneck: the inability to monolithically integrate high-performance active regions and high-performance DBR mirrors. Specifically, high-performance active regions refer to long-wavelength active regions based on InP / InGaAsP and other material systems. Their adaptability to long-wavelength scenarios, inherent carrier recombination advantages, and flexible performance optimization space enable long-wavelength VCSELs to exhibit performance value that short-wavelength VCSELs cannot replace in fields such as long-distance optical communication and medical sensing. High-performance DBR mirrors refer to GaAs-based DBR mirrors. These mirrors possess high reflectivity, providing efficient optical feedback for GaAs-based short-wavelength VCSELs. Furthermore, they exhibit good lattice matching with GaAs-based short-wavelength VCSELs, have low manufacturing difficulty, and are easily mass-produced at low cost.

[0004] The main reasons why high-performance active regions and high-performance DBR mirrors cannot be monolithically integrated in long-wavelength VCSELs are as follows: 1. Huge lattice mismatch: The lattice constant mismatch between the long-wavelength active region material system and the GaAs-based material system is as high as 3.7%. During direct epitaxial growth, a large number of penetrating dislocations will be generated at the interface. These dislocations will extend to the active region and become non-radiative recombination centers, resulting in a significant reduction in the luminous efficiency of the device, or even direct failure.

[0005] 2. Mismatch in thermal expansion coefficients: There is a significant difference in the thermal expansion coefficients between long-wavelength active region material systems and GaAs-based material systems. During the process of cooling from high temperature growth to room temperature in traditional epitaxial processes, huge thermal stress will be generated between materials due to the difference in thermal contraction, leading to wafer warping and thin film cracking, which further reduces the yield and reliability of devices.

[0006] 3. For long-wavelength active region materials and GaAs-based materials, the direct epitaxy of different material systems in traditional epitaxial growth processes can lead to interface defects such as antiphase domains due to polarity discontinuity, which can damage the carrier transport path and the integrity of the optical resonator, thus limiting device performance.

[0007] Due to the inability to use high-performance DBR mirrors in short-wavelength VCSELs, existing long-wavelength VCSELs typically employ semiconductor DBR materials with relatively low reflectivity. However, this leads to numerous insurmountable shortcomings in practical applications. For example, with a 1550nm indium phosphide-based VCSEL: if lattice-matched semiconductor materials like InGaAsP / InP or InAlGaAs / InAlAs are used, the thickness of the top DBR mirror needs to be increased to 8μm to achieve 99% reflectivity. Excessive DBR thickness significantly increases light absorption loss, leading to higher device threshold current and insertion loss. Simultaneously, thicker layers increase series resistance, exacerbating heat dissipation difficulties. Furthermore, the high reflectivity requirements necessitate a large number of DBR layers, demanding precise control over the thickness and composition of each layer, significantly increasing fabrication complexity and production costs. Therefore, the key bottleneck of existing long-wavelength VCSELs lies in the inability to achieve monolithic integration of high-reflectivity GaAs-based DBRs with long-wavelength active regions, severely limiting device efficiency and reliability.

[0008] In summary, overcoming the technical bottlenecks limited by long-wavelength VCSEL material systems and achieving monolithic integration of high-performance long-wavelength active regions and high-performance GaAs-based DBR mirrors, thereby enabling long-wavelength VCSELs to meet the demands of high power, low power consumption, and low-cost mass production, is a crucial research direction for long-wavelength VCSELs to escape the performance and cost dilemmas. Summary of the Invention

[0009] This invention provides a novel long-wavelength vertical surface emitting laser, the main purpose of which is to solve the problem that the long-wavelength active region of existing long-wavelength VCSELs is incompatible with GaAs-based DBR mirrors.

[0010] The present invention adopts the following technical solution: A novel long-wavelength vertical-plane emitting laser includes, from bottom to top, a substrate, a bottom GaAs-based digital laser (DBR), a first van der Waals buffer layer, a long-wavelength resonant cavity, a second van der Waals buffer layer, and a top GaAs-based DBR; both the first and second van der Waals buffer layers are graphene; the bottom GaAs-based DBR and the long-wavelength resonant cavity are heterogeneously integrated through the first van der Waals buffer layer, and the long-wavelength resonant cavity and the top GaAs-based DBR are heterogeneously integrated through the second van der Waals buffer layer; the bottom GaAs-based DBR, the first van der Waals buffer layer, the second van der Waals buffer layer, and the top GaAs-based DBR together constitute a multi-dimensional thermal management network.

[0011] Furthermore, the long-wavelength resonant cavity includes, from bottom to top, a first N-type doped layer, an active region, a P-type doped layer, a tunnel junction, and a second N-type doped layer.

[0012] Furthermore, both the bottom GaAs-based DBR and the top GaAs-based DBR are AlGaAs material systems, and the active region is an InGaAsP / InGaAsP or InGaAsP / InAlGaAs multi-quantum-well active region.

[0013] Furthermore, both the first van der Waals buffer layer and the second van der Waals buffer layer are located at the standing wave nodes within the long-wavelength resonant cavity.

[0014] Furthermore, the substrate is a GaAs substrate.

[0015] Furthermore, the substrate is an InP substrate, and a third van der Waals buffer layer is provided between the InP substrate and the bottom GaAs-based DBR.

[0016] Furthermore, the substrate is a GaN substrate, and a nitride layer, a third van der Waals buffer layer, a nucleation layer and a gradient buffer layer are provided between the GaN substrate and the bottom GaAs-based DBR.

[0017] Furthermore, the substrate is a SiC substrate, and a third van der Waals buffer layer, a nucleation layer, and a gradient buffer layer are provided between the SiC substrate and the bottom GaAs-based DBR.

[0018] Furthermore, the substrate is a Si substrate, and an anti-reflow layer and a superlattice buffer layer are provided between the Si substrate and the bottom GaAs-based DBR.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention breaks through the technical bottleneck of material system limitations. It achieves heterogeneous integration of the bottom GaAs-based DBR, the long-wavelength resonant cavity and the top GaAs-based DBR through two van der Waals buffer layers, thereby realizing the monolithic integration of the high-performance long-wavelength active region and the high-performance GaAs-based DBR mirror. This opens up a new path for the mass production of high-performance, low-cost long-wavelength VCSELs and has great significance for optical communication, sensing and other fields.

[0020] 2. This invention fully utilizes the high in-plane thermal conductivity (approximately 2000-5000 W / m·K) of two van der Waals buffer layers (such as graphene), deeply integrating them into the core of the chip architecture. Together with the bottom GaAs-based DBR and bottom GaAs-based DBR, they form a multi-dimensional thermal management network with high lateral thermal conductivity and low longitudinal thermal resistance, which significantly improves the heat dissipation performance of InP-based long-wavelength VCSELs, thus laying a solid foundation for manufacturing high-performance, high-power, and high-reliability devices. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0022] Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0023] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention.

[0024] Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention.

[0025] Figure 5 This is a schematic diagram of the structure of Embodiment 5 of the present invention.

[0026] In the figure: 1-substrate; 11-nitride layer; 2-bottom GaAs-based DBR; 3-first van der Waals buffer layer; 4-long wavelength resonant cavity; 41-first N-type doped layer; 42-active region; 43-P-type doped layer; 44-tunnel junction; 45-second N-type doped layer; 5-second van der Waals buffer layer; 6-top GaAs-based DBR; 7-third van der Waals buffer layer; 71-nucleation layer; 72-gradient buffer layer; 73-anti-reflow layer; 74-superlattice buffer layer; 8-first N-type electrode; 9-second N-type electrode. Detailed Implementation

[0027] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. Many details are described below to provide a comprehensive understanding of the invention; however, those skilled in the art will be able to implement the invention without these details. Example

[0028] like Figure 1 This embodiment provides a novel long-wavelength vertical-plane emitting laser, comprising, from bottom to top, a substrate 1, a bottom GaAs-based DBR2, a first van der Waals buffer layer 3, a long-wavelength resonant cavity 4, a second van der Waals buffer layer 5, and a top GaAs-based DBR6. The long-wavelength resonant cavity 4, from bottom to top, includes a first N-type doped layer 41, an active region 42, a P-type doped layer 43, a tunnel junction 44, and a second N-type doped layer 45. The bottom GaAs-based DBR2 and the long-wavelength resonant cavity 4 are heterogeneously integrated through the first van der Waals buffer layer 3, and the long-wavelength resonant cavity 4 and the top GaAs-based DBR6 are heterogeneously integrated through the second van der Waals buffer layer 5. Furthermore, the bottom GaAs-based DBR2, the first van der Waals buffer layer 3, the second van der Waals buffer layer 5, and the top GaAs-based DBR6 together constitute a multi-dimensional thermal management network.

[0029] To more clearly illustrate the design principles of this embodiment, the functions and material composition of each layer in the structure are described in detail below: Substrate 1: Substrate 1 is used to provide mechanical support and crystal growth template. In this embodiment, it is preferably a GaAs substrate that best matches the bottom GaAs-based DBR2 lattice.

[0030] Bottom GaAs-based DBR2: The bottom GaAs-based DBR2 and the top GaAs-based DBR6 form the resonant cavity of the laser, providing the main optical feedback. Since the first van der Waals buffer layer 3 enables heterogeneous integration of the bottom GaAs-based DBR2 and the long-wavelength resonant cavity 4, this embodiment can apply the high-performance GaAs-based semiconductor DBR material used in short-wavelength VCSELs to long-wavelength VCSELs. Specifically, the bottom GaAs-based DBR2 is an AlGaAs material system. Due to the high refractive index contrast of the AlGaAs material system, high reflectivity is achieved with a small number of layer pairs, thereby significantly reducing series resistance and optical loss. Preferably, the bottom GaAs-based DBR2 is made of Al... i Ga 1-i As / Al j Ga 1-j Periodic structures made of As materials, such as Al 0.12 Ga 0.8 8As / Al 0.9 Ga 0.1 As material pairs, the number of layer pairs is 30-35, and the optical thickness of each layer is λ / 4.

[0031] First van der Waals buffer layer 3: The first van der Waals buffer layer 3 is a two-dimensional material layer, preferably graphene in this embodiment. Its main function is to act as a lattice mismatch buffer layer, thereby realizing the heterogeneous integration of the bottom GaAs-based DBR2 and the long-wavelength resonant cavity 4. The first van der Waals buffer layer 3 is mainly 1-2 layers, and needs to be optimized for ohmic contact with the upper and lower materials. The graphene layer is lightly chemically doped with p-type or n-type to ensure the stability of current transmission.

[0032] The first N-type doped layer 41: The main function of the first N-type doped layer 41 is to efficiently transport electrons to the active region 42, and at the same time participate in the construction of the long-wavelength resonant cavity 4. In this embodiment, the first N-type doped layer 41 is made of InP-based semiconductor material and is doped with N-type Si at a concentration of 1-2 × 10⁻⁶. 18 cm -3 The thickness design needs to meet the dual requirements of current expansion and optical cavity length, and is usually designed to be 100-200nm.

[0033] Active Region 42: Active Region 42 is the "heart" of the VCSEL, responsible for generating stimulated emission through carrier recombination, thus emitting laser light. Active Region 42 employs a multi-quantum-well structure, with the material system rationally selected based on different wavelengths. Specifically, if the wavelength of Active Region 42 is 1-2 μm, InGaAsP / InGaAsP or InGaAsP / InAlGaAs material systems are selected. As a preferred embodiment, the active region 42 in this embodiment uses an InGaAsP / InGaAsP or InGaAsP / InAlGaAs material system, with InGaAsP quantum wells. By adjusting the As / P ratio, the emission wavelength reaches 1.55 μm. The barrier layer is InGaAsP or InAlGaAs, with 3-5 quantum wells, a well layer thickness of 7-10 nm, and a barrier layer thickness of 10-15 nm.

[0034] P-type doped layer 43: The function of the P-type doped layer 43 is to efficiently transport holes to the active region 42, and to compensate for insufficient hole mobility through a high doping concentration, thus ensuring carrier transport efficiency. The P-type doped layer 43 is made of InP-based semiconductor material and is doped with P-type Zn at a concentration of 2-3 × 10⁻⁶. 18 cm -3 The thickness of the p-type doped layer 43 is slightly higher than that of the first N-type doped layer 41; the thickness of the p-type doped layer 43 is 100-200 nm, consistent with that of the first N-type doped layer 41.

[0035] Tunneling junction 44: The core function of tunneling junction 44 is to convert hole flow into electron flow, which is crucial for the chip to adopt a top-type N-type DBR. Tunneling junction 44 is composed of a P++ layer (InGaAs or InAlGaAs, C or Zn doped) and an N++ layer (InAlAs or InGaAs, Si doped). Both layers are 10-20 nm thick, and to ensure efficient tunneling, a thickness of 1 × 10⁻⁶ nm should be maintained. 20 cm -3 The above are high doping concentrations.

[0036] The second N-type doped layer 45: The function of the second N-type doped layer 45 is to form a complete current channel together with the underlying first N-type doped layer 41, ensuring stable current transmission from bottom to top. Similarly, the second N-type doped layer 45 is made of InP-based semiconductor material and uses N-type Si doping with a concentration of 1-2 × 10⁻⁶. 18 cm -3 Thickness 100-200nm.

[0037] Second van der Waals buffer layer 5: The second van der Waals buffer layer 5 is also a two-dimensional material layer, preferably graphene in this embodiment. Its main function is to act as a lattice mismatch buffer layer and provide a high lateral thermal conductivity channel, thereby realizing the heterogeneous integration of the long-wavelength resonant cavity 4 and the top GaAs-based DBR6. The parameters of the second van der Waals buffer layer 5 are the same as those of the first van der Waals buffer layer 3, and the number of layers is either single or double, ensuring stable connection between modules and smooth current transmission.

[0038] Top GaAs-based DBR6: The top GaAs-based DBR6 and the bottom GaAs-based DBR2 form a resonant cavity to regulate optical feedback and laser output, ultimately achieving stable laser emission. Due to the introduction of the tunnel junction 44, the top GaAs-based DBR6 uses an N-type GaAs-based DBR, which significantly reduces the device's series resistance and operating voltage, improving electro-optical conversion efficiency and output power. Like the bottom GaAs-based DBR2, the top GaAs-based DBR6 is an AlGaAs system. The top GaAs-based DBR6 has 20-25 layer pairs, and the thickness and doping requirements of each layer are consistent with those of the bottom GaAs-based DBR2.

[0039] In this embodiment, both the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5 are made of graphene. Single-layer graphene has extremely low light absorption (approximately 2.3%), and the optical phase change introduced by its atomic-level thickness is negligible. Therefore, inserting it into the long-wavelength resonant cavity 4 causes minimal disturbance to the optical field, does not significantly increase cavity loss, or disrupt laser oscillation conditions, and ensures the high Q value of the long-wavelength resonant cavity 4. This makes the heterogeneous integration concept of this embodiment feasible. Although the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5 are located at different positions in the epitaxial structure, their main functions include the following: (1) Lattice mismatch and stress buffering effect: Graphene has an atomically flat surface without dangling bonds. Its van der Waals bonding characteristics can significantly weaken the interfacial bonding energy between the epitaxial layer and the substrate, allowing the epitaxial layer to spontaneously release mismatch strain on the graphene "slip" interface while maintaining crystal orientation matching. Unlike traditional heteroepitaxial growth, which releases strain energy by forming dislocations, the low interfacial energy of the graphene interface provides another defect-free strain release pathway, thereby effectively suppressing the generation of high-density dislocations and related defects. This "van der Waals buffer layer" mechanism not only isolates the lattice mismatch and thermal mismatch stress between the two material systems, but also breaks through the technical bottleneck of material system limitations, enabling single-crystal epitaxial growth under conditions of large lattice mismatch, providing a feasible path for monolithic heterogeneous integration of long-wavelength active regions and GaAs-based DBR mirrors.

[0040] (2) Current transport function: Vertical current transport exists within long-wavelength VCSELs, while graphene has extremely high in-plane conductivity (10). 6 -10 7 Therefore, it can serve as a low-resistance, high-efficiency current injection channel, which helps to achieve lateral current diffusion within the epitaxial layer, thereby improving the uniformity of current distribution and thus enhancing the overall performance of the device.

[0041] (3) Heat dissipation: The in-plane thermal conductivity of graphene can reach 5000W / mK, which is one of the materials with the highest known thermal conductivity. The two graphene layers above and below the active region 42 can form a thermal management network that wraps around the active region 42, which can quickly dissipate the heat generated and avoid the formation of local hot spots. This greatly improves the heat dissipation performance of the chip, which is crucial for improving the power, efficiency and long-term reliability of long-wavelength VCSELs.

[0042] (4) Performance synergy optimization with tunnel junction 44: On the one hand, tunnel junction 44 is the optimal solution for current and optical field confinement in long-wavelength VCSELs in the prior art. However, tunnel junction 44 itself introduces a certain series resistance. The two layers of graphene located above and below tunnel junction 44, based on their excellent current diffusion effect, can greatly compensate for this resistance, ensuring that the current can be injected into tunnel junction 44 with low loss, thereby alleviating the problem of high resistance. On the other hand, tunnel junction 44 confines the gain region to a specific small range. The two layers of graphene located above and below tunnel junction 44, based on their excellent heat diffusion effect, can more concentratedly and efficiently diffuse the heat of the core heat-generating area in this small range, thereby further improving the overall heat dissipation efficiency. It can be seen that in this embodiment, tunnel junction 44 and the two layers of graphene above and below it can form an ideal combination with complementary functions and synergistic effect.

[0043] like Figure 1As shown, in this embodiment, the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5 are not independent, passive insertion layers. Their parameters are profoundly and multidimensionally interdependent and influenced by the selection of the entire epitaxial structure. This interaction directly determines the feasibility of the scheme and the performance of the final device. Therefore, the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5 should be designed and optimized in conjunction with other epitaxial structures during the design process. The following section analyzes in detail the design considerations of the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5 based on several core parameters: 1. Number of layers: The number (thickness) of the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5 is one of the most critical parameters, mainly affecting the lattice mismatch buffering effect and electrical / optical properties. As a preferred option, the number of graphene layers in this embodiment is preferably 1-2 layers, and the following three factors are considered: (1) Constraints of the underlying epitaxial structure: The epitaxial growth characteristics of graphene depend on its shielding effect on the substrate charge density, which is directly determined by the thickness. With 1-2 layers of graphene, the weak van der Waals potential allows the substrate to interact with the epitaxial layer, thus supporting epitaxial growth. Conversely, if the number of graphene layers increases (e.g., 3-5 layers), its strong van der Waals potential will shield the substrate charge density, making epitaxial growth impossible. Therefore, 1-2 layers of graphene are the optimal choice for achieving high-quality epitaxial growth. In practical applications, the surface flatness of the underlying epitaxial structure should be ensured to reach the atomic level to guarantee the continuity of graphene and the high quality of epitaxial growth.

[0044] (2) Constraints on Current Transport: Graphene is an excellent conductor. Single-layer graphene has extremely low in-plane resistance, benefiting from its high electron mobility and two-dimensional structure, resulting in strong lateral current expansion capability. Simultaneously, single-layer graphene has low out-of-plane resistance, with less restriction on vertical electron migration, leading to high injection efficiency. As the number of layers increases, the in-plane resistance increases slightly, mainly due to enhanced interlayer interactions leading to electron scattering; the out-of-plane resistance increases significantly because the interlayer van der Waals forces are weak, hindering electron migration in the vertical direction. Therefore, in design, 1-2 layers of graphene should be preferred to obtain the best current expansion and injection efficiency.

[0045] (3) Constraints related to optical properties: There is a close relationship between the transmittance of graphene and the number of layers. In the 1-2 μm band, monolayer graphene has a light absorption rate of about 2.3% and a high transmittance, making it suitable for applications in this band. As the number of layers increases, light absorption and transmittance gradually deteriorate. Therefore, monolayer graphene performs best in this band and is the ideal choice for achieving good optical performance.

[0046] 2. Work Function: The work function of graphene is approximately 4.5-4.7 eV. Its work function primarily affects the electrical contact with adjacent upper and lower epitaxial structures. Ideally, it should form ohmic contacts or a low Schottky barrier with both upper and lower epitaxial structures to facilitate hole injection. Therefore, materials with better work function matching should be selected during the design process.

[0047] 3. Position: The optical properties of graphene primarily affect the light field distribution, making its position within the epitaxial structure particularly important. Although monolayer graphene has extremely low light absorption, to avoid unnecessary optical losses in the resonant cavity, it can be precisely placed at the standing wave nodes (the weakest points of light intensity) of the resonant cavity's optical field during optical design to minimize absorption losses. This, in turn, constrains the thickness of other epitaxial structures and the position of the entire active region 42 relative to the two graphene layers, as these parameters collectively determine the distribution of the light field within the cavity.

[0048] like Figure 1 As shown, although graphene's high thermal conductivity is a recognized advantage, in this embodiment, graphene is not an isolated heat sink. Instead, it is deeply integrated into the core of the chip architecture, leveraging its high thermal conductivity to achieve a synergistic heat dissipation effect greater than the sum of its parts (1+1>2) through a dual approach of heat reduction at the source and multi-dimensional thermal management. This systematically solves the heat dissipation problem of InP-based long-wavelength VCSELs, thus laying a solid foundation for manufacturing high-performance, high-power, and high-reliability devices. The following is a detailed analysis of the heat dissipation principle of graphene: (1) Heat Reduction at the Source: In this embodiment, graphene is used as a lattice mismatch buffer layer, and GaAs-based semiconductor DBR material is applied to InP-based long-wavelength VCSEL. Since the resistance of GaAs-based semiconductor DBR material is much lower than that of InP-based semiconductor DBR material, the use of GaAs-based semiconductor DBR material can significantly reduce the series resistance of the device, thereby reducing Joule heat generation. It can be seen that the introduction of graphene can indirectly reduce the total heat that the device needs to dissipate, thus alleviating the heat dissipation burden at the source.

[0049] (2) Lateral heat dissipation: The active region 42 is the heat center of VCSEL. The two layers of graphene located above and below the active region 42 can act like a heat fan to quickly diffuse the heat of the active region 42 laterally and disperse it to a larger area, thereby avoiding the formation of fatal local high temperature near the active region 42. It can be seen that the two layers of graphene embedded in the device can play a localized lateral heat dissipation effect.

[0050] (3) Vertical heat dissipation: Traditional InP-based semiconductor DBR materials have low refractive index contrast and large thickness, resulting in very low lateral and vertical thermal conductivity of both the bottom and top InP-based DBRs, thus leading to poor heat dissipation. However, due to the lattice mismatch buffering effect of graphene, the high-contrast GaAs-based semiconductor DBR material can be adapted to the InP-based active region 42, thereby significantly reducing the number of layers in the bottom GaAs-based DBR2 and top GaAs-based DBR6 and significantly improving the thermal conductivity. It can be seen that graphene can synergistically provide multiple heat dissipation effects, forming a multi-dimensional thermal management network of "high lateral thermal conductivity + low vertical thermal resistance" together with the bottom GaAs-based DBR2 and top GaAs-based DBR6, which significantly improves the heat dissipation performance of InP-based long-wavelength VCSELs.

[0051] like Figure 1 As shown, this embodiment also provides a novel method for fabricating a long-wavelength vertical-plane emitting laser, comprising the following steps: (1) Grow bottom GaAs-based DBR2 on GaAs substrate using MOCVD or MBE process.

[0052] (2) A first van der Waals buffer layer 3 is prepared on the bottom GaAs-based DBR2. Specifically, the CVD-grown monolayer graphene is transferred from the copper foil to the bottom GaAs-based DBR2. The CVD-grown monolayer graphene is synthesized on the copper foil by low-pressure chemical vapor deposition (LPCVD), and its preparation process is existing technology and will not be described in detail here. The graphene transfer process includes the following steps: (2.1) Polymethyl methacrylate (PMMA) is spin-coated onto graphene and baked at a specified temperature. Preferably, the graphene spin-coated with PMMA is baked at 80°C for 10 minutes to obtain a PMMA support layer.

[0053] (2.2) Immerse the graphene in FeCl3 copper etching solution until the copper foil is completely dissolved, and wash it with deionized water to remove the residual FeCl3 solution, thereby obtaining the graphene-PMMA layer; preferably, the immersion time is 15 minutes.

[0054] (2.3) First, the graphene-PMMA layer is transferred to the bottom GaAs-based DBR2 surface and dried at a specified temperature. Then, it is immersed in acetone solution to dissolve the PMMA support layer. Preferably, the drying temperature is 80°C and the drying time is 10 minutes.

[0055] (2.4) Annealing the epitaxial wafer; specifically, the epitaxial wafer is transferred to a 350°C environment and annealed in a hydrogen atmosphere for 30 minutes to remove process residues on the interface and improve the adhesion of graphene.

[0056] (3) A long-wavelength resonant cavity 4 is fabricated on the first van der Waals buffer layer 3. Specifically, a first N-type doped layer 41, an active region 42, a P-type doped layer 43 and a tunneling junction layer are grown sequentially on the first van der Waals buffer layer 3 using MOCVD or MBE processes. Then, a circular mesa is defined by photolithography, and the tunneling junction layer outside the mesa region is selectively etched away to form a tunneling junction 44. Finally, a second N-type doped layer 45 is grown on the surface of the epitaxial wafer to achieve current expansion and surface passivation.

[0057] (4) A second van der Waals buffer layer 5 is prepared on the second N-type doped layer 45. The preparation method of the second van der Waals buffer layer 5 is the same as that of the first van der Waals buffer layer 3, so it will not be described again.

[0058] (5) The top GaAs-based DBR6 is grown on the second van der Waals buffer layer 5 using MOCVD or MBE processes.

[0059] (6) A first N-type electrode 8 is fabricated on the first van der Waals buffer layer 3, and a second N-type electrode 9 is fabricated on the second van der Waals buffer layer 5. The electrode fabrication method is existing technology and will not be described in detail here. Example

[0060] like Figure 2 As shown, unlike Embodiment 1, in this embodiment, substrate 1 is an InP substrate, and a third van der Waals buffer layer 7 is provided between the InP substrate and the bottom GaAs-based DBR2.

[0061] Compared to GaAs substrates, InP substrates offer greater advantages in high-frequency, high photoelectric conversion efficiency, and wide-band optical applications, particularly suited to the demands of high-end radio frequency and optical communication fields. However, due to the material incompatibility between the InP substrate and the underlying GaAs-based DBR2, a third van der Waals buffer layer 7 is required between them. This third van der Waals buffer layer 7 is preferably graphene, thus acting as a lattice mismatch and stress buffer, enabling the InP substrate and the underlying GaAs-based DBR2 to overcome material system limitations and achieve heterogeneous integration on the same chip. Furthermore, the third van der Waals buffer layer 7 also serves for current transport and heat dissipation, contributing to improved overall chip performance.

[0062] In this embodiment, the transfer process of the third van der Waals buffer layer 7 is similar to that of the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5. The preparation processes of other epitaxial structures are also the same as those in Example 1, and therefore will not be described in detail. Example

[0063] like Figure 3As shown, unlike Embodiment 2, in this embodiment, substrate 1 is a GaN substrate, and a nitride layer 11, a third van der Waals buffer layer 7, a nucleation layer 71 and a gradient buffer layer 72 are provided between the GaN substrate and the bottom GaAs-based DBR2.

[0064] GaN substrates are commonly used insulating substrates with low cost. However, there is a large lattice mismatch and thermal mismatch between the GaN substrate and the underlying GaAs-based DBR2. Therefore, a third van der Waals buffer layer 7 is required to achieve heterogeneous integration of the two.

[0065] Due to the significant differences in interfacial interaction, thermodynamics, and mechanical properties between the GaN substrate and the bottom GaAs-based DBR2, directly growing the bottom GaAs-based DBR2 on the GaN substrate and the third van der Waals buffer layer 7 presents two core challenges: 1. Poor wettability: The inertness and lack of dangling bonds on the graphene surface result in extremely high mobility of metal atoms such as Al and Ga, making nucleation difficult and leading to island-like growth rather than flat layered growth; 2. Lack of epitaxial relationship: The lattice symmetry of graphene differs from that of III-V crystals, failing to provide direct epitaxial guidance and easily resulting in polycrystalline or disordered oriented films. Therefore, this embodiment includes a nitride layer 11 between the GaN substrate and the third van der Waals buffer layer 7, and a nucleation layer 71 and a gradient buffer layer 72 between the third van der Waals buffer layer 7 and the bottom GaAs-based DBR2. The specific preparation method is as follows: Nitride layer 11: During the preparation of the third van der Waals buffer layer 7, nitriding treatment (such as annealing in NH3 atmosphere) is performed at the interface between the GaN substrate and the third van der Waals buffer layer 7, so that an extremely thin nitride layer 11, namely the AlN layer, is formed between the two, thereby significantly improving the wettability of subsequent AlGaAs.

[0066] Nucleation layer 71: Under low-temperature conditions, a thin layer of AlN or GaN is deposited on the surface of the third van der Waals buffer layer 7 as the nucleation layer 71. Low temperature can suppress three-dimensional island growth and promote two-dimensional spreading. The nucleation layer 71 is the basis for subsequent growth of high-quality AlGaAs.

[0067] Gradient buffer layer 72: A set of compositionally gradient buffer layers 72, from nitride to arsenide, is grown above the nucleation layer 71. In this embodiment, the gradient buffer layer 72 is a buffer layer that is gradient from AlN to AlGaN and then to AlGaAs, thereby smoothly transitioning the lattice constant and reducing defects.

[0068] In this embodiment, the transfer process of the third van der Waals buffer layer 7 is similar to that of the first van der Waals buffer layer 3 and the second van der Waals buffer layer 5. The preparation processes of other epitaxial structures are also the same as those in Example 1, and therefore will not be described in detail. Example

[0069] like Figure 4 As shown, unlike Embodiment 2, in this embodiment, substrate 1 is a SiC substrate, and a third van der Waals buffer layer 7, a nucleation layer 71 and a gradient buffer layer 72 are provided between the SiC substrate and the bottom GaAs-based DBR2.

[0070] SiC substrates possess extremely high thermal conductivity, making them an ideal choice for achieving optimal heat dissipation performance. However, a lattice mismatch exists between the SiC substrate and the underlying GaAs-based DBR2, necessitating the addition of a third van der Waals buffer layer 7 to achieve heterogeneous integration. However, due to the high compatibility between the crystal structure and chemical properties of the SiC substrate and the atomic arrangement of graphene, and the controllable process for the ordered recombination and growth of C atoms, a layer of graphene can be directly epitaxially grown on the SiC substrate surface using high-temperature annealing or chemical vapor deposition. Compared to the graphene transfer processes in Examples 1 to 3, this embodiment employs direct epitaxial growth, eliminating the need for transfer, avoiding contamination and damage, and yielding high-quality graphene with strong adhesion to substrate 1 and a clean interface.

[0071] Similar to the GaN substrate in Example 3, the SiC substrate also suffers from poor wettability with the bottom GaAs-based DBR2. Therefore, in this example, a nucleation layer 71 and a gradient buffer layer 72 are provided between the third van der Waals buffer layer 7 and the bottom GaAs-based DBR2. The nucleation layer 71 is preferably a thin AlN layer deposited at low temperature, and the gradient buffer layer 72 is a buffer layer that gradients from AlN to AlGaAs. Thanks to the small lattice mismatch between SiC and AlN, there is a certain epitaxial relationship between AlN and SiC. Therefore, this example does not require a nitride layer, and a high-quality nucleation layer 71 can be grown directly on the third van der Waals buffer layer 7. Furthermore, in this example, the thickness of the gradient buffer layer 72 can be made thinner and the structure simpler, which helps to reduce the total thickness and resistance of the DBR.

[0072] In summary, the greatest advantage of SiC substrates is that they can be used to prepare high-quality, transfer-free graphene, and by utilizing their good lattice and thermal matching with AlGaAs materials, high-quality epitaxy can be achieved, making them very suitable for high-performance, high-power devices.

[0073] The fabrication processes for other epitaxial structures in this embodiment are the same as in Embodiment 1, and therefore will not be described again. Example

[0074] like Figure 5 As shown, unlike Example 3, in this example, substrate 1 is a Si substrate, and a third van der Waals buffer layer 7, an anti-reflow layer 73, and a superlattice buffer layer 74 are provided between the Si substrate and the bottom GaAs-based DBR2.

[0075] Si substrates offer significant advantages in terms of cost and optoelectronic integration. However, a lattice mismatch exists between the Si substrate and the underlying GaAs-based DBR2. Therefore, a graphene layer is needed as a third van der Waals buffer layer 7 to achieve heterogeneous integration between the two. In this embodiment, the graphene preparation method is similar to that in Example 3. The Si substrate surface has natural silicon dioxide or a thermally grown oxide layer, which facilitates the transfer and adhesion of graphene.

[0076] There is a significant thermal mismatch between the Si substrate and the bottom GaAs-based DBR2, with a difference in their coefficients of thermal expansion exceeding 100%. During cooling, the bottom GaAs-based DBR2 is subjected to enormous tensile stress, which can easily lead to cracking or peeling off from the substrate 1. Furthermore, during high-temperature growth, As atoms react with the Si substrate, causing a deterioration in the quality of the epitaxial layer. For these reasons, this embodiment includes a reflow-resistant layer 73 and a superlattice buffer layer 74 between the third van der Waals buffer layer 7 and the bottom GaAs-based DBR2. The reflow-resistant layer 73 is a low-temperature grown GaAs or AlAs layer, which protects the silicon surface. The superlattice buffer layer 74 is a GaAs / AlGaAs superlattice layer or a low-temperature GaAs layer. The superlattice buffer layer 74 effectively releases and relaxes thermal stress by introducing and controlling a dislocation network.

[0077] In addition to the aforementioned issues, when polar III-V materials are grown on non-polar Si substrates, antiphase domain defects are easily formed. Therefore, in practical designs, methods such as off-center substrate 1 or pretreatment to form single-atom steps are needed to suppress antiphase domains. In summary, the core challenge of Si substrates is managing the huge thermal mismatch. The focus of the process is not on nucleation, but on designing complex superlattice buffer layers 74 to prevent cracking and overcome crystal defects such as antiphase domains. The goal is to achieve usable crystal quality to serve integrated applications, rather than pursuing ultimate crystal perfection.

[0078] The fabrication processes for other epitaxial structures in this embodiment are the same as in Embodiment 1, and therefore will not be described again.

[0079] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using the design concept shall be considered an infringement of the protection scope of the present invention.

Claims

1. A novel long-wavelength vertical-plane emitting laser, characterized in that: It includes, from bottom to top, a substrate, a bottom GaAs-based DBR, a first van der Waals buffer layer, a long-wavelength resonant cavity, a second van der Waals buffer layer, and a top GaAs-based DBR; Both the first and second van der Waals buffer layers are graphene. The bottom GaAs-based DBR and the long-wavelength resonant cavity are heterogeneously integrated through the first van der Waals buffer layer, and the long-wavelength resonant cavity and the top GaAs-based DBR are heterogeneously integrated through the second van der Waals buffer layer. The bottom GaAs-based DBR, the first van der Waals buffer layer, the second van der Waals buffer layer, and the top GaAs-based DBR together constitute a multi-dimensional thermal management network.

2. The novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: The long-wavelength resonant cavity includes, from bottom to top, a first N-type doped layer, an active region, a P-type doped layer, a tunnel junction, and a second N-type doped layer.

3. A novel long-wavelength vertical-plane emitting laser as described in claim 2, characterized in that: Both the bottom GaAs-based DBR and the top GaAs-based DBR are AlGaAs material systems, and the active region is an InGaAsP / InGaAsP or InGaAsP / InAlGaAs multi-quantum-well active region.

4. A novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: Both the first van der Waals buffer layer and the second van der Waals buffer layer are located at the standing wave nodes within the long-wavelength resonant cavity.

5. A novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: The substrate is a GaAs substrate.

6. A novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: The substrate is an InP substrate, and a third van der Waals buffer layer is provided between the InP substrate and the bottom GaAs-based DBR.

7. A novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: The substrate is a GaN substrate, and a nitride layer, a third van der Waals buffer layer, a nucleation layer and a gradient buffer layer are provided between the GaN substrate and the bottom GaAs-based DBR.

8. A novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: The substrate is a SiC substrate, and a third van der Waals buffer layer, a nucleation layer and a gradient buffer layer are provided between the SiC substrate and the bottom GaAs-based DBR.

9. A novel long-wavelength vertical-plane emitting laser as described in claim 1, characterized in that: The substrate is a Si substrate, and an anti-reflow layer and a superlattice buffer layer are provided between the Si substrate and the bottom GaAs-based DBR.

Images