Decoder turn-off control method, decoder and chip
By setting external and internal pass-through paths in the decoder to determine the codeword convergence status and control the decoder's function shutdown, the problem of the decoder not being able to be completely shut down after premature termination is solved, and a low-power decoder design is achieved.
Patent Information
- Application Number
- CN202411169310.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2026-03-03
AI Technical Summary
During the decoding process, if the codeword is output from the decoder immediately after satisfying the early termination rule, the preceding and following information bits will be out of order. This continues to be passed on until it is output from the last stage decoder, which makes it impossible for the decoder to be completely turned off, resulting in high power consumption.
By setting external and internal pass-through paths in the decoder, the codeword convergence status is determined, the shifting, storage, and calculation functions of non-convergent codewords are stopped, and the converged codeword is transmitted to the subsequent processor through the pass-through path until the last stage processor outputs, and the corresponding function of the decoder is turned off.
This effectively solves the problem of ensuring correct transmission of information bits under early termination conditions while maximizing the shutdown of the decoder and reducing power consumption.
Smart Images
Figure CN121603151A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to channel decoding in the fields of optical communication and power line communication. Specifically, it relates to a method for controlling the shutdown of a decoder, a decoder, and a chip. Background Technology
[0002] In the fields of communication and storage, the pursuit of low power consumption has become an important trend. Incorporating early termination rules into the decoding process can effectively reduce the average number of iterations, thereby reducing the decoder's power consumption. However, immediately outputting the codeword from the decoder after satisfying the early termination rule leads to out-of-order information bits. Continuing to propagate the codeword until it is output from the last stage decoder results in the decoder not being able to be completely turned off even without decoding, leading to high power consumption. Therefore, ensuring correct transmission of information bits while maximizing decoder shutdown under early termination conditions is a crucial problem that needs to be solved in low-power decoder design. Summary of the Invention
[0003] This invention provides a decoder shutdown control method, decoder, and chip to at least solve the problem in related technologies where the codeword is immediately output from the decoder after satisfying the early termination rule, resulting in out-of-order information bits. This continues to propagate until it is output from the last stage decoder, which in turn causes the decoder to be unable to be completely shut down even if no decoding is performed, resulting in high power consumption.
[0004] According to an embodiment of the present invention, a method for controlling the shutdown of a decoder is provided, comprising: determining whether a codeword in the local processor of the decoder has converged, wherein the decoder includes multiple processors, each processor corresponding to one large decoding iteration, and one large decoding iteration including multiple small decoding iterations; if the codeword converges on its first entry into the local processor, stopping all decoding of the converged codeword in the local processor, shutting down the shifting, storage, and calculation functions of the local processor for the codeword, and transmitting the converged codeword to the next-stage processor of the decoder through an external pass-through path, and outputting the converged codeword in the last-stage processor; if the codeword converges only after entering the local processor and undergoing decoding, stopping the subsequent decoding of the converged codeword in the local processor, shutting down the calculation function of the decoding part of the codeword in the local processor, and transmitting the converged codeword to the next-stage processor of the decoder through an internal pass-through path, and outputting the converged codeword in the last-stage processor.
[0005] According to another embodiment of the present invention, a decoder is provided, the decoder including a multi-level processor, each level of the processor corresponding to one large decoding iteration, one large decoding iteration including multiple small decoding iterations, wherein an external pass-through path and an internal pass-through path are provided between adjacent levels of the processor, each level of the processor including: a judgment module, used to judge whether the codeword in the current level of the decoder has converged; a first execution module, used to, when the codeword has converged, stop all decoding of the converged codeword in the current level of the processor, disable the shift, storage and calculation functions of the codeword in the current level of the processor, and transmit the converged codeword to the subsequent level of the decoder through the external pass-through path so as to output the converged codeword in the last level of the processor; and a second execution module, used to, when the codeword has converged, stop the subsequent decoding of the converged codeword in the current level of the processor, disable the calculation function of the decoding part of the codeword in the current level of the processor, and transmit the converged codeword to the subsequent level of the decoder through the internal pass-through path so as to output the converged codeword in the last level of the processor.
[0006] According to yet another embodiment of the present invention, a chip is also provided, wherein the chip is configured to perform the steps of any of the above method embodiments at runtime.
[0007] This invention addresses the issue that, due to the presence of both external and internal pass-through paths in each processor stage, when transmitting convergent codewords via the external pass-through path, the decoder's shifting, calculation, and storage functions can be disabled, and the convergent codeword is output at the last processor stage. Similarly, when transmitting convergent codewords via the internal pass-through path, the decoder's calculation function can be disabled, and the convergent codeword is output at the last processor stage. This solves the problem in existing technologies where, after a codeword satisfies the early termination rule, its immediate output from the decoder leads to out-of-order information bits, and continuing transmission until the last decoder outputs results in the decoder not being fully shut down even without decoding, leading to high power consumption. This invention effectively reduces decoder power consumption. Attached Figure Description
[0008] Figure 1 This is a flowchart of a decoder shutdown control method according to an embodiment of the present invention;
[0009] Figure 2 This is a structural block diagram of the first-stage processor of the decoder according to an embodiment of the present invention;
[0010] Figure 3 This is a block diagram of the receiver side of the communication system.
[0011] Figure 4 This is an overall structural block diagram of a decoder according to an embodiment of the present invention;
[0012] Figure 5 This is another structural block diagram of the first-stage processor of the decoder according to an embodiment of the present invention;
[0013] Figure 6 This is a hardware structure diagram of the computing module according to an embodiment of the present invention;
[0014] Figure 7 This is another flowchart of the decoder shutdown control method according to an embodiment of the present invention. Detailed Implementation
[0015] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.
[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0017] I. Channel Encoding and Decoding Technology
[0018] Channel coding and decoding technology is indispensable for ensuring the reliability of communication and storage systems. Forward Error Correction (FEC) is a commonly used method in channel coding and decoding. Its principle is to add redundant information to the original data at the transmitting end, and then use this redundant information at the receiving end to detect and correct errors generated during transmission. FEC can be divided into geometric codes and algebraic codes. Low-Density Parity-Check (LDPC) is currently the most widely used geometric code, with good error correction performance and suitability for large-scale parallel hardware implementation. Low-Density Parity-Check Convolutional Code (LDPC-CC) is a type of LDPC code whose parity-check matrix has convolutional properties. LDPC-CC combines the advantages of LDPC and convolutional codes, possessing not only good error correction performance but also supporting arbitrary length codes according to the requirements of the source, making it more suitable for variable-length applications. For example, the IEEE 1901 standard includes LDPC-CC as an optional FEC solution. The IEEE 1901 standard is the most mature and stable broadband standard in the world's power standards.
[0019] II. Early Termination Rules
[0020] In the fields of communication and storage, with the increasing demands of applications, the pursuit of low power consumption has become an important trend. Decoders are usually the biggest power consumers in a system. Incorporating early termination rules into the decoding process can effectively reduce the average number of iterations, thereby reducing the power consumption of the decoder.
[0021] Early termination is achieved by determining the convergence of the codeword using various rules. If the codeword converges, decoding is not performed. Commonly used early termination rules include: (1) Parity check. After each iteration, the decoder calculates its parity check equation (H*vT, where H represents the parity check matrix and v represents the codeword). If the result is 0 or the result is 0 multiple times consecutively, the decoding of this codeword is terminated. (2) Compare whether the codeword has changed in two iterations. If it has not changed, the decoding of this codeword is terminated. (3) Set a confidence threshold. If the absolute value of the codeword confidence is greater than the threshold, the decoding of this codeword is terminated. The above methods are implemented by directly outputting the codeword after satisfying the early termination rules. This is mostly applicable to storage scenarios and not applicable to scenarios where convolutional code decoding is used in optical communication or power line communication. On the one hand, the characteristics of convolutional codes can lead to some codewords terminating early while others do not. Therefore, directly outputting the codeword after early termination will lead to out-of-order output, which will cause functional errors. On the other hand, directly outputting codewords cannot guarantee that the decoding delay remains unchanged, and it cannot be applied to scenarios where the external world is unaware of the premature termination.
[0022] In scenarios such as optical communication, the purpose of early termination is to prevent converged codewords from being decoded, thereby reducing power consumption. However, converged codewords still need to be passed to subsequent processors until they are output from the last-stage processor, and the overall decoding delay remains unchanged. Therefore, the passing of codewords prevents the decoder from being completely shut down. Inefficient early termination implementation methods can render early termination meaningless and fail to achieve the goal of reducing power consumption.
[0023] III. Problems Existing in the Existing Technology
[0024] Since LDPC-CC is a bitstream, decoders are typically implemented using an iterative expansion approach. Each iteration corresponds to one level of processor, and T iterations require T levels of processors. If the codeword is output from the decoder immediately after satisfying the early termination rule, the preceding and following information bits will be out of order. However, if the codeword is not decoded after satisfying the early termination rule, the information bits still need to be passed to subsequent processors and eventually output from the last level of processor. This results in the decoder not being able to be completely turned off even without decoding. Therefore, ensuring the correct transmission of information bits under early termination conditions while maximizing the shutdown of the decoder is a critical problem that needs to be solved in low-power decoder design, and its importance is no less than the design of the decoder's functionality.
[0025] To address the aforementioned issues, this embodiment provides a method for controlling the shutdown of a decoder. It should be noted that the method in this embodiment is not limited to LDPC-CC and is applicable to other codewords. Figure 1 This is a flowchart of a decoder shutdown control method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:
[0026] Step S102: Determine whether the codewords in the current level processor of the decoder have converged. The decoder includes multiple levels of processors, each level of processor corresponds to one large decoding iteration, and one large decoding iteration includes multiple small decoding iterations.
[0027] In step S104, if the codeword converges on the first entry into the local processor, stop all decoding of the converged codeword in the local processor, shut down the local processor's shift, storage and calculation functions for the codeword, and transmit the converged codeword to the next-stage processor of the decoder through an external pass-through path, and output the converged codeword in the last stage processor.
[0028] In this embodiment, the converged codeword can be transmitted to the decoder's subsequent processor through an external transparent transmission path within a delay period, where the delay period is the duration of one large decoding iteration.
[0029] Step S106: If the codeword converges only after being decoded by the local processor, stop the subsequent decoding of the converged codeword in the local processor, shut down the calculation function of the local processor for the decoding part of the codeword, and transmit the converged codeword to the next level processor of the decoder through the internal pass-through path, and output the converged codeword in the last level processor.
[0030] In this embodiment, the converged codeword can only be transmitted to the subsequent processor through the internal transparent transmission path when the interval between the codeword to be converged and the codeword that has just entered the current level processor is greater than the relevant code length.
[0031] In one embodiment, if the codeword does not converge, the codeword needs to be decoded in the current processor and the decoded codeword is passed to the next processor after the decoder. The decoded codeword is then output in the last processor.
[0032] In this embodiment, the local processor can perform one or more small decoding iterations on the codeword, moving the codeword after each decoding iteration and determining whether the decoded codeword has converged. If the decoded codeword has converged, the subsequent processor stops decoding the converged codeword, disables the subsequent processor's calculation function for the decoded part of the converged codeword, and transmits the converged codeword to the subsequent processor of the decoder through an internal pass-through path.
[0033] In one embodiment, before determining whether the codewords in the local processor of the decoder have converged, the messages of the check node can be initialized to predetermined values, and the messages of the variable node can be initialized to codewords.
[0034] In one embodiment, when the codeword does not converge, the codeword is decoded in the current stage processor and the decoded codeword is passed to the subsequent stage processor. The decoded codeword is output by the last stage processor, which may specifically be as follows:
[0035] First, shift the variable node's message according to the predetermined shift factor. Then, determine the variable node's message to the check node based on the check node's message and the shifted variable node's message. Next, update the check node's message. Finally, update the shifted variable node's message based on the variable node's message to the check node and the updated check node's message.
[0036] The system checks if the updated variable node message satisfies the parity check equation. If it does, the counter is incremented by 1; otherwise, the counter is set to 0. The small iteration count is incremented by 1, and it is checked whether the small iteration count has reached the preset small iteration count. If the small iteration count has reached the preset small iteration count, the converged variable node message is passed to the current level processor. The large iteration count is incremented by 1, and it is checked whether the large iteration count has reached the preset large iteration count. If the large iteration count has reached the preset large iteration count, the converged variable node message is output at the last level processor.
[0037] In one embodiment, determining whether the codewords in the local processor of the decoder have converged can specifically be done by: determining whether the value of the counter has reached a threshold; if the value of the counter is at the threshold, determining that the message of the updated variable node has converged; otherwise, determining that the message of the updated variable node has not converged.
[0038] By taking the above steps, the problem of high power consumption in the prior art is solved by immediately outputting the codeword from the decoder after the codeword meets the early termination rule, resulting in the disorder of the preceding and following information bits. This continues to be passed on until it is output from the last stage decoder, which in turn causes the decoder to be unable to be completely turned off even if it is not decoded. This achieves the effect of reducing the power consumption of the decoder.
[0039] This embodiment also provides a decoder for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0040] Figure 2 This is a structural block diagram of the first-level processor of the decoder according to an embodiment of the present invention, such as... Figure 2 As shown, the decoder includes multiple levels of processors, each corresponding to one large decoding iteration. One large decoding iteration includes multiple small decoding iterations. External and internal pass-through paths are provided between adjacent levels of processors. Each level of processor 20 includes:
[0041] Judgment module 22 is used to determine whether the codewords in the local processor of the decoder have converged;
[0042] The first execution module 24 is used to stop all decoding of the converged codeword in the current stage processor when the codeword is converged, shut down the shift, storage and calculation functions of the current stage processor for the codeword, and pass the converged codeword to the subsequent stage processor of the decoder through an external transparent transmission path so as to output the converged codeword in the last stage processor.
[0043] The second execution module 26 is used to stop the subsequent decoding of the converged codeword in the current stage processor when the codeword is converged, shut down the calculation function of the current stage processor for the decoding part of the codeword, and pass the converged codeword to the subsequent stage processor of the decoder through the internal pass-through path so as to output the converged codeword in the last stage processor.
[0044] In this embodiment, each processor stage includes a shift module, a calculation module, a storage module, a delay module, and a selection module.
[0045] The shift module is used to shift the message of the variable node according to a predetermined shift factor, wherein the message of the variable node is initialized as a codeword;
[0046] The calculation module is used to perform one or more small decoding iterations on the codeword when the codeword does not converge, and to pass the converged codeword to the subsequent processor of the decoder through an internal transparent transmission path when the codeword converges.
[0047] The storage module is used to store the messages of the verification nodes, wherein the messages of the verification nodes are initialized to predetermined values;
[0048] The delay module is used to transmit the converged codeword to the decoder's subsequent processor through an external transparent transmission path within a delay period when the codeword has converged. The delay period is the duration of one large decoding iteration.
[0049] The selection module is used to select the codewords to be passed to the subsequent processor;
[0050] Among them, the path between the delay module and the selection module is an external transparent path, and the path between the calculation module and the selection module is an internal transparent path.
[0051] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.
[0052] Embodiments of the present invention also provide a chip, wherein the chip is configured to execute the steps of any of the above method embodiments at runtime.
[0053] Example 1
[0054] Figure 3 A block diagram of the receiver side of a communication system, such as Figure 3 As shown, it includes a noise source, channel, demodulation, channel decoding, source decoding, and decryption. This embodiment is mainly applied to channel decoding, taking LDPC-CC as an example.
[0055] LDPC-CC decoding employs a soft-decision iterative decoding algorithm. The normalized minimum sum algorithm and the offset minimum sum algorithm, based on hierarchical scheduling, are the most common in engineering applications due to their good error correction performance, low complexity, and ease of hardware implementation. The basic idea is to utilize the connection relationship between variable nodes (VNs) and check nodes (CNs), iterating messages back and forth between these two types of nodes to increase the confidence of codeword byte points, eventually stabilizing and reaching a convergent state. Based on this algorithm, an early termination strategy can be added to terminate the decoding process early when the codeword reaches the convergent state.
[0056] Figure 4 This is an overall structural block diagram of a decoder according to an embodiment of the present invention, such as... Figure 4 As shown, this includes processors 0 to T-1. The LDPC-CC decoder implementation uses an iterative expansion method, with each large iteration corresponding to a single-level processor. The maximum number of iterations is set to T, thus requiring T levels of processors. Figure 4 The codewords are processed from processor 0 to processor T-1. The codewords enter from processor 0, move to the right after each major decoding iteration, and are finally output from processor T-1.
[0057] Figure 5 This is another structural block diagram of the first-level processor of the decoder according to an embodiment of the present invention. It should be noted that the module division in this embodiment is different from that in the previous embodiments. The functions of some modules in this embodiment may correspond to the functions of modules in the previous embodiments, or be part of the functions of modules in the previous embodiments, or be a combination of the functions of multiple modules in the previous embodiments. For example... Figure 5 As shown, the system includes a shift module, a calculation module, a storage module, a delay module, and a selection module. The path between the delay module and the selection module is an external transparent path, while the path between the calculation module and the selection module is an internal transparent path. In this embodiment, the calculation module employs a minimum-sum algorithm.
[0058] The codeword length processed by the computing module is the relevant code length L. When the interval between the codeword in the current level processor and the latest codeword entering the current level processor is greater than L, the codeword in the current level processor will be passed to the next level processor; otherwise, it will be decoded or passed through in the current level processor.
[0059] For example, when the codeword interval length is no greater than L, the codewords in the current level processor can be decoded together with the latest codeword, but the convergence state of the codewords in the current level processor will not change. Once the interval length between the codewords in the current level processor and the latest codeword entering the current level processor is greater than L, the codewords in the current level processor are passed to the next level processor. Alternatively, the codewords in the current level processor may not be decoded together with the latest codeword. Once the interval length between the codewords in the current level processor and the latest codeword entering the current level processor is greater than L, the codewords in the current level processor are passed to the next level processor.
[0060] Figure 6 This is a hardware structure diagram of the computing module according to an embodiment of the present invention, such as... Figure 6 As shown, it includes a convergence flag (AND gate), a variable node to check node (V2C) message calculation module, an extremum lookup module, a selector, registers, a CN message update module, and a VN message update module.
[0061] Example 2
[0062] Figure 7 This is another flowchart of the decoder shutdown control method according to an embodiment of the present invention, such as... Figure 7 As shown, the process includes the following steps:
[0063] S701: Initialization. Initialize the message CN of the check node to a predetermined value, and initialize the message VN of the variable node to a codeword. For example, the message of the check node can be initialized to 0.
[0064] S702: Determine convergence status. The convergence of the codeword is determined by checking if the counter value reaches a threshold. If the counter value reaches the threshold, the codeword is considered convergent; otherwise, it is considered non-convergent.
[0065] Can be combined Figure 6 If the codeword converges, the convergence flag (AND gate &&) is equal to 0; otherwise, it is equal to 1. The AND gate is used for operand isolation to prevent the circuit from flipping when decoding is not in progress. The converged codeword is multiplexed and passed forward using the register that transmits V2C messages.
[0066] For example, a parity check can be performed to determine if the result is 0 multiple times consecutively. If it is 0 multiple times, the codeword is considered convergent; otherwise, it is considered non-convergent. A counter can be used to count the number of 0s. If the counter value is greater than or equal to a threshold m, meaning the number of times the parity check result is 0 is greater than or equal to m, then the codeword is considered convergent; otherwise, it is considered non-convergent.
[0067] In one embodiment, if a codeword converges on its first entry into the current processor, then the codeword that stops converging is disabled in all decoding processes of the current processor. Figure 6 The decoder's shift module, storage module, and computation module transmit the hard-determined bits to the subsequent processor of the decoder through an external transparent path within a delay period, i.e., through the delay module, and output them at the final processor stage. The delay period is the duration of one large decoding iteration. Since the delay module only needs to transmit the codeword hard-determined message, its implementation cost is low, significantly reducing the decoder's power consumption.
[0068] For example, a single large decoding iteration of a codeword in this level of processor includes three small decoding iterations (the preset number of small decoding iterations depends on the relevant code length L; for example, if the relevant code length L = 3, then the preset number of small decoding iterations is 3). If convergence occurs on the first entry into this level of processor, then all decoding of the codeword that stops converging in this level of processor is stopped, i.e., the decoding is shut down. Figure 6 The shift module, storage module, and calculation module in the decoder are passed to the subsequent processor of the decoder through the delay module within a delay time of 3 decoding iterations, and output at the last stage processor.
[0069] In one embodiment, if a codeword converges only after being decoded by the current processor, then the codeword that stops converging will be disabled in subsequent decoding by the current processor. Figure 6 The decoding function in the computation module is used to transmit the converged codeword to the subsequent processor of the decoder through an internal transparent transmission path, and the converged codeword is output by the final processor.
[0070] For example, if the codeword has a preset decoding iteration count of 3 in the current processor (correlation code length L = 3), and the codeword converges after 1 decoding iteration, the subsequent 2 decoding iterations in the calculation module are turned off. Within a delay of 2 decoding iterations, the calculation module transmits the converged codeword to the subsequent processor of the decoder through an internal pass-through path.
[0071] In one embodiment, if the codeword does not converge, the following steps are required: the codeword is decoded in the current stage processor, and the decoded codeword is passed to the subsequent stage processor of the decoder, and the decoded codeword is output in the last stage processor.
[0072] S703: V2C message update. The message from the variable node to the check node is determined based on the message from the check node and the message from the shifted variable node, according to the predefined shift factor. V2C is an intermediate value.
[0073] For example, a VN message is shifted according to a shift factor value, with N variable nodes and M check nodes, and the variable node j (j∈[1,N]) is passed to the check node i (i∈[1,M]) in message V2C. ji =VN j -CN ij V2C ji This represents the V2C transmission from node j to node i. ji VN for node j j Subtract the CN passed from node i to node j ij .
[0074] S704: CN message update. For example, the CN message passed from check node i to variable node j can be calculated using a minimum sum algorithm. ij .
[0075] S705: VN message update. Update the shifted variable node message based on the variable node to check node message and the updated check node message.
[0076] For example, the message update method for variable node j is VN. j =V2C ji +CN ij , where the message VN of variable node j j V2C transmission from node j to node i ji Add the message CN that verifies node i and passes to variable node j ij .
[0077] S706: Calculate the parity check equation and update the counter. Determine whether the updated variable node's message satisfies the parity check equation. If it does, increment the counter by 1; otherwise, set the counter to 0.
[0078] For example, each processor can be equipped with a counter. After each small decoding iteration, if the parity check equation is satisfied, the counter is incremented by 1; otherwise, the counter is set to 0. When the counter reaches the set threshold m, the counter remains unchanged.
[0079] S707: Increment the number of small iterations by 1, and determine whether the number of small iterations has reached the preset number of small iterations L.
[0080] For example, if the preset number of small iterations L is reached, the current processor will pass a message to the subsequent processor indicating that the variable node has converged.
[0081] S708: Increment the maximum iteration count by 1, and determine whether the maximum iteration count has reached the preset maximum iteration count T. If the maximum iteration count is the preset maximum iteration count T, output the message of the converged variable node in the last-level processor T-1; otherwise, return to step S702 until T is reached, and output the message of the converged variable node from the last-level processor.
[0082] By taking the above steps, the problem of high power consumption in the prior art is solved by immediately outputting the codeword from the decoder after the codeword meets the early termination rule, resulting in the disorder of the preceding and following information bits. This continues to be passed on until it is output from the last stage decoder, which in turn causes the decoder to be unable to be completely turned off even if it is not decoded. This achieves the effect of reducing the power consumption of the decoder.
[0083] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.
[0084] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for controlling the shutdown of a decoder, characterized in that, include: Determine whether the codewords in the current processor of the decoder have converged, wherein the decoder includes multiple processors, each processor corresponds to one large decoding iteration, and one large decoding iteration includes multiple small decoding iterations; If the codeword converges on the first entry into the local processor, stop all decoding of the converged codeword in the local processor, shut down the local processor's shift, storage and calculation functions for the codeword, and transmit the converged codeword to the next-stage processor of the decoder through an external pass-through path. The converged codeword is then output by the last-stage processor. If the codeword converges only after being decoded by the local processor, the subsequent decoding of the converged codeword in the local processor is stopped, the calculation function of the local processor for the decoding part of the codeword is turned off, and the converged codeword is transmitted to the next-stage processor of the decoder through an internal pass-through path. The converged codeword is then output by the last-stage processor.
2. The method according to claim 1, characterized in that, The method includes: If the codeword does not converge, the codeword is decoded in the current stage processor and the decoded codeword is passed to the subsequent stage processor of the decoder. The decoded codeword is then output in the last stage processor.
3. The method according to claim 1, characterized in that, The converged codewords are transmitted to the subsequent processor of the decoder via an external transparent transmission path, including: The converged codeword is transmitted to the subsequent processor of the decoder through an external transparent transmission path within a delay period, wherein the delay period is the duration of one large decoding iteration.
4. The method according to claim 2, characterized in that, If the codeword does not converge, the codeword is decoded in the current-level processor, and the decoded codeword is passed to the subsequent processor. The decoded codeword is output by the last-level processor, including: The processor at this level performs one or more small decoding iterations on the codeword; Move the decoded codeword each time and determine whether the decoded codeword converges; When the decoded codeword converges, the subsequent processor stops decoding the converged codeword, shuts down the computation function of the subsequent processor for the decoding part of the converged codeword, and transmits the converged codeword to the subsequent processor of the decoder through an internal pass-through path.
5. The method according to claim 1 or 4, characterized in that, The converged codewords are transmitted to the subsequent processor of the decoder via an internal transparent transmission path, including: When the interval between the converged codeword and the latest codeword entering the current level processor is greater than the relevant code length, the converged codeword is transmitted to the subsequent level processor through the internal transparent transmission path.
6. The method according to claim 2, characterized in that, Before determining whether the codewords in the decoder's local processor have converged, the method includes: Initialize the messages of the verification node to predetermined values; The message of the variable node is initialized to the codeword.
7. The method according to claim 6, characterized in that, If the codeword does not converge, the codeword is decoded in the current-level processor, and the decoded codeword is passed to the subsequent processor. The decoded codeword is output by the last-level processor, including: The message that shifts the variable node according to the predetermined shift factor; The message from the variable node to the verification node is determined based on the message from the verification node and the shifted message from the variable node. Update the message of the verification node; Update the shifted message of the variable node based on the message from the variable node to the check node and the updated message of the check node; Determine whether the updated variable node's message satisfies the parity check equation; If the conditions are met, the counter value is incremented by 1; If the condition is not met, the counter value is set to 0; Increment the number of small iterations by 1, and determine whether the number of small iterations has reached the preset number of small iterations; When the number of small iterations is a preset number of small iterations, the current processor passes the message of the converged variable node to the subsequent processor; Increment the maximum iteration count by 1, and determine whether the maximum iteration count has reached the preset maximum iteration count; When the number of large iterations is a preset number of large iterations, the message of the converged variable node is output at the last stage processor.
8. The method according to claim 7, characterized in that, Determining whether the codewords in the decoder's local processor have converged includes: Determine whether the value of the counter has reached the threshold; If the value of the counter is a threshold, it is determined that the message of the updated variable node has converged; otherwise, it is determined that the message of the updated variable node has not converged.
9. A decoder, characterized in that, The decoder includes multiple processor levels, each corresponding to one large decoding iteration. Each large decoding iteration includes multiple small decoding iterations. External and internal pass-through paths are provided between adjacent processor levels. Each processor level includes: The judgment module is used to determine whether the codewords in the local processor of the decoder have converged. The first execution module is configured to, when the codeword is converged, stop all decoding of the converged codeword in the current stage processor, shut down the shift, storage and calculation functions of the current stage processor for the codeword, and transmit the converged codeword to the subsequent stage processor of the decoder through the external transparent transmission path, so as to output the converged codeword in the last stage processor. The second execution module is used to, when the codeword is converged, stop the subsequent decoding of the converged codeword in the current stage processor, shut down the calculation function of the current stage processor for the decoding part of the codeword, and transmit the converged codeword to the subsequent stage processor of the decoder through the internal transparent transmission path, so as to output the converged codeword in the last stage processor.
10. The decoder according to claim 9, characterized in that, Each stage of the processor includes a shift module, a calculation module, a storage module, a delay module, and a selection module. The shift module is used to shift the message of the variable node according to a predetermined shift factor, wherein the message of the variable node is initialized to the codeword; The computing module is used to perform one or more small decoding iterations on the codeword when the codeword does not converge, and to transmit the converged codeword to the subsequent processor of the decoder through an internal transparent transmission path when the codeword converges after decoding. The storage module is used to store messages of the verification node, wherein the messages of the verification node are initialized to predetermined values; The delay module is used to transmit the converged codeword to the decoder's subsequent processor through an external transparent transmission path within a delay period when the codeword is converged, wherein the delay period is the duration of one large decoding iteration. The selection module is used to select the codeword to be passed to the subsequent processor; The path between the delay module and the selection module is an external transparent path, and the path between the calculation module and the selection module is an internal transparent path.
11. A chip comprising the decoder according to any one of claims 9-10.