Packaging substrate circuit based on semi-additive process and preparation method thereof

Abstract

The invention relates to a packaging substrate circuit based on a semi-additive process and a preparation method thereof, and belongs to the technical field of integrated circuit packaging. A chemical copper seed layer is firstly deposited on the surface of a pretreated insulating base material, and then a flash-erosion-resistant copper layer is electroplated to form a stepped copper layer structure; coating photoresist on the surface of the anti-flash-corrosion copper layer, and exposing and developing to form a circuit pattern window; electroplating a target circuit copper layer in the circuit pattern window, and synchronously filling the micro blind holes in the substrate; removing the photoresist, and exposing the anti-flash-corrosion copper layer in a non-circuit area; and selectively etching the copper layer in the exposed area by adopting an acidic etching solution containing an organic corrosion inhibitor, and reserving a laminated structure of a target circuit and the flash-corrosion-resistant copper layer, thereby obtaining the packaging substrate with high yield and low cost. Through the stepped copper layer structure design and the differential etching technology, the problem of lateral erosion of a superfine line is solved, a precise circuit with the line width / line distance smaller than or equal to 10 microns is achieved, meanwhile, micro blind hole filling is compatible, and the method is suitable for packaging of 5G and 6G high-performance computing chips.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging technology, and in particular to a packaging substrate circuit based on a semi-additive method and its fabrication method. Background Technology

[0002] The conductive patterns on a printed circuit board (PCB) are metal circuit systems attached to the surface of an insulating substrate. They are the core functional part of the PCB, enabling the interconnection of electronic components, signal transmission, and power distribution. The core methods for fabricating PCB conductive patterns fall into three main categories: subtractive processes, fully additive processes, and modified semi-additive processes (mSAP). All three revolve around the deposition, retention, or removal of metal layers to achieve circuit formation, adapting to different precision, cost, and production capacity requirements. However, subtractive processes suffer from severe copper etching side etching, making it difficult to produce linewidths <20 μm and resulting in low material utilization. Fully additive processes require specialized chemical copper plating solutions, leading to high costs, weak adhesion, and a tendency to produce plating voids. The semi-additive process, on the other hand, involves first chemically depositing a thin metal layer (conductive substrate) on the insulating substrate surface, then defining the circuit pattern through photolithography, electroplating to thicken the target circuit, and finally etching away the excess thin metal layer not covered by electroplating to form the conductive pattern. However, existing modified semi-additive processes rely on ultra-thin copper foil (≤3μm), which is costly and the thin copper layer is easily scratched.

[0003] Currently, 5G / 6G and AI chips require substrate circuit precision to be improved to below 10 μm, and traditional processes are difficult to meet the yield and cost requirements. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a packaging substrate circuit based on a semi-additive method and its fabrication method. This invention is applicable to the fabrication of micro-circuit patterns on high-density packaging substrates (such as FC-BGA and SiP substrates), achieving precision circuit patterns with linewidth / spacing ≤10 μm through a semi-additive method.

[0005] This invention is achieved through the following technical solution:

[0006] The first objective of this invention is to provide a method for fabricating packaging substrate circuitry based on a semi-additive method, comprising the following steps:

[0007] S1. First, deposit a chemical copper seed layer on the surface of the pretreated insulating substrate, and then electroplate an anti-flashover copper layer to form a stepped copper layer structure.

[0008] S2. Photoresist is coated on the surface of the anti-flashover copper layer obtained in step S1, and then exposed and developed to form a circuit pattern window.

[0009] S3. Electroplating the target circuit copper layer in the circuit pattern window obtained in step S2, and simultaneously filling the micro blind holes on the substrate;

[0010] S4. Remove the photoresist to expose the anti-flashover copper layer in the non-circuit area;

[0011] S5. Selectively etch the copper layer in the exposed area using an acidic etching solution containing an organic corrosion inhibitor, preserving the stacked structure of the target circuit and the anti-flashover copper layer.

[0012] Further, in step S1, the pretreated insulating substrate is prepared by the following method: the insulating substrate is cleaned and then activated by plasma.

[0013] The activation is performed using Ar plasma; wherein the argon gas is 60-80 vol%, the power is 200-400 W, and the processing time is 60-120 seconds.

[0014] The thickness of the insulating substrate is 30-50 μm;

[0015] The insulating substrate is ABF film or BT resin.

[0016] Further, in step S1, the thickness of the chemical copper seed layer is 0.5-1.2 μm;

[0017] The chemical copper seed layer is obtained by immersing the pretreated insulating substrate in a chemical copper plating solution for deposition; the chemical copper plating solution consists of 5-15 g / L copper sulfate, 30-40 g / L EDTA complexing agent, 35-40 mL / L formaldehyde, and a pH value of 10.0-12.0.

[0018] Furthermore, in step S1, the thickness of the anti-flashover copper layer is 2-6 μm;

[0019] The electroplated anti-flashover copper layer is obtained by electroplating a substrate with a deposited chemical copper seed layer in an electroplating solution; the electroplating solution includes copper pyrophosphate and cobalt pyrophosphate.

[0020] The electroplating conditions are: current density of 12-14 ASD, temperature of 50-60℃, and time of 15-30 min.

[0021] Further, in step S2, the photoresist is a negative epoxy resin photoresist; the thickness of the photoresist is 5-20 μm;

[0022] The exposure amount is 150-200 mJ / cm²;

[0023] The developing solution is a 2.0-2.5% TMAH (tetramethylammonium hydroxide) solution.

[0024] Further, in step S3, the copper layer of the target circuit is electroplated to 5-15 μm;

[0025] The diameter of the micro-blind hole is ≤30 μm and the aspect ratio is ≤1:1;

[0026] And / or, the micro-blind vias on the filled substrate employ pulsed reverse current technology, wherein the pulsed reverse current technology satisfies the following parameters:

[0027] The forward current density is 23-25 ​​ASD, and the pulse width is 9-11 ms.

[0028] The reverse current density is 0.5-1.0 ASD, and the pulse width is 1-3 ms.

[0029] Blind hole diameter ≤30 μm, depth-to-width ratio ≤1:1, and filling void ratio <1%.

[0030] Further, in step S5, the acidic etching solution containing the organic corrosion inhibitor comprises the following components: 10 wt% H2SO4, 5 wt%-8 wt% H2O2 and 0.05 wt%-0.1 wt% benzotriazole.

[0031] Furthermore, in step S5, the etching temperature is 35-45°C; the etching time is 45-75 seconds.

[0032] The acidic etching solution containing organic corrosion inhibitor has an etching rate of >5 μm / min for the chemical copper seed layer;

[0033] The acidic etchant containing organic corrosion inhibitor has an etching rate of <0.1 μm / min against the flash layer.

[0034] A second objective of this invention is to provide a packaging substrate circuit based on a semi-additive method obtained by the aforementioned preparation method.

[0035] Furthermore, the minimum linewidth / line spacing of the packaging substrate is ≤10μm, the verticality of the line sidewall is >85°, and the surface roughness Ra is ≤0.2 μm.

[0036] The technical solution of the present invention has the following advantages compared with the prior art:

[0037] This invention provides a packaging substrate circuit based on a semi-additive method and its fabrication method. The packaging substrate obtained by the fabrication method of this invention has high-precision circuit fabrication capabilities, high industrial integration, and strong practicality.

[0038] This invention provides a high-yield, low-cost packaging substrate. By employing a stepped copper layer structure design and differential etching technology, the problem of side etching for ultra-fine lines is solved, enabling precision circuits with linewidth / spacing ≤10 μm. It also supports micro-blind via filling and is suitable for packaging 5G and 6G high-performance computing chips. Attached Figure Description

[0039] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein:

[0040] Figure 1 This is a schematic diagram of the semi-additive electroplating process for filling blind holes in this invention;

[0041] Figure 2 This is a process flow diagram of the present invention. Detailed Implementation

[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0043] Unless otherwise specified, the experimental methods used in the following examples are conventional methods, and the materials and reagents used are commercially available.

[0044] Example 1: Fabrication of FC-BGA substrate

[0045] This embodiment provides a method for fabricating packaging substrate circuitry based on a semi-additive method (process flow diagram as shown). Figure 2 (As shown), the specific steps are as follows:

[0046] (1) Preparation of insulating substrate:

[0047] A 50 μm thick ABF film was selected as the insulating substrate, and surface oil and impurities were cleaned and removed.

[0048] The cleaned ABF film was placed in a plasma treatment machine, and argon gas (70 vol%) was introduced as the treatment gas. The parameters for plasma activation were as follows: power 350 W, time 80 s, gas flow rate 20 sccm, and chamber pressure 0.5 Torr.

[0049] (2) Stepped copper deposition:

[0050] The insulating substrate treated in step (1) was completely immersed in the chemical copper plating solution. The plating solution temperature was 40℃ and the time was 20min. Finally, a chemical copper seed layer with a thickness of 0.8 μm was deposited on the substrate surface. The chemical copper plating solution consisted of: 5 g / L copper sulfate, 30 g / L EDTA (ethylenediaminetetraacetic acid) complexing agent, 38 mL / L formaldehyde reducing agent, and pH value of 11.

[0051] A substrate with a deposited chemical copper seed layer was used as the cathode, and a pure copper plate (purity ≥99.95%) was used as the anode. The plate was immersed in a copper plating solution containing pyrophosphate for electroplating. The current density was 13 ASD, the temperature was 55℃, and the time was 15 min, resulting in a 4 μm thick anti-flashover copper layer. The electroplating solution consisted of a 200 mg / L pyrophosphate copper plating system, with the main components being copper pyrophosphate and cobalt pyrophosphate, of which the cobalt pyrophosphate content was 0.01%.

[0052] (3) Patterning and electroplating: Photoresist is coated on the obtained anti-flash etch copper layer, and the circuit pattern window is formed by exposure and development; the target circuit copper layer is electroplated in the pattern window.

[0053] Photoresist coating: A negative epoxy resin photoresist is coated on the surface of the anti-flashover copper layer obtained in step (2) by spin coating and dried at 95°C for 2 min to obtain a photoresist layer with a thickness of 15 μm.

[0054] Exposure: Using a 365 nm (i-line) light source wavelength, the photomask with the circuit pattern and blind hole positions is precisely aligned with the substrate (alignment accuracy ≤ ±1 μm), and the exposure energy is set to 180 mJ / CM²; the exposure time is 12 s, and after exposure, it is dried at 110℃ for 2 min.

[0055] Development: Use a 2.0% TMAH (tetramethylammonium hydroxide) solution for spray development for 50 seconds. Then dry in an oven at 130°C for 25 minutes to form the circuit pattern window.

[0056] Copper plating of the target circuit: Prepare a copper plating solution with a specific composition of 5 g / L copper sulfate and 30 g / L EDTA complexing agent; use the patterned substrate as the cathode and the pure copper plate as the anode, immerse it in the above plating solution for electroplating (current density of 1.0 ASD, temperature of 55℃, time of 40 min) to obtain a copper layer with a thickness of 7 μm.

[0057] Simultaneously, the filling and activation of micro-blind vias are performed (see schematic diagram of semi-additional electroplating process for filling micro-blind vias). Figure 1 (As shown): Pulse reverse current technology, parameters satisfying:

[0058] Forward current density 24 ASD, pulse width 10 ms;

[0059] Reverse current density 0.5-1.0 ASD, pulse width 2 ms;

[0060] Blind hole diameter ≤30μm, depth-to-width ratio ≤1:1, and filling void ratio <1%.

[0061] (4) Remove the photoresist to expose the anti-flashover copper layer in the non-circuit area;

[0062] (5) Differential etching: Prepare an acidic etching solution containing organic corrosion inhibitors: 10 wt% H2SO4, 5 wt% H2O2 and 0.1 wt% BTA (benzotriazole), with a pH of 0.7.

[0063] The copper layer in the exposed areas was selectively etched using an acidic etchant containing an organic corrosion inhibitor. The selective etching conditions were: 40°C for 60 s. The etching rate ratio of the anti-flashover copper layer in non-circuit areas to the target circuit copper layer was 12.5:1. Online conductivity endpoint detection was performed, and etching was terminated when the conductivity change rate dropped to <0.1% / s. The stacked structure of the target circuit and the anti-flashover copper layer was preserved, resulting in a packaging substrate circuit based on a semi-additive method.

[0064] Example 2:

[0065] This embodiment provides a method for fabricating packaging substrate circuits based on a semi-additive method, similar to Embodiment 1, except that: in step (2), the thickness of the chemical copper seed layer is 0.5 μm; and the thickness of the electroplated anti-flashover copper layer is 2 μm.

[0066] In step (5), the differential etching conditions are: etching at 35°C for 45 s;

[0067] The remaining steps are consistent with those in Example 1.

[0068] Example 3

[0069] This embodiment provides a method for fabricating packaging substrate circuits based on a semi-additive method, similar to Embodiment 1, except that: in step (2), the thickness of the chemical copper seed layer is 1.2 μm; and the thickness of the electroplated anti-flashover copper layer is 6 μm.

[0070] In step (5), the differential etching conditions are: etching at 45°C for 75 s;

[0071] The remaining steps are consistent with those in Example 1.

[0072] Comparative Example 1

[0073] This comparative example provides a method for preparing a packaging substrate circuit based on a semi-additive method, which is similar to Example 1, except that in step (2), only a chemical copper seed layer with a thickness of 0.8 μm is deposited on the surface of the insulating substrate, without electroplating an anti-flashover copper layer, and the other steps remain the same.

[0074] Comparative Example 2

[0075] This comparative example provides a method for preparing a packaging substrate circuit based on a semi-addition method, which is similar to Example 1, except that in step (4), the acid etching solution does not contain BTA, but only contains 10 wt% H2SO4 and 5 wt% H2O2 for etching, while the other steps remain the same.

[0076] Performance testing:

[0077] The minimum linewidth / line spacing, line roughness, and peel strength of the packaging substrate circuits based on the semi-additive method obtained in the examples and comparative examples were tested. The specific test methods are as follows:

[0078] (1) Minimum line width / line spacing: Use a scanning electron microscope (SEM) to photograph the cross-section and top view of the line. Measurement: Measure the top width, bottom width and spacing of the line, and calculate the line width loss and lateral corrosion. Lateral corrosion = (top width of line - bottom width of line) / 2.

[0079] (2) Line roughness (Ra): Measured by SEM cross-sectional photographs. Steepness = Line height / [(top width + bottom width) / 2]. The closer this value is to 1, the more vertical the line sidewalls are.

[0080] (3) Peel strength: Refer to IPC-TM-650 2.4.8 standard, use a universal testing machine to peel a copper wire of a certain width from the substrate at 90° and measure the required force.

[0081] The test results are shown in Table 1:

[0082] Table 1

[0083]

[0084] As shown in Table 1, the packaging substrate obtained using the semi-additive fabrication process provided by this invention exhibits excellent overall circuit performance. First, it achieves high wiring density, with a minimum linewidth / spacing of 8μm / 8μm, meeting the high integration requirements of advanced packaging. Second, it achieves excellent signal transmission characteristics, with a line roughness (Ra) as low as 0.2μm, effectively reducing skin effect loss and scattering during signal transmission, which is beneficial for high-frequency and high-speed applications. Third, it ensures extremely high reliability: a peel strength of 0.8 kN / m indicates a very strong bond between the copper lines and the ABF insulating substrate, guaranteeing the long-term reliability of the packaging structure under thermal and mechanical stress.

[0085] In Comparative Example 1, due to the lack of a flashover-resistant copper layer and the use of only a single chemical copper seed layer, the thin copper layer in the non-patterned areas was rapidly and completely etched through during the etching process, resulting in severe lateral erosion (side etching) of the sidewalls of the target circuit copper layer. This caused the bottom width of the circuit to be much smaller than the top width, resulting in uncontrolled line width accuracy (minimum line width / spacing > 15 μm), poor sidewall steepness, and increased surface roughness (Ra > 0.5 μm). At the same time, the side etching affected the bonding anchor points between the circuit and the substrate, leading to a significant decrease in peel strength to 0.5 kN / m.

[0086] Comparative Example 2 shows that the acidic etching solution did not contain the organic corrosion inhibitor benzotriazole (BTA), which prevented the etching solution from effectively distinguishing and protecting the target circuit copper layer and the anti-flashover copper layer.

[0087] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for fabricating packaging substrate circuitry based on a semi-additive method, characterized in that, Includes the following steps: S1. First, deposit a chemical copper seed layer on the surface of the pretreated insulating substrate, and then electroplate an anti-flashover copper layer to form a stepped copper layer structure. S2. Photoresist is coated on the surface of the anti-flashover copper layer obtained in step S1, and then exposed and developed to form a circuit pattern window. S3. Electroplating the target circuit copper layer in the circuit pattern window obtained in step S2, and simultaneously filling the micro blind holes on the substrate; S4. Remove the photoresist to expose the anti-flashover copper layer in the non-circuit area; S5. Selectively etch the copper layer in the exposed area using an acidic etching solution containing an organic corrosion inhibitor, preserving the stacked structure of the target circuit and the anti-flashover copper layer.

2. The preparation method according to claim 1, characterized in that, In step S1, the pretreated insulating substrate is prepared by the following method: the insulating substrate is cleaned and then activated by plasma. The activation is performed using Ar plasma activation; wherein the argon gas is 60-80 vol%, the power is 200-400 W, and the processing time is 60-120 seconds. The thickness of the insulating substrate is 30-50 μm; The insulating substrate is ABF film or BT resin.

3. The preparation method according to claim 1, characterized in that, In step S1, the thickness of the chemical copper seed layer is 0.5-1.2 μm; The chemical copper seed layer is obtained by immersing the pretreated insulating substrate in a chemical copper plating solution for deposition; the chemical copper plating solution consists of 5-15 g / L copper sulfate, 30-40 g / L EDTA complexing agent, 35-40 mL / L formaldehyde, and a pH value of 10.0-12.

0.

4. The preparation method according to claim 1, characterized in that, In step S1, the thickness of the anti-flashover copper layer is 2-6 μm; The electroplated anti-flashover copper layer is obtained by electroplating a substrate with a deposited chemical copper seed layer in an electroplating solution; the electroplating solution includes copper pyrophosphate and cobalt pyrophosphate. The electroplating conditions are: current density of 12-14 ASD, temperature of 50-60℃, and time of 15-30 min.

5. The preparation method according to claim 1, characterized in that, In step S2, the photoresist is a negative epoxy resin photoresist; the thickness of the photoresist is 5-20 μm; The exposure amount is 150-200 mJ / cm²; The developing solution is a 2.0-2.5% TMAH (tetramethylammonium hydroxide) solution.

6. The preparation method according to claim 1, characterized in that, In step S3, the copper layer of the target circuit is electroplated to 5-15 μm; The diameter of the micro-blind hole is ≤30 μm and the aspect ratio is ≤1:1; And / or, the micro-blind vias on the filled substrate employ pulsed reverse current technology, wherein the pulsed reverse current technology satisfies the following parameters: The forward current density is 23-25 ​​ASD, and the pulse width is 9-11 ms. The reverse current density is 0.5-1.0 ASD, and the pulse width is 1-3 ms. Blind hole diameter ≤30 μm, depth-to-width ratio ≤1:1, and filling void ratio <1%.

7. The preparation method according to claim 1, characterized in that, In step S5, the acidic etching solution containing organic corrosion inhibitor comprises the following components: 10 wt% H2SO4, 5 wt%-8 wt% H2O2 and 0.05 wt%-0.1 wt% benzotriazole.

8. The preparation method according to claim 1, characterized in that, In step S5, the etching temperature is 35-45℃; the etching time is 45-75 s. The acidic etching solution containing organic corrosion inhibitor has an etching rate of >5 μm / min for the chemical copper seed layer; The acidic etchant containing organic corrosion inhibitor has an etching rate of <0.1 μm / min against the flash layer.

9. The packaging substrate circuit based on the semi-addition method obtained by the preparation method of any one of claims 1-8.

10. The packaging substrate circuit based on the semi-additive method according to claim 9, characterized in that, The minimum line width / line spacing of the packaging substrate is ≤10μm, the verticality of the line sidewall is >85°, and the surface roughness Ra is ≤0.2 μm.

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