Semiconductor devices and their manufacturing methods, electronic devices

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same, as well as an electronic device. The method includes forming a stacked structure on a substrate; forming a plurality of initial isolation structures arranged along a first direction and extending along a second direction in the stacked structure; wherein at least one initial isolation structure contains a cavity; forming a trench on at least one of the opposite sides of the initial isolation structures along the second direction, the trench extending along the first direction, and the sidewalls of the trench exposing the plurality of initial isolation structures; laterally etching the plurality of initial isolation structures based on the trench to expose the cavity; filling the space and cavity where the initial isolation structures are removed based on the trench with an isolation material, the remaining initial isolation structures and isolation material constituting an isolation structure. This isolation structure after eliminating cavities can improve the consistency of isolation performance between functional devices located on opposite sides of the isolation structure along the first direction, and improve the process window and device reliability during semiconductor device fabrication.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices and their manufacturing methods, and electronic devices. Background Technology

[0002] With the rapid development of computer technology and the diversification of application scenarios, the market has placed higher demands on the storage density and performance of memory. To overcome the bottleneck of traditional two-dimensional memory in terms of storage density, three-dimensional memory technology has emerged. This technology, through a structural design that vertically stacks multiple memory cell layers, can integrate more memory cells within a unit chip area, achieving a significant increase in storage density and becoming a mainstream research direction in memory. However, the structure of three-dimensional memory is more complex than that of two-dimensional memory, and how to improve the performance of three-dimensional memory has become the main challenge currently faced. Summary of the Invention

[0003] This disclosure provides a semiconductor device, a method for manufacturing the same, and an electronic device.

[0004] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, including:

[0005] A stacked structure is formed on the substrate;

[0006] In the stacked structure, a plurality of initial isolation structures are formed along a first direction, and the initial isolation structures extend along a second direction; wherein, at least one of the initial isolation structures contains a cavity; the first direction and the second direction intersect and are both parallel to the substrate surface;

[0007] A trench is formed on at least one of the opposite sides of the initial isolation structure along the second direction, the trench extends along the first direction, and the sidewalls of the trench expose a plurality of the initial isolation structures;

[0008] Based on the trench, multiple initial isolation structures are laterally etched to expose the cavity;

[0009] The groove is filled with insulating material in the space where the initial insulating structure is removed and the cavity; wherein the remaining initial insulating structure and the insulating material constitute the insulating structure.

[0010] In some embodiments, forming a trench on at least one of the opposite sides of the initial isolation structure along the second direction includes:

[0011] A mask layer is formed on the stacked structure;

[0012] The mask layer is patterned to form openings in the mask layer; the openings extend along the first direction and overlap with the top surface portions of the plurality of initial isolation structures;

[0013] The trench is formed by etching the stacked structure and the plurality of initial isolation structures based on the opening.

[0014] In some embodiments, forming a trench on at least one of the opposite sides of the initial isolation structure along the second direction includes: forming a first trench and a second trench on the opposite sides of the initial isolation structure along the second direction, wherein the first trench and the second trench both extend along the first direction and both expose a plurality of the initial isolation structures.

[0015] The step of etching multiple initial isolation structures based on the trench to expose the cavity includes: laterally etching multiple initial isolation structures based on the first trench to expose the cavity, and laterally etching multiple initial isolation structures based on the second trench to expose the cavity;

[0016] The step of filling the space where the initial isolation structure is removed and the cavity with isolation material based on the trench includes: filling the space where the initial isolation structure is removed and the cavity with isolation material based on the first trench and the second trench.

[0017] In some embodiments, forming a first trench and a second trench on opposite sides of the initial isolation structure along the second direction includes:

[0018] The mask layer on the stacked structure is patterned to form a first opening and a second opening in the mask layer; the first opening and the second opening both extend along the first direction and overlap with the top surface portions of the plurality of initial isolation structures respectively;

[0019] Based on the first opening and the second opening, the stacked structure and the plurality of initial isolation structures are etched to form the first trench and the second trench.

[0020] In some embodiments, the top surface of the initial isolation structure exposed at the first opening has a first dimension along the second direction, the first dimension being smaller than the width of the first opening along the second direction;

[0021] The initial isolation structure has a second dimension on its top surface exposed at the second opening along the second direction, the second dimension being smaller than the width of the second opening along the second direction.

[0022] In some embodiments, the substrate includes a capacitor region and a transistor region arranged along the second direction, the first trench being located in the stacked structure on the side of the transistor region away from the capacitor region, and the second trench being located in the stacked structure on the side of the capacitor region away from the transistor region;

[0023] The method of forming a stacked structure on a substrate includes: forming alternating layers of semiconductor layers and sacrificial layers along a third direction on the substrate, wherein the third direction is perpendicular to the surface of the substrate;

[0024] The manufacturing method further includes:

[0025] A first side cavity is formed by removing the sacrificial layer and multiple isolation structures of the transistor region based on the first trench;

[0026] Based on the first trench, a first dielectric layer and a word line located in the first dielectric layer and extending along the first direction are formed in the first side cavity;

[0027] The semiconductor layer of the capacitor region is removed based on the second trench to form a second side cavity; the second side cavity exposes the isolation structure of the capacitor region.

[0028] A first electrode is formed in the second side cavity, and the first electrode is coupled to the semiconductor layer of the transistor region.

[0029] In some embodiments, the step of removing the sacrificial layer and the plurality of isolation structures based on the first trench to form a first side cavity includes:

[0030] Based on the first trench, the sacrificial layer of the transistor region is removed, and the exposed semiconductor layer is thinned at the location where the sacrificial layer is removed to form a first chamber;

[0031] A second chamber is formed by removing the isolation structure of the transistor region based on the first trench, and the second chamber is in communication with the first chamber; wherein the remaining isolation structure has a flat surface exposed on the sidewall of the second chamber.

[0032] In some embodiments, forming a first dielectric layer and a word line located in the first dielectric layer and extending along the first direction in the first side cavity based on the first trench includes:

[0033] A first dielectric material is deposited on the surfaces of the second chamber and the first chamber; wherein the first dielectric material surrounding the semiconductor layer is connected to each other in the first direction;

[0034] A second dielectric layer is formed in the remaining space of the second chamber and the first chamber;

[0035] Remove a portion of the first medium material;

[0036] Word lines extending along the first direction are formed in the space where the first dielectric material is removed; wherein, the remaining first dielectric material forms a first dielectric layer.

[0037] In some embodiments, the manufacturing method further includes: replacing the sacrificial layer of the capacitor region with a third dielectric layer based on the second trench;

[0038] The step of forming a first electrode in the second side cavity includes: forming a first electrode on the surface of the isolation structure and the third dielectric layer exposed in the second side cavity based on the second trench;

[0039] The manufacturing method further includes: forming a capacitor dielectric layer on the surface of the first electrode, and forming a second electrode on the surface of the capacitor dielectric layer.

[0040] Some embodiments of this disclosure provide a semiconductor device, including:

[0041] A plurality of memory cells are stacked on a substrate along a first direction and a second direction parallel to the substrate and along a third direction perpendicular to the substrate. Each memory cell includes a semiconductor portion and a first electrode arranged side by side along the second direction. The semiconductor portion extends along the second direction, and the first electrode is coupled to the semiconductor portion. The first direction intersects the second direction.

[0042] An isolation structure is located between the first electrodes that are adjacent in the first direction;

[0043] A first dielectric layer is located between adjacent semiconductor portions in the first direction; wherein the contact interface between the isolation structure and the first dielectric layer is a flat surface.

[0044] In some embodiments, a plurality of isolation structures are provided in the first direction and spaced apart by the first electrode, wherein the plurality of isolation structures are flush with each other near the sidewall of the first dielectric layer.

[0045] In some embodiments, the semiconductor device further includes:

[0046] Word lines, the word lines being located on the side of the first dielectric layer away from the isolation structure, the word lines extending along the first direction and surrounding the plurality of semiconductor portions arranged in the first direction;

[0047] A gate dielectric layer is located between the word line and the semiconductor portion;

[0048] The second dielectric layer is located on the side of the first dielectric layer away from the isolation structure and between the word lines adjacent to it in the third direction; the second dielectric layer extends along the first direction.

[0049] A fourth dielectric layer is located on the side of the word line away from the first dielectric layer and extends along the first direction;

[0050] Bit lines are located on the side of the fourth dielectric layer away from the word lines, the bit lines extend along the first direction and the third direction, and are coupled to a plurality of the semiconductor portions.

[0051] In some embodiments, the semiconductor device further includes a capacitor, the capacitor including the first electrode, a capacitor dielectric layer, and a second electrode;

[0052] The first electrode is a hollow structure with an opening on one side, wherein the sidewall opposite to the opening is coupled to the semiconductor portion;

[0053] The second electrode is located within the hollow structure and extends along the first direction and the third direction on the side of the first electrode away from the semiconductor portion;

[0054] The capacitor dielectric layer is located between the first electrode and the second electrode.

[0055] Some embodiments of this disclosure provide an electronic device, including:

[0056] Processing devices; and

[0057] The storage device, coupled to the processing device, includes a semiconductor device manufactured using the semiconductor device manufacturing method described in any of the preceding claims, and / or includes a semiconductor device described in any of the preceding claims.

[0058] The semiconductor device manufacturing method provided in this disclosure involves first etching an initial isolation structure through trenches to expose a cavity, and then depositing an isolation material within the cavity and the initial isolation structure to obtain an isolation structure without a cavity. This ensures that when a portion of the isolation structure is subsequently etched away through trenches, the remaining isolation structure has substantially equal dimensions along the second direction, improving the consistency of isolation performance between functional devices (e.g., memory cells) located on opposite sides of the remaining isolation structure along the first direction. Furthermore, the remaining isolation structure has a complete surface without any connection points to the internal cavity, preventing short circuits between conductive materials when forming conductive materials such as a first electrode on the isolation structure surface. In other words, the cavity-free isolation structure improves the process window and reliability during semiconductor device fabrication, thereby enhancing the reliability of the final semiconductor device. Attached Figure Description

[0059] Figure 1a A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0060] Figure 1b for Figure 1a The diagram shows a cross-sectional view of the semiconductor structure.

[0061] Figure 2 for Figure 1b A schematic diagram showing the semiconductor structure being etched laterally;

[0062] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0063] Figure 4a A schematic diagram of the initial isolation structure provided in an embodiment of this disclosure;

[0064] Figure 4b for Figure 4a A schematic cross-sectional view of the initial isolation structure is shown below;

[0065] Figure 5a A schematic diagram of a semiconductor device including a mask layer provided for embodiments of this disclosure;

[0066] Figure 5b for Figure 5a The diagram shown is a top view of a semiconductor device including a mask layer.

[0067] Figure 6 A schematic diagram of a semiconductor device including a first trench and a second trench provided for embodiments of this disclosure;

[0068] Figure 7a A schematic diagram of the initial isolation structure after lateral etching provided in an embodiment of this disclosure;

[0069] Figure 7b for Figure 7a A schematic cross-sectional view of the initial isolation structure after lateral etching is shown.

[0070] Figure 8a A schematic diagram of a semiconductor device including an isolation structure provided for embodiments of this disclosure;

[0071] Figure 8b for Figure 8a The diagram shows a cross-sectional view of a semiconductor device including an isolation structure.

[0072] Figure 9 A schematic diagram of a semiconductor device including an isolation structure, a first trench, and a second trench, provided for embodiments of this disclosure;

[0073] Figure 10A schematic flowchart illustrating another method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0074] Figure 11a This is a schematic diagram of a stacked structure with an isolation structure provided in an embodiment of the present disclosure;

[0075] Figure 11b for Figure 11a The diagram shows a cross-sectional view of a stacked structure with an isolation structure.

[0076] Figure 12 A schematic diagram of a stacked structure having a third dielectric layer provided in an embodiment of this disclosure;

[0077] Figure 13 A schematic diagram of a stacked structure having a first chamber provided for an embodiment of this disclosure;

[0078] Figure 14a A schematic diagram of a stacked structure having a second chamber provided for an embodiment of this disclosure;

[0079] Figure 14b for Figure 14a A schematic cross-sectional view of the stacked structure forming the second chamber is shown in Figure 1.

[0080] Figure 14c for Figure 14a The schematic cross-section of the stacked structure forming the second chamber is shown. Figure 2 ;

[0081] Figure 15a This is a schematic diagram of a stacked structure with word lines provided in an embodiment of the present disclosure;

[0082] Figure 15b for Figure 15a The diagram shows a cross-sectional view of the stacked structure with letter lines.

[0083] Figure 15c for Figure 15a The diagram shows a cross-section of a stacked structure with letter lines. Figure 2 ;

[0084] Figure 16 A schematic diagram of a stacked structure having a second side cavity provided in an embodiment of this disclosure;

[0085] Figure 17 A schematic diagram of a stacked structure having a first electrode formed, provided for an embodiment of this disclosure;

[0086] Figure 18 A schematic diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0087] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0088] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0089] Figure 1a This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 1b for Figure 1a The diagram shows a cross-sectional view of the semiconductor structure along the AA′ plane. In the diagram, the X and Y directions are perpendicular to each other and both parallel to the surface of the substrate 100, while the Z direction is perpendicular to the surface of the substrate 100. Figure 1a and Figure 1b As shown, the semiconductor structure includes a substrate 100 and a stacked structure 200 located on the substrate 100. The stacked structure 200 includes semiconductor layers 210 spaced apart in the Z direction. A plurality of insulating trenches 10 are formed in the stacked structure 200, spaced apart in the Y direction. The insulating trenches 10 extend in the X direction, and first side-hole trenches 20 and second side-hole trenches 30 are formed on both sides of the insulating trenches 10 in the X direction, respectively. The first side-hole trenches 20, second side-hole trenches 30, and the plurality of insulating trenches 10 divide each semiconductor layer 210 into multiple portions, each portion for forming a memory cell.

[0090] See Figure 1a and Figure 1b When insulating material 11 is deposited in insulating trench 10, the size of insulating trench along Z direction is larger than that along Y direction. This may cause the opening of the trench to be sealed by insulating material 11 before the inside of insulating trench 10 is completely filled, thus forming a cavity 12 in insulating trench 10.

[0091] See Figure 2In subsequent steps, a filling material 31 needs to be temporarily formed within the second side trench 30, and the insulating material 11 in the insulating trench 10 is etched away based on the first side trench 20 to form a continuous side cavity along the Y direction to prepare word lines extending along the Y direction. However, during the lateral etching of the insulating material 11, the cavity 12 may be exposed, causing the etching solution to enter the cavity and etch the insulating material 11 near the second side trench 30. On the one hand, after etching for a preset duration, the size of the remaining insulating material 11 in the X direction in the insulating trenches with cavities 12 will be smaller than the size of the insulating material in the X direction without cavities, which may affect the performance consistency of multiple transistors arranged in the Y direction. On the other hand, as Figure 2 As shown, the cavities 12 expand during the etching process. The remaining insulating material within the insulating trenches containing these cavities 12 may expose the sidewalls of the semiconductor layer 210. In subsequent capacitor fabrication steps, when the first electrode is fabricated by removing part of the semiconductor layer 210 based on the second side trench 30, the cavities 12 in the remaining insulating material may be exposed, affecting the isolation performance of the first electrodes of multiple capacitors in the Y direction. In other words, the cavities 12 within the insulating trenches 10 pose a certain risk to the fabrication and performance of the three-dimensional memory.

[0092] In view of this, embodiments of the present disclosure provide a method for manufacturing a semiconductor device to eliminate or significantly reduce cavities within insulating trenches. Figure 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 3 As shown, the manufacturing method includes:

[0093] S100: A stacked structure is formed on the substrate;

[0094] S200: A plurality of initial isolation structures are formed in the stacked structure along a first direction, and the initial isolation structures extend along a second direction; wherein, at least one initial isolation structure contains a cavity; the first direction and the second direction intersect and are both parallel to the substrate surface;

[0095] S300: A trench is formed on at least one of the opposite sides of the initial isolation structure along the second direction, the trench extends along the first direction, and the sidewalls of the trench expose a plurality of initial isolation structures.

[0096] S400: Based on trench lateral etching, multiple initial isolation structures are etched to expose the cavity;

[0097] S500: Based on the trench, the space and cavity where the initial isolation structure is removed are filled with isolation material; wherein, the remaining initial isolation structure and isolation material constitute the isolation structure.

[0098] It should be understood that Figure 3The steps shown are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Figures 4a to 9 This is a schematic diagram illustrating the manufacturing process of a semiconductor device provided in an embodiment of this disclosure. The following is in conjunction with... Figure 3 , Figures 4a to 9 The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0099] In this disclosure, the first direction intersects the second direction and is parallel to the surface of the substrate 100. The intersection of the first and second directions includes the first direction being perpendicular to the second direction. Subsequent references to the third direction indicate that it is perpendicular to the surface of the substrate 100. This disclosure uses the Y direction in the accompanying drawings as the first direction, the X direction as the second direction, and the Z direction as the third direction as an example for illustration. However, it should be understood that the descriptions of directions in the following embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0100] See Figure 4a and Figure 4b , Figure 4b yes Figure 4a A cross-sectional schematic diagram along the AA′ plane shows step S100, in which a stacked structure 200 is formed on the substrate 100. For example, the substrate 100 may be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compounds (e.g., GaN, GaAs, InAs, etc.), or any other suitable semiconductor material. The substrate 100 may also be made of other materials. In this embodiment, the substrate 100 is a silicon substrate.

[0101] This disclosure does not limit the film materials or film stacking methods of the stacked structure 200. The stacked structure 200 can be any commonly used stacked structure in the art for forming a three-dimensional stacked memory. For example, the stacked structure 200 may include alternating layers of interlayer dielectric layers and semiconductor layers, or it may include alternating layers of interlayer dielectric layers and sacrificial layers, or it may include alternating layers of a first sacrificial layer and a second sacrificial layer, etc. The stacked structure 200 can also be any stacked structure that requires the formation of an isolation structure.

[0102] See also Figure 4a and Figure 4bIn step S200, a plurality of initial isolation structures 310 arranged along the first direction Y are formed in the stacked structure 200. Each initial isolation structure 310 extends along the second direction X and penetrates the stacked structure 200 along the third direction Z. For example, the fabrication process of the initial isolation structure 310 includes: sequentially performing photolithography and etching processes to form a plurality of isolation trenches 311 arranged along the first direction in the stacked structure 200, with the bottom of the isolation trenches 311 exposing the substrate 100; then, initial isolation material can be deposited in the isolation trenches 311 using processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD) to obtain the initial isolation structure 310. As mentioned above, due to the elongated and deep structural characteristics of the isolation trenches 311, the opening of the trench may be prematurely closed by the initial isolation material before the interior of the isolation trench 311 is completely filled, resulting in at least one cavity 12 in the initial isolation structure 310.

[0103] See Figures 5a to 6 In step S300, a trench is formed on at least one of the opposite sides of the initial isolation structure 310 along the second direction X. For example, a trench may be formed on only one side of the initial isolation structure 310 along the second direction X. This trench may be a first side-drilled trench used in transistor fabrication processes or a second side-drilled trench used in capacitor fabrication processes. Alternatively, as shown in this embodiment, a first trench 510 and a second trench 520 may be formed on opposite sides of the initial isolation structure 310 along the second direction X, i.e., trenches are formed on both sides of the initial isolation structure 310.

[0104] In some embodiments, step S300, which forms a trench, specifically includes: forming a mask layer on a stacked structure; patterning the mask layer to form an opening in the mask layer; the opening extending along a first direction and overlapping with the top surface portion of a plurality of initial isolation structures; and etching the stacked structure and the plurality of initial isolation structures based on the opening to form a trench.

[0105] Specifically, see Figure 5a and Figure 5b , Figure 5b yes Figure 5aThe diagram shows a top view of a stacked structure 200, on which a protective layer 410 is formed, and a mask layer 420 is formed on the protective layer 410. For example, the protective layer 410 and the initial isolation structure 310 may have a certain etching selectivity ratio, such that the protective layer 410 is not etched during subsequent lateral etching of the initial isolation structure 310. The protective layer 410 and the initial isolation structure 310 may be made of different materials; for example, the initial isolation structure may include silicon oxide, and the protective layer 410 may include silicon nitride. The mask layer 420 generally refers to a film layer capable of selectively protecting specific areas of the wafer surface, allowing the target area to be processed. The mask layer 420 may include at least one of a photoresist layer or a hard mask layer. The hard mask layer may be selected from one or a combination of carbon layers, polysilicon layers, silicon oxynitride layers, silicon carbide nitride layers, silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0106] Furthermore, it should be understood that the mask layer 420 can also serve a protective function. Therefore, in some embodiments, the protective layer 410 can be omitted, and the mask layer 420 can be used to cover the top of the initial isolation structure 310 to enable lateral etching of the initial isolation structure 310 in subsequent steps.

[0107] Next, the mask layer 420 on the stacked structure 200 is patterned to form a first opening 421 and a second opening 422 in the mask layer 420. When the mask layer 420 consists only of a photoresist layer, the patterning of the mask layer 420 is achieved through exposure and development. When the mask layer 420 includes a photoresist layer and a hard mask layer, the photoresist layer can be exposed and developed first to transfer the pattern on the mask to the photoresist layer, and then the hard mask layer can be etched based on the patterned photoresist layer to obtain a patterned hard mask layer. Figure 5a and Figure 5b As shown, a first opening 421 and a second opening 422 are formed in the patterned mask layer 420. The first opening 421 and the second opening 422 are spaced apart along the second direction X and both extend along the first direction Y.

[0108] For example, the spacing S1 between the first opening 421 and the second opening 422 is less than the width W1 of the initial isolation structure 310 along the second direction X. The spacing S1 between the first opening 421 and the second opening 422 refers to the minimum distance between their edges. This allows the first opening 421 to overlap with the top surface portions of the plurality of initial isolation structures 310, that is, the first opening 421 overlaps with the orthographic projection portions of the plurality of initial isolation structures 310 on the surface of the substrate 100. And / or, the second opening 422 can overlap with the top surface portions of the plurality of initial isolation structures 310, that is, the second opening 422 overlaps with the orthographic projection portions of the plurality of initial isolation structures 310 on the surface of the substrate 100.

[0109] In this embodiment, the first opening 421 and the second opening 422 overlap with the top surface portions of a plurality of initial isolation structures 310, respectively. For example, the overlapping area of ​​the initial isolation structure 310 and the first opening 421 has a first dimension D1 along a second direction, where the first dimension D1 is greater than zero and less than the width W2 of the first opening 421 along the second direction. The overlapping area of ​​the initial isolation structure 310 and the second opening 422 has a second dimension D2 along the second direction, where the second dimension D2 is greater than zero and less than the width W3 of the second opening 422 along the second direction. This allows for simultaneous etching of the initial isolation structure 310 and simultaneous deposition of isolation material through the first opening 421 and the second opening 422 in subsequent steps, thereby accelerating the etching rate of the initial isolation structure 310 and the filling rate of the cavity, and shortening the process time.

[0110] In some embodiments, the first dimension D1 is equal to the second dimension D2. That is, the perpendicular bisectors of the first opening 421 and the second opening 422 (i.e., their axes of symmetry) overlap with the centerline of the initial isolation structure 310 (the axis that divides the initial isolation structure 310 into two perfectly symmetrical parts in the second direction X). This balances the etching rates on both sides of the initial isolation structure 310, making the time when the cavity is exposed on both sides close, thus minimizing the etching time. Furthermore, it balances the deposition rate of the isolation material on both sides, accelerating the deposition of the isolation material within the cavity.

[0111] See Figure 5b and Figure 6 Based on the first opening 421 and the second opening 422, the stacked structure 200 and the plurality of initial isolation structures 310 are etched to form a first trench 510 and a second trench 520. Specifically, the protective layer 410 is first etched based on the first opening 421 and the second opening 422 to expose the top surface of the stacked structure 200 and the plurality of initial isolation structures 310. Figure 5b As shown, the top surface of the initial isolation structure 310 exposed at the first opening 421 has a first dimension D1 along the second direction, which is smaller than the width W2 of the first opening 421 along the second direction. The top surface of the initial isolation structure 310 exposed at the second opening 422 has a second dimension D2 along the second direction, which is smaller than the width W3 of the second opening 422 along the second direction.

[0112] Next, an etchant with a high etching rate for both the stacked structure 200 and the initial isolation structure 310 can be used to etch both simultaneously; alternatively, a multi-step etching scheme can be employed, for example, etching the stacked structure 200 first, and then etching the multiple initial isolation structures 310. In one specific embodiment, if the stacked structure 200 includes silicon and silicon-germanium layers alternately stacked along the third direction Z, and the material of the initial isolation structure 310 is silicon oxide, then when using a dry etching process, chlorine-based gases (e.g., hydrogen chloride, chlorine) can be used to simultaneously etch the silicon and silicon-germanium layers, and then fluorine-based gases (e.g., carbon tetrafluoride, trifluoromethane) can be used to etch the multiple initial isolation structures 310. Alternatively, when using a wet etching process, a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) can be used to simultaneously etch the silicon and silicon-germanium layers, and then an HF solution can be used to etch the multiple initial isolation structures 310. This disclosure does not impose too many restrictions on the formation process of the first trench 510 and the second trench 520.

[0113] like Figure 6 As shown, the first trench 510 and the second trench 520 extend along the first direction Y and pass through the stacked structure 200 along the third direction Z. The sidewalls of both the first trench 510 and the second trench 520 expose a plurality of initial isolation structures 310 arranged along the first direction Y. It is worth noting that, see Figure 4a Because the initial isolation structure 310 required by the design has unequal and significant dimensions in the first direction Y and the second direction X, during the etching process to form the isolation trench 311, the long side of the isolation trench 311 is prone to taper due to ion scattering and shielding effects and micro-loading effects, and the bottom of the sidewall of the long side slopes inward. For example... Figure 6 As shown, this could result in the first trench 510 and the second trench 520 exposing only the upper section of the initial isolation structure 310. However, in some embodiments, if the taper of the long side of the isolation groove 311 is small, the first trench 510 and the second trench 520 can expose the entire area of ​​the sidewall of the initial isolation structure 310. It is understood that both cases allow for the subsequent step of removing a portion of the initial isolation structure 310 through the first trench 510 and the second trench 520.

[0114] See Figure 7a and Figure 7b , Figure 7b yes Figure 7a A cross-sectional schematic diagram along the AA′ plane is shown. Step S400 is performed, in which multiple initial isolation structures 310 are laterally etched based on the first trench 510 to expose the cavity 12, and multiple initial isolation structures 310 are laterally etched based on the second trench 520 to expose the cavity 12. The lateral etching process includes wet etching and / or gas etching.

[0115] Taking wet etching as an example, the etching solution enters the first trench 510 and the second trench 520, and simultaneously etches the exposed initial isolation structure 310 from opposite sides in the second direction X. For example, the etching solution flows from... Figure 6 The etching process begins on the upper section of the sidewall of the initial isolation structure 310 exposed in the cavity 12, continuing until both sides of the cavity 12 are exposed. It should be noted that when forming the trench using the multi-step etching scheme described above, in the second etching step of the wet etching process, after etching away the initial isolation structure 310 exposed by the first opening 421 and the second opening 422, the initial isolation structure 310 can be etched further until the cavity 12 is exposed. For example, the cavity 12 can be ensured to be exposed by controlling etching parameters, such as the etching duration.

[0116] See Figure 8a and Figure 8b , Figure 8b yes Figure 8a A schematic diagram of the cross-section along plane AA′. Figure 8a The area where the remaining initial isolation structure 310 is located is shown in dashed lines. Step S500 is performed, in which isolation material 320 is filled into the space and cavity 12 where the initial isolation structure 310 has been removed, based on the first trench 510 and the second trench 520.

[0117] For example, atomic layer deposition, chemical vapor deposition, or other processes can be used to deposit isolation material 320 in the cavity 12, the space where the initial isolation structure 310 is removed, the first trench 510, the second trench 520, and the top surface of the stacked structure (specifically, the top surface of the protective layer 410). For example, the isolation material 320 is made of the same material as the initial isolation structure 310 to ensure consistent isolation performance between the first electrodes. The isolation material 320 includes, but is not limited to, at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide.

[0118] It should be noted that in some embodiments, trenches can be formed only on one side of the initial isolation structure 310 along the second direction X to etch and deposit isolation material. However, in this embodiment, the isolation material is deposited into the cavity from the first trench 510 and the second trench 520. Compared to single-end etching and deposition with trenches only on one side, this significantly reduces the risk of secondary gaps appearing in the isolation material within the cavity. In this embodiment, the open ends of the cavity form a bidirectional gas flow path, allowing reactive gases to enter from both ends of the cavity and byproduct gases generated during deposition to exit from both ends. Sufficient gas diffusion ensures uniform deposition of isolation material on the surface of the cavity until it completely fills the cavity and the space where the initial isolation structure was removed, resulting in a material within the isolation trench. Figure 8a The solid insulating material 320 shown.

[0119] See Figure 9 , Figure 9 The remaining area of ​​the initial isolation structure 310 is shown in dashed lines. Dry etching is used to remove the isolation material 320 within the first trench 510 and the second trench 520, leaving only the isolation material 320 within the isolation groove 311—that is, the isolation material 320 within the cavity 12 and the space where the initial isolation structure 310 was removed—forming the isolation structure 300. The isolation structure 300 completely fills the space of the isolation groove 311 located between the first trench 510 and the second trench 520.

[0120] In this embodiment, the initial isolation structure is first etched using a first trench and a second trench until the cavity is exposed. Then, isolation material is deposited within the cavity and the initial isolation structure to obtain an isolation structure without the cavity. This way, when a portion of the isolation structure is subsequently etched away using the first trench (or the second trench), the remaining isolation structure has substantially equal dimensions along the second direction X, improving the consistency of isolation performance between memory cells. Furthermore, the remaining isolation structure has a complete surface without any connection points to the internal cavity. This prevents short circuits between the first electrodes when forming the first electrode on the isolation structure surface, thus improving the isolation of the first electrode. In other words, the cavity-free isolation structure improves the process window and reliability during semiconductor device fabrication, thereby enhancing the reliability of the final semiconductor device.

[0121] It should be noted that even if gaps may remain in the isolation material within the cavity due to trench etching and deposition on one side, the isolation material 320 has already significantly reduced the size of the cavity. These remaining gaps will not cause problems during the etching of the isolation structure, for example... Figure 2 The exposed semiconductor layer does not affect the isolation performance of the capacitor, and the impact on the memory cell array is within an acceptable range.

[0122] In addition, compared to Figure 1a The first side-cut groove 20 and the second side-cut groove 30 are isolated from the insulating groove 10. In this embodiment, the distance between the first groove and the second groove can be increased while maintaining the distance between the first side-cut groove and the second side-cut groove equal to the distance between the first side-cut groove and the second side-cut groove. Figure 4bThe size of the isolation trench 311 along the second direction X is such that both the first trench and the second trench partially overlap with the initial isolation structure. This reduces the distance between the bottom of the initial isolation structure (or the isolation structure) and the first and second trenches. The size of the subsequently formed first electrode along the second direction X mainly depends on the size of the bottom of the isolation structure along the second direction. In this embodiment, when the distance between the bottom of the isolation structure and the first and second trenches is reduced, it is beneficial to increase the size of the first electrode along the second direction X. That is, while maintaining the original distance between the first and second trenches, increasing the size of the first electrode along the second direction is beneficial to increasing the capacity of the memory cell. Alternatively, while keeping the size of the initial isolation structure along the second direction X unchanged, the distance between the first and second trenches can be reduced so that they partially overlap. This reduces the distance between memory cells in the second direction while keeping the size of the memory cell in the second direction unchanged. In summary, the partial overlap of the first trench, the second trench, and the initial isolation structure helps to reduce the area waste of the memory cell in the second direction caused by the taper.

[0123] This disclosure also provides another method for manufacturing a semiconductor device. Figure 10 A schematic flowchart illustrating another method for manufacturing a semiconductor device according to an embodiment of this disclosure is shown below. Figure 10 As shown, the manufacturing method includes:

[0124] S101: A semiconductor layer and a sacrificial layer are alternately stacked along a third direction on a substrate, the third direction being perpendicular to the substrate surface; the substrate includes capacitor regions and transistors arranged along a second direction;

[0125] S600: A first side cavity is formed by removing the sacrificial layer of the transistor region and multiple isolation structures based on the first trench;

[0126] S700: Based on the first trench, a first dielectric layer and a word line located in the first dielectric layer and extending along the first direction are formed in the first side cavity;

[0127] S800: The semiconductor layer of the capacitor region is removed based on the second trench to form a second side cavity; the second side cavity exposes the isolation structure of the capacitor region.

[0128] S900: A first electrode is formed in the second side cavity, and the first electrode is coupled to the semiconductor layer of the transistor region.

[0129] It should be understood that Figure 10 The steps shown are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Figures 11a to 17 This is a schematic diagram illustrating the manufacturing process of another semiconductor device provided in an embodiment of this disclosure. The following is in conjunction with... Figure 10 , Figures 11a to 17Another method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0130] See Figure 11a and Figure 11b , Figure 11b yes Figure 11a A schematic cross-sectional view along BB′. Step S101 is performed to form a stacked structure 200 on the substrate 100. The stacked structure 200 includes semiconductor layers 210 and sacrificial layers 220 alternately stacked along the third direction Z. The substrate 100 includes adjacent transistor regions and capacitor regions in the second direction X, and both the semiconductor layers 210 and the sacrificial layer 220 extend within the transistor regions and capacitor regions.

[0131] For example, the sacrificial layer 220 serves as a seed layer, and a single-crystal semiconductor layer 210 is grown on the sacrificial layer 220 using an epitaxial process. The materials of the sacrificial layer 220 include silicon-germanium, sapphire (alumina), silicon carbide, germanium, etc. The semiconductor layer 210 can be a single-crystal semiconductor such as single-crystal silicon, single-crystal germanium, or single-crystal silicon-germanium, prepared by an epitaxial process. Single-crystal semiconductors have good electrical uniformity, high performance consistency, and extremely high carrier mobility, which is beneficial for improving the switching speed of transistors. Using a single-crystal semiconductor as a channel improves the switching speed, reliability, and overall performance of the transistor. In this embodiment, the material of the sacrificial layer 220 is silicon-germanium, and the material of the semiconductor layer 210 is epitaxially grown single-crystal silicon.

[0132] See Figure 11b The steps S200 to S500 as shown in any of the above embodiments are performed to form multiple rows of isolation structures 300 arranged along the second direction X within the stacked structure 200, and a first trench 510 and a second trench 520 located on opposite sides of each row of isolation structures 300 along the second direction X. For example, adjacent rows of isolation structures 300 may share the same first trench 510, and / or adjacent rows of isolation structures 300 may share the same second trench 520. This embodiment illustrates the case where adjacent rows of isolation structures 300 share the first trench 510, and the two opposite sidewalls of the first trench 510 expose the two rows of isolation structures 300 respectively. In the above steps S200 to S500, two rows of initial isolation structures can be simultaneously etched to expose cavities based on the first trench 510 and the two second trenches 520, and isolation material can be deposited simultaneously to obtain two rows of isolation structures 300.

[0133] Each column of isolation structures 300 includes a plurality of isolation structures 300 spaced apart along a first direction Y. The isolation structures 300 extend along a second direction X in the transistor region and the capacitor region, and the isolation structures 300 penetrate the stacked structure 200 along a third direction Z. For example, the material of the isolation structures 300 is silicon oxide. Figure 11bIt can be seen that the isolation structure 300 prepared by the aforementioned method of etching back the initial isolation structure and depositing isolation material has basically no internal cavity and is a solid structure.

[0134] A first trench 510 is located in the stacked structure 200 on the side of the transistor region away from the capacitor region, and a second trench 520 is located in the stacked structure 200 on the side of the capacitor region away from the transistor region. Both the first trench 510 and the second trench 520 extend along a first direction Y and a third direction Z, and their sidewalls expose the isolation structure 300. Figure 9 After the steps shown form the isolation structure 300, the first support structure 610 is then filled into the first trench 510, and the second support structure 620 is filled into the second trench 520. For example, both the first support structure 610 and the second support structure 620 include a support body and a stop layer surrounding the sidewalls and bottom of the support body. The material of the support body is, for example, polycrystalline silicon, and the material of the stop layer is, for example, silicon oxide.

[0135] See Figure 12 The second support structure 620 is removed to expose the second trench 520, and the sacrificial layer 220 of the capacitor region is replaced with a third dielectric layer 710 based on the second trench 520. For example, the replacement process includes: removing the sacrificial layer 220 of the capacitor region along the second trench 520, and etching the semiconductor layer 210 from the location where the sacrificial layer 220 was removed to increase the vertical spacing between adjacent semiconductor layers 210 in the third direction Z; then, depositing the third dielectric layer 710 in the space between adjacent semiconductor layers 210. The thickness of the third dielectric layer 710 in the third direction Z is greater than that of the original sacrificial layer 220. For example, the material of the third dielectric layer 710 includes, but is not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbide nitride. In this embodiment, the material of the third dielectric layer 710 is silicon oxide.

[0136] Next, a third support structure 630 is filled into the second trench 520. The third support structure 630 has the same structure as the second support structure 620, including, for example, a support body and a stop layer surrounding the sidewalls and bottom of the support body. The material of the support body is, for example, polycrystalline silicon, and the material of the stop layer is, for example, silicon oxide.

[0137] See Figure 12 and Figure 13The first support structure 610 is removed to release the first trench 510. Specifically, a first top protective layer 770 is formed covering the third support structure 630 and the first support structure 610. Then, the first top protective layer 770 is etched to expose the first support structure 610. The support body of the first support structure 610 is removed by dry etching or wet etching, and the stop layer of the first support structure 610 is removed by dry etching or wet etching to expose the sacrificial layer 220 and semiconductor layer 210 arranged alternately in the stacked structure. The first top protective layer 770 can protect the third support structure 630 during the removal of the first support structure 610 and subsequent deposition and etching steps.

[0138] See also Figure 13 The sacrificial layer 220 of the transistor region is removed based on the first trench 510, and the exposed semiconductor layer 210 is thinned at the location where the sacrificial layer 220 is removed to form a first chamber 531. For example, each exposed sacrificial layer 220 is etched laterally (e.g., wet etching) along the first trench 510, and the etching can stop at the surface of the third dielectric layer 710 of the capacitor region to form a plurality of first initial chambers arranged in an array along intersecting first directions Y and third directions Z. The surface of the first initial chambers exposes the third dielectric layer 710 and the isolation structure 300 (see reference). Figure 11b ) and semiconductor layer 210.

[0139] Next, the semiconductor layer 210 is thinned using wet etching. The etching solution uniformly etches the semiconductor layer 210 from both the top and bottom sides within the first initial chamber, resulting in a uniform thinning of the semiconductor layer 210 from both sides. Simultaneously, the etching solution within the first trench 510 can etch the semiconductor layer 210 from a second direction. (See also...) Figure 9 When the isolation structure 300 has a certain taper, it may cause the semiconductor layer at the bottom of the stacked structure 200 to partially connect in the first direction Y. In this step, the etching solution in the first trench 510 can etch the semiconductor layer from the second direction to remove this part, so that the semiconductor layers in the first direction Y are isolated from each other. After thinning the semiconductor layer, the area where the sacrificial layer 220 and the semiconductor layer 210 are removed forms the first chamber 531. Along the first direction Y, a plurality of first chambers 531 are separated by the isolation structure 300, but each first chamber 531 is connected to the first trench 510. The surface of the first chamber 531 exposes the third dielectric layer 710, the isolation structure 300 and the semiconductor layer 210.

[0140] See Figures 14a to 14c , Figure 14b yes Figure 14a A schematic diagram of the cross-section along BB′. Figure 14c yes Figure 14aA cross-sectional view along CC′ shows the removal of the isolation structure 300 in the transistor region from the first trench 510, forming a second chamber 532. For example, the isolation structure 300 can be wet-etched. Etching solution enters the first chamber 531 to etch the two opposing sidewalls of the isolation structure 300 along the first direction Y, while simultaneously, etching solution within the first trench 510 etches the isolation structure 300 along the second direction X. By controlling the etching time, the isolation structure 300 in the transistor region is removed while the isolation structure 300 in the capacitor region is retained. The second chamber 532 formed after removing the isolation structure 300 in the transistor region is as follows... Figure 14c As shown by the dashed box, the second chamber 532 is connected to a plurality of first chambers 531 arranged in the third direction Z. All the second chambers 532 and all the first chambers 531 constitute the first side cavity 530. At this time, the semiconductor layer 210 of the transistor region is suspended in the first side cavity 530, and the upper and lower sidewalls of the semiconductor layer 210 and the two opposite sidewalls along the first direction Y are exposed, so that the plurality of transistors arranged along the first direction Y can be isolated from each other.

[0141] like Figure 14b As shown, since the isolation structure 300 formed by the aforementioned steps 200 to S500 has virtually no cavities, the etching solution can be prevented from etching the isolation structure 300 of the capacitor region through cavities. This ensures that there are no cavities in the isolation structure of the capacitor region that connect to its surface, thereby guaranteeing a good morphology of the first electrode and the insulating layer between the first electrodes. Furthermore, since the isolation structure 300 has virtually no cavities, after the lateral etching process, the remaining isolation structure 300 exposes a basically flat surface at the second chamber 532. In this disclosure, a flat surface refers to a surface that is macroscopically continuous, without obvious depressions or open holes.

[0142] join Figures 15a to 15c , Figure 15b yes Figure 15a A schematic diagram of the cross-section along BB′. Figure 15c yes Figure 15aAlong the cross-sectional view of CC′, step S700 is performed to form a first dielectric layer 720 and a word line 810. In some embodiments, the fabrication steps of the first dielectric layer 720 and the word line 810 are as follows: First, a first dielectric material is deposited on the surfaces of the first chamber and the second chamber. The first dielectric material covers the sidewalls of the isolation structure 300 in the capacitor region, the sidewalls of the third dielectric layer 710, and the exposed surface of the semiconductor layer 210 in the transistor region. The first dielectric material surrounding the surface of the semiconductor layer 210 is interconnected with each other in the first direction Y. Next, a second dielectric material is deposited on the surface of the first dielectric material. The second dielectric material fills the remaining space of the first chamber 531 and the remaining space of the second chamber 532, wherein the second dielectric material is also located within the first trench 510. Next, the second dielectric material within the first trench 510 is removed by dry etching or wet etching, and the remaining second dielectric material located within the first side cavity 530 forms the second dielectric layer 730. Subsequently, the first dielectric material is etched back from the first trench 510, retaining a portion of the first dielectric material near the third dielectric layer 710 to obtain the first dielectric layer 720. For example, a wet etching process can be used to etch back the first dielectric material.

[0143] like Figure 15b As shown, the contact interface between the first dielectric layer 720 and the isolation structure 300 is a flat surface. Furthermore, the multiple isolation structures 300 are flush with each other near the sidewalls of the first dielectric layer 720.

[0144] Furthermore, it should be noted that even though etching the initial isolation structure and depositing isolation material through single-sided trenches may leave residual gaps within the isolation structure, these gaps are extremely small and will not expose the semiconductor layer of the capacitor region. Moreover, these small gaps are easily sealed during the deposition of the first dielectric material and will not affect the subsequent word line morphology. In other words, even with the presence of small gaps, the impact on the performance of the memory cell array is minimal.

[0145] See also Figures 15a to 15c A thin-film gate dielectric layer 740 is deposited in the space formed after the first dielectric material is etched back, and word line material is deposited on the surface of the gate dielectric layer 740 to fill the space. It is understood that since the first dielectric materials surrounding the semiconductor layer 210 are interconnected in the first direction, the space formed after the first dielectric material is etched back extends continuously along the first direction Y, and several semiconductor layers 210 are suspended therein. The word line material deposited in this space obviously surrounds the suspended semiconductor layers 210 and extends continuously along the first direction Y.

[0146] Next, word line material is etched back from the first trench 510 to remove part of the word line material, leaving word line material with the required width as designed, resulting in word line 810. Word line 810 extends along the first direction Y and surrounds multiple semiconductor layers 210 of the transistor region. A gate dielectric layer 740 is provided between word line 810 and semiconductor layer 210.

[0147] Finally, the space released after the word line material is etched back is filled with a fourth dielectric layer 750. For example, the first dielectric layer 720 is made of silicon nitride, the gate dielectric layer 740 is made of silicon oxide, the second dielectric layer 730 is made of silicon oxide, and the fourth dielectric layer 750 is made of silicon nitride. The word line 810 is made of at least one of metals such as tungsten, copper, aluminum, gold, titanium, silver, cobalt, and nickel, and metal nitrides such as titanium nitride, tungsten nitride, and tantalum nitride. In this embodiment, the word line 810 is made of titanium nitride.

[0148] See Figure 15a and Figure 15b Bit lines 830 are formed within the first trench 510 to contact the semiconductor layer 210. The bit lines 830 can be a single-layer structure or a multi-layer composite structure. In this embodiment, the bit lines 830 are multi-layer composite structures, including a polysilicon layer 831, a metal layer 832, and a metal nitride layer 833 stacked sequentially. The polysilicon layer 831 is located on the sidewalls and bottom of the first trench 510 and is in contact with the semiconductor layer 210. The metal layer 832 covers the polysilicon layer 831, and the metal nitride layer 833 covers the metal layer 832 and fills the remaining space of the first trench 510.

[0149] For example, the bit lines can be heat-treated to react the polysilicon layer 831 and the metal layer 832 to form a metal silicide layer. This metal silicide layer can reduce the contact resistance between the metal or metal nitride layer and the semiconductor layer. For example, the polysilicon layer 831 can be intrinsic polysilicon or doped polysilicon doped with elements such as phosphorus or boron. The material of the metal layer includes, but is not limited to, nickel, cobalt, tungsten, and titanium, and the formed metal silicide includes, but is not limited to, titanium silicide, nickel silicide, tungsten silicide, and cobalt silicide. The material of the metal nitride includes, but is not limited to, titanium nitride, tungsten nitride, and tantalum nitride.

[0150] Next, proceed to step S800. See also... Figure 15a and Figure 16The third support structure 630 is removed to release the second trench 520. Specifically, a second top protective layer 780 is formed covering the bit line 830 and the third support structure 630. Then, the second top protective layer 780 is etched to expose the third support structure 630. The support body of the third support structure 630 is removed using dry or wet etching, followed by dry or wet etching to remove the stop layer of the third support structure 630, exposing the alternating third dielectric layer 710 and semiconductor layer 210 within the stacked structure 200. Next, the semiconductor layer 210 is laterally etched based on the second trench 520 to remove the semiconductor layer 210 of the capacitor region, forming the second side cavity 540. The lateral etching process includes wet etching and / or gas etching. The second top protective layer 780 protects the bit line 830 during the removal of the third support structure 630, the etching of the semiconductor layer 210, and subsequent deposition and etching steps.

[0151] A contact layer 840 is formed within the second cavity 540, contacting the semiconductor layer 210 of the transistor region. For example, the contact layer formation steps include: forming a contact material layer using processes such as chemical vapor deposition or atomic layer deposition, then etching back the contact material layer, retaining only the section of the contact material layer in contact with the semiconductor layer 210 of the transistor region, to obtain the contact layer 840. The material of the contact layer 840 includes metal silicides, such as titanium silicide, nickel silicide, tungsten silicide, etc. The contact layer 840 is located between the semiconductor layer 210 of the transistor region and the first electrode of the capacitor, and can reduce the contact resistance between the first electrode and the semiconductor layer.

[0152] As mentioned earlier, if a cavity exists in the isolation structure, Figure 14b When etching the isolation structure 300 of the transistor region, the isolation structure 300 of the capacitor region may also be etched. This could lead to the cavity in the isolation structure 300 potentially connecting to the second side cavity 540 or the second trench 520 during the formation of the second side cavity 540 in this step. During the deposition of the contact material layer, the contact material may fill the cavity, causing the subsequently formed first electrodes to short-circuit with each other through the contact material within the cavity. In this embodiment, since there are essentially no cavities within the isolation structure 300 of the capacitor region, and no open holes or similar features on the two opposing surfaces of the isolation structure 300 exposed in the second side cavity 540 along the first direction Y, or on the surface of the isolation structure 300 exposed in the second trench 520 perpendicular to the second direction X, the short-circuiting problem of the first electrode subsequently formed within the second side cavity 540 can be avoided.

[0153] See Figure 17In step S900, a first electrode 851 is formed on the surfaces of the isolation structure 300 and the third dielectric layer 710 exposed in the second side cavity 540 based on the second trench 520. For example, the step of forming the first electrode includes: on the surface of the second side cavity 540, the surface of the second trench 520, and the top surface of the stacked structure (specifically...) Figure 16 The first electrode material is deposited on the top surface of the second top protective layer 780. The first electrode material is then etched away from the top surface of the stacked structure and within the first trench 510, leaving only the first electrode material on the surface of the isolation structure 300 and the surface of the third dielectric layer 710 to obtain the first electrode 851. It is worth noting that, as... Figure 9 As shown, when the isolation structure 300 has a certain taper, the etching time should be controlled to ensure that the bottom of the isolation structure 300 and the first electrode material located on the surface of the isolation structure 300 perpendicular to the second direction X are removed, so as to ensure that the first electrodes 851 are isolated from each other. It can be seen that the taper of the isolation structure affects the size of the first electrode 851 along the second direction X. Specifically, the size of the first electrode along the second direction X mainly depends on the size of the bottom of the isolation structure. In this embodiment, by making the first trench, the second trench overlap with the initial isolation structure portion, the area waste of the memory cell in the second direction caused by the taper of the isolation structure can be reduced.

[0154] The first electrode 851 is a hollow structure with one side open. The hollow structure includes a sidewall close to the semiconductor layer 210, and a top wall, a bottom wall, a front wall, and a rear wall extending from the sidewall away from the semiconductor layer 210. The top wall and bottom wall are opposite each other along the third direction Z and contact the third dielectric layer 710, while the front wall and rear wall are opposite each other along the first direction Y and contact the isolation structure 300. The sidewall, top wall, bottom wall, front wall, and rear wall are an integrated structure, and the sidewall opposite the open sidewall is coupled to the semiconductor layer 210 through a contact layer.

[0155] The manufacturing method further includes: forming a capacitor dielectric layer on the surface of the first electrode, and forming a second electrode on the surface of the capacitor dielectric layer.

[0156] See also Figure 17 A capacitor dielectric layer 852 is deposited on the inner surface of the hollow structure of the first electrode 851 and the surface of the second trench 520, and a second electrode 853 is covered on the surface of the capacitor dielectric layer 852. For example, the second electrode 853 can fill the remaining space of the second side cavity 540 and the second trench 520. Also for example, as... Figure 17As shown, the second electrode 853 can be a thin film covering the surface of the capacitor dielectric layer 852, not completely filling the second side cavity 540 and the second trench 520. Subsequently, a filling layer 854 is deposited in the remaining space of the second side cavity 540 and the second trench 520. The capacitor 850 includes a first electrode 851, a capacitor dielectric layer 852, and a second electrode 853. For example, the material of the capacitor dielectric layer 852 can be an insulating dielectric material such as silicon oxide, silicon nitride, or hafnium oxide, or a ferroelectric material such as lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT). The materials of the first electrode 851 and the second electrode 853 include metals and / or metal nitrides. After forming the capacitor, a semiconductor device is formed.

[0157] This disclosure also provides a semiconductor device, which is a semiconductor device manufactured using the manufacturing method described in any of the above embodiments. Therefore, the semiconductor device provided in this disclosure also has the beneficial effects corresponding to the manufacturing methods of any of the above semiconductor devices, which will not be repeated here.

[0158] In some embodiments, such as Figure 17 As shown, the semiconductor device includes a plurality of memory cells arranged on a substrate 100 along a first direction Y and a second direction X parallel to the substrate 100 and stacked along a third direction Z perpendicular to the substrate 100. Each memory cell includes a transistor and a first electrode 851 arranged side by side along the second direction X. The transistor includes a semiconductor portion extending along the second direction X. The first electrode 851 is coupled to the semiconductor portion. The first direction Y intersects the second direction X.

[0159] In this embodiment, the semiconductor part is the semiconductor layer 210 located in the transistor region in the above embodiment.

[0160] The semiconductor device also includes an isolation structure 300 and a first dielectric layer 720 (the positions of the isolation structure 300 and the first dielectric layer 720 are referenced). Figure 15b The isolation structure 300 is located between adjacent first electrodes 851 in the first direction Y, and the first dielectric layer 720 is located between adjacent semiconductor portions (semiconductor layers 210) in the first direction, wherein the contact interface between the isolation structure 300 and the first dielectric layer 720 is a flat surface.

[0161] For example, the isolation structure 300 extends along the second direction X and the third direction Z to isolate the first electrode 851 adjacent in the first direction Y. The first dielectric layer 720 surrounds the semiconductor layer 210 and extends along the first direction Y and the third direction Z. That is, the contact interface between the isolation structure 300 and the first dielectric layer 720 extends along the first direction Y and the third direction Z.

[0162] In the semiconductor device provided in this embodiment, the contact interface between the isolation structure 300 and the first dielectric layer 720 is a flat surface without obvious depressions (or protrusions). This ensures the consistency of isolation performance between memory cells in the first direction, avoids problems such as large device performance fluctuations and small operating voltage windows caused by large differences in isolation performance, and can improve the read / write voltage window and improve the reliability of data storage.

[0163] For example, a plurality of isolation structures 300 spaced apart by a first electrode 851 are provided in the first direction Y. (Reference) Figure 15b Multiple isolation structures 300 are flush with each other near the sidewalls of the first dielectric layer 720. This ensures the consistency of isolation performance between memory cells in the same layer.

[0164] In some embodiments, the isolation structure 300 has essentially no internal cavity, meaning it is essentially a solid structure. This ensures the consistency of isolation performance between the first electrodes 851 in the first direction.

[0165] In some embodiments, see Figure 15a and Figure 15b The transistor also includes a word line 810, which is located on the side of the first dielectric layer 720 away from the isolation structure 300. The word line 810 extends along a first direction Y and surrounds a plurality of semiconductor portions arranged in the first direction Y. A gate dielectric layer 740 is provided between the word line 810 and the semiconductor portions.

[0166] In some embodiments, see Figure 15a and Figure 15b The semiconductor device further includes a second dielectric layer 730 and a fourth dielectric layer 750. The second dielectric layer 730 is located on the side of the first dielectric layer 720 away from the isolation structure 300 and is situated between adjacent word lines 810 in the third direction Y. The second dielectric layer 730 extends along the first direction Y to isolate adjacent word lines 810 in the third direction Z. The fourth dielectric layer 750 is located on the side of the word lines 810 away from the first dielectric layer 720 and extends along the first direction Y. The fourth dielectric layer 750 is used to isolate word lines 810 from bit lines 830. Furthermore, the second dielectric layer 730 also extends along the second direction X between adjacent fourth dielectric layers 750 in the third direction Z.

[0167] In some embodiments, see Figure 17 The semiconductor device also includes a third dielectric layer 710 located between adjacent first electrodes 851 in the third direction Z. The third dielectric layer 710 is in contact with the first dielectric layer 720.

[0168] In some embodiments, see Figure 17The memory cell also includes a contact layer 840 located between the first electrode 851 and the semiconductor portion. The contact layer 840 is made of metal silicide and can reduce the contact resistance between the semiconductor portion and the first electrode 851, thereby reducing the power consumption of the semiconductor device.

[0169] In some embodiments, such as Figure 17 As shown, the semiconductor device also includes a capacitor 850. The capacitor includes a first electrode 851, a capacitor dielectric layer 852, and a second electrode 853. The first electrode 851 is a hollow structure with one open side, wherein the sidewall opposite the open side is in contact with a contact layer. The capacitor dielectric layer 852 is located on the surface of the hollow structure and extends along a third direction Z and a first direction Y on the side of the first electrode 851 away from the semiconductor portion. The second electrode 853 is located on the surface of the capacitor dielectric layer 852. Specifically, the second electrode 853 is located inside the hollow structure and is disposed opposite to the first electrode 851 through the capacitor dielectric layer 852. The second electrode 853 also extends along a third direction Z and a first direction Y on the side of the first electrode 851 away from the semiconductor portion.

[0170] For example, the semiconductor device provided in this disclosure is a memory, including but not limited to dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) synchronous dynamic random access memory, enhanced synchronous dynamic random access memory (ESDRAM), synclink dynamic random access memory (SLDRAM), direct rambus random access memory (DRRAM), ferroelectric memory, etc.

[0171] This disclosure also provides an electronic device, including the semiconductor device described above and / or a semiconductor device prepared using the manufacturing method of the semiconductor device described above.

[0172] Figure 18 A schematic diagram of an electronic device provided in an embodiment of this disclosure, such as... Figure 18As shown, the electronic device 40 includes a processing device 41 and a storage device 42 coupled to the processing device 41. The storage device 42 includes the semiconductor device described in any of the above embodiments, and / or includes a semiconductor device manufactured using the manufacturing method of the semiconductor device described in any of the above embodiments. When the electronic device 40 of the embodiments of this disclosure includes any of the above technical features, it has the technical effect corresponding to that technical feature, which will not be elaborated further here.

[0173] For example, electronic device 40 includes storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks, etc. Storage devices may include solid-state drives (SSDs) in computers, but this application does not limit the scope of the application to this type.

[0174] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0175] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is formed on the substrate; In the stacked structure, a plurality of initial isolation structures are formed along a first direction, and the initial isolation structures extend along a second direction; wherein, at least one of the initial isolation structures contains a cavity; the first direction and the second direction intersect and are both parallel to the substrate surface; A trench is formed on at least one of the opposite sides of the initial isolation structure along the second direction, the trench extends along the first direction, and the sidewalls of the trench expose a plurality of the initial isolation structures; Based on the trench, multiple initial isolation structures are laterally etched to expose the cavity; The groove is filled with insulating material in the space where the initial insulating structure is removed and the cavity; wherein the remaining initial insulating structure and the insulating material constitute the insulating structure.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The formation of a trench on at least one of the opposite sides of the initial isolation structure along the second direction includes: A mask layer is formed on the stacked structure; The mask layer is patterned to form openings in the mask layer; the openings extend along the first direction and overlap with the top surface portions of the plurality of initial isolation structures; The trench is formed by etching the stacked structure and the plurality of initial isolation structures based on the opening.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The step of forming a trench on at least one of the opposite sides of the initial isolation structure along the second direction includes: forming a first trench and a second trench on the opposite sides of the initial isolation structure along the second direction, wherein the first trench and the second trench both extend along the first direction and both expose a plurality of the initial isolation structures. The step of laterally etching multiple initial isolation structures based on the trench to expose the cavity includes: laterally etching multiple initial isolation structures based on the first trench to expose the cavity, and laterally etching multiple initial isolation structures based on the second trench to expose the cavity; The step of filling the space where the initial isolation structure is removed and the cavity with isolation material based on the trench includes: filling the space where the initial isolation structure is removed and the cavity with isolation material based on the first trench and the second trench.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The formation of a first trench and a second trench on opposite sides of the initial isolation structure along the second direction includes: The mask layer on the stacked structure is patterned to form a first opening and a second opening in the mask layer; the first opening and the second opening both extend along the first direction and overlap with the top surface portions of the plurality of initial isolation structures respectively; Based on the first opening and the second opening, the stacked structure and the plurality of initial isolation structures are etched to form the first trench and the second trench.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The initial isolation structure has a first dimension on its top surface exposed at the first opening along the second direction, the first dimension being smaller than the width of the first opening along the second direction; The initial isolation structure has a second dimension on its top surface exposed at the second opening along the second direction, the second dimension being smaller than the width of the second opening along the second direction.

6. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The substrate includes a capacitor region and a transistor region arranged along the second direction, the first trench is located in the stacked structure on the side of the transistor region away from the capacitor region, and the second trench is located in the stacked structure on the side of the capacitor region away from the transistor region; The method of forming a stacked structure on a substrate includes: forming a semiconductor layer and a sacrificial layer alternately stacked along a third direction on the substrate, wherein the third direction is perpendicular to the surface of the substrate; The manufacturing method further includes: A first side cavity is formed by removing the sacrificial layer and multiple isolation structures of the transistor region based on the first trench; Based on the first trench, a first dielectric layer and word lines located in the first dielectric layer and extending along the first direction are formed in the first side cavity; The semiconductor layer of the capacitor region is removed based on the second trench to form a second side cavity; the second side cavity exposes the isolation structure of the capacitor region. A first electrode is formed in the second side cavity, and the first electrode is coupled to the semiconductor layer of the transistor region.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The step of removing the sacrificial layer and multiple isolation structures of the transistor region based on the first trench to form a first side cavity includes: Based on the first trench, the sacrificial layer of the transistor region is removed, and the exposed semiconductor layer is thinned at the location where the sacrificial layer is removed to form a first chamber; A second chamber is formed by removing the isolation structure of the transistor region based on the first trench, and the second chamber is in communication with the first chamber; wherein the remaining isolation structure has a flat surface exposed on the sidewall of the second chamber.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The step of forming a first dielectric layer and a word line located in the first dielectric layer and extending along the first direction in the first side cavity based on the first trench includes: A first dielectric material is deposited on the surfaces of the second chamber and the first chamber; wherein the first dielectric material surrounding the semiconductor layer is connected to each other in the first direction; A second dielectric layer is formed in the remaining space of the second chamber and the first chamber; Remove a portion of the first medium material; Word lines extending along the first direction are formed in the space where the first dielectric material is removed; wherein, the remaining first dielectric material forms a first dielectric layer.

9. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The manufacturing method further includes: replacing the sacrificial layer of the capacitor region with a third dielectric layer based on the second trench; The step of forming a first electrode in the second side cavity includes: forming a first electrode on the surface of the isolation structure and the third dielectric layer exposed in the second side cavity based on the second trench; The manufacturing method further includes: forming a capacitor dielectric layer on the surface of the first electrode, and forming a second electrode on the surface of the capacitor dielectric layer.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the manufacturing method as described in claim 1, and the semiconductor device comprises: A plurality of memory cells are arranged on a substrate along a first direction and a second direction parallel to the substrate and stacked along a third direction perpendicular to the substrate. Each memory cell includes a semiconductor portion and a first electrode arranged side by side along the second direction. The semiconductor portion extends along the second direction, and the first electrode is coupled to the semiconductor portion. The first direction intersects the second direction. An isolation structure is located between the first electrodes that are adjacent in the first direction; A first dielectric layer is located between adjacent semiconductor portions in the first direction; wherein the contact interface between the isolation structure and the first dielectric layer is a flat surface.

11. The semiconductor device according to claim 10, characterized in that, A plurality of isolation structures are provided in the first direction and spaced apart by the first electrode, wherein the plurality of isolation structures are flush with each other near the sidewall of the first dielectric layer.

12. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: Word lines, the word lines being located on the side of the first dielectric layer away from the isolation structure, the word lines extending along the first direction and surrounding the plurality of semiconductor portions arranged in the first direction; A gate dielectric layer is located between the word line and the semiconductor portion; The second dielectric layer is located on the side of the first dielectric layer away from the isolation structure and between the word lines adjacent to it in the third direction; the second dielectric layer extends along the first direction. A fourth dielectric layer is located on the side of the word line away from the first dielectric layer and extends along the first direction; Bit lines are located on the side of the fourth dielectric layer away from the word lines, the bit lines extend along the first direction and the third direction, and are coupled to a plurality of the semiconductor portions.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes a capacitor, which includes the first electrode, a capacitor dielectric layer, and a second electrode. The first electrode is a hollow structure with an opening on one side, wherein the sidewall opposite to the opening is coupled to the semiconductor portion; The second electrode is located within the hollow structure and extends along the first direction and the third direction on the side of the first electrode away from the semiconductor portion; The capacitor dielectric layer is located between the first electrode and the second electrode.

14. An electronic device, characterized in that, include: Processing devices; as well as The storage device, coupled to the processing device, includes a semiconductor device manufactured using the manufacturing method of a semiconductor device as described in any one of claims 1 to 9, and / or includes a semiconductor device as described in any one of claims 10 to 13.

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