Memory device

Abstract

A memory device is provided in which a ground transistor of a string select line is connected to a dummy word line to reduce a chip size. In one aspect, a memory device includes: a memory block including cell strings respectively selected by string selection lines, where each cell string is connected to word lines stacked in a vertical direction; a pass transistor circuit including pass transistors connected to the plurality of string selection lines and the plurality of word lines, respectively, in which the pass transistors are configured to be turned on based on the memory blocks being selected; and a ground transistor circuit including ground transistors respectively connected to the word lines, in which the ground transistors are configured to be turned on based on the memory blocks being not selected. The number of ground transistors is less than the number of string selection lines.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0111619, filed with the Korean Intellectual Property Office on August 20, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure provides a memory device that can reduce the number of transistors in a ground transistor circuit by connecting a ground transistor to a dummy word line instead of connecting the ground transistor to a serial select line, thereby reducing the chip size. Background Technology

[0003] Recently, with the increasing multifunctionality of information and communication devices, there is a need for memory devices with larger capacities and higher integration. As the size of memory cells decreases to achieve higher integration, the operational circuitry and / or wiring structures included in memory devices for operation and electrical connections become increasingly complex. Therefore, memory devices with excellent electrical characteristics and higher integration are required. To improve the storage capacity and integration of memory devices, non-volatile memory devices with memory cells stacked in a three-dimensional structure, such as 3D NAND flash memory, have been investigated.

[0004] In 3D NAND flash memory, as the capacity of the memory blocks increases, the number of word lines stacked vertically on the substrate also increases. Simultaneously, the number of transfer transistors connected to the word lines increases, thus increasing the chip size. Summary of the Invention

[0005] According to one aspect of this disclosure, a storage device is provided. The storage device includes: a memory block comprising a plurality of cell strings, each cell string being configured to be selected by a plurality of string select lines, wherein each cell string is connected to a plurality of word lines stacked in a vertical direction; a transfer transistor circuit comprising a plurality of transfer transistors, each transfer transistor being connected to the plurality of string select lines and the plurality of word lines, wherein the plurality of transfer transistors are configured to be turned on based on the memory block being selected; and a ground transistor circuit comprising a plurality of ground transistors, each ground transistor being connected to the plurality of word lines, wherein the plurality of ground transistors are configured to be turned on based on the memory block not being selected, wherein the number of ground transistors is less than the number of the plurality of string select lines.

[0006] According to another aspect of this disclosure, a storage device is provided. The storage device includes: a memory block formed on a first semiconductor layer and comprising a plurality of cell strings selected by a plurality of string select lines, wherein each cell string comprises a plurality of memory cells, the plurality of memory cells being connected to a plurality of word lines stacked vertically; a plurality of dummy word lines formed on the first semiconductor layer and located between the plurality of string select lines and a ground select line; a transfer transistor circuit formed on a second semiconductor layer vertically below the first semiconductor layer, the transfer transistor circuit comprising a plurality of transfer transistors connected to the plurality of string select lines, the plurality of word lines, the plurality of dummy word lines, and the ground select line, wherein the plurality of transfer transistors are configured to be turned on based on the memory block being selected; and a ground transistor circuit formed on the second semiconductor layer, the ground transistor circuit comprising at least one ground transistor connected to at least one of the plurality of dummy word lines, wherein the at least one ground transistor is configured to be turned on based on the memory block not being selected.

[0007] According to another aspect of this disclosure, a storage device is provided. The storage device includes: a memory block including a plurality of control lines, the plurality of control lines including a plurality of string select lines, a plurality of word lines, a ground select line, and a plurality of dummy word lines, the plurality of dummy word lines being arranged between the plurality of string select lines and the plurality of word lines or between the ground select line and the plurality of word lines; and the plurality of control lines including a first set of control lines, the first set of control lines including at least one word line among the plurality of word lines and at least one dummy word line among the plurality of dummy word lines; a transmission transistor circuit including transmission transistors respectively connected to the plurality of control lines; and a ground transistor circuit including at least one ground transistor respectively connected to the first set of control lines. Attached Figure Description

[0008] Embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram showing an example storage device;

[0010] Figure 2 This is a block diagram showing an example block gating circuit and a memory cell array;

[0011] Figure 3 This is a diagram that schematically illustrates an example structure of a storage device;

[0012] Figure 4 This is a block diagram showing an example memory cell array;

[0013] Figure 5 This is an example equivalent circuit diagram of a memory block;

[0014] Figure 6 It is a diagram showing the address decoder, the first grounding transistor circuit, the first transmission transistor circuit, and the first memory block;

[0015] Figure 7 It is a diagram showing the address decoder, the first grounding transistor circuit, the first transmission transistor circuit, and the first memory block;

[0016] Figure 8 It is a diagram showing the address decoder, the first grounding transistor circuit, the first transmission transistor circuit, and the first memory block;

[0017] Figure 9 This is a circuit diagram illustrating the first grounding transistor circuit, the first transmission transistor circuit, and the first memory block;

[0018] Figure 10 This is a circuit diagram illustrating the first grounding transistor circuit, the first transmission transistor circuit, and the first memory block;

[0019] Figure 11 This is a table showing example voltage conditions during read operations of a storage device;

[0020] Figure 12 This is a circuit diagram illustrating an example operation of the first transfer transistor circuit, the first ground transistor circuit, and the first memory block during a read operation of the memory device;

[0021] Figure 13 This is a table showing example voltage conditions during the programming operation of the storage device;

[0022] Figure 14 This is a circuit diagram illustrating an example operation of the first transmission transistor circuit, the first ground transistor circuit, and the first memory block during programming operations of the memory device;

[0023] Figure 15 This is a table showing example voltage conditions during an erase operation of a storage device;

[0024] Figure 16 This is a circuit diagram illustrating an example operation of the first transmission transistor circuit, the first ground transistor circuit, and the first memory block during an erase operation of the memory device;

[0025] Figure 17 This is a block diagram illustrating an example of a storage device applied to a solid-state drive (SSD) system; and

[0026] Figure 18 This is a block diagram used to describe a system of an example electronic device that includes storage devices. Detailed Implementation

[0027] Figure 1 This is a block diagram illustrating a storage device 10 according to one or more embodiments.

[0028] Reference Figure 1 The storage device 10 may include a memory cell array 100 and peripheral circuitry 200. Peripheral circuitry 200 may include a block gating circuit 210, an address decoder 220, control logic 230, and a page buffer 240. Although not shown, peripheral circuitry 200 may also include a voltage generator, data input / output circuitry, an input / output interface, a temperature sensor, or a command decoder. According to embodiments, storage device 10 may be a non-volatile storage device, and hereinafter, "storage device" may refer to a non-volatile storage device.

[0029] The memory cell array 100 may include multiple memory blocks. Each memory block may include multiple memory cells arranged on a substrate along both row-wise and column-wise directions. For example, the memory cells may be flash memory cells. Hereinafter, implementations will be described in detail based on the example scenario where the memory cells are NAND flash memory cells. However, this disclosure is not limited thereto, and in some implementations, the memory cells may be resistive memory cells, such as resistive RAM (ReRAM) cells, phase-change RAM (PRAM) cells, and magnetic RAM (MRAM) cells. Each cell string may include multiple memory cells stacked in a direction perpendicular to the substrate. In other words, the memory cells are arranged along rows and columns on the substrate and may be stacked in a direction perpendicular to the substrate to form a three-dimensional structure. For example, the memory cell array 100 may include multiple memory cells, each capable of storing one or more bits. However, this disclosure is not limited thereto. In some implementations, the memory cell array 100 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include multiple cell strings arranged along both row and column directions.

[0030] Block gating circuit 210 can be connected to memory cell array 100 via serial select line SSL, word line WL, and ground select line GSL. Block gating circuit 210 can be connected to address decoder 220 via serial line SS, select line S, and ground line GS. Serial line SS, select line S, and ground line GS can be referred to as "drive signal lines". Block gating circuit 210 can receive block select signal BSS from address decoder 220. For example, block select signal BSS may include a first block select signal (…). Figure 6 BLKSEL) and the second block selection signal ( Figure 6 BLKWL).

[0031] The block gating circuit 210 can select a memory block of the memory cell array 100 in response to the block select signal BSS. The block gating circuit 210 can electrically connect the serial select line SSL, word line WL and ground select line GSL of the selected memory block to the serial line SS, select line S and ground line GS.

[0032] With advancements in semiconductor technology, the number of memory cells arranged in the memory cell array 100 increases (in other words, the number of word lines WL stacked vertically increases), leading to an increase in the number of transistors used to drive the word lines WL, and consequently, an increase in the area occupied by the block gating circuit 210. According to embodiments, the peripheral circuitry 200 can be disposed above or below the memory cell array 100 in the vertical direction, and specifically, the block gating circuit 210 can be disposed above or below the stepped region of the word lines WL in the vertical direction. Therefore, since the area where the block gating circuit 210 is located overlaps with the stepped region of the word lines WL in the vertical direction, an increase in the chip size of the memory device 10 can be prevented despite the increase in the number of transistors due to the increase in the number of stacked word lines WL. (Referring later...) Figure 3 A more detailed description is provided.

[0033] Address decoder 220 can be connected to block gating circuit 210 via serial line SS, select line S, and ground line GS. Address decoder 220 is configured to operate in response to control of control logic 230. Address decoder 220 can receive row address X-ADDR from control logic 230.

[0034] Address decoder 220 can output a block select signal BSS for selecting one of a plurality of memory blocks in response to the received row address X-ADDR. Furthermore, in response to row address X-ADDR, address decoder 220 can output a word line drive signal to select line S for selecting one of the word lines WL for the selected memory block, output a serial select line drive signal to serial select line SSL for selecting one of the serial lines SS, and output a ground select line drive signal to ground line GS for selecting one of the ground select lines GSL.

[0035] Page buffer 240 can be connected to memory cell array 100 via bit line BL. Page buffer 240 can be configured to exchange data with external systems. Page buffer 240 operates in response to control logic 230. Page buffer 240 can select some bit lines from bit line BL in response to column address Y_ADDR.

[0036] Control logic 230 can be connected to address decoder 220 and page buffer 240. Control logic 230 can generate various control signals based on command CMD, address ADDR, and control signal CTRL for programming data into memory cell array 100, reading data from memory cell array 100, or erasing data stored in memory cell array 100. For example, control logic 230 can output row address X-ADDR and column address Y-ADDR. Therefore, control logic 230 can comprehensively control various operations within memory device 10.

[0037] Figure 2 This is a block diagram illustrating a block gating circuit 210 and a memory cell array 100 according to one or more embodiments.

[0038] Reference Figure 2 The storage cell array 100 may include multiple storage blocks BLK1 to BLKz. Each storage block can be connected to the block gating circuit 210 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0039] The block selection circuit 210 may include multiple selection circuits 211 to 21z. The multiple selection circuits 211 to 21z may each correspond to multiple memory blocks BLK1 to BLKz. The multiple selection circuits 211 to 21z may each include multiple ground transistor circuits 211_1 to 21z_1 and multiple transmission transistor circuits 211_2 to 21z_2. Each selection circuit may include one ground transistor circuit and one transmission transistor circuit.

[0040] In grounding transistor circuits 211_1 to 21z_1, the grounding transistor circuits corresponding to the unselected memory blocks can respectively provide a low voltage to the ground selection line GSL of the unselected memory blocks. For example, grounding transistor circuits 211_1 to 21z_1 can provide the ground voltage GND.

[0041] The transmission transistor circuits 211_2 to 21z_2 corresponding to the selected memory blocks can respond to the block selection signal BSS by setting the serial selection lines SSL of the selected memory blocks BLK1 to BLKz respectively. <1> To SSL <3> The first word line WL1 to the m-th word line WLm and the ground select line GSL are electrically connected to the serial select line SSL. <1> To SSL <3> Select lines S1 to Sm and ground line GS.

[0042] The configuration of the first grounding transistor circuit 211_1 and the first transmission transistor circuit 211_2 of the first selection circuit 211 will be referred to later. Figure 6 and Figure 8 Detailed description.

[0043] Figure 3 This is a schematic diagram illustrating the structure of a storage device 10 according to one or more embodiments.

[0044] Simultaneously refer to Figure 1 and Figure 3 The memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 in the vertical direction VD. Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the third direction D3, and therefore, the second semiconductor layer L2 may be disposed close to the substrate. According to an embodiment, a memory cell array 100 may be formed in the first semiconductor layer L1, and peripheral circuitry 200 may be formed in the second semiconductor layer L2. Therefore, the memory device 10 may have a structure in which the memory cell array 100 is disposed above some peripheral circuitry, i.e., a cell-on-periphery (COP) structure.

[0045] The first semiconductor layer L1 may include a cell region CA and a stepped region SA, and multiple memory cells may be arranged in the cell region CA. In the first semiconductor layer L1, multiple bit lines BL may extend in a second horizontal direction D2, and multiple word lines WL may extend in a first horizontal direction D1. One end of the multiple word lines WL may be implemented in a stepped shape, and in this specification, the region in the first semiconductor layer L1 that includes the multiple word lines WL with a stepped shape is referred to as the "stepped region" (SA) or "word line extension region".

[0046] The second semiconductor layer L2 may include a substrate, and peripheral circuitry 200 may be formed in the second semiconductor layer L2 by forming semiconductor devices such as transistors and patterns for distributing devices on the substrate. After forming the peripheral circuitry 200 on the second semiconductor layer L2, a first semiconductor layer L1 including a memory cell array 100 may be formed, and patterns for electrically connecting word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuitry 200 formed in the second semiconductor layer L2 may be formed. The second semiconductor layer L2 may include a first region R1 corresponding to a step region SA and a second region R2 corresponding to a cell region CA. According to an embodiment, a block selection circuit 210 may be provided in the first region R1, but this disclosure is not limited thereto.

[0047] As described above, according to this embodiment, the storage device 10 may have a COP structure, and the block gating circuit 210 may be disposed at the bottom of the stepped region SA. According to this embodiment, multiple select line drive signal lines connected to the multiple transistor blocks included in the block gating circuit 210 may extend in the first horizontal direction D1.

[0048] The storage device 10 according to this disclosure can be applied to situations where blocks are shared in a structure in which transistors are arranged in multiple stages.

[0049] Figure 4 This is a block diagram illustrating a storage cell array 100 according to one or more embodiments.

[0050] Reference Figure 4 The storage cell array 100 may include multiple storage blocks BLK1 to BLKz, where z can be a positive integer. Storage blocks BLK1 to BLKz may each have a 3D structure (or a vertical structure). Specifically, each storage block BLK1 to BLKz may include multiple NAND strings extending in the vertical direction VD. Here, the NAND strings may be spaced apart by a specific distance in the first horizontal direction D1 and the second horizontal direction D2. Storage blocks BLK1 to BLKz can be decoded by an address decoder (…). Figure 1 (220) Selection. For example, address decoder 220 can select the memory block corresponding to the block address from memory blocks BLK1 to BLKz.

[0051] Figure 5 It is an equivalent circuit diagram of a storage block according to one or more embodiments.

[0052] Figure 5 The storage block shown is the one referenced above. Figure 4 An example of one of the plurality of memory blocks BLK1 to BLKz is described, and the first memory block BLK1 is shown. In the following, the implementation will be described in detail using the first memory block BLK1 as an example. For ease of explanation, the first memory block BLK1 can be interchangeably referred to as memory block BLK1. Memory block BLK1 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. The plurality of memory cell strings included in memory block BLK1 can be formed in a direction perpendicular to the substrate.

[0053] Reference Figure 5 The storage block BLK1 may include cell strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground select line GSL, and string select line SSL. <1> To SSL <3> and the common source line CSL. Despite Figure 5 Each of the cell strings NS11 to NS33 is shown to include eight memory cells MC connected to eight word lines WL1 to WL8 respectively, but this is merely an example to aid understanding and the implementation is not limited thereto.

[0054] Each cell string (e.g., NS11) may include a series-connected string select transistor SST, multiple memory cells MC, and ground select transistor GST. The string select transistor SST is connected to a corresponding string select line SSL. <1> The memory cells MC are connected to the corresponding word lines WL1 to WL8. The ground select transistor GST is connected to the ground select line GSL. The string select transistor SST is connected to the corresponding bit lines BL1 to BL3, and the ground select transistor GST is connected to the common source line CSL.

[0055] In memory block BLK1, word lines WL1 to WL8 are commonly connected to the memory cell transistors included in the same layer. The memory cell transistors included in the same layer are supplied with the same word line voltage. Multiple string select transistors SST, formed in the same layer, are connected to multiple string select lines SSL. <1> To SSL <3> The ground select transistor GST is also controlled. In other words, the ground select transistor GST included in memory block BLK1 is controlled by the ground select line GSL.

[0056] According to some implementations, each cell string may have one or more dummy memory cells between the string select transistor SST and the memory cell MC. Each cell string may also have one or more dummy memory cells between the ground select transistor GST and the memory cell MC. Each cell string may also have one or more dummy memory cells between the memory cells MC. The dummy memory cells have the same structure as the memory cells MC and may not be programmed (e.g., unprogrammable) or may be programmed differently from the memory cells MC. For example, when the memory cells MC are programmed to have two or more threshold voltage distributions, the dummy memory cells may be programmed to have one threshold voltage distribution range or fewer threshold voltage distributions than the memory cells MC.

[0057] Figure 6 The diagram illustrates an address decoder 220, a first ground transistor circuit 211_1, a first transmission transistor circuit 211_2, and a first memory block BLK1 according to one or more embodiments.

[0058] Reference Figure 6 The storage device 10 may include a first ground transistor circuit 211_1 and a first transmission transistor circuit 211_2 connected between the address decoder 220 and the first memory block BLK1. The memory block BLK1 may include a ground select line GSL, multiple word lines (i.e., the first word line WL1 to the m-th word line WLm), and multiple dummy word lines DWL. <1> To DWL <4> and multiple serial select lines SSL <1> To SSL <3> , where m is a positive integer.

[0059] exist Figure 6In the storage device 10, the storage block BLK1 may further include a first dummy word line DWL. <1> Up to the fourth dummy word line DWL <4> First DWL (Dummy Word Line) <1> Second Dummy Word Line (DWL) <2> It can be positioned between the ground selection line GSL and the first word line WL1, and the third dummy word line DWL <3> and the fourth dummy word line DWL <4> It can be arranged on the m-th word line WLm and the first string selection line SSL. <1> Between. According to some implementations, storage block BLK1 may include a first dummy word line DWL. <1> Up to the fourth dummy word line DWL <4> At least one of them. According to the implementation, the number of dummy word lines included in memory block BLK1 can vary. Multiple dummy word lines DWL <1> To DWL <4> It can be deployed on multiple serial select lines SSL <1> To SSL <3> Between multiple word lines WL1 to WLm, or between the ground select line GSL and multiple word lines WL1 to WLm. In other words, multiple dummy word lines can be arranged between: (1) multiple string select lines and multiple word lines, or (2) the ground select line and multiple word lines, or (3) some of the dummy word lines are between multiple string select lines and multiple word lines, while some of the dummy word lines are between the ground select line and multiple word lines.

[0060] Address decoder 220 may include block decoder 221 and drive signal line decoder 222. First ground transistor circuit 211_1 may include multiple ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm, and first transmission transistor circuit 211_2 may include multiple transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3, where m is a positive integer. First transmission transistor circuit 211_2 can be used for memory blocks ( Figure 4 It can be set for each storage block in BLK1 to BLKz, and can be set for storage blocks ( Figure 4 One or more memory blocks (BLK1 to BLKz) jointly set up block decoder 221 and drive signal line decoder 222.

[0061] The block decoder 221 can be connected to the first ground transistor circuit 211_1 via a first block select signal line, and to the first transmission transistor circuit 211_2 via a second block select signal line. The first block select signal line can be connected to the gates of multiple ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm. Furthermore, the second block select signal line can be connected to the gates of multiple transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3. For example, when the first memory block BLK1 is not selected and the first block select signal BLKSEL connected to the first block select signal line is activated, the multiple ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm can be turned on and driven, and the transmission transistor circuit 211_2 can be turned off in response to the second block select signal BLKWL provided via the second block select signal line. For example, when the first memory block BLK1 is selected and the second block selection signal BLKWL provided through the second block selection signal line is activated, multiple transmission transistors TRg, TRd1 to TRd4, TR1 to TRm and TRs1 to TRs3 can be turned on and driven, and the first grounding transistor circuit 211_1 can be turned off.

[0062] According to the implementation, the phases of the first selection signal BLKSEL and the second selection signal BLKWL can be opposite to each other. For example, when the logic level of the first selection signal BLKSEL is high, the logic level of the second selection signal BLKWL can be low, and when the logic level of the first selection signal BLKSEL is low, the logic level of the second selection signal BLKWL can be high.

[0063] The drive signal line decoder 222 can be controlled via selection lines S1 to Sm and dummy selection line DS. <1> To DS <4> The ground selection line drive signal line GS is connected to the first ground transistor circuit 211_1, and the series selection line drive signal line SS can be used. <1> To SS <3> Select lines S1 to Sm, and dummy selection lines DS <1> To DS <4> The ground selection line drive signal line GS is connected to the first transmission transistor circuit 211_2. Specifically, the selection lines S1 to Sm and the dummy selection line DS... <1> To DS <4> The series select line drive signal line GS can be connected to one end (e.g., source or drain) of multiple ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm, respectively, and the other end (e.g., drain or source) of the multiple ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm can be respectively applied with ground voltage GND. Furthermore, one end of the multiple ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm can be connected to some of the transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3, namely TRd1 to TRd4, TR1 to TRm, and TRg. Series select line drive signal line SS <1> To SS <3> Select lines S1 to Sm, and dummy selection lines DS <1> To DS <4> The ground selection line drive signal line GS can be connected to one end (e.g., source or drain) of multiple transmission transistors TRg, TRd1 to TRd4, TR1 to TRm and TRs1 to TRs3 respectively.

[0064] The first grounding transistor circuit 211_1 can be connected via the ground selection line GSL, multiple word lines (i.e., the first word line WL1 to the m-th word line WLm), and multiple dummy word lines DWL. <1> To DWL <4> Connect to the first memory block BLK1. One end of the ground transistor GTRg can be connected to the ground select line drive signal line GS. The gate of the ground transistor GTRg can provide the first block select signal BLKSEL, and the other end of the ground transistor GTRg can provide the ground voltage GND. One end of the ground transistors GTR1 to GTRm can be connected to the select lines S1 to Sm respectively. The gates of the ground transistors GTR1 to GTRm can provide the first block select signal BLKSEL, and the other end of the ground transistors GTR1 to GTRm can provide the ground voltage GND. One end of the ground transistors GTRd1 to GTRd4 can be connected to the dummy select line drive signal line DS. <1> To DS <4> The gates of ground transistors GTRd1 to GTRd4 can provide the first block selection signal BLKSEL, and the other ends of ground transistors GTRd1 to GTRd4 can provide the ground voltage GND. For example, when the first block selection signal BLKSEL is activated, ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm can respectively drive the signal lines DS through selection lines S1 to Sm and dummy selection lines. <1> To DS <4> The drive signal provided by the ground selection line drive signal line GS is supplied to the first word line WL1 to the m-th word line WLm and the dummy word line DWL. <1> To DWL <4> And select the GSL line.

[0065] The first transmission transistor circuit 211_2 can be connected via the ground selection line GSL, multiple word lines (i.e., the first word line WL1 to the m-th word line WLm), and multiple dummy word lines DWL. <1> To DWL <4> and serial select line SSL <1> To SSL <3> Connected to the first memory block BLK1. Transmission transistor TRg can be connected between the ground select drive signal line GS and the ground select line GSL. Multiple transmission transistors TR1 to TRm can be connected between select lines S1 to Sm and multiple word lines (i.e., the first word line WL1 to the m-th word line WLm), respectively. Transmission transistors TRd1 to TRd4 can be connected to the dummy select drive signal line DS, respectively. <1> To DS <4> With multiple dummy word lines DWL <1> To DWL <4> Between. Transmission transistors TRs1 to TRs3 can be connected to the series select line drive signal line SS respectively. <1> To SS <3> With Serial Select Line SSL <1> To SSL <3> Between. The gates of the transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 can each be provided with a second block select signal BLKWL. For example, when the second select signal BLKWL is activated, the transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 can drive the signal line SS through the series select line. <1> To SS <3> Select lines S1 to Sm, and dummy select line drive signal line DS <1> To DS <4> The drive signals provided by the ground select line drive signal line GS are respectively supplied to the serial select line SSL. <1> To SSL <3> First character line WL1 to m-th character line WLm, and virtual character line DWL <1> To DWL <4> And select the GSL line.

[0066] According to the implementation, the number of grounding transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm included in the first grounding transistor circuit 211_1 can be less than the number of transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 included in the first transmission transistor circuit 211_2. In other words, the first grounding transistor circuit 211_1 may not include those connected to multiple string select lines SSL. <1> To SSL <3> The grounding transistor.

[0067] Therefore, the first grounding transistor circuit 211_1 may not include multiple series select lines SSL. <1> To SSL <3> The grounding transistor in the circuit. Conversely, the first grounding transistor circuit 211_1 can control the grounding transistors connected to the first dummy word line DWL respectively. <1> Up to the fourth dummy word line DWL <4> The first ground transistor circuit 211_1 includes ground transistors GTRd1 to GTRd4 and ground transistors GTR1 to GTRm for the first word line WL1 to the m-th word line WLm. Therefore, the first ground transistor circuit 211_1 can reduce the number of ground transistors and reduce the chip size of the memory device 10.

[0068] According to the implementation, the number of grounding transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm included in the first grounding transistor circuit 211_1 can be equal to the number of multiple word lines (i.e., the first word line WL1 to the m-th word line WLm) and multiple dummy word lines DWL. <1> To DWL <4> The number of grounding transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm connected to the ground select line GSL. The number of transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 included in the first transmission transistor circuit 211_2 can be equal to the number of multiple serial select lines SSL connected to it. <1> To SSL <3> Multiple character lines (i.e., the first character line WL1 to the m-th character line WLm), and multiple virtual character lines DWL <1> To DWL <4> The number of transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 connected to the ground select line GSL. In other words, the first ground transistor circuit 211_1 may not include connections to multiple string select lines SSL. <1> To SSL <3> The grounding transistor. Transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 are connected to the ground select line GSL and the dummy word line DWL. <1> To DWL <4> The first word line WL1 to the m-th word line WLm and the string select line SSL <1> To SSL <3> .

[0069] According to the implementation method, when from multiple storage blocks ( Figure 4 When selecting the first memory block BLK1 from BLK1 to BLK2, the activated second block selection signal BLKWL can be provided to the first transmission transistor circuit 211_2 corresponding to the first memory block BLK1. Conversely, when the first memory block BLK1 is not selected among multiple memory blocks, the activated first block selection signal BLKSEL can be provided to the first grounding transistor circuit 211_1 corresponding to the first memory block BLK1.

[0070] In other words, the selected storage block's string selection line SSL <1> To SSL <3> First character line WL1 to m-th character line WLm, and virtual character line DWL <1> To DWL <4> The ground selection line GSL can be connected to the address decoder 220. The fourth dummy word line DWL can be used to select unselected memory blocks. <4> Provides ground voltage and enables the first word line WL1 to the m-th word line WLm and the ground selection line GSL, as well as the dummy word line DWL, of the unselected memory block. <1> To DWL <4> Floating.

[0071] although Figure 6 The first grounding transistor circuit 211_1 is shown, but the configuration of the first grounding transistor circuit 211_1 can be applied in the same way. Figure 2 The second grounding transistor circuit 212_1 to the z-th grounding transistor circuit 21z_1 are shown. Furthermore, although... Figure 6 The first transmission transistor circuit 211_2 is shown, but the configuration of the first transmission transistor circuit 211_2 can be applied in the same way. Figure 2 The second transmission transistor circuit 212_2 to the z-th transmission transistor circuit 21z_2 are shown.

[0072] It should be noted that in this disclosure, the ground selection line GSL, multiple word lines (e.g., the first word line WL1 to the m-th word line WLm), and multiple dummy word lines DWL are used. <1> To DWL <4> and serial select line SSL <1> To SSL <3> These can be referred to as control lines. Control lines can include a first set of control lines and a second set of control lines. The first set of control lines can include control lines connected to a grounded transistor, while the second set of control lines can include the remaining control lines not connected to a grounded transistor. For example, in... Figure 6 In the example implementation shown, the first set of control lines may include multiple dummy word lines (DWL). <1> To DWL <4> The second set of control lines may include the serial select line SSL. <1> To SSL <3> Multiple word lines (e.g., first word line WL1 to m-th word line WLm) and ground selection line GSL. In another example, as follows: Figure 7 As shown, the first group of control lines may include multiple word lines (e.g., the first word line WL1 to the m-th word line WLm) and multiple dummy word lines DWL. <1> To DWL <4> The first set of control lines is the ground select line GSL, while the second set of control lines may include the serial select line SSL. <1> To SSL <3> In yet another example, as shown below Figure 8 As shown, the first set of control lines may include a single dummy word line DWL connected to the ground transistor GTRd4. <4> The second set of control lines includes the remaining control lines, such as multiple word lines (e.g., first word line WL1 to m-th word line WLm), and dummy word line DWL. <1> To DWL <3> Serial select line SSL <1> To SSL <3> And the ground selection line GSL.

[0073] In some implementations, although Figure 6 Not shown, but at least one of the ground transistors GTR is connected to at least one of the serial select lines SSL, and the number of ground transistors GTR is less than the number of serial select lines SSL. For example, ground transistors GTR may be connected to some of the serial select lines SSL, but not to all of them.

[0074] Figure 7 This is a diagram illustrating an address decoder, a first grounding transistor circuit, a first transmission transistor circuit, and a first memory block according to one or more embodiments. (Refer to the above...) Figure 6Descriptions that are identical to those given will be omitted.

[0075] Reference Figure 7 The first grounding transistor circuit 211_1 may include multiple grounding transistors GTRd1 to GTRd4. Figure 6 Unlike the first grounding transistor circuit 211_1 shown, one end of the plurality of grounding transistors GTRd1 to GTRd4 is only connected to the dummy select line drive signal line DS. <1> To DS <4> .

[0076] The first grounding transistor circuit 211_1 can be connected via multiple dummy word lines DWL <1> To DWL <4> Connect to the first storage block BLK1.

[0077] One end of the ground transistors GTRd1 to GTRd4 can be connected to the dummy select line drive signal line DS. <1> To DS <4> The gates of ground transistors GTRd1 to GTRd4 can provide the first block select signal BLKSEL, and the other end of ground transistors GTRd1 to GTRd4 can provide the ground voltage GND.

[0078] According to the implementation, the first grounding transistor circuit 211_1 may not include connections to multiple string select lines SSL. <1> To SSL <3> A grounding transistor for multiple word lines (e.g., first word line WL1 to m-th word line WLm) and ground select line GSL. Conversely, the first grounding transistor circuit 211_1 can control the connection to the first dummy word line DWL. <1> Up to the fourth dummy word line DWL <4> The grounding transistors GTRd1 to GTRd4 are used. Therefore, the first grounding transistor circuit 211_1 can reduce the number of grounding transistors and reduce the chip size of the memory device 10.

[0079] Figure 8 This is a diagram illustrating an address decoder 220, a first ground transistor circuit 211_1, a first transmission transistor circuit 211_2, and a first memory block BLK1 according to one or more embodiments. (Refer to the above...) Figure 6 Descriptions that are identical to those given will be omitted.

[0080] Reference Figure 8 The first grounding transistor circuit 211_1 may include a grounding transistor GTRd4. (And...) Figure 6 Unlike the first grounding transistor circuit 211_1 shown, one end of the grounding transistor GTRd4 is only connected to the dummy select line drive signal line DS. <4> .

[0081] The first grounding transistor circuit 211_1 can be connected via the fourth dummy word line DWL <4> Connect to the first storage block BLK1.

[0082] One end of the ground transistor GTRd4 can be connected to the dummy select line drive signal line DS. <4> The gate of the ground transistor GTRd4 can provide the first block select signal BLKSEL, and the other end of the ground transistor GTRd4 can provide the ground voltage GND.

[0083] According to the implementation, the first grounding transistor circuit 211_1 may not include connections to multiple string select lines SSL. <1> To SSL <3> First DWL (Dual Word Line) <1> Up to the third dummy word line DWL <3> A grounding transistor for multiple word lines (i.e., the first word line WL1 to the m-th word line WLm) and the ground select line GSL. Conversely, the first grounding transistor circuit 211_1 can control the connection to the fourth dummy word line DWL. <4> The grounding transistor GTRd4. Therefore, the first grounding transistor circuit 211_1 can reduce the number of grounding transistors and reduce the chip size of the memory device 10.

[0084] Figure 9 This is a circuit diagram illustrating a first grounding transistor circuit 211_1, a first transmission transistor circuit 211_2, and a first storage block BLK1 according to one or more embodiments.

[0085] Reference Figure 9 The first grounding transistor circuit 211_1 can correspond to Figure 6 The implementation method, and the first transmission transistor circuit 211_2 can correspond to Figure 6 The implementation method. According to the implementation method, the first storage block BLK1 can correspond to Figure 5 and Figure 6 The first storage block BLK1 shown is an implementation of the above.

[0086] The first storage block BLK1 may include multiple cell strings NS11 to NS33 and multiple string select lines SSL. <1> To SSL <3> Multiple character lines (i.e., the first character line WL1 to the m-th character line WLm), and multiple virtual character lines DWL <1> To DWL <4> Multiple bit lines BL1 to BL3, ground select line GSL, and common source line CSL. Here, the number of NAND strings, the number of string select lines, the number of word lines, the number of dummy word lines, the number of bit lines, and the number of ground select lines can vary depending on the implementation method.

[0087] NAND strings NS11, NS21, and NS31 are positioned between the first bit line BL1 and the common source line CSL, and NAND strings NS12, NS22, and NS32 are positioned between the second bit line BL2 and the common source line CSL. Each NAND string (e.g., NS33) may include a series-connected string select transistor SST, multiple memory cells MC, and a ground select transistor GST.

[0088] The serial select transistor SST is coupled to the corresponding serial select line SSL. <1> To SSL <3> Multiple memory cells (MCs) are connected to their respective word lines (i.e., the first word line WL1 to the m-th word line WLm) and their corresponding dummy word lines (DWL). <1> To DWL <4> The ground select transistor GST is connected to its corresponding ground select line GSL. The string select transistors SST are connected to the corresponding bit lines BL1 to BL3 respectively, and the ground select transistor GST is connected to the common source line CSL.

[0089] According to the implementation, word lines of the same height (i.e., arranged at the same level) (e.g., WL1) are connected to each other, while selection lines S1 to Sm are separated from each other. Although Figure 8 Three string select lines SSL are shown. <1> To SSL <3> Word lines can share the same height, but this disclosure is not limited to this. For example, two string select lines can share word lines of the same height. In another example, four string select lines can share word lines of the same height.

[0090] The first grounding transistor circuit 211_1 may include a grounding transistor GTRg connected to the ground selection line GSL, grounding transistors GTR1 to GTRm connected to the first word line WL1 to the m-th word line WLm respectively, and grounding transistors connected to the dummy word line DWL respectively. <1> To DWL <4> Grounding transistors GTRd1 to GTRd4 are used. For example, one end of grounding transistor GTRg can be connected to the ground select line drive signal line GS or the ground select line GSL. The gate of grounding transistor GTRg can provide the first select signal BLKSEL, and the other end of grounding transistor GTRg can provide the ground voltage GND. One end of grounding transistors GTR1 to GTRm can be connected to select lines S1 to Sm or the first word line WL1 to the m-th word line WLm. The gate of grounding transistors GTR1 to GTRm can provide the first select signal BLKSEL, and the other end of grounding transistors GTR1 to GTRm can provide the ground voltage GND. One end of grounding transistors GTRd1 to GTRd4 can be connected to the dummy select line drive signal line DS. <1> To DS <4> Or a virtual word line DWL <1> To DWL <4> The gates of ground transistors GTRd1 to GTRd4 can provide the first block select signal BLKSEL, and the other ends of ground transistors GTRd1 to GTRd4 can provide ground voltage GND. Ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm can be turned on according to the first block select signal BLKSEL provided along the first block select signal line, and will drive the signal line DS through select lines S1 to Sm and the dummy select line. <1> To DS <4> The drive signals provided by the ground selection line drive signal line GS are respectively supplied to the first word line WL1 to the m-th word line WLm and the dummy word line DWL. <1> To DWL <4> And the ground selection line GSL.

[0091] The first transmission transistor circuit 211_2 may include a transmission transistor TRg connected to the ground selection line GSL, transmission transistors TR1 to TRm respectively connected to the first word line WL1 to the m-th word line WLm, and a dummy word line DWL respectively. <1> To DWL <4> Transmission transistors TRd1 to TRd4, and SSL connected to the serial select line respectively. <1> To SSL <3> The transmission transistors TRs1 to TRs3. Transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs3 can be turned on according to the second block select signal BLKWL provided along the second block select signal line, and will drive the series select signal line SS through the series select line. <1> To SS <3> Select lines S1 to Sm, and dummy select line drive signal line DS <1> To DS <4> The drive signals provided by the ground selection line drive signal line GS are respectively provided to the serial selection line SSL. <1> To SSL <3> First character line WL1 to m-th character line WLm, and virtual character line DWL <1> To DWL <4> And the ground selection line GSL.

[0092] According to the implementation, the number of grounding transistors GTRg, GTRd1 to GTRd4 and GTR1 to GTRm included in the first grounding transistor circuit 211_1 may be less than the number of transmission transistors TRg, TRd1 to TRd4, TR1 to TRm and TRs1 to TRs3 included in the first transmission transistor circuit 211_2.

[0093] According to the implementation method, the first grounding transistor circuit 211_1 may not include multiple series select lines SSL. <1> To SSL <3> The grounding transistor in the middle. Conversely, the connection to the first dummy word line DWL can be controlled. <1> Up to the fourth dummy word line DWL <4> The first ground transistor circuit 211_1 includes ground transistors GTRd1 to GTRd4 and ground transistors GTR1 to GTRm for the first word line WL1 to the m-th word line WLm. Therefore, the first ground transistor circuit 211_1 can reduce the number of ground transistors and reduce the chip size of the memory device 10.

[0094] Figure 10 This is a circuit diagram illustrating a first grounding transistor circuit 211_1, a first transmission transistor circuit 211_2, and a first memory block BLK1 according to one or more embodiments. Referring to the above... Figure 9 Descriptions that are identical to those given will be omitted.

[0095] Reference Figure 10 The first grounding transistor circuit 211_1 can correspond to Figure 8 One implementation, and the first transmission transistor circuit 211_2 can correspond to Figure 8 One implementation method. According to this implementation method, the first storage block BLK1 can correspond to... Figure 5 and Figure 8 The first storage block BLK1 shown is an implementation of the above.

[0096] The first grounding transistor circuit 211_1 may include a connection to the fourth dummy word line DWL. <4> The grounding transistor GTRd4. For example, one end of the grounding transistor GTRd4 can be connected to the fourth dummy select line drive signal line DS. <4> Or the fourth dummy word line DWL <4> The gate of the ground transistor GTRd4 can provide the first block select signal BLKSEL, and the other end of the ground transistor GTRd4 can provide the ground voltage GND. The ground transistor GTRd4 can be turned on according to the first block select signal BLKSEL provided along the first block select signal line, and can drive the signal line DS through the fourth dummy select line. <4> The provided drive signal is supplied to the fourth dummy word line DWL <4> .

[0097] According to the implementation, the number of grounding transistors GTRd4 included in the first grounding transistor circuit 211_1 may be less than the number of transmission transistors TRg, TRd1 to TRd4, TR1 to TRm and TRs1 to TRs3 included in the first transmission transistor circuit 211_2.

[0098] According to the implementation, the first grounding transistor circuit 211_1 may not include connections to multiple string select lines SSL. <1> To SSL <3> First DWL (Dual Word Line) <1> Up to the third dummy word line DWL <3> A grounding transistor for multiple word lines (i.e., the first word line WL1 to the m-th word line WLm) and the ground select line GSL. Conversely, the first grounding transistor circuit 211_1 can control the connection to the fourth dummy word line DWL. <4> The grounding transistor GTRd4. Therefore, the first grounding transistor circuit 211_1 can reduce the number of grounding transistors and reduce the chip size of the memory device 10.

[0099] Figure 11 This is a table showing the voltage conditions during read operations of a storage device according to one or more embodiments. Figure 12 This is a circuit diagram illustrating the operation of the first transmission transistor circuit 211_2, the first ground transistor circuit 211_1, and the first memory block BLK1 during a read operation of a memory device according to one or more embodiments.

[0100] Simultaneously refer to Figure 11 and Figure 12 Assuming that when storage block BLK1 is selected, the first selection line SSL <1> Not selected, second selection line SSL <2> The first line BL1 is selected, and the second line BL2 is not selected. Here, the term "not selected" can mean that it was not selected.

[0101] In this configuration, all ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm in the first ground transistor circuit 211_1 can be turned off, and all transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs2 in the first transmission transistor circuit 211_2 can be turned on. The read voltage Vread can be applied to the selected second string select line SSL. <2> And ground voltage (e.g., 0V) can be applied to the unselected first string select line SSL. <1> A precharge voltage Vpre can be applied to the selected first bit line BL1, and a ground voltage (e.g., 0V) can be applied to the unselected second bit line BL2. A read voltage Vread can be applied to the fourth dummy word line DWL. <4> The unselected word line and ground select line GSL can apply a select voltage Vsel to the selected word line and can apply a ground voltage (e.g., 0V) to the common source line CSL.

[0102] Reference Figure 11 and Figure 12 Assuming that storage block BLK1 is not selected, the first selection line SSL <1> Not selected, second selection line SSL <2> When selected, the first bit line BL1 is selected, and the second bit line BL2 is not selected. In this case, only the ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm included in the first ground transistor circuit 211_1 can be turned on, and the transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs2 included in the first transmission transistor circuit 211_2 can be turned off. In one or more embodiments, if the first ground transistor circuit 211_1 includes a ground transistor GTRd4, then the first string selection line SSL... <1> Second String Select Line SSL <2> It can be floated, and the first word line WL1 to the m-th word line WLm, and the first dummy word line DWL <1> Up to the third dummy word line DWL <3> The ground select line GSL can be floated. However, a ground voltage (e.g., 0V) can be applied to the fourth dummy word line DWL. <4> And the common source line CSL.

[0103] In other words, such as Figure 12As shown, the first grounding transistor circuit 211_1 according to one or more embodiments may not include connections to multiple string select lines SSL. <1> To SSL <3> First DWL (Dual Word Line) <1> Up to the third dummy word line DWL <3> A grounding transistor for multiple word lines (i.e., the first word line WL1 to the m-th word line WLm) and the ground select line GSL. Conversely, the first grounding transistor circuit 211_1 can control the connection to the fourth dummy word line DWL. <4> The ground transistor GTRd4 is included. Therefore, the first ground transistor circuit 211_1 can reduce the number of ground transistors and reduce the chip size of the memory device 10. In one or more other embodiments, if the first ground transistor circuit 211_1 includes a ground transistor GTRg, then a ground voltage (e.g., 0V) can be applied to the ground select line GSL when the memory block BLK1 is not selected. If the first ground transistor circuit 211_1 includes ground transistors GTRd1 to GTRd4, then a ground voltage (e.g., 0V) can be applied to the first dummy word line DWL when the memory block BLK1 is not selected. <1> Up to the fourth dummy word line DWL <4> If the first ground transistor circuit 211_1 includes ground transistors GTR1 to GTRm, then when memory block BLK1 is not selected, a ground voltage (e.g., 0V) can be applied to the first word line WL1 to the m-th word line WLm. In other words, if the first ground transistor circuit 211_1 includes ground transistors GTRg, GTRd1 to GTRd4, and / or GTR1 to GTRm, then when memory block BLK1 is not selected, a ground voltage (e.g., 0V) can be applied to the ground selection line GSL, the first dummy word line DWL... <1> Up to the fourth dummy word line DWL <4> And / or the first word line WL1 to the m-th word line WLm.

[0104] Figure 13 This is a table showing the voltage conditions during programming operations of a storage device according to one or more embodiments. Figure 14 This is a circuit diagram illustrating the operation of the first transmission transistor circuit 211_2, the first ground transistor circuit 211_1, and the first memory block BLK1 during programming operations of a memory device according to one or more embodiments.

[0105] Simultaneously refer to Figure 13 and Figure 14 Assuming that when storage block BLK1 is selected, the first selection line SSL <1> Not selected, second selection line SSL <2> The first line BL1 was selected, and the second line BL2 was not selected.

[0106] In this configuration, all grounding transistors GTRg, GTRd1 to GTRd4, GTR1 to GTRm in the first grounding transistor circuit 211_1, and all transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs2 in the first transmission transistor circuit 211_2, can be turned on. The internal voltage Vcc can be applied to the selected second string selection line SSL. <2> And ground voltage (e.g., 0V) can be applied to the unselected first string select line SSL. <1> A ground voltage (e.g., 0V) can be applied to the selected first bit line BL1, and an internal voltage Vcc can be applied to the unselected second bit line BL2. The voltage Vpass can be applied to the unselected word line and the dummy word line DWL. <1> To DWL <4> Furthermore, the programming voltage Vpgm can be applied to the selected word line. A ground voltage (e.g., 0V) can be applied to the ground select line GSL, and a common source voltage Vcsl can be applied to the common source line CSL.

[0107] Reference Figure 13 and Figure 14 Assuming that storage block BLK1 is not selected, the first selection line SSL <1> Not selected, second selection line SSL <2> When selected, the first bit line BL1 is selected, and the second bit line BL2 is not selected. In this case, only the ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm included in the first ground transistor circuit 211_1 can be turned on, and the transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs2 included in the first transmission transistor circuit 211_2 can be turned off. The first selection line SSL <1> Second String Select Line SSL <2> It can be floated, and the word line, the first dummy word line DWL <1> Up to the third dummy word line DWL <3> The ground select line GSL can be floated. However, a ground voltage (e.g., 0V) can be applied to the fourth dummy word line DWL. <4> Furthermore, the common source voltage Vcsl can be applied to the common source line CSL.

[0108] In other words, such as Figure 14 As shown, the first grounding transistor circuit 211_1 according to one or more embodiments may not include connections to multiple string select lines SSL. <1> To SSL <3> First DWL (Dual Word Line) <1> Up to the third dummy word line DWL <3> A grounding transistor for multiple word lines (i.e., the first word line WL1 to the m-th word line WLm) and the ground select line GSL. Conversely, the first grounding transistor circuit 211_1 can control the connection to the fourth dummy word line DWL. <4> The grounding transistor GTRd4. Therefore, the first grounding transistor circuit 211_1 can reduce the number of grounding transistors and reduce the chip size of the memory device 10.

[0109] Figure 15 This is a table showing the voltage conditions during an erase operation of a storage device according to one or more embodiments. Figure 16 This is a circuit diagram illustrating the operation of the first transmission transistor circuit 211_2, the first ground transistor circuit 211_1, and the first memory block BLK1 during an erase operation of a memory device according to one or more embodiments.

[0110] Simultaneously refer to Figure 15 and Figure 16 Assuming that when storage block BLK1 is selected, the first selection line SSL <1> Not selected, second selection line SSL <2> The first line BL1 was selected, and the second line BL2 was not selected.

[0111] In this configuration, all grounding transistors GTRg, GTRd1 to GTRd4, GTR1 to GTRm in the first grounding transistor circuit 211_1, and all transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs2 in the first transmission transistor circuit 211_2, can be switched on. The first select line SSL <1> Second String Select Line SSL <2> It can be floated and has a virtual word line (DWL). <1> To DWL <4> The ground select line GSL can be floated. A ground voltage (e.g., 0V) can be applied to the selected word line. The erase voltage Vers can be applied to the common source line CSL.

[0112] Reference Figure 15 and Figure 16 Assuming that storage block BLK1 is not selected, the first selection line SSL <1> Not selected, second selection line SSL <2> When selected, the first bit line BL1 is selected, and the second bit line BL2 is not selected. In this case, only the ground transistors GTRg, GTRd1 to GTRd4, and GTR1 to GTRm included in the first ground transistor circuit 211_1 can be turned on, and the transmission transistors TRg, TRd1 to TRd4, TR1 to TRm, and TRs1 to TRs2 included in the first transmission transistor circuit 211_2 can be turned off. The first selection line SSL <1> Second String Select Line SSL <2> It can be floated, and the first word line WL1 to the m-th word line WLm, and the dummy word line DWL <1> To DWL <4> The ground selection line GSL can be floated. The erase voltage Vers can be applied to the common source line CSL.

[0113] Figure 17 This is a block diagram illustrating an example of a storage device applied to a solid-state drive (SSD) system 1000 according to an embodiment.

[0114] Reference Figure 17 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 exchanges signals with the host 1100 via a signal connector and receives power via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and multiple storage devices 1230, 1240, and 1250. The storage devices 1230, 1240, and 1250 may be vertically stacked NAND flash memory devices. Here, the SSD 1200 can be referenced above... Figures 1 to 16 The described implementation method shall be used to achieve this.

[0115] Figure 18 This is a block diagram for describing a system 2000 of an electronic device including a storage device according to one or more embodiments.

[0116] Reference Figure 18 System 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAM 2500a and 2500b, flash memory 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. System 2000 can be implemented as a laptop computer, mobile phone, smartphone, tablet PC, wearable device, healthcare device, or IoT device. Furthermore, system 2000 can be implemented as a server or PC.

[0117] Camera 2100 can capture still images or videos according to user control, and can store the captured image / video data or send the captured image / video data to display 2200. Audio processor 2300 can process audio data or network content included in flash memory 2600a and 2600b. Modem 2400 can send modulated signals for wired / wireless data transmission / reception to receiver, and receiver can demodulate the modulated signals to recover the original signals. I / O devices 2700a and 2700b may include devices that provide digital input and / or digital output functions, such as Universal Serial Bus (USB), memory, digital camera, Secure Digital (SD) card, Digital Multifunction Disk (DVD), network adapter, touch screen, etc.

[0118] AP 2800 can control the overall operation of system 2000. AP 2800 may include controller block 2810, accelerator block or accelerator chip 2820, and interface block 2830. AP 2800 can control display 2200, causing a portion of the contents stored in flash memory 2600a and 2600b to be displayed on display 2200. When user input is received through I / O devices 2700a and 2700b, AP 2800 can perform control operations corresponding to the user input. AP 2800 may include accelerator block (which is circuitry dedicated to computing artificial intelligence (AI) data), or may include accelerator chip 2820 separate from AP 2800. DRAM 2500b may be additionally disposed in accelerator block or accelerator chip 2820. An accelerator block is a functional block specifically designed to perform the functions of AP 2800, and may include a GPU (a functional block specifically designed to process graphics data), a neural processing unit (NPU) (a block specifically designed to perform AI computation and inference), and a data processing unit (DPU) (a block specifically designed to perform data transmission). According to an implementation, images captured by the user via camera 2100 are signal-processed and stored in DRAM 2500b, and the accelerator block or accelerator chip 2820 can use the data stored in DRAM 2500b and the inference function to perform AI data computation for data recognition.

[0119] System 2000 may include multiple DRAMs 2500a and 2500b. AP 2800 can configure the DRAM interface protocol and communicate with DRAMs 2500a and 2500b to control them via JEDEC-compliant Command and Mode Register (MRS) settings, or to utilize company-specific features such as low-voltage / high-speed / reliability and Cyclic Redundancy Check (CRC) / Error Correction Code (ECC) functions. For example, AP 2800 can communicate with DRAM 2500a via a JEDEC-compliant interface (e.g., LPDDR4 and LPDDR5), and accelerator block or accelerator chip 2820 can configure and use a new DRAM interface protocol to control DRAM 2500b for accelerators with greater bandwidth than DRAM 2500a.

[0120] although Figure 18Only DRAMs 2500a and 2500b are shown, but this disclosure is not limited thereto. Memory types such as PRAM, SRAM, MRAM, RRAM, FRAM, and hybrid RAM can be used, provided the bandwidth, response speed, and voltage conditions of the AP 2800 or accelerator chip 2820 are met. DRAMs 2500a and 2500b have relatively low latency and bandwidth compared to I / O devices 2700a and 2700b or flash memory 2600a and 2600b. DRAMs 2500a and 2500b are initialized when the system 2000 is powered on and OS and application data are loaded, and therefore DRAMs 2500a and 2500b can be used as temporary storage for OS and application data, or as execution space for various software codes.

[0121] In DRAM 2500a and 2500b, four arithmetic operations (addition, subtraction, multiplication, and division), vector computation, address computation, or Fast Fourier Transform (FFT) computation can be performed. Furthermore, DRAM 2500a and 2500b can perform operations for inference. Here, inference can be performed using deep learning algorithms employing artificial neural networks. Deep learning algorithms can include training operations for learning a model from various data and inference operations for recognizing data using the trained model.

[0122] System 2000 may include multiple memories or multiple flash memory devices 2600a and 1600b, with a capacity greater than that of DRAM 2500a and 2500b. An accelerator block or accelerator chip 2820 may use flash memory 2600a and 2600b to perform training operations and AI data computations. According to an embodiment, flash memory 2600a and 2600b may include a memory controller 2610 and flash memory devices 2620, and the training operations and inference AI data computations performed by AP 2800 and / or accelerator chip 2820 can be performed more efficiently by using an arithmetic unit included in the memory controller 2610. Flash memory 2600a and 2600b may store images captured by camera 2100 or data transmitted via a data network. For example, flash memory 2600a and 2600b may store augmented reality / virtual reality content, high-definition (HD) content, or ultra-high-definition (UHD) content.

[0123] In System 2000, flash memory 2600a and 2600b may include the above-mentioned references. Figures 1 to 17The described storage device may include: a storage block comprising multiple serial select lines, multiple word lines, a ground select line, and multiple dummy word lines, the dummy word lines being arranged between the multiple serial select lines and the multiple word lines or between the ground select line and the multiple word lines; a transmission transistor circuit comprising multiple transmission transistors respectively connected to the multiple serial select lines, the multiple word lines, the ground select lines, and the multiple dummy word lines of the storage block, and the multiple transmission transistors being driven when the storage block is selected; and a ground transistor circuit comprising multiple ground transistors respectively connected to some of the multiple serial select lines, the multiple word lines, the ground select lines, and the multiple dummy word lines of the storage block, and the multiple ground transistors being driven when the storage block is not selected. In the storage device, the number of ground transistors included in the storage block may be less than the number of serial select lines.

[0124] Furthermore, a ground transistor circuit can connect the serial select line to the gate of one of the multiple dummy word lines of a ground transistor, instead of connecting the ground transistor to the serial select line. In other words, a ground transistor circuit can reduce the number of ground transistors and reduce the chip size of the memory device.

[0125] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims. In a single embodiment, specific features described in the context of a standalone implementation of this disclosure may also be combined and implemented. Conversely, various features described in the context of a single implementation may also be implemented independently in multiple embodiments, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations thereof.

Claims

1. A storage device, comprising: A storage block includes multiple cell strings, each of which is configured to be selected by multiple string selection lines, wherein each of the multiple cell strings is connected to multiple word lines stacked in a vertical direction; A transmission transistor circuit includes a plurality of transmission transistors respectively connected to the plurality of string select lines and the plurality of word lines, wherein the plurality of transmission transistors are configured to be turned on based on the selection of the memory block; and A grounding transistor circuit includes a plurality of grounding transistors respectively connected to the plurality of word lines, wherein the plurality of grounding transistors are configured to be turned on based on the memory block not being selected. The number of grounding transistors is less than the number of multiple string select lines.

2. The storage device according to claim 1, wherein, Each of the plurality of unit strings is connected to a dummy word line between the plurality of word lines and the ground select line. The plurality of transmission transistors are respectively connected to the dummy word line and the ground select line, and The grounding transistor circuit also includes at least one grounding transistor connected to at least one of the dummy word lines.

3. The storage device according to claim 1, wherein, Each of the plurality of unit strings is connected to a dummy word line between the plurality of word lines and the plurality of string select lines. The plurality of transmission transistors are respectively connected to the dummy word lines, and The grounding transistor circuit also includes at least one grounding transistor connected to at least one of the dummy word lines.

4. The storage device according to claim 1, wherein, The number of grounding transistors in the grounding transistor circuit is less than the number of transmission transistors in the transmission transistor circuit.

5. The storage device according to claim 1, wherein, At least one end of the grounding transistor in the grounding transistor circuit is configured to have a ground voltage applied.

6. The storage device according to claim 1, wherein: Based on the selection of the memory block, the transmission transistor circuit is configured to drive the plurality of string select lines and the plurality of word lines in response to a first phase of the first block select signal, and the ground transistor circuit is configured to turn off in response to a first phase of the second block select signal; and Since the memory block is not selected, the grounding transistor circuit is configured to drive the multiple word lines in response to the second phase of the second block selection signal, and the transmission transistor circuit is configured to turn off in response to the second phase of the first block selection signal.

7. The storage device according to claim 6, wherein, The first phase of the first block selection signal is opposite to the first phase of the second block selection signal.

8. The storage device according to claim 6, wherein: During a read operation of the memory block, based on the fact that the memory block is not selected, the multiple word lines are configured to have a ground voltage level applied, and the multiple string select lines are configured to float.

9. The storage device according to claim 6, wherein: During the programming operation of the memory block, based on the fact that the memory block is not selected, the multiple word lines are configured to be applied with a ground voltage level, and the multiple string select lines are configured to be floating.

10. A storage device comprising: A memory block is formed on a first semiconductor layer and includes a plurality of cell strings selected by a plurality of string select lines, wherein each cell string includes a plurality of memory cells, the plurality of memory cells being connected to a plurality of word lines stacked in a vertical direction; Multiple dummy word lines are formed on the first semiconductor layer and located between the multiple serial select lines and the ground select lines; A transfer transistor circuit is formed on a second semiconductor layer located below the first semiconductor layer along the vertical direction. The transfer transistor circuit includes a plurality of transfer transistors, which are respectively connected to a plurality of string select lines, a plurality of word lines, a plurality of dummy word lines, and a ground select line. The plurality of transfer transistors are configured to be turned on based on the selection of the memory block. A ground transistor circuit is formed on the second semiconductor layer, the ground transistor circuit including at least one ground transistor connected to at least one of the plurality of dummy word lines, wherein the at least one ground transistor is configured to be turned on based on the memory block not being selected.

11. The storage device according to claim 10, wherein: The multiple dummy character lines include: The first group of dummy word lines is located between the plurality of string select lines and the plurality of word lines; and The second group of dummy word lines is located between the plurality of word lines and the ground selection line; The grounding transistor circuit includes: One or more first ground transistors are respectively connected to the first set of dummy word lines; and One or more second ground transistors are respectively connected to the second set of dummy word lines.

12. The storage device according to claim 10, wherein, The number of the at least one grounding transistor in the grounding transistor circuit is less than the number of the plurality of series select lines.

13. The storage device according to claim 10, wherein, The number of at least one grounding transistor in the grounding transistor circuit is less than the number of the plurality of transmission transistors in the transmission transistor circuit.

14. The storage device according to claim 10, wherein, The first terminal of the grounding transistor in the at least one grounding transistor is configured to have a ground voltage applied, and the second terminal of the grounding transistor in the at least one grounding transistor is connected to a dummy word line in the plurality of dummy word lines.

15. The storage device according to claim 10, wherein: Based on the selection of the memory block, the transmission transistor circuit is configured to drive the plurality of string select lines and the plurality of word lines in response to a first phase of the first block select signal, and the ground transistor circuit is configured to turn off in response to a first phase of the second block select signal; and Since the memory block is not selected, the grounding transistor circuit is configured to drive the multiple word lines in response to the second phase of the second block selection signal, and the transmission transistor circuit is configured to turn off in response to the second phase of the first block selection signal.

16. The storage device according to claim 15, wherein: During a read operation of the memory block, based on the fact that the memory block is not selected, the multiple word lines are configured to have a ground voltage level applied, and the multiple string select lines are configured to float.

17. The storage device according to claim 15, wherein: During the programming operation of the memory block, based on the fact that the memory block is not selected, the multiple word lines are configured to be applied with a ground voltage level, and the multiple string select lines are configured to be floating.

18. A storage device comprising: The storage block includes multiple control lines, among which: The multiple control lines include multiple serial select lines, multiple word lines, a ground select line, and multiple dummy word lines. The multiple dummy word lines are arranged between the multiple serial select lines and the multiple word lines, or between the ground select line and the multiple word lines. The plurality of control lines include a first group of control lines, wherein the first group of control lines includes at least one word line among the plurality of word lines and at least one dummy word line among the plurality of dummy word lines; A transmission transistor circuit, comprising transmission transistors respectively connected to the plurality of control lines; and The grounding transistor circuit includes at least one grounding transistor connected to the first set of control lines.

19. The storage device according to claim 18, wherein: The first set of control lines includes the plurality of dummy word lines and the ground selection line. The transmission transistor circuit is configured to drive the plurality of control lines. The grounding transistor circuit is configured to drive the first set of control lines, and The number of at least one grounding transistor in the grounding transistor circuit is less than the number of transmission transistors in the transmission transistor circuit.

20. The storage device according to claim 18, wherein, The transmission transistor circuit is configured to drive the plurality of serial select lines among the plurality of control lines based on the selection of the memory block and in response to a first block select signal, and The multiple string selection lines among the multiple control lines are configured to float based on the storage block not being selected.

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