Package structure comprising at least two memory elements, assembly structure and preparation method thereof

Abstract

The invention provides a packaging structure comprising at least two memory elements, an assembly structure and a preparation method thereof. The package structure includes a molded structure, a logic element, a non-volatile memory element and a volatile memory element. The molded structure includes a memory controller element, an interconnect element, and an encapsulant encapsulating the memory controller element and the interconnect element. The logic element is electrically connected with the interconnection element. The nonvolatile memory element and the volatile memory element are electrically connected with the logic element through the memory controller element. The volatile memory element is electrically connected with the nonvolatile memory element through the memory controller element.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 804,435 (priority date August 14, 2024), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a packaging structure, an assembly structure, and a method for preparing the same, and particularly to a packaging structure comprising at least two memory elements, an assembly structure comprising the packaging structure, and a method for preparing the same. Background Technology

[0004] Semiconductor electronics are widely used in various electronic applications, and their size is constantly shrinking to meet the demands of current applications. However, shrinking the size of semiconductor electronics presents several challenges, affecting their final electrical characteristics, quality, cost, and yield. To meet the trend of miniaturization, semiconductor electronics require more functions and high-capacity data processing capabilities. Therefore, increasing the integration of semiconductor components used in electronic products is becoming increasingly important. However, due to limitations in semiconductor integration technology, it is extremely challenging to meet all the necessary functions using only a single semiconductor chip. To address this issue, semiconductor packages containing multiple semiconductor chips have been developed.

[0005] The prior art description above is merely to provide background information and does not acknowledge that the prior art description above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the prior art above should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a packaging structure including a molding structure, a logic element, a non-volatile memory element, and a volatile memory element. The molding structure includes a memory controller element, an interconnect element, and an encapsulant. The memory controller element includes a first conductive structure, and the first conductive structure includes a first circuit, a second circuit, and a third circuit. The interconnect element is arranged side-by-side with the memory controller element and includes a second conductive structure. The encapsulant encapsulates the memory controller element and the interconnect element. The logic element is disposed on the molding structure and includes a circuit structure, and the circuit structure includes a fourth circuit, a fifth circuit, and a sixth circuit. The sixth circuit of the logic element is electrically connected to the second conductive structure of the interconnect element. The non-volatile memory element is disposed on the molding structure and is electrically connected to the fourth circuit of the logic element through the second circuit of the memory controller element. The volatile memory element is disposed on the molding structure and is electrically connected to the fifth circuit of the logic element through the third circuit of the memory controller element. The volatile memory element is electrically connected to the non-volatile memory element through the first circuit of the memory controller element.

[0007] Another aspect of this disclosure provides an assembly structure including a substrate, an interconnect element, a first memory controller element, a second memory controller element, a logic element, a first non-volatile memory element, a first volatile memory element, a second non-volatile memory element, and a second volatile memory element. The interconnect element is disposed on and electrically connected to the substrate. The first memory controller element is disposed above and electrically connected to the substrate. The second memory controller element is disposed above and electrically connected to the substrate, wherein the first memory controller element and the second memory controller element are disposed on different sides of the interconnect element. The logic element is disposed above the interconnect element, the first memory controller element, and the second memory controller element, and is electrically connected to the first memory controller element. The first non-volatile memory element is disposed above and electrically connected to the first memory controller element. The first volatile memory element is arranged side-by-side with the first non-volatile memory element, and is disposed above and electrically connected to the first memory controller element. The second non-volatile memory element is disposed above the second memory controller element and is electrically connected to the second memory controller element. The second volatile memory element is disposed side by side with the second non-volatile memory element, and is disposed above the second memory controller element and is electrically connected to the second memory controller element.

[0008] Another aspect of this disclosure provides a method of fabrication. The method includes: providing a molded structure comprising a first memory controller element, an interconnect element disposed side-by-side with the first memory controller element, and an encapsulant for encapsulating the first memory controller element and the interconnect element; electrically connecting a logic element to the first memory controller element and the interconnect element; and electrically connecting a first non-volatile memory element and a first volatile memory element to the first memory controller element.

[0009] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0010] A more complete understanding of the disclosure of this application can be obtained by referring to the detailed description and taking into account the accompanying drawings, wherein similar reference numerals refer to similar elements throughout the drawings.

[0011] Figure 1 This is a flowchart illustrating a method for preparing an assembly structure according to some embodiments of this disclosure.

[0012] Figure 2A This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0013] Figure 2B This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0014] Figure 2C This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure of some embodiments of this disclosure.

[0015] Figure 3 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0016] Figure 4 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0017] Figure 5 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0018] Figure 6AThis is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0019] Figure 6B This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0020] Figure 7A This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0021] Figure 7B This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0022] Figure 7C This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0023] Figure 8 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0024] Figure 9 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0025] Figure 10 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0026] Figure 11A This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0027] Figure 11B This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0028] Figure 11C This is a schematic diagram illustrating the various stages of the preparation method of the packaging structure according to some embodiments of this disclosure.

[0029] Figure 11D This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0030] Figure 12A This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0031] Figure 12B This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0032] Figure 12C This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0033] Figure 13 This is a schematic diagram illustrating the various stages of the preparation method of the assembly structure according to some embodiments of this disclosure.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 1: First memory controller element

[0036] 1': Second memory controller element

[0037] 2: Interconnecting elements

[0038] 3: Logic elements

[0039] 4: First volatile memory element

[0040] 4': Second volatile memory element

[0041] 5: First non-volatile memory element

[0042] 5': Second non-volatile memory element

[0043] 6: Packaging structure

[0044] 6a: Packaging structure

[0045] 7: Assembly Structure

[0046] 7a: Assembly structure

[0047] 8: Molded Structure

[0048] 10: First base

[0049] 11: Top surface

[0050] 12: Bottom

[0051] 13: Side view

[0052] 14: First conductive structure

[0053] 14a: First dielectric layer

[0054] 14b: First circuit layer

[0055] 14c: Second dielectric layer

[0056] 14d: Second circuit layer

[0057] 14e: Internal through hole

[0058] 14f: Third dielectric layer

[0059] 15: First upper structure

[0060] 16: First lower structure

[0061] 17: First conductive via

[0062] 18: Welding materials

[0063] 20: Base

[0064] 21: Top surface

[0065] 22: Bottom surface

[0066] 23: Side view

[0067] 24: Conductive structure

[0068] 24a: First dielectric layer

[0069] 24b: First circuit layer

[0070] 24c: Second dielectric layer

[0071] 24d: Second circuit layer

[0072] 24e: Internal through hole

[0073] 24f: Third dielectric layer

[0074] 25: Upper Structure

[0075] 26: Lower structure

[0076] 27: Conductive via

[0077] 28: Welding materials

[0078] 30: Main Part

[0079] 31: First Surface

[0080] 32: Second surface

[0081] 33: Side view

[0082] 35: Circuit Structure

[0083] 35a: Dielectric structure

[0084] 35b: Circuit layer

[0085] 35c: Inner padding

[0086] 35d: Internal through hole

[0087] 36: First joint pad

[0088] 37: Second joint pad

[0089] 38: Third joint pad

[0090] 41: First Semiconductor Wafer

[0091] 42: Second semiconductor wafer

[0092] 43: Third semiconductor wafer

[0093] 44: Fourth Semiconductor Wafer

[0094] 45: Base semiconductor wafer

[0095] 46: Encapsulant

[0096] 51: First Chip

[0097] 52: Second chip

[0098] 70: Base

[0099] 72: External connector

[0100] 74: Welding materials

[0101] 76: Welding materials

[0102] 80: Carrier

[0103] 82: Adhesive layer

[0104] 84: Encapsulant

[0105] 101: First Surface

[0106] 102: Second Surface

[0107] 141: First Circuit

[0108] 142: Second Circuit

[0109] 143: Third Circuit

[0110] 151: First upper dielectric layer

[0111] 152: First pad

[0112] 161: First lower dielectric layer

[0113] 162: First pad

[0114] 201: First Surface

[0115] 202: Second Surface

[0116] 251: Upper dielectric layer

[0117] 252: Pad

[0118] 261: Lower dielectric layer

[0119] 262: Underpad

[0120] 351: Fourth Circuit

[0121] 352: Fifth Circuit

[0122] 353: Seventh Circuit

[0123] 354: The Eighth Circuit

[0124] 356: The Sixth Circuit

[0125] 410: First basement portion

[0126] 411: Bottom

[0127] 412: Top surface

[0128] 413: Side view

[0129] 414: Conductive structure of the first wafer

[0130] 415: First lower structure

[0131] 416: First superstructure

[0132] 417: First conductive hole

[0133] 450: Fifth base

[0134] 451: Top surface

[0135] 452: Bottom

[0136] 454: Fifth conductive structure

[0137] 455: Fifth superstructure

[0138] 456: Fifth Lower Structure

[0139] 457: Fifth conductive via

[0140] 841: Top surface

[0141] 842: Bottom

[0142] 900: Preparation method

[0143] 4151: First lower dielectric layer

[0144] 4152: First lower solder pad

[0145] 4161: First upper dielectric layer

[0146] 4162: First upper solder pad

[0147] 4551: Fifth upper dielectric layer

[0148] 4552: Fifth upper solder pad

[0149] 4561: Fifth lower dielectric layer

[0150] 4562: Fifth lower solder pad

[0151] G1: Gap

[0152] G2: Gap

[0153] G3: Gap

[0154] II: Section

[0155] II-II: Section

[0156] III-III: Sectioning

[0157] IV-IV: Section

[0158] IX-IX: Section

[0159] S901: Steps

[0160] S902: Steps

[0161] S903: Steps

[0162] VIII-VIII: Sectioning

[0163] VII-VII: Section

[0164] VI-VI: Section

[0165] VV: Section line

[0166] XX: Section Detailed Implementation

[0167] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as commonly done by one of ordinary skill in the art related to the content of this disclosure. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0168] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present invention.

[0169] The terminology used herein is for describing specific embodiments only and is not intended to limit the scope of the invention. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprising” and “including,” when used in this specification, indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0170] Figure 1 This is a flowchart illustrating a method 900 for preparing the assembly structure 7 according to some embodiments of this disclosure. Figure 2A , Figure 2B , Figure 2C , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 11D These are schematic diagrams illustrating various stages of the preparation method of the assembly structure 7 according to some embodiments of the present disclosure. At least some of the figures have been simplified for a better understanding of the various aspects of the present disclosure.

[0171] Please refer to Figure 1 and Figures 2A to 6B In step S901, a molded structure 8 may be provided or formed.

[0172] Reference Figure 2A , Figure 2B , Figure 2C , Figure 3 and Figure 4 It can provide a first memory controller element 1, an interconnect element 2, a second memory controller element 1', and a carrier 80 having an adhesive layer 82 (or a release layer). Figure 2A This is an example Figure 2Band Figure 2C A top view. Or, Figure 2B It can be an example along Figure 2A Sectional view with center section II. Figure 2C Then it is along Figure 2A Sectional view along section line II-II. Figure 3 This is a cross-sectional view illustrating a first memory controller element 1 according to some embodiments of the present disclosure. Figure 4 This is a cross-sectional view illustrating interconnecting elements 2 in some embodiments of this disclosure.

[0173] The function and size of the first memory controller element 1 may differ from those of the interconnect element 2. The function and size of the first memory controller element 1 may be the same as those of the second memory controller element 1'. The thickness of the first memory controller element 1 may be equal to the thickness of the interconnect element 2 and the thickness of the second memory controller element 1'.

[0174] In some embodiments, the first memory controller element 1 may be configured to control different memory elements and may also be referred to as a "first memory controller die," "first memory controller chip," "first memory controller semiconductor die," or "first memory controller semiconductor chip." The interconnect element 2 may be configured for vertical electrical connection and may also be referred to as an "interconnect die," "interconnect chip," "interconnect semiconductor die," "interconnect semiconductor chip," "intermediate," "intermediate die," or "intermediate chip." The second memory controller element 1' may be configured to control different memory elements and may also be referred to as a "second memory controller die," "second memory controller chip," "second memory controller semiconductor die," or "second memory controller semiconductor chip."

[0175] Reference Figure 3 The first memory controller element 1 may have a top surface 11 (e.g., a first surface), a bottom surface 12 (e.g., a second surface), and a side surface 13 extending between the top surface 11 and the bottom surface 12. The first memory controller element 1 may include a first base 10, a first conductive structure 14, a first upper structure 15, a first lower structure 16, a plurality of first conductive vias 17, and a plurality of solder materials 18.

[0176] The first base 10 may have a first surface 101 (e.g., a top surface) and a second surface 102 (e.g., a bottom surface) opposite the first surface 101. The first base 10 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials or combinations thereof. In some embodiments, the first base 10 may include a semiconductor-insulator substrate, such as a silicon-insulator (SOI) substrate, a silicon-germanium-insulator (SGOI) substrate, or a germanium-insulator (GOI) substrate. In some embodiments, the first base 10 may be a bulk semiconductor substrate composed entirely of at least one semiconductor material; the bulk semiconductor substrate does not contain any dielectric, insulating layer, or conductive features.

[0177] The first conductive structure 14 may be formed or disposed on the first surface 101 (e.g., the top surface) of the first base 10. In some embodiments, the first conductive structure 14 may include a plurality of front-end-of-line (FEOL) elements, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bijunction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC elements, or combinations thereof. In some embodiments, the first conductive structure 14 may also include at least one back-end-of-line (BEOL) interconnect pattern, such as a plurality of patterned circuit layers for electrical connection to the front-end (FEOL) elements. In some embodiments, the first conductive structure 14 may also include at least one dielectric layer or at least one dielectric structure to cover the front-end (FEOL) elements and the back-end (BEOL) interconnect pattern.

[0178] The first conductive structure 14 may include a first dielectric layer 14a, a first circuit layer 14b (including multiple traces and multiple pads), a second dielectric layer 14c, a second circuit layer 14d (including multiple traces and multiple pads), multiple vias 14e, and a third dielectric layer 14f. The first dielectric layer 14a may be disposed on a first surface 101 (e.g., the top surface) of the first base 10. The first dielectric layer 14a may be an interlayer dielectric (ILD) layer and may include SiO2, SiN, and / or SiCN. The first circuit layer 14b (including traces and pads) may be disposed on the first dielectric layer 14a.

[0179] A second dielectric layer 14c may be disposed on the first dielectric layer 14a to cover the first circuit layer 14b. The second dielectric layer 14c may be an inter-metal dielectric (IMD) layer and may include SiO2, SiN, and / or SiCN. A second circuit layer 14d (including traces and pads) may be disposed on the second dielectric layer 14c.

[0180] An internal via 14e may be disposed in the second dielectric layer 14c and may connect the first circuit layer 14b and the second circuit layer 14d. A third dielectric layer 14f may surround the second circuit layer 14d. The third dielectric layer 14f may include SiO2, SiN and / or SiCN.

[0181] Reference Figure 2A and Figure 3 The second circuit layer 14d of the first conductive structure 14 may include the first circuit 141 ( Figure 11D ), second circuit 142 ( Figure 11C ) and the third circuit 143 ( Figure 2B The first circuit 141 may also be referred to as a "first circuit region," "first circuit structure," or "first circuit trace." The second circuit 142 may also be referred to as a "second circuit region," "second circuit structure," or "second circuit trace." The third circuit 143 may also be referred to as a "third circuit region," "third circuit structure," or "third circuit trace." The first circuit 141, the second circuit 142, and the third circuit 143 of the first memory controller element 1 may be spaced apart from each other and may be electrically connected to each other in a horizontal direction. This horizontal direction may be defined as a direction substantially parallel to the top surface 21 of the interconnecting element 2 or the top surface 11 of the first memory controller element 1.

[0182] Reference Figure 3 A first upper structure 15 may be formed or disposed on a first conductive structure 14. The first upper structure 15 may include a first upper dielectric layer 151 and a plurality of first upper pads 152. The first upper pads 152 may be disposed on a second circuit layer 14d and may be embedded in the first upper dielectric layer 151. Each first upper pad 152 may be a hybrid bonding (HB) pad and may comprise copper or aluminum. Each first upper pad 152 may be a solder bonding pad. The first upper pads 152 may be exposed by the first upper dielectric layer 151. The first upper dielectric layer 151 may be a hybrid bonding (HB) dielectric layer and may comprise SiO2, SiN, and / or SiCN. In some embodiments, the top surface of the first upper pad 152 may be substantially aligned with the top surface of the first upper dielectric layer 151. In some embodiments, the thickness of the first upper pad 152 may be substantially equal to the thickness of the first upper dielectric layer 151.

[0183] A first conductive via 17 may be formed or disposed in the first base 10 and may extend beyond the first surface 101 (e.g., the top surface) of the first base 10. The first conductive via 17 may extend through the first dielectric layer 14a to connect to or contact the first circuit layer 14b. Therefore, the first conductive via 17 may extend into the first conductive structure 14 and may be electrically connected to the first conductive structure 14. Thus, the first upper pad 152 may be electrically connected to the first conductive via 17 through the first conductive structure 14. Furthermore, the first conductive via 17 may extend beyond the second surface 102 (e.g., the bottom surface) of the first base 10. The first conductive via 17 may extend through the first base 10. Therefore, the first conductive via 17 may be a monolithic structure, and the length of the first conductive via 17 may be greater than the thickness of the first base 10.

[0184] The first lower structure 16 may be formed or disposed on the second surface 102 (e.g., the bottom surface) of the first base 10. The first lower structure 16 may include a first lower dielectric layer 161 and a plurality of first lower pads 162. The first lower dielectric layer 161 may be disposed on the second surface 102 (e.g., the bottom surface) of the first base 10 and may cover the bottom of the first conductive via 17. The first lower dielectric layer 161 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiN and / or SiCN.

[0185] The first underpad 162 may be embedded in and exposed within the first lower dielectric layer 161. The first underpad 162 may be electrically connected to the first conductive via 17. In some embodiments, the first underpad 162 may directly contact the first conductive via 17. Each first underpad 162 may be a hybrid bonding (HB) pad and may comprise copper or aluminum. Each first underpad 162 may be a solder bonding pad. In some embodiments, the bottom surface of the first underpad 162 may be substantially aligned with the bottom surface of the first lower dielectric layer 161. In some embodiments, the thickness of the first underpad 162 may be less than the thickness of the first lower dielectric layer 161.

[0186] The welding material 18 can be a reflowable welding material and can be disposed on the first pad 162.

[0187] Reference Figure 4 The interconnect element 2 may have a structure similar to that of the first memory controller element 1. The interconnect element 2 may have a top surface 21 (e.g., a first surface), a bottom surface 22 (e.g., a second surface), and a side surface 23 extending between the top surface 21 and the bottom surface 22. The interconnect element 2 may include a base 20, a conductive structure 24, an upper structure 25, a lower structure 26, a plurality of conductive vias 27, and a plurality of solder materials 28.

[0188] The base 20 may have a first surface 201 (e.g., a top surface) and a second surface 202 (e.g., a bottom surface) opposite the first surface 201. The base 20 may be similar to the first base 10 of the first memory controller element 1.

[0189] The conductive structure 24 may be formed or disposed on the first surface 201 (e.g., the top surface) of the base 20. In some embodiments, the conductive structure 24 may be similar to the first conductive structure 14 of the first memory controller element 1. The conductive structure 24 may include a first dielectric layer 24a, a first circuit layer 24b (including a plurality of traces and a plurality of pads), a second dielectric layer 24c, a second circuit layer 24d (including a plurality of traces and a plurality of pads), a plurality of vias 24e, and a third dielectric layer 24f. The first dielectric layer 24a may be disposed on the first surface 201 (e.g., the top surface) of the base 20. The first circuit layer 24b may be disposed on the first dielectric layer 24a.

[0190] A second dielectric layer 24c may be disposed on the first dielectric layer 24a to cover the first circuit layer 24b. A second circuit layer 24d may be disposed on the second dielectric layer 24c. An internal via 24e may be disposed in the second dielectric layer 24c and may connect the first circuit layer 24b and the second circuit layer 24d. A third dielectric layer 24f may surround the second circuit layer 24d.

[0191] The upper structure 25 may be formed or disposed on the conductive structure 24. The upper structure 25 may include an upper dielectric layer 251 and a plurality of upper pads 252. The upper pads 252 may be disposed on the second circuit layer 24d and may be embedded in the upper dielectric layer 251. Each upper pad 252 may be a hybrid bond (HB) pad. The upper pads 252 may be exposed by the upper dielectric layer 251. The upper dielectric layer 251 may be a hybrid bond (HB) dielectric layer. In some embodiments, the top surface of the upper pad 252 may be substantially aligned with the top surface of the upper dielectric layer 251. In some embodiments, the thickness of the upper pad 252 may be substantially equal to the thickness of the upper dielectric layer 251.

[0192] A conductive via 27 may be formed or disposed in the base 20 and may extend beyond the first surface 201 (e.g., the top surface) of the base 20. The conductive via 27 may extend through the first dielectric layer 24a to connect to or contact the first circuit layer 24b. Therefore, the conductive via 27 may extend into and be electrically connected to the conductive structure 24. Thus, the upper pad 252 may be electrically connected to the conductive via 27 through the conductive structure 24. Furthermore, the conductive via 27 may extend beyond the second surface 202 (e.g., the bottom surface) of the base 20. The conductive via 27 may extend through the base 20.

[0193] The lower structure 26 may be formed or disposed on the second surface 202 (e.g., the bottom surface) of the base 20. The lower structure 26 may include a lower dielectric layer 261 and a plurality of lower pads 262. The lower dielectric layer 261 may be disposed on the second surface 202 (e.g., the bottom surface) of the base 20 and may cover the bottom of the conductive via 27. The lower dielectric layer 261 may be a hybrid bonding (HB) dielectric layer.

[0194] The lower pad 262 may be embedded in and exposed within the lower dielectric layer 261. The lower pad 262 may be electrically connected to the conductive via 27. In some embodiments, the lower pad 262 may directly contact the conductive via 27. Each lower pad 262 may be a hybrid bonding (HB) pad. In some embodiments, the bottom surface of the lower pad 262 may be substantially aligned with the bottom surface of the lower dielectric layer 261. In some embodiments, the thickness of the lower pad 262 may be less than the thickness of the lower dielectric layer 261.

[0195] The welding material 28 can be a reflowable welding material and can be disposed on the underpad 262.

[0196] Reference Figure 2B The structure of the second memory controller element 1' may be the same as or similar to that of the first memory controller element 1. The second memory controller element 1' may have a top surface 11 (e.g., a first surface), a bottom surface 12 (e.g., a second surface), and a side surface 13 extending between the top surface 11 and the bottom surface 12. The second memory controller element 1' may include a first circuit 141, a second circuit 142, a third circuit 143, and a plurality of soldering materials 18.

[0197] Reference Figure 5 The first memory controller element 1, the interconnect element 2, and the second memory controller element 1' may be attached to or bonded to the adhesive layer 82 (or release layer) of the carrier 80. The first memory controller element 1, the interconnect element 2, and the second memory controller element 1' may be arranged in a row. The interconnect element 2 may be arranged side by side with the first memory controller element 1 and the second memory controller element 1'. The first memory controller element 1 and the second memory controller element 1' may be disposed on different sides of the interconnect element 2.

[0198] The solder material 18 of the first memory controller element 1 can be embedded in the adhesive layer 82 (or release layer), and the bottom surface 12 of the first memory controller element 1 can contact the top surface of the adhesive layer 82 (or release layer). Similarly, the solder material 28 of the interconnect element 2 can be embedded in the adhesive layer 82 (or release layer), and the bottom surface 22 of the interconnect element 2 can contact the top surface of the adhesive layer 82 (or release layer). Likewise, the solder material 18 of the second memory controller element 1' can be embedded in the adhesive layer 82 (or release layer), and the bottom surface 12 of the second memory controller element 1' can contact the top surface of the adhesive layer 82 (or release layer).

[0199] Reference Figure 6A and Figure 6B An encapsulant 84 may be formed or disposed on the adhesive layer 82 (or release layer) of the carrier 80 to encapsulate the first memory controller element 1, the interconnect element 2, and the second memory controller element 1'. Figure 6A This is an example Figure 6B A top view. Or, Figure 6B It can be an example along Figure 6A Sectional view along section line III-III.

[0200] The encapsulant 84 may be a molding compound with or without fillers. The encapsulant 84 may have a top surface 841 and a bottom surface 842 opposite to the top surface 841. The top surface 11 and bottom surface 12 of the first memory controller element 1 are substantially aligned with the top surface 841 and bottom surface 842 of the encapsulant 84, respectively. The top surface 21 and bottom surface 22 of the interconnect element 2 are substantially aligned with the top surface 841 and bottom surface 842 of the encapsulant 84, respectively. The top surface and bottom surface of the second memory controller element 1' are substantially aligned with the top surface 841 and bottom surface 842 of the encapsulant 84, respectively.

[0201] Simultaneously, a molded structure 8 may be provided or formed. The molded structure 8 may include a first memory controller element 1, a second memory controller element 1', an interconnect element 2, and an encapsulant 84. The first memory controller element 1, the second memory controller element 1', and the interconnect element 2 are arranged side by side. The encapsulant 84 encapsulates the first memory controller element 1, the second memory controller element 1', and the interconnect element 2.

[0202] Reference Figure 7A , Figure 7B , Figure 7C , Figure 8 and Figure 9 It can provide logic element 3, first volatile memory element 4, first non-volatile memory element 5, second volatile memory element 4' and second non-volatile memory element 5'. Figure 7A This is an example Figure 7B and Figure 7C A top view. Or, Figure 7B It can be an example along Figure 7A Sectional view along the center section IV-IV. Figure 7C Then, an example is shown along... Figure 7A A cross-sectional view with the center section line VV. Figure 8 This is a sectional view illustrating logic element 3, which represents some examples of this disclosure. Figure 9 This is a cross-sectional view illustrating a first volatile memory element 4, representing some examples of this disclosure.

[0203] The function and size of logic element 3 may differ from the function and size of the first volatile memory element 4, the first non-volatile memory element 5, the second volatile memory element 4', and the second non-volatile memory element 5'.

[0204] The function and size of the first volatile memory element 4 can be the same as those of the second volatile memory element 4'. The function and size of the first non-volatile memory element 5 can be the same as those of the second non-volatile memory element 5'.

[0205] In some embodiments, the logic element 3 may be configured to process data or signals and may also be referred to as a "logic die," "logic chip," "logic semiconductor die," or "logic semiconductor wafer." In some embodiments, the logic element 3 may be an application processor (AP) die, a central processing unit (CPU) die, a graphics processing unit (GPU), an application-specific integrated circuit (ASIC) die, a microcontroller unit (MCU) die, or an input / output (IO) die.

[0206] The first volatile memory element 4 and the second volatile memory element 4' can be configured to store data, and the stored data may be lost when the power is cut off. The first volatile memory element 4 may also be referred to as a "first volatile memory die", "first volatile memory chip", "first volatile memory semiconductor die", and "first volatile memory semiconductor chip". The second volatile memory element 4' may also be referred to as a "second volatile memory die", "second volatile memory chip", "second volatile memory semiconductor die", and "second volatile memory semiconductor chip".

[0207] The first non-volatile memory element 5 and the second non-volatile memory element 5' can be configured to store data, and the stored data can be retained (e.g., preserved) when the power supply is cut off. The first non-volatile memory element 5 may also be referred to as a "first non-volatile memory die", "first non-volatile memory chip", "first non-volatile memory semiconductor die", and "first non-volatile memory semiconductor chip". The second non-volatile memory element 5' may also be referred to as a "second non-volatile memory die", "second non-volatile memory chip", "second non-volatile memory semiconductor die", and "second non-volatile memory semiconductor chip".

[0208] Reference Figure 8The logic element 3 may have a first surface 31 (e.g., a top surface or a back surface), a second surface 32 (e.g., a bottom surface or an active surface), and a side surface 33. The second surface 32 (e.g., the bottom surface) may be opposite to the first surface 31 (e.g., the top surface). The side surface 33 may extend between the first surface 31 (e.g., the top surface) and the second surface 32 (e.g., the bottom surface).

[0209] The logic element 3 may include a main part 30 and a circuit structure 35. The material of the main part 30 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InA), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0210] Circuit structure 35 may be configured on main portion 30. Circuit structure 35 may include dielectric structure 35a (including multiple dielectric layers), at least one circuit layer 35b (including fourth circuit 351, fifth circuit 352, sixth circuit 356, seventh circuit 353, and eighth circuit 354), multiple inner pads 35c, multiple inner vias 35d, multiple first bonding pads 36, multiple second bonding pads 37, and multiple third bonding pads 38. Circuit layer 35b, inner pads 35c, inner vias 35d, first bonding pads 36, second bonding pads 37, and third bonding pads 38 are embedded in dielectric structure 35a. The bottom surfaces of the first bonding pads 36, second bonding pads 37, and third bonding pads 38 may be exposed from the second surface 32 of logic element 3. Each of the first bonding pads 36, second bonding pads 37, and third bonding pads 38 may be a hybrid bonding (HB) pad and may include copper or aluminum. Each of the first bonding pad 36, the second bonding pad 37, and the third bonding pad 38 may be a solder bonding pad.

[0211] Circuit layer 35b can be horizontally connected to inner pad 35c. Internal via 35d can vertically connect inner pad 35c to first bonding pad 36, second bonding pad 37, and third bonding pad 38. For example, first bonding pad 36 can correspond to fifth circuit 352. Second bonding pad 37 can correspond to sixth circuit 356. Third bonding pad 38 can correspond to eighth circuit 354. In some embodiments, fourth circuit 351, fifth circuit 352, sixth circuit 356, seventh circuit 353, and eighth circuit 354 of logic element 3 can be horizontally non-electrically connected to each other.

[0212] Reference Figure 9The first volatile memory element 4 may be, for example, a high bandwidth memory (HBM). In some embodiments, the first volatile memory element 4 may include a first semiconductor wafer 41, a second semiconductor wafer 42, a third semiconductor wafer 43, a fourth semiconductor wafer 44, a base semiconductor wafer 45, and an encapsulant 46.

[0213] The first semiconductor wafer 41 may have a bottom surface 411 (e.g., a first surface), a top surface 412 (e.g., a second surface), and a side surface 413 extending between the bottom surface 411 and the top surface 412. The first semiconductor wafer 41 may include a first substrate portion 410, a first wafer conductive structure 414, a first lower structure 415, a first upper structure 416, and a plurality of first conductive vias 417. The first semiconductor wafer 41 may be a memory wafer, such as a dynamic random-access memory (DRAM) wafer, a static random-access memory (SRAM) wafer, and / or resistive random-access memory (RRAM).

[0214] The first conductive structure 414 can be disposed on the bottom surface of the first substrate portion 410. A first conductive via 417 can extend through the first substrate portion 410 and be electrically connected to the first conductive structure 414. In some embodiments, the bottom end of the first conductive via 417 can extend beyond the bottom surface of the first substrate portion 410 and can extend to the first conductive structure 414. Therefore, the first conductive via 417 can be an integral structure, and the length of the first conductive via 417 can be greater than the thickness of the first substrate portion 410. In some embodiments, the first conductive via 417 can extend beyond the top surface of the first substrate portion 410.

[0215] A first lower structure 415 may be disposed on a first wafer conductive structure 414. The first lower structure 415 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a first lower dielectric layer 4151 and a plurality of first lower pads 4152. The first lower dielectric layer 4151 may be a hybrid bonding (HB) dielectric layer. Each first lower pad 4152 may be a hybrid bonding (HB) pad. Each first lower pad 4152 may be a solder bonding pad. The first lower pads 4152 may be embedded in the first lower dielectric layer 4151 and may be exposed by the first lower dielectric layer 4151. The first lower pads 4152 may be surrounded by the first lower dielectric layer 4151. The first lower pads 4152 may be electrically connected to a first conductive via 417 through the first wafer conductive structure 414.

[0216] In some embodiments, the bottom surface of the first lower solder pad 4152 may be substantially aligned with the bottom surface of the first lower dielectric layer 4151. Therefore, the bottom surface of the first lower solder pad 4152 may be exposed by the bottom surface of the first lower dielectric layer 4151. In some instances, the thickness of the first lower solder pad 4152 may be substantially equal to the thickness of the first lower dielectric layer 4151.

[0217] The first upper structure 416 may be disposed on the top surface of the first base portion 410. The first upper structure 416 may be a hybrid bonding (HB) structure and may include a first upper dielectric layer 4161 and a plurality of first upper pads 4162.

[0218] The first upper dielectric layer 4161 may be a hybrid bonding (HB) dielectric layer. Each first upper pad 4162 may be a hybrid bonding (HB) pad. The first upper pad 4162 may be embedded in the first upper dielectric layer 4161 and may be exposed by the first upper dielectric layer 4161. The first upper pad 4162 may be surrounded by the first upper dielectric layer 4161. The first upper pad 4162 may be electrically connected to the first conductive via 417. In some embodiments, the first upper pad 4162 may be in direct contact with the first conductive via 417. The first upper pad 4162 may be electrically connected to the first wafer conductive structure 414 and the first lower pad 4152 via the first conductive via 417.

[0219] In some embodiments, the top surface of the first upper solder pad 4162 may be substantially aligned with the top surface of the first upper dielectric layer 4161. Therefore, the top surface of the first upper solder pad 4162 may be exposed by the top surface of the first upper dielectric layer 4161. The bottom surface of the first upper solder pad 4162 may contact the first conductive via 417. In some embodiments, the thickness of the first upper solder pad 4162 may be less than the thickness of the first upper dielectric layer 4161.

[0220] The second semiconductor wafer 42 can be stacked on the first semiconductor wafer 41 and can be electrically connected to the first semiconductor wafer 41 by hybrid bonding or metal-to-metal bonding. The structure of the second semiconductor wafer 42 can be the same as or similar to the structure of the first semiconductor wafer 41.

[0221] The third semiconductor wafer 43 may be stacked on the second semiconductor wafer 42 and may be electrically connected to the second semiconductor wafer 42 by hybrid bonding or metal-to-metal bonding. The structure of the third semiconductor wafer 43 may be the same as or similar to the structure of the first semiconductor wafer 41.

[0222] The fourth semiconductor wafer 44 may be stacked on the third semiconductor wafer 43 and may be electrically connected to the third semiconductor wafer 43 by hybrid bonding or metal-to-metal bonding. The structure of the fourth semiconductor wafer 44 may be similar to that of the first semiconductor wafer 41, except that the fourth semiconductor wafer 44 may not include the first upper structure 416 and the first conductive hole 417 of the first semiconductor wafer 41.

[0223] The base semiconductor wafer 45 (or the fifth semiconductor wafer) may have a top surface 451 (e.g., a first surface) and a bottom surface 452 (e.g., a second surface). The base semiconductor wafer 45 may include a fifth base 450, a fifth conductive structure 454, a fifth upper structure 455, a plurality of fifth conductive vias 457, and a fifth lower structure 456. The base semiconductor wafer 45 may be a controller wafer, such as an application processor (AP) wafer.

[0224] A fifth conductive structure 454 may be disposed on the top surface of a fifth base 450. A fifth conductive via 457 may extend through the fifth base 450 and may be electrically connected to the fifth conductive structure 454. In some embodiments, one end of the fifth conductive via 457 may extend into the fifth conductive structure 454.

[0225] The fifth upper structure 455 can be disposed on the fifth conductive structure 454. The fifth upper structure 455 can be a hybrid bond (HB) structure or a solder bond structure, and can include a fifth upper dielectric layer 4551 and a plurality of fifth upper pads 4552. The fifth upper dielectric layer 4551 can be a hybrid bond (HB) dielectric layer. Each fifth upper pad 4552 can be a hybrid bond (HB) pad. The fifth upper pads 4552 can be embedded in the fifth upper dielectric layer 4551 and can be exposed by the fifth upper dielectric layer 4551.

[0226] A fifth lower structure 456 may be disposed on the bottom surface of the fifth base 450. The fifth lower structure 456 may be a hybrid bond (HB) structure or a solder bond structure, and may include a fifth lower dielectric layer 4561 and a plurality of fifth lower pads 4562. The fifth lower dielectric layer 4561 may be a hybrid bond (HB) dielectric layer. Each fifth lower pad 4562 may be a hybrid bond (HB) pad. The fifth lower pads 4562 may be embedded in the fifth lower dielectric layer 4561 and may be exposed by the fifth lower dielectric layer 4561.

[0227] The first lower pad 4152 of the first lower structure 415 of the first semiconductor wafer 41 can be bonded and electrically connected to the fifth upper pad 4552 of the fifth upper structure 455 of the substrate semiconductor wafer 45 by hybrid bonding.

[0228] The encapsulant 46 may be a molding compound with or without fillers. The encapsulant 46 may encapsulate the top surface 451 of the first semiconductor wafer 41, the second semiconductor wafer 42, the third semiconductor wafer 43, the fourth semiconductor wafer 44, and the base semiconductor wafer 45. The encapsulant 46 may cover the side surfaces 413 of the first semiconductor wafer 41, the side surfaces of the second semiconductor wafer 42, the third semiconductor wafer 43, the fourth semiconductor wafer 44, and the top surface 451 of the base semiconductor wafer 45.

[0229] Reference Figure 7C The first non-volatile memory element 5 may be a read-only memory (ROM), flash memory, and / or non-volatile random access memory (NVRAM). In some instances, the first non-volatile memory element 5 may include a first chip 51 and a second chip 52 stacked on the first chip 51.

[0230] Please refer to Figure 1 and Figure 10 In step S902, logic element 3 can be electrically connected and coupled to the first memory controller element 1, the second memory controller element 1', and the interconnect element 2. Furthermore, in step S903, the first volatile memory element 4 and the first non-volatile memory element 5 can be electrically connected and coupled to the first memory controller element 1. Additionally, the second volatile memory element 4' and the second non-volatile memory element 5' can be electrically connected and coupled to the second memory controller element 1'.

[0231] Reference Figure 11A , Figure 11B , Figure 11C and Figure 11D The carrier 80 and the adhesive layer 82 can be removed from the molded structure 8 to form the encapsulation structure 6. Figure 11A This is an example Figure 11B , Figure 11C and Figure 11D A top view. Or, Figure 11B It can be an example along Figure 11A Sectional view along the center section line VI-VI. Figure 11C It can be an example along Figure 11A Sectional view along section line VII-VII. Figure 11D Then we can exemplify along Figure 11A Sectional view along the central section line VIII-VIII.

[0232] Logic element 3 can be disposed on and electrically connected to interconnect element 2, first memory controller element 1, and second memory controller element 1'. First non-volatile memory element 5 can be disposed above and electrically connected to the first memory controller element 1. First volatile memory element 4 can be disposed side-by-side with first non-volatile memory element 5, and can be disposed above and electrically connected to the first memory controller element 1. Second non-volatile memory element 5' can be disposed above and electrically connected to the second memory controller element 1'. Second volatile memory element 4' can be disposed side-by-side with second non-volatile memory element 5', and can be disposed above and electrically connected to the second memory controller element 1'.

[0233] Interconnect element 2 can be fully disposed within the vertical projection of logic element 3. The vertical direction can be defined as a direction substantially perpendicular to the top surface 21 of interconnect element 2 or the top surface 11 of the first memory controller element 1. The sixth circuit 356 of logic element 3 can be fully disposed within the vertical projection of interconnect element 2. The sixth circuit 356 of logic element 3 can be electrically connected to the conductive structure 24 of interconnect element 2 via a hybrid bonding. Therefore, the second bonding pad 37 corresponding to the sixth circuit 356 of logic element 3 can be bonded to or attached to the upper pad 252 of the upper structure 25 of interconnect element 2 via a metal-to-metal bonding manner. Figure 4 The dielectric structure 35a of the circuit structure 35 of logic element 3 can be directly attached to or directly contact the upper dielectric layer 251 of the upper structure 25 of interconnecting element 2. Figure 4 ).

[0234] Reference Figure 11B In some embodiments, the fifth circuit 352 of logic element 3 may overlap vertically and be electrically connected to the third circuit 143 of the first memory controller element 1. Logic element 3 may be electrically connected to the first memory controller element 1 via hybrid bonding. Therefore, the first bonding pad 36 corresponding to the fifth circuit 352 of logic element 3 may be bonded to or connected to the first upper pad 152 of the first upper structure 15 of the first memory controller element 1 corresponding to the third circuit 143 via a metal-to-metal bonding manner. Figure 3 The dielectric structure 35a of the circuit structure 35 of the logic element 3 can be directly attached to or directly contact the first upper dielectric layer 151 of the first upper structure 15 of the first memory controller element 1.

[0235] Similarly, the eighth circuit 354 of logic element 3 can overlap in the vertical direction and be electrically connected to the third circuit 143 of the second memory controller element 1'. Logic element 3 can be electrically connected to the second memory controller element 1' via a hybrid bonding. Therefore, the third bonding pad 38 corresponding to the eighth circuit 354 of logic element 3 can be bonded to or connected to the upper pad of the second memory controller element 1' corresponding to the third circuit 143 of the second memory controller element 1' via a metal-to-metal bonding method. The dielectric structure 35a of the circuit structure 35 of logic element 3 can be directly connected to or directly contact the upper layer of an upper structure of the second memory controller element 1'.

[0236] Reference Figure 11A In some embodiments, the fourth circuit 351 of logic element 3 may overlap vertically and be electrically connected to the second circuit 142 of the first memory controller element 1. Similarly, the seventh circuit 353 of logic element 3 may overlap vertically and be electrically connected to the second circuit 142 of the second memory controller element 1'. Logic element 3 may overlap the first memory controller element 1 and the second memory controller element 1' vertically.

[0237] Logic element 3, first non-volatile memory element 5, first volatile memory element 4, second non-volatile memory element 5', and second volatile memory element 4' are arranged side by side. The first non-volatile memory element 5 can be disposed above the molding structure 8 and can be electrically connected to the fourth circuit 351 of the logic element 3 via the second circuit 142 of the first memory controller element 1. The first volatile memory element 4 can be disposed on the molding structure 8 and can be electrically connected to the fifth circuit 352 of the logic element 3 via the third circuit 143 of the first memory controller element 1. Figure 11D As shown, the first volatile memory element 4 can be electrically connected to the first non-volatile memory element 5 via the first circuit 141 of the first memory controller element 1.

[0238] Reference Figure 11A The first non-volatile memory element 5 and the first volatile memory element 4 can be completely disposed within the projection of the first memory controller element 1 in the vertical direction. For example... Figure 11D As shown, the first non-volatile memory element 5 and the first volatile memory element 4 can overlap with the first circuit 141 of the first memory controller element 1 in the vertical direction. Both the first non-volatile memory element 5 and the first volatile memory element 4 are electrically connected to the first memory controller element 1 via a hybrid bonding process. For example, the fifth lower pad 4562 of the first volatile memory element 4 can be bonded to or attached to the first upper pad 152 of the first upper structure 15 of the first memory controller element 1 via a metal-to-metal bonding process. Figure 3 The fifth lower dielectric layer 4561 of the first volatile memory element 4 may be directly attached to or directly contact the first upper dielectric layer 151 of the first upper structure 15 of the first memory controller element 1.

[0239] The second non-volatile memory element 5' and the second volatile memory element 4' can be completely disposed within the vertical projection of the second memory controller element 1'. Both the second non-volatile memory element 5' and the second volatile memory element 4' can overlap with the first circuit 141 of the second memory controller element 1' in the vertical direction. Both the second non-volatile memory element 5' and the second volatile memory element 4' are electrically connected to the second memory controller element 1' via a hybrid connection.

[0240] Reference Figure 11A and Figure 11B The gap G1 between logic element 3 and the first non-volatile memory element 5 may overlap with the second circuit 142 of the first memory controller element 1 in the vertical direction. The gap G2 between logic element 3 and the first volatile memory element 4 may overlap with the third circuit 143 of the first memory controller element 1 in the vertical direction. The gap G3 between the first memory controller element 1 and the interconnect element 2 may overlap with the logic element 3 in the vertical direction.

[0241] Reference Figure 12A , Figure 12B and Figure 12C The encapsulation structure 6 can be attached to the substrate 70 and electrically connected to the substrate 70 via welding materials 18 and 28 to form the assembly structure 7. Figure 12A This is an example Figure 12B and Figure 12C A top view. Or, Figure 12B It can be an example along Figure 12A A cross-sectional view along the center section line IX-IX. Figure 12C It can be an example along Figure 12A A sectional view with the center section line XX.

[0242] The substrate 70 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate 70 may include a semiconductor-insulator substrate, such as a silicon-insulator (SOI) substrate, a silicon-germanium-insulator (SGOI) substrate, or a germanium-insulator (GOI) substrate. In some embodiments, the substrate 70 may include organic materials, glass, ceramic materials, or similar materials. For example, the substrate 70 may be made of a cured photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including a photoguide. For example, the substrate 70 may include a homogeneous material. For example, the material of the substrate 70 may include epoxy FR5, FR4, BT resin substrate (Bismaleimide triazine, BT), printed circuit board (PCB) material, prepreg (PP), Ajinomoto build-up film (ABF) or other suitable materials.

[0243] In assembly structure 7, molding structure 8 can be disposed on and electrically connected to substrate 70. Therefore, interconnect element 2 can be disposed on and electrically connected to substrate 70. First memory controller element 1 can be disposed on and electrically connected to substrate 70. Second memory controller element 1' can be disposed on and electrically connected to substrate 70.

[0244] Then, a plurality of external connectors 72 may be configured on the bottom surface of the substrate 70 to provide electrical connections to the substrate 70, such as I / O connections. Each of the external connectors 72 may include reflowable soldering material, such as solder balls or solder including AgSn.

[0245] Figure 12A , Figure 12B and Figure 12C Assembly structures 7 are illustrated in some embodiments of this disclosure. Figure 12A This is an example Figure 12B and Figure 12C Top view. Figure 12B It is along Figure 12A A cross-sectional view along the center section line IX-IX. Figure 12C This is an example along Figure 12A Sectional view with center section line XX.

[0246] Assembly structure 7 may include a substrate 70 and a package structure 6 disposed above and electrically connected to the substrate 70. Package structure 6 may include a molded structure 8, logic element 3, a first non-volatile memory element 5, a first volatile memory element 4, a second non-volatile memory element 5', and a second volatile memory element 4'. Molded structure 8 may include a first memory controller element 1, an interconnect element 2, a second memory controller element 1', and a package agent 84 encapsulating the first memory controller element 1, the interconnect element 2, and the second memory controller element 1'.

[0247] The logic element 3 can be electrically connected to and coupled to the first memory controller element 1, the second memory controller element 1', and the interconnect element 2.

[0248] The first non-volatile memory element 5 and the first volatile memory element 4 can be completely disposed within the vertical projection of the first memory controller element 1. Both the first non-volatile memory element 5 and the first volatile memory element 4 are electrically connected to the first memory controller element 1.

[0249] The second non-volatile memory element 5' and the second volatile memory element 4' can be completely disposed within the projection of the second memory controller element 1' in the vertical direction. The second non-volatile memory element 5' and the second volatile memory element 4' are both electrically connected to the second memory controller element 1'.

[0250] exist Figure 12A , Figure 12B and Figure 12C In the illustrated embodiments, heterogeneous electronic components (e.g., semiconductor wafers or semiconductor dies) can be integrated into the assembly structure 7 and the package structure 6 without the need for a redistribution structure or interposer. For example, the first non-volatile memory element 5 and the first volatile memory element 4 can communicate with each other via the first circuit 141 of the first memory controller element 1. The first non-volatile memory element 5 and the logic element 3 can communicate with each other via the second circuit 142 of the first memory controller element 1. The first volatile memory element 4 and the logic element 3 can communicate with each other via the third circuit 143 of the first memory controller element 1.

[0251] Furthermore, logic element 3 can communicate directly with substrate 70 via interconnect element 2. First volatile memory element 4 and first non-volatile memory element 5 can communicate directly with substrate 70 via first memory controller element 1. Second volatile memory element 4' and second non-volatile memory element 5' can communicate directly with substrate 70 via second memory controller element 1'.

[0252] Therefore, the assembly structure 7 and the packaging structure 6 can meet a variety of required functions. This increases design flexibility and reduces manufacturing costs.

[0253] Figure 13 This is a cross-sectional view illustrating an assembly structure 7a according to some embodiments of the present disclosure. Apart from the structure of the encapsulation structure 6a, the assembly structure 7a can be similar to... Figure 12B Assembly structure 7. In package structure 6a, logic element 3 is electrically connected to interconnect element 2, first memory controller element 1, and second memory controller element 1' via multiple solder materials 76. First non-volatile memory element 5 and first volatile memory element 4 are both electrically connected to first memory controller element 1 via multiple solder materials 74. Second non-volatile memory element 5' and second volatile memory element 4' are both electrically connected to second memory controller element 1' via multiple solder materials 74. Solder materials 74, 76 may include reflowable soldering materials such as AgSn.

[0254] One embodiment of this disclosure provides a packaging structure including a molding structure, a logic element, a non-volatile memory element, and a volatile memory element. The molding structure includes a memory controller element, an interconnect element, and an encapsulant. The memory controller element includes a first conductive structure, and the first conductive structure includes a first circuit, a second circuit, and a third circuit. The interconnect element is arranged side-by-side with the memory controller element and includes a second conductive structure. The encapsulant encapsulates the memory controller element and the interconnect element. The logic element is disposed on the molding structure and includes a circuit structure, and the circuit structure includes a fourth circuit, a fifth circuit, and a sixth circuit. The sixth circuit of the logic element is electrically connected to the second conductive structure of the interconnect element. The non-volatile memory element is disposed on the molding structure and is electrically connected to the fourth circuit of the logic element through the second circuit of the memory controller element. The volatile memory element is disposed on the molding structure and is electrically connected to the fifth circuit of the logic element through the third circuit of the memory controller element. The volatile memory element is electrically connected to the non-volatile memory element through the first circuit of the memory controller element.

[0255] Another aspect of this disclosure provides an assembly structure including a substrate, an interconnect element, a first memory controller element, a second memory controller element, a logic element, a first non-volatile memory element, a first volatile memory element, a second non-volatile memory element, and a second volatile memory element. The interconnect element is disposed on and electrically connected to the substrate. The first memory controller element is disposed above and electrically connected to the substrate. The second memory controller element is disposed above and electrically connected to the substrate, wherein the first memory controller element and the second memory controller element are disposed on different sides of the interconnect element. The logic element is disposed above the interconnect element, the first memory controller element, and the second memory controller element, and is electrically connected to the first memory controller element. The first non-volatile memory element is disposed above and electrically connected to the first memory controller element. The first volatile memory element is arranged side-by-side with the first non-volatile memory element, and is disposed above and electrically connected to the first memory controller element. The second non-volatile memory element is disposed above the second memory controller element and is electrically connected to the second memory controller element. The second volatile memory element is disposed side by side with the second non-volatile memory element, and is disposed above the second memory controller element and is electrically connected to the second memory controller element.

[0256] Another aspect of this disclosure provides a method of fabrication. The method includes: providing a molded structure comprising a first memory controller element, an interconnect element disposed side-by-side with the first memory controller element, and an encapsulant for encapsulating the first memory controller element and the interconnect element; electrically connecting a logic element to the first memory controller element and the interconnect element; and electrically connecting a first non-volatile memory element and a first volatile memory element to the first memory controller element.

[0257] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and other processes, or combinations thereof, can be substituted for many of the processes described above.

[0258] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A packaging structure, comprising: A molded structure comprising: A memory controller element includes a first conductive structure, and the first conductive structure includes a first circuit, a second circuit and a third circuit; An interconnect element, arranged side-by-side with the memory controller element, includes a second conductive structure; and An encapsulant for encapsulating the memory controller element and the interconnect element; A logic element is disposed on the molded structure and includes a circuit structure, wherein the circuit structure includes a fourth circuit, a fifth circuit and a sixth circuit, wherein the sixth circuit of the logic element is electrically connected to the second conductive structure of the interconnecting element. A non-volatile memory element is disposed on the molded structure and electrically connected to the fourth circuit of the logic element via the second circuit of the memory controller element; and A volatile memory element is disposed on the molded structure and electrically connected to the fifth circuit of the logic element through the third circuit of the memory controller element, wherein the volatile memory element is electrically connected to the non-volatile memory element through the first circuit of the memory controller element.

2. The packaging structure as claimed in claim 1, wherein a top surface and a bottom surface of the memory controller element are substantially aligned with a top surface and a bottom surface of the encapsulant, respectively.

3. The packaging structure as claimed in claim 1, wherein a top surface and a bottom surface of the interconnecting element are substantially aligned with a top surface and a bottom surface of the encapsulant, respectively.

4. The packaging structure of claim 1, wherein the interconnect element is entirely disposed within a projection of the logic element in a vertical direction.

5. The packaging structure of claim 4, wherein the sixth circuit of the logic element is entirely disposed within a projection of the interconnect element along the vertical direction.

6. The packaging structure of claim 1, wherein the fourth circuit of the logic element overlaps the second circuit of the memory controller element in a vertical direction.

7. The packaging structure of claim 1, wherein the fifth circuit of the logic element overlaps with the third circuit of the memory controller element in a vertical direction.

8. The packaging structure of claim 1, wherein the logic element, the non-volatile memory element, and the volatile memory element are arranged side by side.

9. The packaging structure of claim 1, wherein the non-volatile memory element and the volatile memory element are completely disposed within a projection of the memory controller element along a vertical direction.

10. The packaging structure of claim 1, wherein both the non-volatile memory element and the volatile memory element overlap with the first circuitry of the memory controller element in a vertical direction.

11. The packaging structure of claim 1, wherein the logic element is electrically connected to the interconnect element via hybrid bonding, and the logic element is electrically connected to the memory controller element via hybrid bonding.

12. The packaging structure of claim 1, wherein both the non-volatile memory element and the volatile memory element are electrically connected to the memory controller element via hybrid bonding.

13. The packaging structure of claim 1, wherein the logic element is electrically connected to the interconnect element via a plurality of solder materials, and the logic element is electrically connected to the memory controller element via the plurality of solder materials.

14. The packaging structure of claim 11, wherein both the non-volatile memory element and the volatile memory element are electrically connected to the memory controller element via a plurality of solder materials.

15. The packaging structure of claim 8, wherein a gap between the logic element and the non-volatile memory element overlaps with the second circuitry of the memory controller element in a vertical direction.

16. The packaging structure of claim 1, wherein a gap between the logic element and the volatile memory element overlaps with the third circuitry of the memory controller element in a vertical direction.

17. The packaging structure of claim 1, wherein a gap between the memory controller element and the interconnect element overlaps with the logic element in a vertical direction.

18. The packaging structure of claim 1, wherein the first circuit, the second circuit, and the third circuit of the memory controller element are not electrically connected to each other in a horizontal direction.

19. The packaging structure of claim 1, wherein the fourth circuit, the fifth circuit, and the sixth circuit of the logic element are not electrically connected to each other in a horizontal direction.

20. The packaging structure of claim 1, wherein the memory controller element comprises a memory controller semiconductor die or a memory controller semiconductor wafer, the interconnect element comprises an interconnect semiconductor die or an interconnect semiconductor wafer, and the encapsulant comprises a molding compound.

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