Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an oxide semiconductor layer including a plurality of metals, in which a content of indium (In) is less than 50 at% and a content of zinc (Zn) is 0 at% with respect to the plurality of metals, a gate electrode separated from the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, and a first electrode and a second electrode. The first electrode and the second electrode are on the oxide semiconductor layer and are separated from each other with the gate electrode interposed therebetween.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices including oxide semiconductors and methods for manufacturing such semiconductor devices. Background Technology

[0002] Transistors are semiconductor devices that perform electrical switching functions and are used in various integrated circuit (IC) devices, including memory, driver ICs, and logic devices. To improve the integration density of IC devices and reduce the space occupied by transistors included in the IC devices, research is underway to reduce transistor size while maintaining transistor performance.

[0003] Oxide-semiconductor (OSB) devices, characterized by wide bandgap of 3.0 eV or greater, have been studied for many years. OSB devices used in large-area display driver devices possess excellent characteristics such as low cutoff current and high on / off ratio. Research has been conducted to utilize OSB devices with these advantages as memory or logic devices.

[0004] When oxide semiconductor devices are used as memory or logic devices, they need to operate stably under the heat applied during the line back-end (e.g., at 500°C). Summary of the Invention

[0005] A semiconductor device with improved thermal stability and / or a method for manufacturing the semiconductor device are provided.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the exemplary embodiments presented in this disclosure.

[0007] According to an exemplary embodiment of this disclosure, a semiconductor device includes: an oxide semiconductor layer comprising a plurality of metals, wherein the content of indium (In) is less than 50 at% and the content of zinc (Zn) is 0 at% relative to the plurality of metals; a gate electrode separated from the oxide semiconductor layer; a gate insulating layer located between the oxide semiconductor layer and the gate electrode; and a first electrode and a second electrode on the oxide semiconductor layer and spaced apart from each other, wherein the gate electrode is inserted between the first electrode and the second electrode.

[0008] The oxide semiconductor layer may further include at least one of gallium (Ga), tin (Sn), cadmium (Cd), aluminum (Al), germanium (Ge) and hafnium (Hf).

[0009] The content of indium (In) relative to the various metals may be 10 at% or more.

[0010] The oxide semiconductor layer may further include gallium (Ga), and the content of gallium (Ga) may be greater than the content of indium (In).

[0011] The oxide semiconductor layer may consist of only InGaO, and the gallium (Ga) content may be 50 at% or more.

[0012] The oxide semiconductor layer can maintain an amorphous phase at temperatures ranging from approximately 450°C to approximately 700°C.

[0013] The first electrode, the oxide semiconductor layer, and the second electrode can be arranged sequentially in a direction perpendicular to the surface of the first electrode.

[0014] In a cross-sectional view perpendicular to the surface of the first electrode, the oxide semiconductor layer may include a first region extending in a direction parallel to the surface of the first electrode and a second region extending from the first electrode toward the second electrode.

[0015] The semiconductor device may further include: a capacitor electrically connected to an oxide semiconductor layer, wherein the first electrode may be a bit line component and the gate electrode may be a word line component.

[0016] The semiconductor device may further include: a metal nitride layer located between the oxide semiconductor layer and at least one of the first electrode and the second electrode; and an oxide layer located between the metal nitride layer and the oxide semiconductor layer, wherein the oxide layer is an indium (In) based oxide layer.

[0017] The metal nitride layer can be in direct contact with at least one of the first and second electrodes.

[0018] The oxide layer can be in direct contact with at least one of the oxide semiconductor layer and the metal nitride layer.

[0019] The oxide layer may include indium (In), and the content of indium (In) relative to the various metals included in the oxide layer may be 50 at% or more.

[0020] The metal nitride layer may include a metal different from the first metal included in the first electrode, the second metal included in the second electrode, and the various metals included in the oxide semiconductor layer.

[0021] The metal nitride layer may include at least one of titanium (Ti), molybdenum (Mo), niobium (Nb), and tantalum (Ta).

[0022] The thickness of the oxide layer can be 5 nm or less.

[0023] The thickness of the metal nitride layer can be 10 nm or less.

[0024] The metal nitride layer may include a first metal nitride layer disposed between the first electrode and the oxide semiconductor layer and a second metal nitride layer disposed between the second electrode and the oxide semiconductor layer. The oxide layer may include a first oxide layer disposed between the first metal nitride layer and the oxide semiconductor layer and a second oxide layer disposed between the second metal nitride layer and the oxide semiconductor layer.

[0025] According to an exemplary embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a first insulating layer on a first electrode, the first insulating layer including an opening exposing the first electrode; sequentially forming a first metal nitride layer and a first oxide layer on the first electrode exposed through the opening; forming an oxide semiconductor layer on the first oxide layer and the first insulating layer, the oxide semiconductor layer including a plurality of metals, wherein, relative to the plurality of metals, the content of indium (In) is less than 50 at% and the content of zinc (Zn) is 0 at%; sequentially forming a gate insulating layer and a gate electrode on a first surface of the oxide semiconductor layer; and forming a second electrode on a second surface of the oxide semiconductor layer that is different from the first surface of the oxide semiconductor layer.

[0026] Forming a gate insulating layer and a gate electrode may include: etching the gate insulating layer and the gate electrode in a direction toward the upper portion of the first insulating layer to expose the surface of the oxide semiconductor layer, such that the gate insulating layer is divided into a first gate insulating layer and a second gate insulating layer and the gate electrode is divided into a first gate electrode and a second gate electrode, the second surface of the oxide semiconductor layer being parallel to the upper surface of the first electrode; and partially etching the first gate electrode and the second gate electrode such that the height of the upper surface of the first gate electrode and the gate electrode from the first electrode is lower than the height of the upper surface of the first gate insulating layer and the second gate insulating layer from the first electrode, respectively.

[0027] Forming the second electrode may include: forming a second oxide layer on a second surface of the oxide semiconductor layer; forming a second metal nitride layer on the second oxide layer; and forming the second electrode on the second metal nitride layer. Attached Figure Description

[0028] The above and other aspects, features and advantages of certain exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0029] Figure 1 This is a diagram of a semiconductor device according to an example embodiment;

[0030] Figure 2 This is a diagram of a semiconductor device that further includes a metal nitride layer between an oxide semiconductor layer and a metal layer;

[0031] Figure 3AThe graph shows the IV characteristics of a transistor used as a comparative example, which includes a channel layer formed of indium gallium zinc oxide (IGZO) and electrodes formed of W, after heat treatment at 300°C.

[0032] Figure 3B The graph shows the IV characteristics of a transistor, which serves as a comparative example, after being heat-treated at 500°C, including a channel layer formed of IGZO and electrodes formed of W.

[0033] Figure 4 The graph shows the IV characteristics of a transistor used as a comparative example, which includes a channel layer formed of indium gallium oxide (IGO) (In content of 57 at%) and electrodes formed of W, after heat treatment (ANL) at 500°C.

[0034] Figure 5 A graph is shown, illustrating the IV characteristics of a transistor, as an example embodiment 1, after heat treatment at 500°C, including a channel layer formed of IGO (In content of 34 at%) and an electrode formed of W.

[0035] Figure 6 A graph is shown, illustrating the IV characteristics of a transistor, as an example embodiment 2, after heat treatment at 500°C, including a channel layer formed of IGO (In content of 34 at%), an electrode formed of W, and a layer formed of InO and a layer formed of TiN between the channel layer and the electrode.

[0036] Figure 7 This is a diagram of a semiconductor device according to an example embodiment;

[0037] Figure 8 This is a diagram of a semiconductor device according to another example embodiment;

[0038] Figure 9 This is a diagram of a semiconductor device according to another example embodiment;

[0039] Figure 10 This is a diagram of a semiconductor device according to another example embodiment;

[0040] Figure 11 This is a diagram of a semiconductor device according to another example embodiment;

[0041] Figure 12 This is a flowchart of a method for manufacturing a semiconductor device according to an example embodiment;

[0042] Figures 13 to 20 The manufacturing process is shown sequentially. Figure 10 A cross-sectional view of a method for developing semiconductor devices;

[0043] Figure 21 This is a perspective view illustrating an example of a schematic structure of a vertically stacked memory device according to an exemplary embodiment;

[0044] Figure 22 This is a perspective view illustrating an example of a schematic structure of a vertically stacked storage device according to another exemplary embodiment;

[0045] Figure 23 This is a block diagram illustrating an electronic system according to an example embodiment; and

[0046] Figure 24 This is a block diagram illustrating an electronic system according to an example embodiment. Detailed Implementation

[0047] Reference will now be made in detail to some exemplary embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the exemplary embodiments presented may take different forms and should not be construed as limited to the description set forth herein. Therefore, the exemplary embodiments presented are described below only by reference to the accompanying drawings to illustrate various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…”, when preceding a column of elements, modify the entire column of elements without modifying any individual elements within that column.

[0048] In the following, semiconductor devices including multilayer structures according to various exemplary embodiments are described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and the dimensions of parts in the drawings may be exaggerated for clarity and ease of explanation.

[0049] A singular expression may encompass a plural expression unless it has a distinctly different meaning in the context. When a part “includes” a component, it may further include another component, rather than excluding the presence of that other component, unless otherwise stated. The dimensions or thicknesses of components in the figures may be arbitrarily exaggerated for ease of illustration. Additionally, when a material layer is described as being disposed on a substrate or another layer, that material layer may be in contact with that other layer, or a third layer may exist between that material layer and that other layer. In the example embodiments presented, the materials constituting each layer are provided by way of example only, and other materials may also be used.

[0050] Furthermore, the terms "department" and "module" refer to a unit that processes at least one function or operation, and can be implemented by hardware, software, or a combination thereof.

[0051] The specific embodiments shown and described herein are illustrative examples of some exemplary embodiments and are not intended to limit the scope of the exemplary embodiments in any way. For the sake of brevity, conventional electronics, control systems, software development, and / or other functional aspects of the system may not be described in detail.

[0052] Furthermore, the connecting lines or connectors shown in the various accompanying figures are intended to illustrate example functional relationships and / or physical or logical connections between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual equipment.

[0053] In the context of describing the exemplary embodiments (especially in the context of the appended claims), the terms “a”, “an”, and “the”, as well as similar indicators, should be interpreted as encompassing both the singular and the plural.

[0054] Expressions such as “at least” used to list elements are intended to limit all elements in a list, rather than individual elements in the list. For example, expressions such as “at least one of A, B, and C” or “at least one of the groups consisting of A, B, and C” can be interpreted as only A, only B, only C, or a combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0055] When terms such as “about” or “substantially” are used to describe numerical values, the relevant numerical values ​​can be interpreted to include manufacturing or operational deviations (e.g., ±10%). Additionally, when expressions such as “approximately” and “substantially” are used to describe geometry, geometric precision may not be required, and the intention is to describe the degree of tolerance of the shape within the scope of embodiments of this disclosure. Furthermore, regardless of whether the numerical value of a shape is limited by the use of “about” or “substantially”, such a numerical value or shape should be understood to include manufacturing or operational deviations (e.g., ±10%).

[0056] Although the terms “same,” “equal,” or “identical” are used in the description of the example implementations, it should be understood that some imprecisions may exist. Therefore, when an element or value is referred to as being the same as another element or value, it should be understood that the element or value is the same as the other element or value within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0057] While terms such as "first" and "second" can be used to describe various components, these components are not necessarily limited to these terms. The terms above are only used to distinguish one component from another.

[0058] Unless otherwise stated, any and all examples or examples of language used herein are intended only to better illustrate the technical concepts and do not constitute a limitation on the scope of the exemplary implementations.

[0059] Figure 1 This is a diagram of semiconductor device 1 according to an example embodiment. Figure 1 The semiconductor device 1 can be a component of a transistor or a memory cell. (See reference...) Figure 1 The semiconductor device 1 may include an oxide semiconductor layer 11 and a metal layer 12 disposed on the oxide semiconductor layer 11.

[0060] The oxide semiconductor layer 11 according to the example embodiment may include various metals. The oxide semiconductor layer 11 according to the example embodiment may include oxides of Group 12, Group 13, and Group 14 metals, such as indium (In), gallium (Ga), tin (Sn), cadmium (Cd), aluminum (Al), germanium (Ge), or hafnium (Hf), and materials selected from combinations thereof. For example, the oxide semiconductor layer 11 may have a single-layer structure or a multi-layer structure. The thickness of the oxide semiconductor layer 11 may be about 10 nm or less, about 8 nm or less, or about 7 nm or less. When the semiconductor device 1 is a component of a memory cell or a transistor, the oxide semiconductor layer 11 may be a channel layer.

[0061] Because In requires a lower bond dissociation energy than oxygen, oxygen vacancies can be easily formed. Therefore, the charge carrier concentration of the oxide semiconductor layer 11 can be increased, which can facilitate the formation of electron conduction pathways via 5s orbitals. However, because In is thermally unstable, the electrical properties of the oxide semiconductor layer 11 may change with temperature when In is included in a dominant position within it. For example, when heat of approximately 400°C or higher is applied to the oxide semiconductor layer 11, In may diffuse or disperse within it, and thus the oxide semiconductor layer 11 may lose its semiconductor properties and exhibit conductor properties.

[0062] The oxide semiconductor layer 11 according to the example embodiment may contain a variety of metals including In; however, the content of In relative to the variety of metals may be less than about 50 at%, about 40 at% or less, about 35 at% or less, about 10 at% or more, or about 5 at% or more.

[0063] The oxide semiconductor layer 11 according to the exemplary embodiment may not contain zinc (Zn). Zn is a thermally unstable material. The recrystallization temperature of Zn is 50°C or lower. Zn can be recrystallized by heat of about 200°C to about 300°C, and its electrical properties will change. Since the oxide semiconductor layer 11 according to the exemplary embodiment does not contain Zn, its semiconductor properties can be maintained even when heat of about 400°C to about 500°C is applied.

[0064] Since the oxide semiconductor layer 11 does not contain thermally unstable Zn and contains a small amount of In, it may not crystallize even when heat of about 400°C or higher is applied to it, but can remain in an amorphous phase instead. Therefore, the oxide semiconductor layer 11 according to the example embodiment can have an amorphous phase and can remain in an amorphous phase even when heat of about 450°C to about 700°C or about 500°C to about 700°C is applied.

[0065] The oxide semiconductor layer 11 according to the example embodiment may contain In and Ga. The content of Ga may be greater than the content of In. The content of Ga may be about 50 at% or more. For example, the metal in the oxide semiconductor layer 11 may contain only In and Ga, and the content of Ga in In and Ga is about 50 at% or more.

[0066] The thickness of the oxide semiconductor layer 11 can be about 10 nm or less, about 8 nm or less, or about 7 nm or less.

[0067] The semiconductor device 1 according to the example embodiment may include a metal layer 12 disposed on an oxide semiconductor layer 11. The metal layer 12 may contain only metal. The metal layer 12 may contain at least one of tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sn), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg).

[0068] The thickness of the metal layer 12 can be about 20 nm or less. For example, the thickness of the metal layer 12 can be about 1 nm or more, about 3 nm or more, or about 5 nm or more, and can be about 15 nm or less, about 10 nm or less, or about 7 nm or less.

[0069] When the semiconductor device 1 is a component of a transistor, the metal layer 12 can be a source electrode or a drain electrode. When the semiconductor device 1 is a component of a memory cell, the metal layer 12 can be a local region of a bit line.

[0070] Since the oxide semiconductor layer 11 according to the exemplary embodiment does not contain Zn and contains a small amount of In, its semiconductor properties can be maintained even when heat of about 450°C to about 700°C or about 500°C to about 700°C is applied to it. Therefore, the thermal stability of the semiconductor device 1 according to the exemplary embodiment can be improved.

[0071] When the semiconductor device 1 according to the example embodiment operates as a transistor, the threshold voltage of the semiconductor device 1 can be approximately -1V to approximately +1V. Additionally, the on / off current ratio of the semiconductor device 1 can be 3E4 (i.e., 3 × 10⁻⁴). 4 (or larger.)

[0072] The semiconductor device according to the example embodiment may further include an additional layer between the oxide semiconductor layer 11 and the metal layer 12 to improve electrical properties.

[0073] Figure 2 This is a diagram illustrating a semiconductor device 2 further comprising a metal nitride layer 13 and an oxide layer 14 between an oxide semiconductor layer 11 and a metal layer 12. When compared... Figure 1 and Figure 2 hour, Figure 2 The semiconductor device 2 may further include a metal nitride layer 13 between the oxide semiconductor layer 11 and the metal layer 12. The metal nitride layer 13 may be in direct contact with the metal layer 12. Due to the strong binding force of nitrogen, the metal nitride layer 13 can reduce or prevent interdiffusion between the oxide semiconductor layer 11 and the metal layer 12.

[0074] The metal nitride layer 13 may be a conductive material and may include a metal. The metal included in the metal nitride layer 13 may be different from at least one of the metals included in the oxide semiconductor layer 11 and the metal included in the metal layer 12. For example, the metal nitride layer 13 may be a nitride including at least one of Ti, Mo, Nb, and Ta. When the metal layer 12 includes W, the metal nitride layer 13 may include TiN.

[0075] The thickness of the metal nitride layer 13 can be less than the thickness of the metal layer 12. For example, the thickness of the metal nitride layer 13 can be less than or equal to about half the thickness of the metal layer 12. The thickness of the metal nitride layer 13 can be about 10 nm or less. The thickness of the metal nitride layer 13 can be about 0.1 nm or more, about 0.3 nm or more, about 0.5 nm or more, about 0.8 nm or more, or about 1 nm or more, and can be about 8 nm or less, about 7 nm or less, about 6 nm or less, or about 5 nm or less. For example, the thickness of the metal nitride layer 13 can be from about 0.1 nm to about 10 nm.

[0076] The semiconductor device 2 according to the example embodiment may further include an oxide layer 14 disposed between the oxide semiconductor layer 11 and the metal nitride layer 13. The oxide layer 14 may be in direct contact with at least one of the metal nitride layer 13 and the oxide semiconductor layer 11.

[0077] The oxide layer 14 may comprise an oxide with a predominantly In content (e.g., an In-based oxide layer). Predominantly In content can mean that the In content is the highest relative to the metal contained in the oxide layer 14. For example, of the metal contained in the oxide layer 14, the oxide layer 14 may contain at least about 50 at% In. In some example embodiments, the oxide layer 14 may be an indium oxide containing only In.

[0078] The oxide layer 14 may further comprise metals other than In. The oxide layer 14 may contain at least one metal contained in the oxide semiconductor layer. For example, the type of metal contained in the oxide layer 14 may be the same as the type of metal contained in the oxide semiconductor layer 11. For example, in addition to In, the oxide layer 14 may also contain at least one of Ga, Sn, Cd, Al, Ge, and Hf.

[0079] The thickness of oxide layer 14 can be less than the thickness of oxide semiconductor layer 11. For example, the thickness of oxide layer 14 can be less than or equal to about half the thickness of oxide semiconductor layer 11. The thickness of oxide layer 14 can be 5 nm or less. The thickness of oxide layer 14 can be about 0.1 nm or more, about 0.5 nm or more, or about 1 nm or less, and can be about 3 nm or less, about 3.5 nm or less, about 4 nm or less, or about 5 nm or less. In some example embodiments, the thickness of oxide layer 14 can be from about 0.5 nm to about 5 nm.

[0080] The interface between oxide layer 14 and oxide semiconductor layer 11 may be unclear. For example, oxide layer 14 may be formed as part of oxide semiconductor layer 11. When forming oxide semiconductor layer 11, oxide layer 14 can be formed by increasing the In content, and oxide semiconductor layer 11 can be formed by decreasing the In content.

[0081] Figure 1 The oxide semiconductor layer 11 can be used as Figure 2 The oxide semiconductor layer 11. However, the example implementation is not limited to this. Figure 2 The oxide semiconductor layer 11 may contain at least 50 at% In and may contain Zn.

[0082] The metal nitride layer 13 can reduce or prevent material diffusion between the oxide semiconductor layer 11 and the metal layer 12, but it increases the contact resistance. However, by configuring an oxide layer 14 with a high In content, the contact resistance between the oxide semiconductor layer 11 and the metal nitride layer 13 can be improved.

[0083] Figure 3AA graph is shown illustrating the IV characteristics of a transistor used as a comparative example, comprising a channel layer formed of indium gallium zinc oxide (IGZO) and electrodes formed of W, after heat treatment at 300°C. (See reference...) Figure 3A The transistor in the comparative example will have a negative threshold voltage. In this respect, the threshold voltage can refer to the minimum voltage at which a current of 1E-10A / μm or less flows in the channel layer.

[0084] Figure 3B A graph is shown illustrating the IV characteristics of a transistor used as a comparative example, comprising a channel layer formed of IGZO and electrodes formed of W, after heat treatment at 500°C. (See reference...) Figure 3B When the transistor in the comparative example is heat-treated at 500°C, the channel layer may lose its semiconductor properties and may not be cut off.

[0085] Figure 4 A graph is shown illustrating the IV characteristics of a transistor used as a comparative example, comprising a channel layer formed of indium gallium oxide (IGO) (In content 57 at%) and electrodes formed of W, after heat treatment at 500°C. Although applied to Figure 4 The channel layer does not contain Zn, but the In content is approximately 57 at%. (Refer to...) Figure 4 When the transistor in the comparative example is heat-treated at 500°C, the channel layer may lose its semiconductor properties and may not be cut off.

[0086] Figure 5 A graph is shown illustrating the IV characteristics of a transistor, as an example embodiment 1, comprising a channel layer formed of IGO (In content 34 at%) and electrodes formed of W, after heat treatment at 500°C. Applied to... Figure 5 The channel layer does not contain Zn, and the In content is approximately 34 at%.

[0087] Reference Figure 5 Even when the transistor according to Example Embodiment 1 is heat-treated at 500°C, the threshold voltage is approximately -0.5V. In this respect, the threshold voltage can refer to the minimum voltage at which a current of 1E-10A / μm or less flows through the channel layer. The on / off current ratio is approximately 3.8E4. In this respect, the off current can be the current value at the threshold voltage, and the on current can be the current value at a voltage obtained by adding 1V to the threshold voltage. When the channel layer does not contain Zn and has an In content of less than 50 at%, the channel can operate as a transistor even after heat treatment at approximately 500°C.

[0088] Figure 6A graph is shown illustrating the IV characteristics of a transistor, as an example embodiment 2, after heat treatment at 500°C. The transistor comprises a channel layer formed of IGO (34 at%), an electrode formed of W, and layers of InO and TiN between the channel layer and the electrode. Figure 6 The channel layer does not contain Zn, and the In content is approximately 34 at%.

[0089] Reference Figure 6 Even when the transistor according to Example Embodiment 2 is heat-treated at 500°C, the threshold voltage is approximately -0.1V. The on / off current ratio is approximately 5.6E6. The transistor according to Example Embodiment 2, which includes a metal nitride layer and an oxide layer, has a larger threshold voltage and an improved on / off current ratio than the transistor according to Example Embodiment 1, which does not include an oxide layer and a metal nitride layer.

[0090] Figure 7 This is a diagram illustrating a semiconductor device 101 according to an example embodiment. Figure 7 The semiconductor device 101 may include an oxide semiconductor layer 10, a gate electrode 20 disposed separately from the oxide semiconductor layer 10, a gate insulating layer 30 disposed between the oxide semiconductor layer 10 and the gate electrode 20, and a first electrode 40 and a second electrode 50 disposed on the oxide semiconductor layer 10 and separated from each other.

[0091] The oxide semiconductor layer 10 can correspond to about Figure 1 or Figure 2 The oxide semiconductor layer 11 will be described without any redundant description.

[0092] The gate electrode 20 may be disposed separately from the oxide semiconductor layer 10. A gate insulating layer 30 may be disposed between the oxide semiconductor layer 10 and the gate electrode 20. The gate electrode 20 may include at least one of a metal, a metal nitride, and a transparent conductive oxide (TCO). The gate insulating layer 30 may include an oxide, which includes at least one of Hf, Zr, Al, and Si. When the semiconductor device 1 is a component of a memory cell, the gate electrode 20 may be a localized region of a word line.

[0093] The first electrode 40 and the second electrode 50 can be arranged separately from each other on the oxide semiconductor layer 11. For example, the first electrode 40 and the second electrode 50 can be arranged on the lower surface of the oxide semiconductor layer 10, and the gate electrode 20 can be arranged on the upper surface of the oxide semiconductor layer 10. However, the exemplary embodiment is not limited thereto. The first electrode 40, the second electrode 50, and the gate electrode 20 can also be arranged on the same surface of the oxide semiconductor layer 10. The first electrode 40 can be a source electrode, and the second electrode 50 can be a drain electrode. At least one of the first electrode 40 and the second electrode 50 can correspond to the following... Figure 1 The metal layer 12 is described, therefore its specific description will be omitted.

[0094] A metal nitride layer 60 may be further disposed between the oxide semiconductor layer 10 and at least one of the first electrode 40 and the second electrode 50. The metal nitride layer 60 may include a first metal nitride layer 60a disposed between the first electrode 40 and the oxide semiconductor layer 10 and a second metal nitride layer 60b disposed between the second electrode 50 and the oxide semiconductor layer 10. The first metal nitride layer 60a and the second metal nitride layer 60b may be disposed separately from each other. Since the characteristics of the metal nitride layer 60 correspond to the above-mentioned… Figure 2 The metal nitride layer 13 is described, so its specific description is omitted. For example, the metal nitride layer 60 may include a metal different from the first metal included in the first electrode 40, the second metal included in the second electrode 50, and the various metals included in the oxide semiconductor layer 10.

[0095] An oxide layer 70 may be further disposed between the oxide semiconductor layer 10 and the metal nitride layer 60. The oxide layer 70 may include a first oxide layer 70a disposed between the oxide semiconductor layer 10 and the first metal nitride layer 60a, and a second oxide layer 70b disposed between the oxide semiconductor layer 10 and the second metal nitride layer 60b. Since the characteristics of the oxide layer 70 correspond to the above-mentioned… Figure 2 The oxide layer 14 is described, so its specific description is omitted. Although Figure 7 The illustration shows a metal nitride layer 60 and an oxide layer 70 disposed between the first electrode 40 and the oxide semiconductor layer 10, and between the second electrode 50 and the oxide semiconductor layer 10; however, the exemplary embodiments are not limited thereto. In some exemplary embodiments, the metal nitride layer 60 and the oxide layer 70 may be disposed at at least one of the locations between the first electrode 40 and the oxide semiconductor layer 10, and between the second electrode 50 and the oxide semiconductor layer 10. In some exemplary embodiments, the metal nitride layer 60 and the oxide layer 70 may not be disposed between the first electrode 40 and the oxide semiconductor layer 10, or between the second electrode 50 and the oxide semiconductor layer 10.

[0096] Figure 8 This is a diagram illustrating a semiconductor device 102 according to another exemplary embodiment. (Refer to...) Figure 8 The semiconductor device 102 may include a substrate S, a first electrode 40 disposed on the substrate S, an oxide semiconductor layer 10 disposed on the first electrode 40, and a second electrode 50 disposed on the oxide semiconductor layer 10. The semiconductor device 102 may further include a first metal nitride layer 60a disposed between the first electrode 40 and the oxide semiconductor layer 10, a first oxide layer 70a disposed between the first metal nitride layer 60a and the oxide semiconductor layer 10, a second metal nitride layer 60b disposed between the second electrode 50 and the oxide semiconductor layer 10, and a second oxide layer 70b disposed between the second metal nitride layer 60b and the oxide semiconductor layer 10. Since the materials of the oxide semiconductor layer 10, gate electrode 20, gate insulating layer 30, first electrode 40, second electrode 50, first metal nitride layer 60a, second metal nitride layer 60b, first oxide layer 70a, and second oxide layer 70b have been described above, their specific descriptions are omitted.

[0097] The oxide semiconductor layer 10 can be arranged such that its longitudinal direction is perpendicular to the substrate S (Z-axis direction). In this disclosure, the longitudinal direction can refer to the direction of the greater length of the component shown in the figures.

[0098] The first electrode 40 and the second electrode 50 can be arranged separately from each other in a direction perpendicular to the substrate S (Z-axis direction). For example, the first electrode 40, the oxide semiconductor layer 10 and the second electrode 50 can be arranged in a straight line in a direction perpendicular to the substrate S or in the thickness direction (Z-axis direction) of the first electrode 40.

[0099] The gate electrode 20 can be disposed on one side of the oxide semiconductor layer 10. The gate insulating layer 30 can be disposed between the oxide semiconductor layer 10 and the gate electrode 20. The gate electrode 20 can be arranged such that its longitudinal direction (Z-axis direction) is perpendicular to the substrate S. The oxide semiconductor layer 10, the gate insulating layer 30, and the gate electrode 20 can be arranged in a straight line in a direction horizontal to the substrate S (X-axis direction).

[0100] An insulating layer 80 can be disposed on the substrate S to fill empty spaces. The first electrode 40 can be disposed separately from the substrate S through the insulating layer 80.

[0101] Figure 9 This is a diagram illustrating a semiconductor device 103 according to another exemplary embodiment. Figure 9 In the middle, by and Figure 8 The same reference numerals in the accompanying drawings indicate parts that have the same meaning as those in relation to... Figure 8The configurations and effects described are basically the same, so any redundant descriptions will be omitted.

[0102] Figure 9 The semiconductor device 103 shown may include a first electrode 40, an oxide semiconductor layer 10, and a second electrode 50 arranged in a direction perpendicular to the substrate S (Z-axis direction). A gate insulating layer 30 may be arranged on the circumference of the oxide semiconductor layer 10, and a gate electrode 20 may be arranged on the circumference of the gate insulating layer 30. Because the gate electrode 20 is arranged on the circumference of the oxide semiconductor layer 10, the area between the gate electrodes 20 and the oxide semiconductor layer 10 facing each other can be increased, and short-channel effects can be suppressed or reduced.

[0103] Figure 10 This is a diagram illustrating a semiconductor device 104 according to another example embodiment. Figure 10 In this drawing, the parts indicated by the same reference numerals as in the foregoing figures have essentially the same configuration and effect as described above, and therefore any redundant description will be omitted.

[0104] Figure 10 The semiconductor device 104 shown may include a first electrode 40 and an oxide semiconductor layer 10 disposed on the first electrode 40. A first metal nitride layer 60a may be disposed between the first electrode 40 and the oxide semiconductor layer 10. The width of the first metal nitride layer 60a in a direction parallel to the surface of the first electrode 40 (e.g., the X direction) may be greater than or equal to the width of the oxide semiconductor layer 10. For example, a local region of the first metal nitride layer 60a may not overlap with the oxide semiconductor layer 10 in a direction perpendicular to the surface of the first electrode 40 (e.g., the Z direction).

[0105] In a cross-sectional view perpendicular to the surface of the first electrode 40, the oxide semiconductor layer 10 may include a first region extending in a direction parallel to the surface of the first electrode 40 and a second region extending in a direction from the first electrode 40 toward the second electrode 50. For example, the oxide semiconductor layer 10 may have a U-shaped cross-section. The oxide semiconductor layer 10 may include a bottom portion 10a parallel to the surface of the first electrode 40, a first vertical extension 10b extending from one end of the bottom portion 10a in a direction perpendicular to the surface of the first electrode 40 (Z-axis direction), and a second vertical extension 10c extending from the other end of the bottom portion 10a in a direction perpendicular to the surface of the first electrode 40 (Z-axis direction).

[0106] The second electrode 50 may be disposed on the oxide semiconductor layer 10. The second electrode 50 may serve as a bonding pad. The second electrode 50 may include a first sub-electrode 51 and a second sub-electrode 52. The first sub-electrode 51 may be electrically connected to the first vertical extension 10b. The second sub-electrode 52 may be electrically connected to the second vertical extension 10c. The first sub-electrode 51 may not be electrically connected to the second sub-electrode 52.

[0107] In an example embodiment, the upper portion of each of the first sub-electrode 51 and the second sub-electrode 52 may have a first width in a first horizontal direction (X-axis direction), and the lower portion of each of the first sub-electrode 51 and the second sub-electrode 52 may have a second width in the first horizontal direction (X-axis direction) that is less than the first width. Each of the first sub-electrode 51 and the second sub-electrode 52 may have a T-shaped vertical cross-section.

[0108] The bottom surface of the lower portion of the first sub-electrode 51 can be disposed on the upper surface of the first vertical extension 10b, and the bottom surface of the lower portion of the second sub-electrode 52 can be disposed on the upper surface of the second vertical extension 10c. The bottom surface of the lower portion of the second electrode 50 can be disposed at a level higher than the upper surfaces of the first gate electrode 20a and / or the second gate electrode 20b, and a portion of the sidewall of the lower portion of the second electrode 50 can be covered by the first gate insulating layer 30a and / or the second gate insulating layer 30b.

[0109] The second metal nitride layer 60b may include a first sub-metal nitride layer 61 disposed between the first sub-electrode 51 and the first vertical extension 10b, and a second sub-metal nitride layer 62 disposed between the second sub-electrode 52 and the second vertical extension 10c. The width of each of the first sub-metal nitride layer 61 and the second sub-metal nitride layer 62 may be smaller than the width of the upper portion of each of the first sub-electrode 51 and the second sub-electrode 52.

[0110] The second oxide layer 70b may include a first sub-oxide layer 71 disposed between the first sub-metal nitride layer 61 and the first vertical extension 10b, and a second sub-oxide layer 72 disposed between the second sub-metal nitride layer 62 and the second vertical extension 10c.

[0111] The width of the first sub-oxide layer 71 can be the same as the width of the first vertical extension 10b, and the width of the second sub-oxide layer 72 can be the same as the width of the second vertical extension 10c.

[0112] The gate electrode 20 may include a first gate electrode 20a disposed separately from the first vertical extension 10b and a second gate electrode 20b disposed separately from the second vertical extension 10c. Furthermore, the gate insulating layer 30 may include a first gate insulating layer 30a disposed between the first vertical extension 10b and the first gate electrode 20a, and a second gate insulating layer 30b disposed between the second vertical extension 10c and the second gate electrode 20b.

[0113] The first gate electrode 20a and / or the second gate electrode 20b may extend in a second horizontal direction (Y-axis direction). The first gate electrode 20a and the second gate electrode 20b may be arranged separately from each other.

[0114] Semiconductor device 104 may be a vertical channel transistor (VCT) structure including a vertical channel region extending in a direction perpendicular to the first electrode 40 (X-axis direction).

[0115] When the same electrical signal is applied to the first gate electrode 20a and the second gate electrode 20b, and the same electrical signal is applied to the first sub-electrode 51 and the second sub-electrode 52, the semiconductor device 104 can operate as a single transistor.

[0116] Optionally, when electrical signals are independently applied to the first gate electrode 20a and the second gate electrode 20b, and when electrical signals are independently applied to the first sub-electrode 51 and the second sub-electrode 52, the semiconductor device 104 can operate as two transistors. For example, the oxide semiconductor layer 10, the first gate electrode 20a, the first gate insulating layer 30a, the first electrode 40, the first sub-electrode 51, the first metal nitride layer 60a, the first oxide layer 70a, the first sub-metal nitride layer 61, and the first sub-oxide layer 71 can operate as one transistor, and the oxide semiconductor layer 10, the second gate electrode 20b, the second gate insulating layer 30b, the first electrode 40, the second sub-electrode 52, the second metal nitride layer 60b, the first oxide layer 70a, the second sub-metal nitride layer 62, and the second sub-oxide layer 72 can operate as another transistor.

[0117] Figure 11 This is a diagram illustrating a semiconductor device 105 according to another example embodiment. Because... Figure 11 China and Figure 10 The parts indicated by the same reference numerals in the accompanying drawings have essentially the same configuration and operating effects, so their detailed descriptions are omitted.

[0118] In comparison Figure 10 and Figure 11 hour, Figure 11 The shape of the oxide semiconductor layer 10 included in the semiconductor device 105 can be consistent with... Figure 10The oxide semiconductor layers 10 included in the semiconductor device 104 have different shapes. The semiconductor device 105 may include a first oxide semiconductor layer 10d and a second oxide semiconductor layer 10e. The first oxide semiconductor layer 10d may have an L-shaped cross-section, and the second oxide semiconductor layer 10e may have a shape symmetrical to the first oxide semiconductor layer 10d about the Z-axis direction. The first oxide semiconductor layer 10d and the second oxide semiconductor layer 10e may be separated from each other.

[0119] Each of the first oxide semiconductor layer 10d and the second oxide semiconductor layer 10e can be arranged in a manner that their longitudinal direction is perpendicular to the substrate (not shown) in a direction (Z-axis direction).

[0120] The first metal nitride layer 60a may include a third sub-metal nitride layer 63 disposed between the first oxide semiconductor layer 10d and the first electrode 40, and a fourth sub-metal nitride layer 64 disposed between the second oxide semiconductor layer 10e and the second electrode 50. The third sub-metal nitride layer 63 and the fourth sub-metal nitride layer 64 may be in contact with each other and integrated (e.g., they may be provided as a single unit).

[0121] The first oxide layer 70a may include a third sub-oxide layer 73 disposed between the third sub-metal nitride layer 63 and the first oxide semiconductor layer 10d, and a fourth sub-oxide layer 74 disposed between the fourth sub-metal nitride layer 64 and the second oxide semiconductor layer 10e. The third sub-oxide layer 73 and the fourth sub-oxide layer 74 may be spaced apart from each other and may not be electrically connected to each other.

[0122] Figure 12 This is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 13 to 20 The manufacturing process is shown sequentially. Figure 10 A cross-sectional view of a method for developing semiconductor devices.

[0123] Reference Figure 12 and Figure 13 A first insulating layer 81, including an opening H that partially exposes the first electrode 40, can be formed on the first electrode 40 (S210). A plurality of first insulating layers 81 extending in a second horizontal direction (Y-axis direction) can be deposited on the first electrode 40 extending in a first horizontal direction (X-axis direction). The first insulating layers 81 can be stacked in a vertical direction (Z-axis direction) to have a certain height.

[0124] Reference Figure 12 and Figure 14A first metal nitride layer 60a and a first oxide layer 70a can be sequentially formed on the first electrode 40 exposed through the opening H (S220). Each of the first metal nitride layer 60a and the first oxide layer 70a can be deposited using a selective atomic layer deposition (ALD) process or a plasma-enhanced atomic layer deposition (PE-ALD) process. Since the materials, thicknesses, etc. of the first metal nitride layer 60a and the first oxide layer 70a have been described above, further descriptions are not provided.

[0125] Reference Figure 12 and Figure 15 An oxide semiconductor layer 10 can be formed on the first oxide layer 70a and the first insulating layer 81 (S230). The oxide semiconductor layer 10 can be deposited using a thermal ALD method or a PE-ALD method. The oxide semiconductor layer 10 can have a U-shaped cross-section.

[0126] Reference Figure 12 A gate insulating layer (30a and 30b) and a gate electrode (20a and 20b) can be formed on the first surface of the oxide semiconductor layer 10 (S240).

[0127] like Figure 16 As shown, a gate insulating layer 30 and a gate electrode 20 can be formed on the surface of the oxide semiconductor layer 10.

[0128] By partially etching Figure 16 The gate insulating layer 30 and gate electrode 20 shown in the diagram, and a portion of the surface of the oxide semiconductor 10 (e.g., bottom portion 13) can be exposed. Furthermore, the gate electrode 20, gate insulating layer 30, and oxide semiconductor layer 10 can be etched in a direction toward the upper portion of the first insulating layer 81 to expose the upper surface of the first insulating layer 81. The upper surface of the first insulating layer 81, the upper surfaces of the first gate electrode 20a and the second gate electrode 20b, and the upper surfaces of the first gate insulating layer 30a and the second gate insulating layer 30b can each be at the same height relative to the first electrode 40.

[0129] Therefore, as Figure 17 As shown, the gate electrode 20 can be divided into a first gate electrode 20a and a second gate electrode 20b, and the gate insulating layer 30 can be divided into a first gate insulating layer 30a and a second gate insulating layer 30b.

[0130] Reference Figure 18 By etching the first gate electrode 20a and the second gate electrode 20b again, the height of the upper surface of the first gate electrode 20a and the second gate electrode 20b relative to the first electrode 40 can be lower than the height of the upper surface of the first gate insulating layer 30a and the second gate insulating layer 30b relative to the first electrode 40.

[0131] The second insulating layer 82 can be deposited from the surface of the bottom portion 13 of the oxide semiconductor layer 10 to the same height as the upper surface of the oxide semiconductor layer 10. The height of the upper surface of the second insulating layer 82 can be the same as the height of the upper surface of the first insulating layer 81 and the upper surface of the oxide semiconductor layer 10.

[0132] A second electrode 50 may be formed on a second surface of the oxide semiconductor layer 10 that is different from the first surface (S250).

[0133] like Figure 19 As shown, the upper portion of the oxide semiconductor layer 10 can be partially etched, and a second oxide layer 70b and a second metal nitride layer 60b can be sequentially deposited on the etched oxide semiconductor layer 10.

[0134] like Figure 20 As shown, a second electrode 50 can be deposited on the second metal nitride layer 60b. After depositing a metal layer on the second insulating layer 82, the first gate insulating layer 30a, the second gate insulating layer 30b, and the second metal nitride layer 60b, the metal layer can be etched to partially expose the first insulating layer 81 and the second insulating layer 82. In this way, the second electrode 50 can be formed from the metal layer.

[0135] The semiconductor device according to the example implementation may be a component of a memory device. Figure 21 This is a perspective view illustrating an example of a schematic structure of a vertically stacked memory device 301 according to an exemplary embodiment. (Refer to...) Figure 21 The vertically stacked memory device 301 may include multiple bit lines BL extending in a first direction (Z direction), multiple oxide semiconductor layers 10 respectively connected to the multiple bit lines BL and extending in a second direction (X direction) perpendicular to the first direction, multiple capacitors Cap respectively electrically connected to the multiple oxide semiconductor layers 10, and multiple word lines WL extending in a third direction (Y direction) perpendicular to the first and second directions to intersect the multiple oxide semiconductor layers 10. Although Figure 21 The illustration shows each of the multiple word lines WL crossing a corresponding oxide semiconductor layer 10 among the multiple oxide semiconductor layers 10, but the example implementation is not limited thereto. In some example implementations, the word lines WL may cross below the oxide semiconductor layer 10.

[0136] Additionally, the vertically stacked memory device 301 may further include a substrate S for growth and a drive circuit board CS disposed on the substrate S for growth. The drive circuit board CS may include circuitry for performing input / output operations such as receiving data from external circuitry connected thereto or outputting data to the outside, as well as for performing operations such as recording data on a capacitor Cap or reading data recorded on a capacitor Cap.

[0137] Multiple bit lines BL can be arranged on the driver circuit board CS perpendicular to the upper surface of the driver circuit board CS. Although Figure 21 The diagram shows only three bit lines BL arranged in a straight line, separated from each other in a third direction (e.g., the Y direction), but a larger number of bit lines BL can be arranged in a 2D manner. For example, multiple bit lines BL extending in a vertical direction (e.g., a first direction) can be arranged in a 2D manner on the driver board CS and spaced apart from each other in a second and third direction. Multiple bit lines BL can also be arranged parallel to each other.

[0138] Multiple oxide semiconductor layers 10, each connected to a corresponding bit line BL in a plurality of bit lines BL, may be spaced apart from each other in a first direction. Although Figure 21 Only two oxide semiconductor layers 10 associated with one bit line BL are shown, but a greater number of oxide semiconductor layers 10 may be spaced apart from each other in the first direction. Additionally, within the same layer, multiple oxide semiconductor layers 10 may be spaced apart from each other in a parallel manner in a third direction. Multiple oxide semiconductor layers 10 arranged in the same layer may be respectively connected to corresponding bit lines among the multiple bit lines BL. Similar to the multiple bit lines BL, multiple oxide semiconductor layers 10 may be spaced apart from each other in a 2D manner in the second direction and the third direction. Each of the multiple oxide semiconductor layers 10 may extend in the second direction. A first end of each of the multiple oxide semiconductor layers 10 may be electrically connected to a corresponding bit line among the multiple bit lines BL. A second end of each of the multiple oxide semiconductor layers 10, opposite to the first end, may be electrically connected to a capacitor Cap.

[0139] A first metal nitride layer 60a can be disposed between the oxide semiconductor layer 10 and the bit line BL, and a first oxide layer 70a can be disposed between the oxide semiconductor layer 10 and the first metal nitride layer 60a. Additionally, a second metal nitride layer 60b can be disposed between the oxide semiconductor layer 10 and the capacitor, and a second oxide layer 70b can be disposed between the oxide semiconductor layer 10 and the second metal nitride layer 60b. Although the accompanying drawings show a pair of metal nitride layers 60 and oxide layers 70 disposed at each end of the oxide semiconductor layer 10, the exemplary embodiment is not limited thereto. The metal nitride layer 60 and oxide layer 70 can be disposed only at one end of the oxide semiconductor layer 10.

[0140] although Figure 21 The capacitor Cap is shown as a block, but it may include a first electrode, a second electrode, and a dielectric layer disposed between the first and second electrodes. The first electrode of the capacitor Cap may be electrically connected to a corresponding oxide semiconductor layer 10 among a plurality of oxide semiconductor layers 10. Thus, one oxide semiconductor layer 10 may be connected to one capacitor Cap. Although not shown in the figures, the second electrode of the capacitor Cap may be connected to the ground wire of a vertically stacked memory device.

[0141] Word lines WL can extend upwards in a third direction to traverse multiple corresponding oxide semiconductor layers 10. Multiple word lines WL can be spaced apart from each other in a first direction. Although Figure 21 Only one word line WL arranged on a layer is shown, but multiple word lines WL can be arranged in parallel on a layer and spaced apart from each other in a second direction.

[0142] The gate insulating layer 30 can be disposed between the oxide semiconductor layer 10 and the word line WL. Although in Figure 21 Not shown, but the vertically stacked memory device 301 may further include insulating material filling the spaces between multiple bit lines BL, multiple oxide semiconductor layers 10 and multiple word lines WL.

[0143] An oxide semiconductor layer 10 can be used to form an oxide semiconductor transistor together with a corresponding word line WL, a corresponding bit line BL, and the first electrode of a capacitor. The first electrode 40 of the oxide semiconductor transistor can be a component of the bit line BL, the gate electrode 20 can be a component of the word line WL, and the second electrode 50 can be the first electrode of the capacitor Cap. However, the exemplary embodiment is not limited thereto. The first electrode 40, the gate electrode 20, and the second electrode 50 can be provided as separate layers and can be electrically connected to the bit line BL, the word line WL, and the capacitor Cap, respectively.

[0144] Since the word line WL can be used as the gate electrode 20 of the oxide semiconductor transistor, current can flow along the oxide semiconductor layer 10 when a gate signal greater than a threshold is applied to the word line WL. In this way, the corresponding bit line BL and capacitor Cap can be electrically connected to each other, so data can be recorded to capacitor Cap, or data recorded to capacitor Cap can be read.

[0145] Accordingly, an oxide semiconductor layer 10 and a corresponding capacitor Cap can form a memory cell. The vertically stacked memory device 301 according to the exemplary embodiment may include a plurality of memory cells arranged in a 2D manner on a single layer. The vertically stacked memory device 301 may have a structure comprising a multi-layer stack including a plurality of memory cells arranged in a 2D manner. Therefore, the integration density of the memory cells can be increased, thereby increasing the recording capacity of the vertically stacked memory device 301.

[0146] Figure 22 This is a perspective view illustrating an example of a schematic structure of a vertically stacked memory device 302 according to another exemplary embodiment. (Refer to...) Figure 21 and Figure 22 , Figure 22 The vertically stacked memory device 302 may have a dual-gate structure. For example, the vertically stacked memory device 302 may include a first word line WL1 extending upward on a third side to cross over a plurality of oxide semiconductor layers 10 disposed on the same layer, and a second word line WL2 extending upward on a third side to cross under the plurality of oxide semiconductor layers 10 disposed on the same layer. The first word line WL1 and the second word line WL2 may be arranged separately from each other in a first direction and the corresponding oxide semiconductor layers 10 are disposed therebetween, and may face each other in a parallel manner. In other words, Figure 22 Each of the multiple word lines WL shown may include a first word line WL1 and a second word line WL2, the first word line WL1 and the second word line WL2 being arranged to face each other in a parallel manner and separated from each other in a first direction, wherein a corresponding oxide semiconductor layer 10 of a plurality of oxide semiconductor layers 10 is arranged between them.

[0147] An oxide semiconductor layer 10 can be formed together with a corresponding pair of first word lines WL1 and second word lines WL2 to form an oxide semiconductor transistor. The operation of the oxide semiconductor transistor can be controlled by the first word line WL1 disposed on the oxide semiconductor layer 10 and the second word line WL2 disposed below the oxide semiconductor layer 10. Therefore, the driving reliability of the oxide semiconductor transistor can be improved. Due to Figure 22 Other components of the vertically stacked memory device 302 shown can be connected with Figure 21 The structure of the vertically stacked memory device 301 shown is the same, so any redundant description of it is omitted.

[0148] although Figure 21 and Figure 22The example shows bit line BL arranged perpendicularly to the upper surface of driver circuit board CS, and word line WL arranged horizontally to the upper surface of driver circuit board CS; however, the example embodiment is not limited to this. Bit line BL can be arranged horizontally to the upper surface of driver circuit board CS, and word line WL can be arranged perpendicularly to the upper surface of driver circuit board CS. That is, oxide semiconductor layer 10 and capacitor Cap can be arranged sequentially from driver circuit board CS.

[0149] Figure 23 This is a block diagram illustrating an electronic system 400 according to an example embodiment.

[0150] Electronic system 400 may include memory 410 and memory controller 420. Memory controller 420 may control memory 410 to read data from memory 410 and / or write data to memory 410 in response to a request from host 430. At least one of memory 410 and memory controller 420 may include semiconductor device 1 according to an example embodiment.

[0151] Figure 24 This is a block diagram illustrating an electronic system 500 according to an example embodiment.

[0152] Electronic system 500 may constitute a wireless communication device or be configured to transmit and / or receive information in a wireless environment. Electronic system 500 may include a controller 510, input / output (I / O) devices 520, a memory 530, and a wireless interface 540 connected to each other via a bus 550.

[0153] Controller 510 may include at least one of a microprocessor, a digital signal processor, and any other similar processor. I / O device 520 may include at least one of a keypad, a keyboard, and a display. Memory 530 may be used to store instructions executed by controller 510. For example, memory 530 may be used to store user data. Electronic system 500 may use wireless interface 540 to send / receive data via a wireless communication network. Wireless interface 540 may include an antenna and / or a wireless transceiver. Electronic system 400 may include semiconductor devices according to an example embodiment.

[0154] Any functional blocks shown in the accompanying drawings and described above can be implemented in processing circuitry, such as hardware including logic circuitry, hardware / software combinations (such as processors executing software), or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0155] A lower In content in the channel layer of a semiconductor device according to an example embodiment can improve the thermal stability of the semiconductor device.

[0156] Since the semiconductor device according to the example embodiment includes a metal nitride layer between the channel layer and the electrode, the diffusion of material from the channel layer to the electrode can be reduced or prevented.

[0157] Since the semiconductor device according to the example embodiment includes an oxide layer with In content dominating between the channel layer and the electrode, the contact resistance between the channel layer and the electrode can be reduced.

[0158] It should be understood that some of the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0159] Cross-reference to related applications

[0160] This application is based on and claims priority to Korean Patent Application No. 10-2024-0110011, filed with the Korean Intellectual Property Office on August 16, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The oxide semiconductor layer comprises multiple metals, wherein, relative to the total amount of the multiple metals, the content of indium (In) is less than 50 at% and the content of zinc (Zn) is 0 at%. The gate electrode is separate from the oxide semiconductor layer; A gate insulating layer is located between the oxide semiconductor layer and the gate electrode; and The first electrode and the second electrode are on the oxide semiconductor layer and spaced apart from each other, and the gate electrode is inserted between the first electrode and the second electrode.

2. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer further includes at least one of gallium (Ga), tin (Sn), cadmium (Cd), aluminum (Al), germanium (Ge) and hafnium (Hf).

3. The semiconductor device according to claim 1, wherein, The content of indium (In) relative to the plurality of metals is 10 at% or more.

4. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer further includes gallium (Ga), and The content of gallium (Ga) is greater than that of indium (In).

5. The semiconductor device according to claim 1, wherein, The multiple metals mentioned include only In and Ga, with the gallium (Ga) content being 50 at% or more.

6. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer remains in an amorphous phase at temperatures ranging from approximately 450°C to approximately 700°C.

7. The semiconductor device according to claim 1, wherein, The first electrode, the oxide semiconductor layer, and the second electrode are arranged sequentially in a direction perpendicular to the surface of the first electrode.

8. The semiconductor device according to claim 7, wherein, In a cross-sectional view perpendicular to the surface of the first electrode, the oxide semiconductor layer includes a first region extending in a direction parallel to the surface of the first electrode and a second region extending from the first electrode toward the second electrode.

9. The semiconductor device according to claim 1, further comprising: The capacitor is electrically connected to the oxide semiconductor layer. The first electrode is a component of the bit line, and the gate electrode is a component of the word line.

10. The semiconductor device of claim 1, further comprising: A metal nitride layer is located between the oxide semiconductor layer and at least one of the first electrode and the second electrode; as well as An oxide layer is located between the metal nitride layer and the oxide semiconductor layer, wherein the oxide layer is an indium (In) based oxide layer.

11. The semiconductor device according to claim 10, wherein, The metal nitride layer is in direct contact with at least one of the first electrode and the second electrode.

12. The semiconductor device according to claim 10, wherein, The oxide layer is in direct contact with at least one of the oxide semiconductor layer and the metal nitride layer.

13. The semiconductor device according to claim 10, wherein, The oxide layer includes indium (In), and the content of indium (In) relative to the various metals included in the oxide layer is 50 at% or more.

14. The semiconductor device according to claim 10, wherein, The metal nitride layer includes a metal that is different from the first metal included in the first electrode, the second metal included in the second electrode, and the various metals included in the oxide semiconductor layer.

15. The semiconductor device according to claim 10, wherein, The metal nitride layer includes at least one of titanium (Ti), molybdenum (Mo), niobium (Nb), and tantalum (Ta).

16. The semiconductor device according to claim 10, wherein, The thickness of the oxide layer is 5 nm or less.

17. The semiconductor device according to claim 10, wherein, The thickness of the metal nitride layer is 10 nm or less.

18. A method for manufacturing a semiconductor device, the method comprising: A first insulating layer is formed on the first electrode, the first insulating layer including an opening exposing the first electrode; A first metal nitride layer and a first oxide layer are sequentially formed on the first electrode exposed through the opening; An oxide semiconductor layer is formed on the first oxide layer and the first insulating layer, the oxide semiconductor layer comprising a plurality of metals, wherein, relative to the plurality of metals, the content of indium (In) is less than 50 at% and the content of zinc (Zn) is 0 at%. A gate insulating layer and a gate electrode are sequentially formed on the first surface of the oxide semiconductor layer; and A second electrode is formed on a second surface of the oxide semiconductor layer that is different from the first surface of the oxide semiconductor layer.

19. The method according to claim 18, wherein, Forming the gate insulating layer and the gate electrode includes: The gate insulating layer and the gate electrode are etched in a direction toward the upper portion of the first insulating layer to expose the surface of the oxide semiconductor layer, such that the gate insulating layer is divided into a first gate insulating layer and a second gate insulating layer, and the gate electrode is divided into a first gate electrode and a second gate electrode, wherein the second surface of the oxide semiconductor layer is parallel to the upper surface of the first electrode; and Partial etching of the first gate electrode and the second gate electrode is performed such that the height of the upper surface of the first gate electrode and the gate electrode above the first electrode is lower than the height of the upper surface of the first gate insulating layer and the second gate insulating layer above the first electrode, respectively.

20. The method according to claim 18, wherein, Forming the second electrode includes: A second oxide layer is formed on the second surface of the oxide semiconductor layer; A second metal nitride layer is formed on the second oxide layer; and The second electrode is formed on the second metal nitride layer.

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