Manufacturing method of trench gate super junction device

Abstract

The invention discloses a manufacturing method of a trench gate super junction device, which comprises the following steps of: providing a concentrated first epitaxial layer, so that the breakdown voltage of the device meets the requirement and the specific on-resistance is reduced at the same time. And forming a super junction structure. A field oxide layer is grown by adopting a thermal oxidation process and a CVD (Chemical Vapor Deposition) process, and the CVD process reduces the thermal process and reduces the specific on-resistance. And performing graphical etching on the field oxide layer. And forming a trench gate, and forming a gate oxide layer by adopting a thermal oxidation growth process of 900-950 DEG C, so as to reduce the thermal process and reduce the specific on-resistance. A first well region is formed and the first well region is activated or annealed activation is cancelled using rapid thermal annealing to reduce the thermal process and reduce the specific on-resistance. And forming a source region. And forming an interlayer film. And forming a contact hole opening, wherein the first distance between the source electrode contact hole opening and the side surface of the trench gate is reduced to 0.5-0.6 micron. And forming a well contact injection region. And filling metal in the contact hole opening to form a contact hole. According to the invention, the specific on-resistance of the device can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a trench gate superjunction (SJ) device. Background Technology

[0002] Compared to existing traditional VDMOS, superjunction MOSFETs have been widely used in various electronic and power fields due to their superior device characteristics. Because the special N-type and P-type pillars in the superjunction MOSFET structure compensate for each other, the area of ​​the built-in electric field in the PN junction is expanded, allowing for high breakdown voltages in denser N-type epitaxial layers (NEPI). Therefore, it exhibits low on-resistance and high breakdown voltage exceeding the Si limit.

[0003] Currently, there are two main manufacturing processes for superjunction MOSFET devices: one is the multiple epitaxial doping process, which involves forming a breakdown layer through multiple epitaxial layers, with either P-type or PN doping types in each layer, ultimately resulting in a structure with alternating P-type and N-type pillars; the other is the deep trench filling process, which involves etching and filling deep trenches on a thick N-epitaxial layer to form a structure with alternating P-type and N-type pillars. The multiple epitaxial doping process has a relatively fixed epitaxial thickness for each layer, and the number of epitaxial layers increases with the breakdown voltage, leading to higher costs. In contrast, the existing deep trench filling process more easily achieves a smaller aspect ratio, and the resulting superjunction N and P regions have a more uniform doping distribution, which is beneficial for reducing Rsp. More importantly, this process is simpler and less expensive.

[0004] In existing trench-gate superjunction MOSFETs, to ensure successful planarization of the deep trench P-type pillars, the P-type pillar formation process is typically performed before the polysilicon formation process. Sometimes, the P-type well process is performed after the P-type pillar formation. This results in the P-type and N-type pillars undergoing gate oxide processing and other high-temperature processes after the P-type pillar formation in the trench. These thermal processes, often exceeding 1000°C, cause cross-diffusion of impurities in the P-type and N-type pillars, increasing the device's specific on-resistance and impacting chip performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a trench gate superjunction device, which can further reduce the specific on-resistance of the device, improve the process window of the device, and optimize the EAS capability.

[0006] To solve the above-mentioned technical problems, the manufacturing method of the trench gate superjunction device provided by the present invention employs a multi-stage step of reducing the specific on-resistance of the superjunction device to reduce the specific on-resistance to below a first required value. The multi-stage step of reducing the specific on-resistance includes: Step 1: Provide a first epitaxial layer doped with a first conductivity type. By increasing the doping concentration of the first epitaxial layer, the breakdown voltage of the device is made to meet the requirements while the specific on-resistance is reduced.

[0007] Step 2: A superjunction structure is formed in the first epitaxial layer. The superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars. The second conductivity type pillars are composed of a second epitaxial layer doped with a second conductivity type and filled in a superjunction trench. The superjunction trench is formed in the first epitaxial layer, and the first conductivity type pillars are composed of the first epitaxial layers between the second conductivity type pillars. The depth of the superjunction trench is less than the thickness of the first epitaxial layer, and a buffer layer is formed by the first epitaxial layer located at the bottom of the superstructure.

[0008] Step 3: Growing a field oxide layer, including: forming a first oxide layer using a thermal oxidation process and forming a second oxide layer using a CVD process, the field oxide layer being formed by superimposing the first oxide layer and the second oxide layer, the thermal process of the field oxide layer being reduced by the CVD process of the second oxide layer, thereby reducing the PN diffusion of the superjunction structure and reducing the specific on-resistance.

[0009] Step 4: Perform a first patterned etching on the field oxide layer to remove the field oxide layer in the active region. A terminal region surrounds the active region, and the terminal region includes a transition region adjacent to the active region. Step 5: Form the gate structure of each superjunction device unit. The gate structure is a trench gate, which includes a gate oxide layer and a polysilicon gate formed in the gate trench. The device unit step is the width and spacing of the trench gate. The gate oxide layer is formed by a thermo-oxidative growth process at 900℃ to 950℃ to reduce the thermal process of the superjunction structure and thereby reduce the specific on-resistance.

[0010] Step 6: Perform ion implantation to form a first well region doped with the second conductivity type in the surface region of the superjunction structure. The trench gate extends longitudinally through the first well region, and the surface of the first well region covered by the side of the trench gate is used to form a conductive channel. After the ion implantation of the first well region is completed, the first well region is activated by rapid thermal annealing or the activation step of unannealing the first well region is performed to reduce the thermal process of the superjunction structure and thereby reduce the specific on-resistance.

[0011] Step 7: Perform ion implantation of the first conductivity type to form a source region aligned with the side of the corresponding gate structure in the surface region of the first well region of the active region.

[0012] Step 8: Formation of interlayer membrane.

[0013] Step 9: Form a contact hole (CT) opening, the contact hole opening including a source contact hole opening, the source contact hole opening passing through the interlayer film at the top of the source region and the source region; reduce the first spacing between the source contact hole opening and the side of the adjacent trench gate to 0.5 micrometers to 0.6 micrometers.

[0014] Under the condition that the device cell step and the trench gate width remain unchanged, the reduction value of the first spacing is the increase value of the source contact hole width. By increasing the width of the source contact hole, the source contact resistance is reduced and the current density of the source contact hole is reduced at the same time, so as to reduce the specific on-resistance and optimize the EAS capability.

[0015] Step 10: Form a well contact injection region doped with a second conductivity type at the bottom of the source contact hole opening.

[0016] Step 11: Fill the contact hole opening with metal to form a contact hole, wherein the source contact hole is composed of metal filled in the source contact hole opening.

[0017] A further improvement is that, in step one, the first epitaxial layer adopts a single-layer doped structure, a double-layer doped structure, or a graded-doped structure; the graded-doped structure includes: The bottom portion of the first epitaxial layer is doped with a fixed doping concentration, and the top portion of the first epitaxial layer is doped with a gradually decreasing doping concentration from the bottom surface to the top surface. The doping concentration at the bottom surface of the top portion of the first epitaxial layer is the same as the doping concentration at the bottom portion of the first epitaxial layer.

[0018] A further improvement is that the thickness of the bottom portion of the first epitaxial layer is 0 micrometers to 8 micrometers, and the thickness of the top portion of the first epitaxial layer is 42 micrometers to 50 micrometers.

[0019] The resistivity of the bottom surface of the top portion of the first epitaxial layer is 0.9 ohm·cm to 1.0 ohm·cm and the resistivity of the top surface of the top portion of the first epitaxial layer is 0.7 ohm·cm to 0.8 ohm·cm.

[0020] A further improvement is that the buffer layer is at least partially located in the bottom portion of the first epitaxial layer.

[0021] A further improvement is that, in step three, the thickness of the first oxide layer is 500 Å to 2000 Å; and the thickness of the second oxide layer is 2000 Å to 14000 Å.

[0022] A further improvement is that, in step four, after the first patterning etching, the innermost portion of the field oxide layer in the transition region is also removed, as is the field oxide layer in the cutoff region located at the outermost periphery of the terminal region.

[0023] After the first patterning etching, the thickness of the field oxide layer is retained as it was during growth or reduced to 2000 Å to 8000 Å.

[0024] A further improvement is that, in step five, the thickness of the gate oxide layer is 500 Å to 2000 Å.

[0025] The thermo-oxidative growth process of the gate oxide layer includes a wet thermo-oxidation process or a dry thermo-oxidation process.

[0026] A further improvement is that, in step six, when the first well region is activated by the rapid thermal annealing, the process conditions for the rapid thermal annealing include: a temperature of 1050°C or 1100°C and a time of 30 seconds.

[0027] A further improvement is that, under the condition that the specific on-resistance is reduced to below the first required value, one or more of steps three, five, and six after the formation of the superjunction structure are changed to steps that do not reduce the specific on-resistance, while at least one of steps three, five, and six remains a step that reduces the specific on-resistance.

[0028] A further improvement is that when step three is changed to a step other than reducing the specific on-resistance, it includes: the field oxidation process is entirely formed by thermal oxidation.

[0029] A further improvement is that when step five is changed to a step other than reducing the specific on-resistance, it includes: the gate oxide layer is formed by a high-temperature thermal oxidation growth process of 1050℃~1100℃, and the process time is 30 minutes~60 minutes.

[0030] A further improvement is that, when step six is ​​changed to a step other than reducing the specific on-resistance, it includes: activating the first well region using an annealing process at 1100°C or higher for 30 minutes or more.

[0031] A further improvement is that, in step ten, composite implantation is used to form the well contact implantation region. The composite implantation uses at least two impurities of different molecular weights and second conductivity types. In the well contact implantation region, the implantation dose of the high molecular weight impurity is greater than the implantation dose of the low molecular weight impurity, and the implantation energy of the high molecular weight impurity is less than the implantation energy of the low molecular weight impurity. The implantation junction depth plus diffusion distance of the low molecular weight impurity in the well contact implantation region is less than the first spacing. The implantation junction depth plus diffusion distance of the high molecular weight impurity in the well contact implantation region is less than the implantation junction depth plus diffusion distance of the low molecular weight impurity in the well contact implantation region. The doping concentration of the surface region of the well contact implantation region is determined by the implantation dose of the high molecular weight impurity and used to ensure the source contact resistance. The implantation dose of the low molecular weight impurity in the well contact implantation region is used to form a transition layer from the well contact implantation region to the first well region and avoids affecting the threshold voltage (VTH) of the conductive channel.

[0032] A further improvement is that the source contact hole opening is located at a depth of 100 angstroms to 400 angstroms below the top surface of the superjunction structure.

[0033] A further improvement is that the trench gate superjunction device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the trench gate superjunction device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0034] A further improvement is that the trench gate superjunction device is an N-type device, the high molecular weight impurity in the well contact implantation region is BF2 and the low molecular weight impurity is B, the implantation energy of BF2 is 20keV to 25keV, and the implantation dose is 1e14cm. -2 ~1e15cm -2 The injection energy for B was 40 keV, and the injection dose was 5e13cm. -2 .

[0035] A further improvement is that the injected impurity in the first well region includes B, the injection energy is 60keV to 180keV, and the injection dose is 1e11cm. -2 ~1e14cm -2 The number of injections is 1, 2, or 3.

[0036] This invention employs a multi-stage process to reduce the specific on-resistance of a superjunction device. This includes enriching the first epitaxial layer before the superjunction structure is formed, controlling the thermal processes of the field oxide layer, gate oxide layer, and first well region after the superjunction structure is formed, and reducing the spacing between the source contact hole and the trench gate (i.e., the first spacing) to achieve multi-stage control. This multi-stage control achieves an overall reduction in specific on-resistance, bringing it below a required value (i.e., a first required value). The reduced thermal processes after the superjunction structure formation reduce PN diffusion in the superjunction, improving the device's process window and simultaneously reducing its specific on-resistance. Therefore, this invention improves the device's process window and further reduces its specific on-resistance. For example, this invention can reduce the specific on-resistance by 5% to 7% at each stage of the specific on-resistance reduction process, ultimately achieving a reduction of over 20%. Finally, it also improves the device's cost and performance.

[0037] Because the superjunction structure significantly reduces thermal degradation, the increased density of the first epitaxial layer ensures that the device's breakdown voltage still meets requirements. Furthermore, this invention allows for a gradient doping structure where the first epitaxial layer gradually decreases in doping from bottom to top, further improving both the device's breakdown voltage and specific on-resistance.

[0038] The present invention can also control the thermal process of the field oxide layer, gate oxide layer and first well region after the superjunction structure according to the application needs. Only some steps are steps to reduce the specific on-resistance, and other parts are steps that do not reduce the specific on-resistance. As long as the overall thermal process after the superjunction structure meets the requirements, the specific on-resistance of the device can still meet the required value.

[0039] This invention reduces the first pitch to 0.5 to 0.6 micrometers, thereby increasing the width of the source contact hole without increasing the device cell step size or reducing the trench gate width. This means that the device cell step size and trench gate width remain constant. The increased width of the source contact hole increases the contact area with the bottom source region and the first well region, thus reducing the source contact resistance and consequently the specific on-resistance of the device. Simultaneously, the increased width of the source contact hole also reduces the current density of the source contact hole while maintaining a constant source current, thus optimizing the device's EAS capability. Therefore, this invention maximizes the reduction of source contact resistance and simultaneously reduces the current density of the source contact hole while keeping the device cell step size and trench gate width constant, thereby simultaneously reducing specific on-resistance and optimizing EAS capability.

[0040] This invention also features a special design for the doping process structure of the well contact implantation region based on the first spacing. The dopant in the well contact implantation region is configured with at least two impurities of different molecular weights and second conductivity types, formed by composite implantation of multiple impurities. Furthermore, the implantation energy and dosage for various molecular weights are set according to the size of the first spacing to ensure that the implantation junction depth plus diffusion distance of small molecular weight impurities in the well contact implantation region is less than the first spacing. Simultaneously, since the implantation junction depth plus diffusion distance of large molecular weight impurities in the well contact implantation region is less than that of small molecular weight impurities, the implantation junction depth plus diffusion distance of large molecular weight impurities in the well contact implantation region will also be less than the first spacing. This allows for a higher and shallower doping concentration of large molecular weight impurities to meet contact resistance requirements without affecting the threshold voltage. The lower doping concentration of small molecular weight impurities, coupled with their deeper penetration, avoids impacting the threshold voltage of the conductive channel, thereby maintaining a stable threshold voltage and ensuring a non-dispersive and consistent threshold voltage distribution. In existing structures, the process for injecting various impurities in the well contact injection region is not set according to the first spacing of the present invention. Compared with the present invention, the injection energy and injection dose of various impurities in the well contact injection region of the existing structure are too large. The present invention can eliminate these defects, thereby satisfying the requirements of the contact resistance of the contact hole and ensuring that the magnitude and distribution of the threshold voltage also meet the requirements.

[0041] The device unit step of the present invention remains unchanged, which can ensure that the integration level of the device and the chip area remain unchanged.

[0042] The trench gate width of the present invention remains unchanged, which can prevent the adverse effects of the reduction of trench gate width on the increase of process complexity, thereby ensuring the consistency of device cells and preventing the deterioration of EAS capability caused by the deterioration of device cell consistency. Attached Figure Description

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of a method for manufacturing a trench gate superjunction device according to an embodiment of the present invention; Figures 2A-2J This is a schematic diagram of the device structure in each step of the manufacturing method of the trench gate superjunction device according to an embodiment of the present invention; Figure 3A This is a simulation diagram of an existing trench gate superjunction device; Figure 3B This is a device simulation diagram showing the first spacing of the trench gate superjunction device according to the embodiment of the present invention and the well contact injection region of the existing trench gate superjunction device; Figure 3C yes Figure 3A and Figure 3BA schematic diagram of the doping concentration distribution at line AA in the diagram; Figure 3D This is a statistical graph of threshold voltage measurements under the first spacing and various well contact injection region doping conditions of the trench gate superjunction device according to the embodiments of the present invention. Figure 4 This is a statistical graph showing the threshold voltage measurement under the doping conditions of the first spacing and the well contact implantation region of the trench gate superjunction device according to an embodiment of the present invention. Detailed Implementation

[0044] like Figure 1 The diagram shown is a flowchart of a method for manufacturing a trench gate superjunction device according to an embodiment of the present invention; as shown Figures 2A to 2J The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the trench gate superjunction device according to an embodiment of the present invention. The manufacturing method of the trench gate superjunction device according to an embodiment of the present invention employs a multi-stage step to reduce the specific on-resistance of the superjunction device to reduce the specific on-resistance to below a first required value. The multi-stage step to reduce the specific on-resistance includes: Step 1, such as Figure 2A As shown, a first epitaxial layer 202 doped with a first conductivity type is provided. By increasing the doping concentration of the first epitaxial layer 202, the breakdown voltage of the device can meet the requirements while reducing the specific on-resistance.

[0045] In this embodiment of the invention, the first epitaxial layer 202 adopts a gradient doping structure. In other embodiments, the first epitaxial layer 202 may also adopt a single-layer doped structure or a double-layer doped structure.

[0046] Gradient-doped structures include: The bottom portion 202a of the first epitaxial layer 202 is fixedly doped, and the top portion 202b of the first epitaxial layer 202 is doped with a gradually decreasing doping concentration from the bottom surface to the top surface. The doping concentration at the bottom surface of the top portion 202b of the first epitaxial layer 202 is the same as the doping concentration of the bottom portion 202a of the first epitaxial layer 202.

[0047] In some embodiments, the thickness of the bottom portion 202a of the first epitaxial layer 202 is 0 micrometers to 8 micrometers, and the thickness of the top portion 202b of the first epitaxial layer 202 is 42 micrometers to 50 micrometers.

[0048] The resistivity of the bottom surface of the top portion 202b of the first epitaxial layer 202 is 0.9 ohm·cm to 1.0 ohm·cm, and the resistivity of the top surface of the top portion 202b of the first epitaxial layer 202 is 0.7 ohm·cm to 0.8 ohm·cm.

[0049] The subsequent buffer layer is located at least partially in the bottom portion 202a of the first epitaxial layer 202.

[0050] like Figure 2A As shown, a first epitaxial layer 202 is formed on the top surface of a heavily doped semiconductor substrate 201 of a first conductivity type. The semiconductor substrate 201 is made of silicon, the first epitaxial layer 202 is made of silicon, and the second epitaxial layer is made of silicon.

[0051] The semiconductor substrate 201 includes an active region 201a and a termination region 201c. The termination region 201c includes a transition region 201b adjacent to the active region 201a. The active region 201a is also the current-flowing region. The transition region 201b belongs to the termination region 201c, but is separately marked 201b for clearer representation. The active region 201a is also the current-flowing region, the termination region 201c is used to withstand lateral voltage, and the top of the transition region 201b is provided with gate-connected metal and field plate metal.

[0052] Step 2, as follows Figure 2C As shown, a superjunction structure is formed in the first epitaxial layer 202. The superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars 203. The second conductivity type pillars 203 are composed of second epitaxial layers doped with the second conductivity type and filled in the superjunction trench. The superjunction trench is formed in the first epitaxial layer 202. The first conductivity type pillars are composed of the first epitaxial layers 202 between the second conductivity type pillars 203. The depth of the superjunction trench is less than the thickness of the first epitaxial layer 202, and a buffer layer is formed by the first epitaxial layers 202 located at the bottom of the superstructure.

[0053] Step 3, as follows Figure 2D As shown, the growth of the field oxide layer 205 includes: forming a first oxide layer by a thermal oxidation process and forming a second oxide layer by a CVD process. The field oxide layer 205 is formed by superimposing the first oxide layer and the second oxide layer. The CVD process of the second oxide layer reduces the thermal process of the field oxide layer 205 and the thermal process of the superjunction structure, thereby reducing the PN diffusion of the superjunction structure and reducing the specific on-resistance.

[0054] In some embodiments, the thickness of the first oxide layer is 500 Å to 2000 Å; the thickness of the second oxide layer is 2000 Å to 14000 Å.

[0055] Step 4, as follows Figure 2D As shown, the field oxide layer 205 is patterned and etched for the first time to remove the field oxide layer 205 of the active region 201a. A terminal region 201c surrounds the active region 201a. The terminal region 201c includes a transition region 201b adjacent to the active region 201a.

[0056] In this embodiment of the invention, after the first patterning etching, the innermost part of the field oxide layer 205 in the transition region 201b is also removed, as is the field oxide layer 205 in the cutoff region located at the outermost periphery of the terminal region 201c.

[0057] In some embodiments, after the first patterning etching, the thickness of the retained field oxide layer 205 is retained as the thickness during growth or reduced to 2000 Å to 8000 Å.

[0058] Step 5, as follows Figure 2E As shown, the gate structure of each superjunction device unit is formed. The gate structure is a trench gate, which includes a gate oxide layer 206 and a polysilicon gate 207 formed in the gate trench. The device unit step is the width and spacing of the trench gate. The gate oxide layer 206 is formed by a thermo-oxidative growth process at 900℃ to 950℃ to reduce the thermal process of the superjunction structure and thereby reduce the specific on-resistance.

[0059] In some embodiments, the thickness of the gate oxide layer 206 is 500 Å to 2000 Å.

[0060] The thermo-oxidative growth process of the gate oxide layer 206 includes either a wet thermo-oxidative process or a dry thermo-oxidative process.

[0061] In this embodiment of the invention, a plurality of polysilicon field plates 207a are formed on the top surface of the field oxide layer 205 by polysilicon deposition and patterning etching.

[0062] Step Six, as Figure 2F As shown, ion implantation is performed to form a first well region 204 doped with a second conductivity type in the surface region of the superjunction structure. A trench gate extends longitudinally through the first well region 204, and the surface of the first well region 204 covered by the side of the trench gate is used to form a conductive channel. After the ion implantation of the first well region 204 is completed, rapid thermal annealing is used to activate the first well region 204 or to cancel the annealing activation step of the first well region 204, so as to reduce the thermal process of the superjunction structure and thereby reduce the specific on-resistance.

[0063] In some embodiments, when the first well region 204 is activated by rapid thermal annealing, the rapid thermal annealing process conditions include: a temperature of 1050°C or 1100°C and a time of 30 seconds.

[0064] In this embodiment of the invention, the trench gate superjunction device is an N-type device, the implanted impurity in the first well region 204 includes boron, the implantation energy is 60 keV to 180 keV, and the implantation dose is 1e11cm. -2 ~1e14cm -2 The number of injections is 1, 2, or 3.

[0065] In other embodiments, the following steps can also be implemented: under the condition that the specific on-resistance is reduced to below the first required value, one or more of steps three, five, and six after the formation of the superjunction structure are changed to steps that do not reduce the specific on-resistance, while at least one of steps three, five, and six remains a step that reduces the specific on-resistance.

[0066] When step three is changed to a step that does not reduce the specific on-resistance, it includes: the field oxidation process is entirely formed by thermal oxidation.

[0067] When step five is changed to a step that does not reduce the specific on-resistance, it includes: the gate oxide layer 206 is formed by a high-temperature thermal oxidation growth process of 1050℃~1100℃, and the process time is 30 minutes~60 minutes.

[0068] When step six is ​​changed to a step that does not reduce the specific on-resistance, it includes: activating the first well region 204 by annealing at 1100°C or above for more than 30 minutes.

[0069] Step six also includes: Step 7, as follows Figure 2G As shown, ion implantation of a first conductivity type is performed in the surface region of the first well region 204 of the active region 201a to form a source region 208 that is side-aligned with the corresponding gate structure.

[0070] Step 8, as Figure 2H As shown, an interlayer membrane 209 is formed.

[0071] Step Nine, as Figure 2H As shown, a contact hole opening is formed, including a source contact hole opening 210, which passes through the interlayer film 209 at the top of the source region 208 and the source region 208; the first spacing L1 between the source contact hole opening 210 and the side of the adjacent trench gate is reduced to 0.5 micrometers to 0.6 micrometers.

[0072] With the device cell step size and trench gate width remaining constant, the reduction value of the first pitch L1 is the increase value of the source contact hole width. By increasing the width of the source contact hole, the source contact resistance is reduced and the current density of the source contact hole is reduced at the same time, so as to reduce the specific on-resistance and optimize the EAS capability.

[0073] In this embodiment of the invention, the source contact hole opening is located at a depth of 100 angstroms to 400 angstroms below the top surface of the superjunction structure.

[0074] Step 10, as follows Figure 2H As shown, a well contact injection region 211 with a second conductivity type doped is formed at the bottom of the source contact hole opening 210.

[0075] In this embodiment of the invention, a composite implantation method is used to form the well contact implantation region 211. The composite implantation uses at least two impurities of different molecular weights and second conductivity types. The implantation dose of the high molecular weight impurity in the well contact implantation region 211 is greater than that of the low molecular weight impurity, and the implantation energy of the high molecular weight impurity is less than that of the low molecular weight impurity. The implantation junction depth plus diffusion distance of the low molecular weight impurity in the well contact implantation region 211 is less than the first spacing L1. The doping concentration of the surface region of the well contact implantation region 211 is determined by the implantation dose of the high molecular weight impurity and used to ensure the source contact resistance. The implantation dose of the low molecular weight impurity in the well contact implantation region 211 is used to form the transition layer from the well contact implantation region 211 to the first well region 204 and avoids affecting the threshold voltage of the conductive channel. That is, the implantation dose of the low molecular weight impurity in the well contact implantation region 211 needs to be reduced to not affect the threshold voltage of the conductive channel.

[0076] In this embodiment of the invention, the trench gate superjunction device is an N-type device. The high molecular weight impurity in the well contact implantation region 211 is BF2, and the low molecular weight impurity is B. The implantation energy of BF2 is 20 keV to 25 keV, and the implantation dose is 1e14cm. -2 ~1e15cm -2 The injection energy for B was 40 keV, and the injection dose was 5e13cm. -2 .

[0077] Step 11, as follows Figure 2I As shown, a contact hole is formed by filling the contact hole opening with metal. The source contact hole consists of metal filling the source contact hole opening 210. The filling metal layer includes a blocking layer 212 composed of a Ti layer and a TiN layer stacked together, and a tungsten layer 213 filling the source contact hole opening 210.

[0078] A front metal layer 214 is formed, and a second patterning etching is performed on the front metal layer 214 to form the source and gate.

[0079] like Figure 2J As shown, a passivation layer 215 and a protective layer 216 are formed. Generally, a high-density silicon oxide layer is deposited under plasma conditions as the passivation layer 215, and then a thicker polyimide film is deposited as the protective layer 216. A protective pattern is then formed through photolithography and development, covering the terminal region 201c, the transition region 201b, and part of the active region 201a.

[0080] Next, back-side thinning is performed, and the drain region is formed by the thinned semiconductor substrate 201. Then, a back-side metal layer 217 is deposited to form the drain electrode.

[0081] In this embodiment of the invention, the superjunction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the superjunction device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0082] This invention employs a multi-stage process to reduce the specific on-resistance of a superjunction device. This includes enriching the first epitaxial layer before the superjunction structure is formed, controlling the thermal processes of the field oxide layer, gate oxide layer 206, and first well region 204 after the superjunction structure is formed, and reducing the spacing between the source contact hole and the trench gate (i.e., the first spacing L1) to achieve multi-stage control. This multi-stage control achieves an overall reduction in specific on-resistance, bringing it below a required value (i.e., a first required value). The reduced thermal processes after the superjunction structure formation reduce PN diffusion in the superjunction, improving the device's process window and simultaneously reducing its specific on-resistance. Therefore, this invention improves the device's process window and further reduces its specific on-resistance. For example, each stage of the specific on-resistance reduction process can reduce the specific on-resistance by 5% to 7%, ultimately reducing it by more than 20%. Finally, it also improves the device's cost and performance.

[0083] Because the superjunction structure significantly reduces thermal degradation, the increased density of the first epitaxial layer ensures that the device's breakdown voltage still meets requirements. Furthermore, this invention allows for a gradient doping structure where the first epitaxial layer gradually decreases in doping from bottom to top, further improving both the device's breakdown voltage and specific on-resistance.

[0084] The present invention can also control the thermal process of the field oxide layer, gate oxide layer 206 and first well region 204 after the superjunction structure according to the application needs. Only some steps are steps to reduce the specific on-resistance, and other parts are steps that do not reduce the specific on-resistance. As long as the overall thermal process after the superjunction structure meets the requirements, the specific on-resistance of the device can still meet the required value.

[0085] This invention also breaks through the conventional thinking that limits the spacing between the source contact hole and the trench gate, i.e., the first spacing L1, by reducing the first spacing L1 to 0.5 micrometers to 0.6 micrometers. This allows for the increase of the source contact hole width by reducing the first spacing L1, without increasing the device cell step size or reducing the trench gate width—that is, while maintaining the same device cell step size and trench gate width. The increased width of the source contact hole increases the contact area with the bottom source region 208 and the first well region 204, thereby reducing the source contact resistance and thus lowering the specific on-resistance of the device. Simultaneously, the increased width of the source contact hole also reduces the current density of the source contact hole while maintaining the same source current, thus optimizing the device's EAS capability. Therefore, this invention can maximize the reduction of source contact resistance and simultaneously reduce the current density of the source contact hole while maintaining the same device cell step size and trench gate width, thereby simultaneously reducing specific on-resistance and optimizing EAS capability.

[0086] In this embodiment of the invention, the doping process structure of the well contact implantation region 211 is specially configured according to the first spacing L1. The doping impurities in the well contact implantation region 211 are set as at least two impurities of different molecular weights and second conductivity types, formed by composite implantation of multiple impurities. The implantation energy and dosage of various molecular weights are set according to the size of the first spacing L1 to ensure that the implantation junction depth plus diffusion distance of the small molecular weight impurities in the well contact implantation region 211 is less than the first spacing L1. Since the implantation junction depth plus diffusion distance of the large molecular weight impurities in the well contact implantation region 211 is less than the implantation junction depth plus diffusion distance of the small molecular weight impurities in the well contact implantation region 211, the implantation junction depth plus diffusion distance of the large molecular weight impurities in the well contact implantation region 211 is also less than the first spacing L1. In this way, the doping concentration of the large molecular weight impurities is set higher and shallower to meet the contact resistance requirements without affecting the threshold voltage. The doping concentration of the small molecular weight impurities is lower than that of the large molecular weight impurities and deeper. The characteristic of the reduced concentration of small molecular weight impurities is used to avoid affecting the threshold voltage of the conductive channel, thereby keeping the threshold voltage stable and the distribution of the threshold voltage non-discrete and with good consistency. In the existing structure, the process for various impurities in the well contact injection region 211 is not set according to the first spacing L1 of the present invention. Compared with the embodiment of the present invention, the injection energy and injection dose of various impurities in the well contact injection region 211 of the existing structure are too large. The embodiment of the present invention can eliminate these defects, thereby satisfying the requirements of the contact resistance of the contact hole and the magnitude and distribution of the threshold voltage.

[0087] The device unit stepping in this embodiment of the invention remains unchanged, which ensures that the device integration level and chip area remain unchanged.

[0088] The trench gate width remains unchanged in this embodiment of the invention, which can prevent the adverse effects of reduced trench gate width on increased process complexity, thereby ensuring the consistency of device cells and preventing the deterioration of EAS capability caused by poor consistency of device cells.

[0089] In existing common trench-gate superjunction MOSFET structures, the distance between the metal contact hole and the gate is approximately 0.8 μm to 1 μm. This limits the width of the contact hole (CT), hindering the reduction of CT contact resistance and specific on-resistance. Furthermore, a narrow CT width leads to increased local current density, making it more susceptible to EAS failures such as metallization layer melting and silicon substrate overheating. By reducing the distance between the CT and the gate (i.e., the first spacing L in this embodiment), L1 is reduced to 0.5 μm to 0.6 μm, allowing for a wider CT design. A wider CT design increases the contact area between the CT and the Si epitaxial layer, reducing contact resistance and thus lowering the specific on-resistance. On the other hand, the increased trench cross-sectional area of ​​the CT reduces the current density per unit area. Under the same avalanche current, the current is more dispersed, preventing localized current concentration that could lead to silicon substrate overheating or metallization, thus improving current carrying capacity and heat conduction efficiency and enhancing the device's EAS capability.

[0090] However, as the distance between the contact hole (CT) and the gate (trench gate) decreases, the chip will experience problems such as a high threshold voltage (VTH) and severely dispersed VTH distribution. For example... Figure 3A The image shown is a simulation schematic of an existing trench gate superjunction device. Figure 3A In this diagram, the gate oxide layer is individually designated as 206a, the polysilicon gate as 207a, the first well region as 204b1, the well contact implantation region as 211a, the tungsten layer of the source contact hole as 213a, and the source region as 208a. The distance between the contact hole (CT) and the trench gate is denoted by L0, which equals 0.8 micrometers.

[0091] like Figure 3B The figure shown is a device simulation diagram when using the first spacing of the trench gate superjunction device according to the embodiment of the present invention and the well contact injection region of the existing trench gate superjunction device. Figure 3B In this diagram, the gate oxide layer is individually designated as 206b, the polysilicon gate as 207b, the first well region as 204b2, the well contact injection region as 211b, the tungsten layer of the source contact hole as 213b, and the source region as 208b. L1 is equal to 0.5 micrometers.

[0092] Compare Figure 3A and Figure 3B As shown, Figure 3BThe well contact injection region 211b is closer to the side of the trench gate, which will have a significant impact on the doping concentration of the first well region 204b2 near the side of the trench gate, thus affecting the threshold voltage of the device.

[0093] like Figure 3C As shown, curve 301 is Figure 3A The doping concentration distribution curve of the first well region at line AA is shown in curve 302. Figure 3B The doping concentration distribution curve of the first well region at line AA in the curve shows that the doping concentration in curve 302 will increase, thus the threshold voltage of the device will increase.

[0094] Therefore, through TCAD simulation and experimental data analysis, it can be seen that the P-type ions injected at the bottom of the CT diffuse into the vertical inversion channel region, i.e., the first well region 204b2 on the side of the trench gate, during the thermal process, increasing the P-type doping concentration in the channel region and thus leading to a higher threshold voltage of the chip. In addition, the different thermal processes experienced by the CT at different locations on the wafer lead to differences in the concentration of P-type ions diffused into the channel region, resulting in severe dispersion of the VTH distribution on a single wafer.

[0095] Specifically, the P-type implanted ions at the bottom of the contact hole typically include boron fluoride (BF2) and boron (B). B has a smaller molecular weight and is a light ion, resulting in a longer range at the same energy. A 30keV B implantation depth is approximately 0.5μm, and B has a high diffusion coefficient in silicon (1.5 times that of BF2), increasing the junction depth to 0.7μm after annealing. However, as a light ion, B causes less lattice damage and has a lower defect density after annealing, resulting in better reliability. BF2, on the other hand, has a larger molecular weight and a shorter range at the same implantation energy. A 30keV BF2 implantation depth is approximately 0.2μm, and its diffusion after annealing is small (<0.1μm). However, the B+ generated by BF2 is mainly concentrated on the contact hole surface, easily forming a heavily doped surface layer and achieving lower ohmic contact resistance. Therefore, in actual manufacturing processes, a BF2+B composite implantation is often used, with BF2 forming a high-concentration surface layer and B forming a transition layer, balancing contact resistance and reliability. Therefore, the main reason is that the implantation and diffusion distance of boron (B) is greater than the distance between the tangent (CT) and the gate. As a result, boron ions affect the vertical channel region of the trench gate MOSFET, thus impacting the voltage threshold (VTH). In this case, it is impossible to adjust the VTH of the chip to the target value by reducing the doping concentration of the P-type well.

[0096] like Figure 3D The figure shown is a statistical graph of threshold voltage measurement under the first pitch and various well contact injection region doping conditions of the trench gate superjunction device according to the embodiment of the present invention. Figure 3DIn the diagram, the horizontal axis represents the wafers, and the vertical axis represents the threshold voltage. The statistical values ​​are the threshold voltages on each wafer. Each wafer corresponds to a process condition for a well contact implantation region 211b. Wafers to the left of the dashed line BB are implanted using single-step CT with BF2 as the implanted impurity; wafers to the right of the dashed line BB are implanted using dual-step CT with BF2 plus B as the implanted impurity. Figure 3D The corresponding implantation conditions are also shown. For example, the implantation conditions for wafer W09 are: BF2 implantation energy of 25 keV and implantation dose of 1E15cm. -2 For example, the implantation conditions for wafer W13 are: BF2 implantation energy of 20 keV and implantation dose of 5E14cm. -2 The injection energy for B was 80 keV, and the injection dose was 5E14cm. -2 .

[0097] It can be seen that when L1 shrinks, increasing B injection increases the threshold voltage and makes its distribution more discrete. Therefore, the process conditions of the well contact injection region 211 are very important.

[0098] The common implantation process for the well contact injection region involves first injecting BF2, which can be set to 40 keV and 1e15 / cm. 2 Subsequently, B is implanted, which can be set to 70-80 keV, 1e15 / cm². This composite implantation can better ensure the ohmic contact between the subsequent metal and the Si in the contact hole, reduce contact resistance, and achieve better reliability. In this embodiment of the invention, the ion implantation energy and dose of BF2 at the bottom of the CT are adjusted to 20-25 keV, 1e14-1e15 / cm². 2 The ion implantation energy dose for B was set at 40 keV and 5e13 / cm. 2 This avoids the impact of boron injection and diffusion on the channel region while maintaining a high surface doping concentration, thus not reducing the chip's EAS capability and stability.

[0099] See the improved VTH data. Figure 4 ,like Figure 4 The figure shown is a statistical graph of threshold voltage measurement under the doping conditions of the first pitch and the well contact implantation region of the trench gate superjunction device according to an embodiment of the present invention. Figure 4 In this embodiment, wafer W21 adopts the process conditions of the well contact injection region 211 corresponding to the present invention, and wafer W19 adopts the implantation process of the existing common well contact injection region. It can be seen that the threshold voltage in wafer W21 has not increased and is evenly distributed, i.e., the consistency is good.

[0100] Therefore, it can be observed that the consistency of VTH in the embodiments of the present invention is significantly improved. Further experimental results show that if BF2 is injected alone, the dose is less than 1e15 / cm². 2For example, with 20 keV 5E14, the chip's EAS capability will decrease by 10%. This indicates that the BF2 dose and energy cannot be too low, as this will affect EAS. However, if a composite implantation is used, BF2 20 keV 5E14 + B 80 keV 5E14, the chip's EAS capability is comparable to that of the BSL process. This shows that the addition of B can improve the chip's EAS capability. Therefore, the ion implantation dose at the bottom of the CT cannot be too small, otherwise it will reduce the chip's EAS capability. The main impact on EAS capability is that a too-small ion implantation dose at the bottom of the CT leads to increased contact resistance, which easily generates more Joule heating in local areas, resulting in ineffective avalanche energy dissipation, thus deteriorating the EAS capability.

[0101] To further enhance understanding of the embodiments of the present invention, the manufacturing method of the trench gate superjunction device of the present invention will be further described below using a 600V deep trench superjunction MOSFET as an example: like Figure 2A As shown, a high-resistivity (0.5–5 ohm*cm) N-type epitaxial layer, i.e., the first epitaxial layer 202, is first grown on a highly doped N-type substrate, i.e., a semiconductor substrate 201. The thickness of the first epitaxial layer 202 is 45–50 µm. The highly doped N-type substrate uses phosphorus (P) or arsenic (As) as the dopant, with As atoms being the most common. This reduces the interface state density and the diffusion of N+ substrate impurities into the withstand voltage layer (composed of the N-type epitaxial layer) during subsequent thermal processes. The N-type substrate doping concentration is 1e19 / cm². 2 The purpose of this is to reduce the substrate resistance. N-type epitaxy can be doped with a single doping concentration (monolayer epitaxy), two doping concentrations (bilayer epitaxy), multiple doping concentrations (multilayer epitaxy), or a gradient doping concentration (gradient epitaxy). In actual production design, the resistivity variation of N-type epitaxy, the specific doping concentration, and the interrelationships between doped atom types can be simulated and designed using computer-aided design software like TCAD.

[0102] Existing conventional N-epitaxial growth primarily uses one or two doping concentrations. Taking one or two doping concentrations as an example, the resistivity of a common N-epitaxial layer is approximately 0.8–0.95 ohm·cm at the top and approximately 0.95–1.1 ohm·cm at the bottom. In this example, the dopant atom in the N-epitaxial layer is phosphorus (P). In this embodiment of the invention, by enriching the N-epitaxial layer as a whole, the specific on-resistance is reduced while maintaining the base volume (BV). The N-epitaxial layer can be set as a gradient epitaxial layer from 0.9–1.0 ohm·cm at the bottom to 0.7–0.8 ohm·cm at the top, which is the top portion 202b of the first epitaxial layer 202. The specific thickness of the gradient epitaxial layer can be 42–50 µm. The bottom of the gradient epitaxial layer is a fixed-doping concentration epitaxial buffer layer with a thickness of 0–8 µm, which is the bottom portion 202a of the first epitaxial layer 202, and its concentration is the same as the bottom concentration of the top portion 202b, which corresponds to 0.9–1.0 ohm·cm. By using graded epitaxy, the specific on-resistance of the device can be reduced by 5% to 7%.

[0103] like Figure 2B As shown, a second well region 204a can be formed in the transition region 201b of the chip near the active region 201a through photolithography and ion implantation. The ion implantation type of the second well region 204a is generally boron (B), the implantation energy is 40-200 keV, and the implantation dose is approximately 1e12-1e14 atoms / cm². 2 The second well region 204a can effectively improve the electric field distribution in the transition region 201b between the active region 201a and the terminal region 201c of the chip, thereby improving the reliability of the chip.

[0104] like Figure 2CAs shown, a dielectric film is deposited on the first epitaxial layer 202 to form a hard mask. The hard mask can be a SiO2 layer with a thickness of 500 Å to 1000 Å, a SiN layer with a thickness of 300 Å to 1500 Å, or a SiO2 layer with a thickness of 2 µm to 5 µm. Then, several deep trenches with a certain aspect ratio, i.e., superjunction trenches, are formed in the first epitaxial layer 202 by photolithography. The width of the deep trenches is set to 3.2 µm, the spacing between adjacent deep trenches is set to 3.8 µm, and the depth is set to 40 to 47 µm. Depending on the characteristics of different products and the selection of the epitaxial substrate, the trench width, spacing, and depth can be adjusted accordingly. A buffer layer of a certain thickness needs to be left at the bottom of the trenches to improve the device's resistance to current surges. After the trench morphology is etched, all the SiO2 and SiN on top of the hard mask are removed, leaving the bottom SiO2 as a protective layer for the Si surface. Then, P-type ions can be injected into the bottom of the trench to improve BVDSS. Commonly used P-type ions are B, with energies of 90–180 keV and doses of 1.0–5.0 e12 / cm2. Next, P-type silicon, i.e., the second conductivity type pillar 203, is completely epitaxially filled into the trench. The doping concentration of the P-type silicon is related to the doping concentration and structure of the N-epitaxy substrate. Subsequently, chemical mechanical polishing is used to remove all Si from the surface.

[0105] like Figure 2D As shown, an oxide film, namely a field oxide layer 205, of 2000–15000 Å is formed on the first epitaxial layer 202, which forms the second conductivity type pillars 203, on the Si epitaxial layer. Commonly, a single thermal oxidation can be performed directly on the silicon wafer, i.e., the first epitaxial layer 202 forming the superjunction structure. The thermal oxidation temperature can be set at 900–980°C, and the thickness of the thermally oxidized film, i.e., the field oxide layer 205, is set to 2000–15000 Å. In this embodiment of the invention, the oxide film is grown using a thermal oxidation + CVD method. Compared to the existing common pure thermal oxidation method, this method reduces the thermal process during chip fabrication, effectively reduces the interdiffusion of impurities between P-type and N-type pillars, and thus effectively reduces the specific on-resistance of the chip, lowering the specific on-resistance of the device by approximately 5%–7%. Specifically, a thermal oxidation process is first performed on the silicon wafer. The thermal oxidation temperature can be set between 900 and 980°C, and the thermal oxide film thickness can be set between 500 and 2000 Å. Then, a CVD oxide film (undoped) with a thickness of 2000 to 14000 Å is deposited. After the oxide film has grown, the film layer in the active region 201a needs to be removed by photolithography, dry etching, or wet etching. The dielectric film, i.e., the field oxide layer 205, in the outermost part (cutoff region) of the terminal region 201c is also removed. In other parts of the transition region 201b and the terminal region 201c, the field oxide layer 205 can also be partially etched, leaving a dielectric film thickness of 2000 to 8000 Å. This film layer prevents the device from being broken down by high voltage. Generally, the higher the device's base voltage (BV), the thicker the oxide film is required.

[0106] like Figure 2E As shown, several shallow trenches, i.e., gate trenches, are formed on the N-epitaxy layer through photolithography and etching. The width of the trenches is set to 0.6–1.5 µm, and the depth is set to 2–4 µm. A gate oxide layer 206 is then deposited, with a thickness of approximately 500 Å–2000 Å. Common gate oxide deposition temperatures and times for 206 are 1050°C–1100°C and 30–60 min, which causes interdiffusion of the PN pillars. In this embodiment, the gate oxide growth process is adjusted to a low-temperature growth process of 900–950°C, which can be either a wet or dry gate oxide process. This low-temperature gate oxide process effectively reduces the specific on-resistance of the device by 5–7%. Then, a polysilicon gate 207 is formed through polysilicon deposition and etching. Then, polysilicon field plates 207a can be deposited in the transition region 201b and the terminal region 201c by photolithography and etching as floating field plates to reduce the peak electric field on the chip terminal surface, optimize the electric field distribution, and improve the breakdown voltage of the chip terminal.

[0107] like Figure 2F As shown, a P-type well, i.e., the first well region 204, is formed in the active region 201a by ion implantation. The implanted impurity is generally B, the implantation energy is 60-180 keV, and the implantation dose is 1e11cm. -2 ~1e14cm -2 During production, the threshold voltage of the device can be affected by product characteristics, such as whether it is an irradiated or non-irradiated product, and other process adjustments. The target threshold voltage can be met by adjusting the implantation dose or energy of the first well region 204. This first well region 204 can also be implemented using two or three different energies of B implantation, thus constructing different P-type wells and adjusting device performance parameters, including threshold voltage and EAS capability. After P-type well ion implantation, the conventional process involves a high-temperature annealing, such as annealing at 1100℃ for 30 minutes or higher for a longer time. This pushes the P-type well to the designated position and repairs some damage caused during ion implantation. In this embodiment of the invention, this annealing process is adjusted to a very short activation process such as rapid thermal annealing (RTA), for example, 1100℃ for 30 seconds or 1050℃ for 30 seconds, or this annealing process is omitted entirely. 1100℃ for 30 seconds indicates an annealing temperature of 1100℃ and a time of 30 seconds; the P-well is then activated through a subsequent annealing process. By reducing this thermal process, the specific on-resistance of the device can be further reduced by 5-7%.

[0108] like Figure 2G As shown, source region 8 is formed by photolithography and ion implantation of N-type impurities. Common N-type impurities include phosphorus and arsenic. For example, As is used at 60 keV, with 1–5e15 atoms / cm². 2After ion implantation, an activation process at a temperature of 950°C or less, such as 900°C for 30 minutes, can be used, or a rapid thermal annealing (RTA) process can be employed. In addition to implanting N-type impurities into the active region 201a to form the source region 208, N-type impurities are also implanted into the outermost cutoff region 208a of the chip.

[0109] like Figure 2H As shown, the current metal electrode process mainly involves the deposition of an interlayer film 209, the etching and filling of contact hole openings (including source contact hole opening 210 and terminal contact hole openings 210a and 210b), and the metal electrode deposition process to form a semiconductor-metal ohmic contact. The contact hole consists of metal filling the contact hole opening. Specifically, a dielectric film is first deposited, for example, 2000 angstroms of undoped SiO2, followed by 8000-10000 angstroms of BPSG, and then the contact hole opening is formed by photolithography etching.

[0110] In existing structures, the distance from the contact hole to the gate is approximately 0.8–1 µm. In this embodiment of the invention, this distance, L1, is reduced to 0.5 µm–0.6 µm. The aim is to design a wider contact hole width in the active region 201a while maintaining the same chip area. This reduces the contact resistance of the contact hole and the current density per unit area, while simultaneously optimizing the specific on-resistance and EAS capability. In the active region 201a, the contact hole opening etches away the silicon in the high-concentration N-type region of the contact hole area, with an etching depth of 100–4000 angstroms. In the transition region 201b, the contact hole opening only needs to penetrate the interlayer film 209 and the protective epoxy film, i.e., the field oxide layer 205. The etching depth of the polysilicon in the transition region 201b does not exceed 500 angstroms.

[0111] Subsequently, composite implantation is performed to form a heavily doped well contact implantation region 211 of the second conductivity type at the bottom of the source contact hole opening 210. The composite implantation uses at least two impurities of the second conductivity type with different molecular weights. The implantation dose of the high molecular weight impurity in the well contact implantation region 211 is greater than the implantation dose of the low molecular weight impurity, and the implantation energy of the high molecular weight impurity is less than the implantation energy of the low molecular weight impurity. The implantation junction depth plus diffusion distance of the low molecular weight impurity in the well contact implantation region 211 is less than the first spacing L1. The implantation junction depth plus diffusion distance of the high molecular weight impurity in the well contact implantation region 211 is less than the implantation junction depth plus diffusion distance of the low molecular weight impurity in the well contact implantation region 211. The doping concentration of the surface region of the well contact implantation region 211 is determined by the implantation dose of the high molecular weight impurity and used to ensure the source contact resistance. The implantation dose of the low molecular weight impurity in the well contact implantation region 211 is used to form a transition layer from the well contact implantation region 211 to the first well region and avoids affecting the threshold voltage of the conductive channel. In some embodiments, taking the trench gate superjunction device as an N-type device as an example, the high molecular weight impurity in the well contact implantation region 211 is BF2 and the low molecular weight impurity is B. The implantation energy of BF2 is 20keV to 25keV, and the implantation dose is 1e14cm. -2 ~1e15cm -2 The injection energy for B was 40 keV, and the injection dose was 5e13cm. -2 .

[0112] The common implantation process for the well contact injection region involves first injecting BF2, which can be set to 40 keV and 1e15 / cm. 2 Subsequently, B is implanted, which can be set to 70-80 keV, 1e15 / cm². This composite implantation can better ensure the ohmic contact between the subsequent metal and the Si in the contact hole, reduce contact resistance, and achieve better reliability. In this embodiment of the invention, the ion implantation energy and dose of BF2 at the bottom of the CT are adjusted to 20-25 keV, 1e14-1e15 / cm². 2 The ion implantation energy dose for B was set at 40 keV and 5e13 / cm. 2 This avoids the impact of boron injection and diffusion on the channel region while maintaining a high surface doping concentration, thus not reducing the chip's EAS capability and stability.

[0113] See the improved VTH data. Figure 4 ,like Figure 4 The figure shown is a statistical graph of threshold voltage measurement under the doping conditions of the first pitch and the well contact implantation region of the trench gate superjunction device according to an embodiment of the present invention. Figure 4In this embodiment, wafer W21 uses the process conditions of the well contact implantation region 211 corresponding to the present invention, while wafer W19 uses the commonly used implantation process for well contact implantation regions. It can be seen that the threshold voltage in wafer W21 does not increase and is evenly distributed, i.e., good consistency. Therefore, it can be observed that the VTH consistency of the present invention is significantly improved. Furthermore, experimental results show that if only BF2 is implanted, the dose is less than 1e15 / cm². 2 For example, with 20 keV 5E14, the chip's EAS capability will decrease by 10%. This indicates that the BF2 dose and energy cannot be too low, as this will affect EAS. However, if a composite implantation is used, BF2 20 keV 5E14 + B 80 keV 5E14, the chip's EAS capability is comparable to that of the BSL process. This shows that the addition of B can improve the chip's EAS capability. Therefore, the ion implantation dose at the bottom of the CT cannot be too small, otherwise it will reduce the chip's EAS capability. The main impact on EAS capability is that a too-small ion implantation dose at the bottom of the CT leads to increased contact resistance, which easily generates more Joule heating in local areas, resulting in ineffective avalanche energy dissipation, thus deteriorating the EAS capability.

[0114] like Figure 2H As shown, platinum (Pt) is then doped through the source contact hole opening 210 and annealed. Doping can be done via ion implantation or diffusion. The annealing temperature can be set to 800–950°C, allowing Pt atoms to diffuse and occupy interstitial or substituted sites in the silicon lattice, forming deep-level defects. This increases the carrier recombination rate, reduces the reverse recovery time, and improves the reverse recovery characteristics of the chip diode. In this step, the reverse recovery characteristics of the chip diode can be adjusted by optimizing the Pt doping concentration and annealing temperature.

[0115] like Figure 2IAs shown, a blocking layer 212 is formed by depositing a Ti layer and a TiN layer stacked together. One setting is that the thickness of the Ti layer is 300 Å to 500 Å, and the thickness of the TiN layer is 500 Å to 1000 Å, to prevent Si from dissolving in AlCu and forming sharp protrusions. The layer is then annealed. Next, a tungsten (W) layer 213 is deposited to fill the contact hole opening. The tungsten fills the contact hole opening by growing along the sidewall of the opening and contacting the central region of the opening. The contact area may or may not have gaps. The tungsten can completely fill the contact hole opening, or it may not, as long as the subsequent metal layer can effectively cover the opening. Then, a front-side metal layer 214, such as AlCu, is deposited. The deposition temperature can be set to 250–450 °C, and the thickness can be set to 2–6 µm. Finally, the AlCu, the underlying W, and the blocking layer 212 are completely removed using metal photolithography and dry etching. In the metal etching step, the metals in the active region 201a, transition region 201b, and terminal region 201c need to be separated. The metal in the transition region 201b can be a single piece, or it can be two or three separate pieces, etc. The metal in the terminal region 201c can be separated, or it can be continuous, or there can be no metal forming a field plate.

[0116] like Figure 2J The diagram illustrates the fabrication process of passivation layer 215 and protective layer 216. Typically, a high-density silicon oxide layer is deposited under plasma conditions as the passivation layer 215, followed by the deposition of a thicker polyimide film as the protective layer 216. Photolithography and development are then used to form a protective pattern covering the terminal region 201c, transition region 201b, and part of the active region 201a. The thickness of the polyimide layer after baking is 4–15 µm. Next, backside thinning is performed, resulting in a silicon wafer (semiconductor substrate) thickness of 60–200 µm. A backside metal layer 217 is then deposited to form the drain. The backside metal layer 217 can be TiNiAg, with thicknesses set to 1000 Å for Ti, 2000 Å for Ni, and 10000 Å for Ag.

[0117] In some improved embodiments, electron irradiation can be performed to improve the reverse recovery characteristics of the chip's body diode without depositing and thermally diffusing Pt. Electron irradiation can be performed after the passivation layer process, followed by the polyimide process; however, processes such as polyimide baking may affect the effectiveness of electron irradiation. Alternatively, electron irradiation can be introduced after the polyimide process, followed by setting appropriate dosage and annealing conditions, for example: a dosage of 60–300 kgy, and annealing conditions including a temperature of 300–380°C and a time of 30–300 min.

[0118] In some improved embodiments, the P-type well of the transition region 201b (i.e., the second well region 204a) and the first well region 204 of the active region 201a can also be formed by another method. That is, between the formation steps of the superjunction structure and the field oxide layer 205, the P-type wells of the transition region 201b and the active region 201a can be formed simultaneously through photolithography and ion implantation. The advantage of simultaneously forming the P-type wells of the transition region 201b and the active region 201a is that it reduces the number of process steps and ensures that the P-type well morphologies of the active region 201a and the transition region 201b are consistent. The advantage of separately forming the P-type wells of the transition region 201b and the active region 201a is that the P-type well morphologies of the active region 201a and the transition region 201b can be adjusted separately. In the two formation methods, if the same threshold voltage is to be achieved, the method of forming the P-type traps of the transition region 201b and the active region 201a separately requires a higher concentration of P-type ion implantation dose because the P-type trap of the active region 201a will undergo more thermal diffusion processes.

[0119] In the method of this invention embodiment, only one contact hole is formed between the two gates, i.e., the trench gate. Alternatively, two, three, or more contact holes can be designed between the two gates.

[0120] In this embodiment of the invention, an N-type device is used. The type of CT injection, i.e., the trap contact injection region 211, is BF2, B. Injection can be performed using a combination of methods or a single method. The general principle is that the dose and energy of the P-type CT injection should not be too high or too low. Too high a dose will affect the channel region of the device, while too low a dose will affect the device's EAS capability and reliability. The specific energy and dose need to be coordinated with the actual process.

[0121] This invention provides a method to reduce specific on-resistance by minimizing the thermal processes following the formation of the PN pillar, i.e., superjunction structure. Specifically, the reduced thermal processes can be the same as those listed above in this invention, namely, simultaneously reducing the thermal processes of thermal oxide film formation, gate oxide growth, and P-type well annealing. Other embodiments may only implement any single step or any two steps mentioned above.

[0122] This invention also implements a method for reducing specific on-resistance by increasing the doping concentration of N-epitaxy, where the specific N-epitaxy concentration distribution can be gradient epitaxy. Other embodiments may also involve single-layer, double-layer, or multi-layer N-epitaxy.

[0123] Furthermore, in this embodiment of the invention, the reduction in PN diffusion in the first epitaxial layer allows for the maintenance of the breakdown voltage (BV) while increasing the doping concentration of the first epitaxial layer. Conversely, in this embodiment of the invention, the BV can also be increased by overall lightening the N-epitaxy layer. For example, lightening the N-epitaxy layer doping concentration by about 10% can increase the BV by about 50V, thereby achieving a device BV of 650V. Similarly, a device BV of 700V can also be achieved using this method.

[0124] In this embodiment of the invention, by adjusting the doping concentration of the N-epitaxy and minimizing the high-temperature thermal process after PN pillar formation (e.g., setting it below 980°C, or using only a very short activation process such as RTA), the mutual diffusion between PN pillars is greatly reduced, thus mitigating the PN charge imbalance caused by concentration differences. This embodiment of the invention improves the device process window and reduces the specific on-resistance by approximately 20%. This significantly improves the cost and performance of trench gate superjunction MOSFETs. Furthermore, by appropriately reducing the P-type ion implantation dose or energy at the bottom of the CT, this embodiment of the invention effectively addresses the high threshold voltage (VTH) and dispersion issues when the CT is close to the gate, further reducing the specific on-resistance, improving EAS capability, and enhancing device consistency.

[0125] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a trench gate superjunction device, characterized in that, The multi-stage reduction of the specific on-resistance of the superjunction device is carried out to reduce the specific on-resistance to below a first required value. The multi-stage reduction of the specific on-resistance includes: Step 1: Provide a first epitaxial layer doped with a first conductivity type. By increasing the doping concentration of the first epitaxial layer, the breakdown voltage of the device can meet the requirements while reducing the specific on-resistance. Step 2: A superjunction structure is formed in the first epitaxial layer. The superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars. The second conductivity type pillars are composed of second epitaxial layers doped with the second conductivity type and filled in the superjunction trench. The superjunction trench is formed in the first epitaxial layer, and the first conductivity type pillars are composed of the first epitaxial layers between the second conductivity type pillars. The depth of the superjunction trench is less than the thickness of the first epitaxial layer, and a buffer layer is formed by the first epitaxial layer located at the bottom of the superstructure. Step 3: Growing a field oxide layer, including: forming a first oxide layer using a thermal oxidation process and forming a second oxide layer using a CVD process, the field oxide layer is formed by superimposing the first oxide layer and the second oxide layer, the CVD process of the second oxide layer reduces the thermal process of the field oxide layer and the thermal process of the superjunction structure, thereby reducing the PN diffusion of the superjunction structure and reducing the specific on-resistance; Step 4: Perform a first patterned etching on the field oxide layer to remove the field oxide layer in the active region. A terminal region surrounds the active region, and the terminal region includes a transition region adjacent to the active region. Step 5: Form the gate structure of each superjunction device unit. The gate structure is a trench gate, which includes a gate oxide layer and a polysilicon gate formed in the gate trench. The device unit step is the width and spacing of the trench gate. The gate oxide layer is formed using a thermo-oxidative growth process at 900℃ to 950℃ to reduce the thermal process of the superjunction structure and thereby reduce the specific on-resistance. Step 6: Perform ion implantation to form a first well region doped with a second conductivity type in the surface region of the superjunction structure. The trench gate extends longitudinally through the first well region, and the surface of the first well region covered by the side of the trench gate is used to form a conductive channel. After the ion implantation of the first well region is completed, a rapid thermal annealing is used to activate the first well region or to deactivate the annealing activation step of the first well region, so as to reduce the thermal process of the superjunction structure and thereby reduce the specific on-resistance. Step 7: Perform ion implantation of the first conductivity type to form a source region aligned with the side of the corresponding gate structure in the surface region of the first well region of the active region; Step 8: Forming an interlayer membrane; Step 9: Forming a contact hole opening, the contact hole opening including a source contact hole opening, the source contact hole opening passing through the interlayer film at the top of the source region and the source region; reducing the first spacing between the source contact hole opening and the side of the adjacent trench gate to 0.5 micrometers to 0.6 micrometers; Under the condition that the device cell step and the trench gate width remain unchanged, the reduction value of the first pitch is the increase value of the source contact hole width. The source contact resistance is reduced and the current density of the source contact hole is reduced by increasing the width of the source contact hole, so as to reduce the specific on-resistance and optimize the EAS capability at the same time. Step 10: Form a well contact implantation region doped with a second conductivity type at the bottom of the source contact hole opening; Step 11: Fill the contact hole opening with metal to form a contact hole, wherein the source contact hole is composed of metal filled in the source contact hole opening.

2. The method for manufacturing the trench gate superjunction device as described in claim 1, characterized in that: In step one, the first epitaxial layer adopts a single-layer doped structure, a double-layer doped structure, or a graded-doped structure; the graded-doped structure includes: The bottom portion of the first epitaxial layer is doped with a fixed doping concentration, and the top portion of the first epitaxial layer is doped with a gradually decreasing doping concentration from the bottom surface to the top surface. The doping concentration at the bottom surface of the top portion of the first epitaxial layer is the same as the doping concentration at the bottom portion of the first epitaxial layer.

3. The method for manufacturing the trench gate superjunction device as described in claim 2, characterized in that: The thickness of the bottom portion of the first epitaxial layer is 0 micrometers to 8 micrometers, and the thickness of the top portion of the first epitaxial layer is 42 micrometers to 50 micrometers; The resistivity of the bottom surface of the top portion of the first epitaxial layer is 0.9 ohm·cm to 1.0 ohm·cm and the resistivity of the top surface of the top portion of the first epitaxial layer is 0.7 ohm·cm to 0.8 ohm·cm.

4. The method for manufacturing the trench gate superjunction device as described in claim 2, characterized in that: The buffer layer is located at least partially in the bottom portion of the first epitaxial layer.

5. The method for manufacturing the trench gate superjunction device as described in claim 1, characterized in that: In step three, the thickness of the first oxide layer is 500 Å to 2000 Å; the thickness of the second oxide layer is 2000 Å to 14000 Å.

6. The method for manufacturing the trench gate superjunction device as described in claim 5, characterized in that: In step four, after the first patterning etching, the innermost part of the field oxide layer in the transition region is also removed, as is the field oxide layer in the cutoff region located at the outermost periphery of the terminal region. After the first patterning etching, the thickness of the field oxide layer is retained as it was during growth or reduced to 2000 Å to 8000 Å.

7. The method for manufacturing a trench gate superjunction device as described in claim 1, characterized in that: In step five, the thickness of the gate oxide layer is 500 Å to 2000 Å; The thermo-oxidative growth process of the gate oxide layer includes a wet thermo-oxidation process or a dry thermo-oxidation process.

8. The method for manufacturing a trench gate superjunction device as described in claim 1, characterized in that: In step six, when the first well region is activated by the rapid thermal annealing, the process conditions for the rapid thermal annealing include: a temperature of 1050°C or 1100°C and a time of 30 seconds.

9. The method for manufacturing the trench gate superjunction device as described in claim 1, characterized in that: Under the condition that the specific on-resistance is reduced to below the first required value, one or more of steps three, five, and six after the formation of the superjunction structure are changed to steps other than steps that reduce the specific on-resistance, while at least one of steps three, five, and six remains a step that reduces the specific on-resistance.

10. The method for manufacturing the trench gate superjunction device as described in claim 9, characterized in that: When step three is changed to a step other than reducing the specific on-resistance, it includes: the field oxidation process is entirely formed by thermal oxidation.

11. The method for manufacturing a trench gate superjunction device as described in claim 9, characterized in that: When step five is changed to a step other than reducing the specific on-resistance, it includes: the gate oxide layer is formed by a high-temperature thermal oxidation growth process of 1050℃~1100℃, and the process time is 30 minutes~60 minutes.

12. The method for manufacturing a trench gate superjunction device as described in claim 9, characterized in that: When step six is ​​changed to a step other than reducing the specific on-resistance, it includes: activating the first well region using an annealing process at 1100°C or higher for 30 minutes or more.

13. The method for manufacturing the trench gate superjunction device as described in claim 1, characterized in that: In step ten, the well contact implantation region is formed using composite implantation. The composite implantation employs at least two impurities of different molecular weights and second conductivity types. In the well contact implantation region, the implantation dose of the high molecular weight impurity is greater than that of the low molecular weight impurity, and the implantation energy of the high molecular weight impurity is less than that of the low molecular weight impurity. The implantation junction depth plus diffusion distance of the low molecular weight impurity in the well contact implantation region is less than the first spacing. The doping concentration of the surface region of the well contact implantation region is determined by the implantation dose of the high molecular weight impurity and used to ensure the source contact resistance. The implantation dose of the low molecular weight impurity in the well contact implantation region is used to form a transition layer from the well contact implantation region to the first well region and to avoid affecting the threshold voltage of the conductive channel.

14. The method for manufacturing a trench gate superjunction device as described in claim 13, characterized in that: The source contact hole opening is located at a depth of 100 angstroms to 400 angstroms below the top surface of the superjunction structure.

15. The method for manufacturing a trench gate superjunction device according to any one of claims 1 to 14, characterized in that: The trench gate superjunction device is an N-type device with N-type as the first conductivity type and P-type as the second conductivity type; or, the trench gate superjunction device is a P-type device with P-type as the first conductivity type and N-type as the second conductivity type.

16. The method for manufacturing a trench gate superjunction device as described in claim 15, characterized in that: The trench gate superjunction device is an N-type device. The high molecular weight impurity in the well contact implantation region is BF2, and the low molecular weight impurity is B. The implantation energy of BF2 is 20 keV to 25 keV, and the implantation dose is 1e14cm. -2 ~1e15cm -2 The injection energy for B was 40 keV, and the injection dose was 5e13cm. -2 .

17. The method for manufacturing a trench gate superjunction device as described in claim 16, characterized in that: The implanted impurity in the first well region includes B, the implantation energy is 60 keV to 180 keV, and the implantation dose is 1e11cm. -2 ~1e14cm -2 The number of injections is 1, 2, or 3.

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