HKMG threshold voltage adjusting method

Abstract

The invention discloses a threshold voltage adjusting method of an HKMG. The threshold voltage adjusting method comprises the steps of 1, completing a process ring of a P-type metal gate so as to form a patterned work function TiN layer on a semiconductor substrate on which a TaN barrier layer is formed; the semiconductor substrate comprises multiple levels of threshold voltage regions, the thicknesses of work function TiN layers of the threshold voltage regions are different, the threshold voltage regions are divided into multiple CPP regions according to different CPP, and the CPP enables the thicknesses of the work function TiN layers of the CPP regions in the threshold voltage regions to generate a first difference. And 2, selective etching with the etching selection ratio of TaN to TiN larger than 1 is carried out through WCl5, and in selective etching, CPP can generate a second influence on the etching thickness of the work function TiN layer so that the first difference can be reduced. And thirdly, a work function TiAl layer is formed. According to the invention, the threshold voltages of different CPP regions can be cooperatively regulated and controlled, the filling thickness of the work function material is reduced, a work function material filling window is effectively expanded, the threshold voltage regulation and control range is expanded, and a reliability test window is expanded.

Description

Technical Field

[0001] This invention relates to a method for semiconductor integrated circuits, and more particularly to a threshold voltage regulation method for a high dielectric constant (HK) metal gate (MG). Background Technology

[0002] In advanced CMOS technology, the critical polypitch (CPP) affects chip density, performance, and energy efficiency. CPP is the sum of the width and pitch of the polysilicon gate. Currently, metal gate manufacturing processes primarily adjust the thickness of the TiN / TiAl work function material in different regions of the metal gate through multiple cycles of deposition (dep), photolithography (PH), and etching (etch) to achieve zoned voltage regulation. As critical dimensions shrink, the challenge lies in the need to coordinately control the threshold voltage of different polysilicon pitches to achieve the target value.

[0003] like Figure 1 The diagram shown is a flowchart of an existing HKMG threshold voltage adjustment method; as shown... Figures 2A to 2B The diagram shows the device structure schematics for each step of the existing HKMG threshold voltage adjustment method; the existing HKMG threshold voltage adjustment method includes:

[0004] A semiconductor substrate 101 is provided, on which an interface (IL) layer 102, a high dielectric constant (HK) layer 103 and a cap (Cap) TiN layer 104 are formed, and a TaN barrier layer 105 is formed on the top surface of the cap TiN layer 104.

[0005] Next, the process loop for the P-type metal gate (PMG) begins, which includes repeating multiple cyclic process steps, said cyclic process steps including:

[0006] Step S101: Deposit work function (PWF) TiN layering, which is PWF TiN dep.

[0007] Step S102: Deposit the BARC layer, and then perform a photolithography (PH) process to define the patterned etched region of the work function TiN layer.

[0008] Step S103: Etch (ET) the BARC layer to form an opening, i.e., Barc open.

[0009] Step S104 involves using the BARC layer as a mask to etch the work function TiN layer to achieve patterned etching of the work function TiN layer, thereby removing the work function TiN layer (RM) in the etched area, i.e., PWFTiN RM.

[0010] Step S105: Use dry etching and stripping to remove the photoresist formed by the photolithography process, i.e., Drystrip.

[0011] Step S106: Perform wet stripping.

[0012] The work function TiN layer 105 in each region is formed by stacking work function TiN layers above the zero layer, and the work function TiN layer 105 in each region is determined by the stacking thickness of each work function TiN layer included therein. A zero-layer work function TiN layer indicates that no work function TiN layer 105 has been formed. Figure 1 In this context, the cyclic process step is repeated 5 times. The cyclic process step is represented by PMGloop, and PMGloop*5 means repeating the cyclic process step 5 times.

[0013] like Figure 2A As shown, the gate work function includes six values, and the corresponding threshold voltages are: NULVT, NLVT, NSVT, PSVT, PLVT and PULVT. The regions corresponding to these six threshold voltages are regions 101a, 101b, 101c, 101d, 101e and 101f, respectively.

[0014] Wherein, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NUSVT is the standard threshold voltage of NMOS.

[0015] PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PUSVT is the standard threshold voltage of PMOS.

[0016] In the NULVT region, after step S101 of the 5th PMG loop is formed, the work function TiN layers 105c, 105d, and 105e are sequentially superimposed. However, as... Figure 2B As shown, after step S106 of the 5th PMG loop is completed, the work function TiN layers 105c, 105d and 105e in the NULVT region are removed, so the work function TiN layer 105 is not formed in the end.

[0017] In the NLVT region, the work function TiN layer 105 is composed of the work function TiN layer 105e of the fifth cycle process step.

[0018] In the NSVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 105d and 105e from the fourth and fifth cycle process steps.

[0019] In the PSVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 105c, 105d and 105e from the third to fifth cycle process steps.

[0020] In the PLVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 105b, 105c, 105d and 105e from the second to fifth cycle process steps.

[0021] In the PULVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 05a, 05b, 105c, 105d and 105e from the first to the fifth cycle process steps.

[0022] Then proceed as follows:

[0023] Step S107 forms the functional TiAl layer, i.e., TiAl dep.

[0024] In existing methods, CPP also affects the threshold voltage. Within the same threshold voltage region, the threshold voltages in different regions of each CPP cannot all reach the target value.

[0025] like Figure 3A The figure shows the curve of NULVT as a function of CPP obtained by the existing threshold voltage adjustment method of HKMG; Figure 3A In the figure, the horizontal axis is CPP, the vertical axis is NULVT, curve 301a is the target curve, and curve 301b is the curve corresponding to the existing method. It can be seen that when CPP increases, curve 301b will deviate from curve 301a and the deviation value is large.

[0026] like Figure 3B The figure shows the curve of PULVT as a function of CPP obtained by the existing threshold voltage adjustment method of HKMG. Figure 3B In the figure, the horizontal axis is CPP, the vertical axis is PULVT, curve 302a is the target curve, and curve 302b is the curve corresponding to the existing method. It can be seen that when CPP increases, curve 302b will deviate from curve 302a and the deviation value is large. Summary of the Invention

[0027] The technical problem to be solved by the present invention is to provide a threshold voltage adjustment method for HKMG, which can coordinately regulate the threshold voltage of different CPP regions so that the threshold voltage of each CPP region reaches the target value; it can also reduce the filling thickness of the work function material, thereby effectively expanding the work function material filling window and expanding the adjustable range of threshold voltage; and it can also expand the reliability test window.

[0028] To solve the above-mentioned technical problems, the threshold voltage adjustment method for HKMG provided by the present invention includes:

[0029] Step 1: Complete the process loop of the P-type metal gate (PMG) to form a patterned work function TiN layer on a semiconductor substrate with a TaN barrier layer. The semiconductor substrate includes multiple threshold voltage regions, each with a different thickness of the work function TiN layer. The threshold voltage of each threshold voltage region is first controlled by adjusting the thickness difference of the work function TiN layer. Each threshold voltage region is divided into multiple CPP regions according to the different CPPs, where CPPs are key polysilicon steps. The CPPs have a first impact on the growth thickness of the work function TiN layer, causing a first difference in the thickness of the work function TiN layer in each CPP region within each threshold voltage region.

[0030] Step 2: Perform selective etching with a first etching selectivity greater than 1. The first etching selectivity is the etching selectivity of TaN to TiN. The etching gas used for selective etching is WCl5. The selective etching thins the work function TiN layer and / or the TaN barrier layer in each threshold voltage region to achieve a second regulation of the threshold voltage in each threshold voltage region.

[0031] In the selective etching, the CPP will have a second effect on the etching thickness of the work function TiN layer. Taking advantage of the fact that the effect of the second effect on the first difference is exactly the opposite of the effect of the first effect on the first difference, the first difference is reduced.

[0032] Step 3: Form the functional TiAl layer to make the threshold voltage of each threshold voltage region reach the target value.

[0033] A further improvement is that the process loop of the P-type metal gate includes repeated cyclic process steps, wherein the cyclic process steps include:

[0034] Deposition work function TiN stratification.

[0035] The work function TiN layers are patterned and etched.

[0036] A further improvement is that, in step one, the work function TiN layer in each threshold voltage region is formed by stacking work function TiN layers above the zero layer, and the work function TiN layer in each threshold voltage region is determined by the stacking thickness of each work function TiN layer included.

[0037] A further improvement is that, prior to the patterned etching of the work function TiN layers, the following steps are included:

[0038] Deposit BARC layer.

[0039] A photolithography process is performed to define the patterned etching region of the work function TiN layer, and then the BARC layer is etched.

[0040] Subsequently, the work function TiN layer is etched using the BARC layer as a mask to achieve patterned etching of the work function TiN layer.

[0041] A further improvement is that the etching of the work function TiN layer includes wet etching.

[0042] A further improvement is that, in step eight, the cyclic process step is repeated five times.

[0043] A further improvement is that the threshold voltages corresponding to each of the threshold voltage regions are: NULVT, NLVT, NSVT, PSVT, PLVT, and PULVT.

[0044] Wherein, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NUSVT is the standard threshold voltage of NMOS.

[0045] PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PUSVT is the standard threshold voltage of PMOS.

[0046] After step one is completed, the work function TiN layers in the threshold voltage region are as follows:

[0047] In the NULVT region, the work function TiN layer is not formed.

[0048] In the NLVT region, the work function TiN layer is composed of the work function TiN layer of the fifth cycle process step.

[0049] In the NSVT region, the work function TiN layer is formed by stacking the work function TiN layers from the fourth and fifth cycle process steps.

[0050] In the PSVT region, the work function TiN layer is formed by stacking the work function TiN layers from the third to the fifth cycle process steps.

[0051] In the PLVT region, the work function TiN layer is formed by stacking the work function TiN layers from the second to the fifth cycle process steps.

[0052] In the PULVT region, the work function TiN layer is formed by stacking the work function TiN layers from the first to the fifth cycle process steps.

[0053] A further improvement is that, in step two, in the NULVT region, the selective etching directly etches the TaN barrier layer, and the maximum etching amount of the TaN barrier layer is such that the TaN barrier layer is completely removed.

[0054] In the NLVT region, the selective etching first etches the work function TiN layer and then etches the TaN blocking layer, thereby partially removing the TaN blocking layer.

[0055] In the NSVT region, the selective etching etches the work function TiN layer, and the work function TiN layer is completely or partially etched. When the work function TiN layer is completely etched, the TaN barrier layer is not etched or is partially etched.

[0056] The work function TiN layers in the PSVT region, PLVT region, and PULVT region are all partially etched, and the thickness of the work function TiN layers in the PSVT region, PLVT region, and PULVT region increases sequentially.

[0057] A further improvement is that the selective etching time is 5s to 60s.

[0058] A further improvement is that the first etching selectivity ratio is 3:1 to 10:1.

[0059] A further improvement is that the first etching selectivity ratio varies with the time of the selective etching, and as time increases, the first etching selectivity ratio decreases from 10:1 to 3:1.

[0060] A further improvement is that the first etching selectivity is adjusted by regulating the flow rate, pressure, reaction temperature, and time of the selectively etched WCl5.

[0061] A further improvement is that, in step two, the reduction in the first difference is greater than 1 nm.

[0062] A further improvement is that, in step three, the thickness of the work function TiAl layer is reduced according to the amount of reduction in the thickness of the work function TiN layer in step two.

[0063] A further improvement is that, in step one, an interface layer, a high dielectric constant layer, and a capping TiN layer are also formed on the semiconductor substrate, and the TaN barrier layer is formed on the top surface of the capping TiN layer.

[0064] This invention, based on the initial regulation of threshold voltage in each threshold voltage region by forming work function TiN layers of different thicknesses through a P-type metal gate process ring, performs selective etching of TiN using WCl5-based TaN. This selective etching allows for differences in the thickness reduction of the work function TiN layer in different CPP regions, thereby compensating for the initial difference in the thickness of the work function TiN layer in different CPP regions during step one and ultimately reducing this initial difference. Thus, this invention can synergistically regulate the threshold voltage in different CPP regions, ensuring that the threshold voltage in each CPP region reaches the target value.

[0065] In this invention, selective etching of TiN with WCl5-based TaN can reduce the thickness of the work function TiN layer. At the same time, since the thickness of the work function TiN layer is reduced, the thickness of the work function TiAl layer corresponding to the target value will also be reduced accordingly. Therefore, this invention can ultimately reduce the filling thickness of the work function material, thereby effectively expanding the filling window of the work function material and expanding the adjustable range of the threshold voltage.

[0066] In this invention, the N content is reduced because the thickness of the work function TiN layer and the corresponding region of the TaN barrier layer are reduced. At the same time, the Al content is also reduced because the thickness of the work function TiAl layer is reduced. The reduction of N and Al content can expand the reliability test window, such as the test window for negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB). Attached Figure Description

[0067] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0068] Figure 1 This is a flowchart of the existing threshold voltage adjustment method for HKMG;

[0069] Figures 2A-2B This is a schematic diagram of the device structure in each step of the existing HKMG threshold voltage adjustment method;

[0070] Figure 3A The curve of NULVT versus CPP obtained by the existing HKMG threshold voltage adjustment method;

[0071] Figure 3B The curve of PULVT versus CPP obtained by the existing HKMG threshold voltage adjustment method is shown.

[0072] Figure 4 This is a flowchart of the threshold voltage adjustment method for HKMG according to an embodiment of the present invention;

[0073] Figure 5 This is a flowchart of the threshold voltage adjustment method for HKMG according to a preferred embodiment of the present invention;

[0074] Figures 6A-6C This is a schematic diagram of the device structure in each step of the threshold voltage adjustment method of HKMG according to an embodiment of the present invention;

[0075] Figure 7A The curve of NULVT versus CPP obtained by the threshold voltage adjustment method of HKMG in this embodiment of the invention;

[0076] Figure 7B This is the curve of PULVT versus CPP obtained by the threshold voltage adjustment method of HKMG in this embodiment of the invention. Detailed Implementation

[0077] like Figure 4 The diagram shown is a flowchart of the threshold voltage adjustment method for HKMG according to an embodiment of the present invention; as shown Figure 5 The diagram shown is a flowchart of a preferred embodiment of the threshold voltage adjustment method for HKMG according to the present invention; as shown... Figures 6A to 6C The diagram shown is a schematic representation of the device structure in each step of the threshold voltage adjustment method for HKMG according to an embodiment of the present invention; the threshold voltage adjustment method for HKMG according to an embodiment of the present invention includes:

[0078] Step 1, such as Figure 6A As shown, the process loop for completing the P-type metal gate is used to form a patterned work function TiN layer 206 on a semiconductor substrate 201 with a TaN barrier layer 205. The work function TiN layer 206 is a P-type work function layer (PWF). The semiconductor substrate 201 includes multiple threshold voltage regions. The thickness of the work function TiN layer 206 in each threshold voltage region is different, and the threshold voltage of each threshold voltage region is first controlled by adjusting the thickness difference of the work function TiN layer 206. According to the different CPP, each threshold voltage region is divided into multiple CPP regions. The CPP is the critical polysilicon step, that is, the sum of the width of the polysilicon gate and the spacing of the polysilicon gate. The metal gate is formed in the region after the polysilicon gate is removed. The CPP will have a first influence on the growth thickness of the work function TiN layer 206, causing a first difference in the thickness of the work function TiN layer 206 in each CPP region within each threshold voltage region.

[0079] In this embodiment of the invention, an interface (IL) layer 202, a high dielectric constant (HK) layer 203 and a cap (Cap) TiN layer 204 are also formed on the semiconductor substrate 201, and the TaN barrier layer 205 is formed on the top surface of the cap TiN layer 204.

[0080] The process loop of the P-type metal gate includes repeated cyclic process steps, wherein the cyclic process steps include:

[0081] Deposition work function TiN stratification. Figure 5 In the preferred embodiment shown, this step is step S201, PWF TiNdep.

[0082] The work function TiN layers are patterned and etched.

[0083] Before performing patterned etching on the work function TiN layer, the following steps are also included:

[0084] Deposit BARC layer.

[0085] A photolithography (PH) process is performed to define the patterned etching regions of the work function TiN layer. Figure 5 In the preferred embodiment shown, this step is step S202, PH.

[0086] The BARC layer is then etched (ET) to form an opening. Figure 5 In the preferred embodiment shown, this step is step S203, Barc open.

[0087] Subsequently, the work function TiN layer is etched using the BARC layer as a mask to achieve patterned etching of the work function TiN layer, thereby removing (RM) the work function TiN layer in the etched region. Preferably, the etching of the work function TiN layer includes wet etching. Figure 5 In the preferred embodiment shown, this step is step S204, PWF TiN RM.

[0088] This then includes removing the photoresist formed during the photolithography process using dry etching and stripping. Figure 5 In the preferred embodiment shown, this step is step S205, Dry strip.

[0089] Then, wet stripping is performed. Figure 5 In the preferred embodiment shown, this step is step S206, Wet strip.

[0090] The work function TiN layer 205 in each region is formed by stacking work function TiN layers above the zero layer, and the work function TiN layer 205 in each region is determined by the stacking thickness of each work function TiN layer included. A zero-layer work function TiN layer indicates that no work function TiN layer 205 has been formed. In step one, the cyclic process step is repeated 5 times. Figure 5 In this context, the cyclic process step is represented by PMG loop, and PMG loop*5 means repeating the cyclic process step 5 times.

[0091] like Figure 6A As shown, the gate work function includes six values, and the corresponding threshold voltages are: NULVT, NLVT, NSVT, PSVT, PLVT and PULVT. The regions corresponding to these six threshold voltages are regions 201a, 201b, 201c, 201d, 201e and 201f, respectively.

[0092] Wherein, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NUSVT is the standard threshold voltage of NMOS.

[0093] PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PUSVT is the standard threshold voltage of PMOS.

[0094] In the NULVT region, after step S201 of the 5th PMG loop is formed, the work function TiN layers 205c, 205d, and 205e are sequentially superimposed. However, as... Figure 6B As shown, after step S206 of the 5th PMG loop is completed, the work function TiN layers 205c, 205d and 205e in the NULVT region are removed, so the work function TiN layer 205 is not formed in the end.

[0095] In the NLVT region, the work function TiN layer 205 is composed of the work function TiN layer 205e of the fifth cycle process step.

[0096] In the NSVT region, the work function TiN layer 205 is formed by superimposing the work function TiN layers 205d and 205e from the fourth and fifth cycle process steps.

[0097] In the PSVT region, the work function TiN layer 205 is formed by superimposing the work function TiN layers 205c, 205d and 205e from the third to fifth cycle process steps.

[0098] In the PLVT region, the work function TiN layer 205 is formed by superimposing the work function TiN layers 205b, 205c, 205d and 205e from the second to fifth cycle process steps.

[0099] In the PULVT region, the work function TiN layer 205 is formed by superimposing the work function TiN layers 05a, 05b, 205c, 205d and 205e from the first to the fifth cycle process steps.

[0100] Step 2, as follows Figure 6C As shown, selective etching with a first etching selectivity greater than 1 is performed. The first etching selectivity is the etching selectivity of TaN to TiN. The etching gas used for selective etching is WCl5. The selective etching thins the work function TiN layer 206 and / or the TaN barrier layer 205 in each threshold voltage region to achieve a second regulation of the threshold voltage in each threshold voltage region.

[0101] In the selective etching, the CPP will have a second effect on the etching thickness of the work function TiN layer 206. Taking advantage of the fact that the effect of the second effect on the first difference is exactly the opposite of the effect of the first effect on the first difference, the first difference is reduced.

[0102] In some embodiments, the first difference reduction is greater than 1 nm, which can improve the threshold voltage trend of different CPPs.

[0103] exist Figure 5 In the preferred embodiment shown, step two is step S207, WCl5 etch, which is to perform WCl5 etching.

[0104] like Figure 6C As shown in the embodiment of the present invention, in the NULVT region, the selective etching directly etches the TaN barrier layer 205, and the maximum etching amount of the TaN barrier layer 205 is when the TaN barrier layer 205 is completely removed.

[0105] In the NLVT region, the selective etching first etches the work function TiN layer 206 and then etches the TaN barrier layer 205, thus partially removing the TaN barrier layer 205. The TaN, acting as an etching barrier layer, can be completely removed after the PMG loop ends, achieving lower threshold voltage regulation and expanding the regulation range.

[0106] In the NSVT region, the selective etching etches the work function TiN layer 206, where the work function TiN layer 206 is completely or partially etched. When the work function TiN layer 206 is completely etched, the TaN barrier layer 205 is not etched or is partially etched.

[0107] The work function TiN layer 206 in the PSVT region, the PLVT region, and the PULVT region is partially etched, and the thickness of the work function TiN layer 206 in the PSVT region, the PLVT region, and the PULVT region increases sequentially.

[0108] In this embodiment of the invention, the selective etching time is 5s to 60s. The first etching selectivity ratio is 3:1 to 10:1. Preferably, the first etching selectivity ratio changes with the selective etching time, and as time increases, the first etching selectivity ratio decreases from 10:1 to 3:1.

[0109] The first etching selectivity is adjusted by regulating the flow rate, pressure, reaction temperature, and time of the selectively etched WCl5.

[0110] Depend on Figure 6C As shown, after the selective etching is completed, a W layer 207 is also formed.

[0111] Step 3, as follows Figure 6C As shown, a functional TiAl layer is formed to make the threshold voltage of each threshold voltage region reach the target value. Figure 5 In the preferred embodiment shown, step three is step S208, TiAl dep.

[0112] In this embodiment of the invention, the thickness of the work function TiAl layer is reduced according to the thickness reduction of the work function TiN layer 206 in step two. Therefore, compared with the existing method, the thickness of the work function TiAl layer formed in this embodiment of the invention is also reduced. In this embodiment of the invention, WCl5 etching can reduce the overall thickness of the PWF material, and the thickness of the N-type work function material (NWF) TiAl is reduced accordingly according to the target Vt value, thereby effectively expanding the filling window of the work function thin film material; at the same time, the reduction of N and Al content can expand the reliability window.

[0113] In this embodiment of the invention, based on the initial regulation of the threshold voltage of each threshold voltage region by forming work function TiN layers 206 of different thicknesses through the process ring of the P-type metal gate, selective etching of TiN using WCl5-based TaN is performed. Selective etching can make the thickness reduction of the work function TiN layer 206 in different CPP regions different, thereby compensating for the first difference in the thickness of the work function TiN layer 206 in different CPP regions in step one and finally reducing the first difference. Thus, this embodiment of the invention can synergistically regulate the threshold voltage of different CPP regions, so that the threshold voltage of each CPP region reaches the target value.

[0114] In this embodiment of the invention, selective etching of TiN with WCl5-based TaN can reduce the thickness of the work function TiN layer 206. At the same time, since the thickness of the work function TiN layer 206 is reduced, the thickness of the work function TiAl layer corresponding to the target value will also be reduced accordingly. Therefore, this embodiment of the invention can ultimately reduce the filling thickness of the work function material, thereby effectively expanding the work function material filling window and expanding the adjustable range of the threshold voltage.

[0115] In this embodiment of the invention, since the thickness of the work function TiN layer 206 and the thickness of the corresponding region of the TaN barrier layer 205 are reduced, the N content will be reduced; at the same time, since the thickness of the work function TiAl layer is reduced, the Al content will also be reduced. The reduction of N and Al content can expand the reliability test window, such as the test window for negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB).

[0116] like Figure 7A The figure shows the curve of NULVT as a function of CPP obtained by the threshold voltage adjustment method of HKMG in this embodiment of the invention. Figure 7A In the figure, the horizontal axis is CPP, the vertical axis is NULVT, curve 301a is the target curve, curve 301b is the curve corresponding to the existing method, and curve 301c is the curve corresponding to the method of the embodiment of the present invention. It can be seen that NULVT in curve 301c is about 5mV lower than NULVT in curve 301b, which is closer to the target value.

[0117] like Figure 7B The figure shows the curve of PULVT as a function of CPP obtained by the threshold voltage adjustment method of HKMG in this embodiment of the invention. Figure 7B In the figure, the horizontal axis is CPP, the vertical axis is PULVT, curve 302a is the target curve, curve 302b is the curve corresponding to the existing method, and curve 302c is the curve corresponding to the method of the embodiment of the present invention. It can be seen that the PULVT in curve 302c is lower than that in curve 302b by about 13mV, which is closer to the target value.

[0118] This invention achieves multi-level threshold voltage (Vt) control for different CPPs through selective etching with metal halide (WCl5). After partitioned deposition, photolithography, and etching of P-type work function material (PWF) TiN, a WCl5 selective etching step is added. By adjusting process parameters such as WCl5 flow rate, pressure, reaction temperature, and time, the etching selectivity ratio and etching amount for TaN / TiN can be controlled, thereby achieving multi-level Vt adjustment. Simultaneously, the method of this invention can expand the filling thickness window of the work function material, thereby expanding the Vt control range and reliability window.

[0119] The embodiments of this invention can improve the threshold voltage offset of different CPPs in N / PMOS by approximately 5-13 mV. It can reduce the fill thickness of the work function material, effectively expanding the work function film fill window, thereby broadening the adjustable threshold voltage range. Reducing the N content in TaN / TiN and the Al content in TiAl can expand the reliability testing window, such as NBTI and TDDB.

[0120] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for adjusting the threshold voltage of an HKMG, characterized in that, include: Step 1: Complete the process loop for the P-type metal gate to form a patterned work function TiN layer on the semiconductor substrate with the TaN barrier layer; The semiconductor substrate includes multiple threshold voltage regions, each with a different thickness of the work function TiN layer. The threshold voltage of each threshold voltage region is initially controlled by adjusting the thickness difference of the work function TiN layer. Each threshold voltage region is divided into multiple CPP regions based on different CPP steps, where CPP represents a key polysilicon step. The CPP has a first impact on the growth thickness of the work function TiN layer, causing a first difference in the thickness of the work function TiN layer in each CPP region within each threshold voltage region. Step 2: Perform selective etching with a first etching selectivity greater than 1. The first etching selectivity is the etching selectivity of TaN to TiN. The etching gas used for selective etching is WCl5. The selective etching thins the work function TiN layer and / or the TaN barrier layer in each threshold voltage region to achieve a second regulation of the threshold voltage in each threshold voltage region. In the selective etching, the CPP will have a second effect on the etching thickness of the work function TiN layer. Taking advantage of the fact that the effect of the second effect on the first difference is exactly the opposite of the effect of the first effect on the first difference, the first difference is reduced. Step 3: Form the functional TiAl layer to make the threshold voltage of each threshold voltage region reach the target value.

2. The threshold voltage adjustment method for HKMG as described in claim 1, characterized in that: The process loop of the P-type metal gate includes repeated cyclic process steps, wherein the cyclic process steps include: Deposition work function TiN stratification; The work function TiN layers are patterned and etched.

3. The threshold voltage adjustment method for HKMG as described in claim 2, characterized in that: In step one, the work function TiN layer in each threshold voltage region is formed by stacking work function TiN layers above the zero layer, and the work function TiN layer in each threshold voltage region is determined by the stacking thickness of each work function TiN layer included.

4. The threshold voltage adjustment method for HKMG as described in claim 2, characterized in that: Before performing patterned etching on the work function TiN layer, the following steps are also included: Deposited BARC layer; A photolithography process is performed to define the patterned etching region of the work function TiN layer, and then the BARC layer is etched. Subsequently, the work function TiN layer is etched using the BARC layer as a mask to achieve patterned etching of the work function TiN layer.

5. The threshold voltage adjustment method for HKMG as described in claim 4, characterized in that: The etching of the work function TiN layer includes wet etching.

6. The threshold voltage adjustment method for HKMG as described in claim 2, characterized in that, In step eight, the cyclic process step is repeated 5 times.

7. The threshold voltage adjustment method for HKMG as described in claim 6, characterized in that: The threshold voltages corresponding to each threshold voltage region are: NULVT, NLVT, NSVT, PSVT, PLVT, and PULVT; Wherein, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NUSVT is the standard threshold voltage of NMOS. PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PUSVT is the standard threshold voltage of PMOS. After step one is completed, the work function TiN layers in the threshold voltage region are as follows: In the NULVT region, the work function TiN layer is not formed; In the NLVT region, the work function TiN layer is composed of the work function TiN layer of the fifth cycle process step; In the NSVT region, the work function TiN layer is formed by stacking the work function TiN layers from the fourth and fifth cycle process steps; In the PSVT region, the work function TiN layer is formed by stacking the work function TiN layers from the third to the fifth cycle process steps; In the PLVT region, the work function TiN layer is formed by stacking the work function TiN layers from the second to the fifth cycle process steps; In the PULVT region, the work function TiN layer is formed by stacking the work function TiN layers from the first to the fifth cycle process steps.

8. The threshold voltage adjustment method for HKMG as described in claim 7, characterized in that: In step two, in the NULVT region, the selective etching directly etches the TaN barrier layer, and the maximum etching amount of the TaN barrier layer is when the TaN barrier layer is completely removed. In the NLVT region, the selective etching first etches the work function TiN layer and then etches the TaN barrier layer, thereby partially removing the TaN barrier layer; In the NSVT region, the selective etching etches the work function TiN layer, and the work function TiN layer is completely or partially etched. When the work function TiN layer is completely etched, the TaN barrier layer is not etched or is partially etched. The work function TiN layers in the PSVT region, PLVT region, and PULVT region are all partially etched, and the thickness of the work function TiN layers in the PSVT region, PLVT region, and PULVT region increases sequentially.

9. The threshold voltage adjustment method for HKMG as described in claim 1, characterized in that: The selective etching time is 5s to 60s.

10. The threshold voltage adjustment method for HKMG as described in claim 9, characterized in that: The first etching selectivity ratio is 3:1 to 10:

1.

11. The threshold voltage adjustment method for HKMG as described in claim 10, characterized in that: The first etching selectivity ratio changes with the time of the selective etching, and decreases from 10:1 to 3:1 as time increases.

12. The threshold voltage adjustment method for HKMG as described in claim 10, characterized in that: The first etching selectivity is adjusted by regulating the flow rate, pressure, reaction temperature, and time of the selectively etched WCl5.

13. The threshold voltage adjustment method for HKMG as described in claim 1, characterized in that: In step two, the first difference reduction is greater than 1 nm.

14. The threshold voltage adjustment method for HKMG as described in claim 8, characterized in that: In step three, the thickness of the work function TiAl layer is reduced according to the amount of reduction in the thickness of the work function TiN layer in step two.

15. The threshold voltage adjustment method for HKMG as described in claim 1, characterized in that: In step one, An interface layer, a high dielectric constant layer, and a capping TiN layer are also formed on the semiconductor substrate, and the TaN barrier layer is formed on the top surface of the capping TiN layer.

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