Heterojunction differential suede battery and manufacturing method thereof

Abstract

The invention discloses a heterojunction differential suede battery and a manufacturing method thereof, and the method sequentially comprises the following steps: firstly, carrying out the first alkali texturing of a crystalline silicon substrate, and forming large-structure pyramid suede on the two surfaces of the crystalline silicon substrate; secondly, phosphorus-rich gettering treatment is carried out in a tubular furnace, a phosphorus-rich silicon oxide layer is synchronously generated on the two faces of the silicon wafer, and the layer has gettering purification and mask functions; then, selectively only removing the phosphorus-rich silicon oxide layer on the single surface of the silicon wafer by adopting chain type cleaning equipment and a low-concentration hydrofluoric acid solution; performing secondary alkali texturing, and etching only one surface which is not protected by the mask to form a small-structure pyramid textured surface, so that the small-structure pyramid textured surface and a large pyramid textured surface which is reserved on the other surface form a differentiated structure; and finally, carrying out acid pickling to remove the residual silicon oxide layer and drying to obtain a final product. The method can be widely applied to mass production preparation of high-efficiency heterojunction solar cells, and is particularly suitable for photovoltaic production scenes with double requirements on cell efficiency and production cost.

Description

Technical Field

[0001] This invention belongs to the field of high-efficiency heterojunction solar cell technology, specifically relating to a heterojunction differentiated textured solar cell and its manufacturing method. Background Technology

[0002] To address the light absorption issue after silicon wafer thinning, the industry has proposed a differentiated textured surface fabrication technology: a large textured surface structure is fabricated on the back of the solar cell. This enhances secondary reflection of long-wavelength light, improving light capture efficiency. Furthermore, the rough surface of the large textured surface improves the uniformity of the passivation film deposition on the back, reducing surface recombination and thus optimizing the cell's open-circuit voltage and fill factor. Conversely, a small textured surface structure is fabricated on the front of the cell to reduce reflection loss of short-wavelength light. This differentiated textured surface design on both sides enables efficient utilization of the entire spectrum.

[0003] A heterojunction solar cell structure with single-sided polishing, Chinese patent number CN205959994U, proposes a structure where the heterojunction cell is designed with single-sided polishing and texturing. The polished surface helps control the uniformity of the amorphous silicon thin film deposition, making the PN junction flatter, and simultaneously increases light absorption in the silicon wafer, improving the battery's electrical performance. However, this patent only describes the structural advantages of single-sided texturing cells and does not disclose the specific process for efficiently fabricating single-sided texturized silicon wafers. Since the implementation process of single-sided texturing is the core foundation for the industrialization of this technology, the proposed solution lacks practical applicability.

[0004] The single-sided texturing process using chain texturing, Chinese patent number CN113363349A, achieves single-sided texturing of silicon wafers using chain texturing equipment, while the other side remains polished. This reduces material loss of 5-10μm in the silicon wafer, lowering wafer costs. Simultaneously, the smoothness of the polished surface reduces surface defects in crystalline silicon, which is beneficial for improving the open-circuit voltage of the battery. However, this process faces two major industrialization bottlenecks: First, the mainstream texturing equipment in the photovoltaic industry is trough-type equipment; adopting chain texturing requires companies to purchase new equipment, resulting in poor compatibility with existing production lines and high equipment modification costs. Second, chain texturing relies on roller transmission; after long-term use, the rollers are prone to detaching metal impurities, causing contact contamination on the silicon wafer surface and affecting the battery's electrical performance and yield.

[0005] Furthermore, existing single-sided texturing processes only focus on differentiating the textured surface structure, without integrating silicon wafer gettering with the texturing process. Texturing increases the specific surface area of ​​the silicon wafer, allowing for more efficient removal of metallic impurities and lattice defects from the substrate, thus improving minority carrier lifetime. However, current technologies fail to utilize this process synergy, resulting in room for improvement in the intrinsic electrical properties of the silicon wafer even after single-sided texturing is achieved, ultimately limiting the upper limit of photoelectric conversion efficiency for heterojunction solar cells. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a heterojunction differentiated textured battery and its manufacturing method, thereby solving the aforementioned technical problems in the prior art.

[0007] The objective of this invention can be achieved through the following technical solutions: A heterojunction differentiated textured solar cell includes a crystalline silicon substrate, wherein the front side of the crystalline silicon substrate has a small-structure pyramid textured surface and the back side has a large-structure pyramid textured surface, and the residual phosphorus doping concentration inside the crystalline silicon substrate is 1×10⁻⁶. 18 ~5×10 19 atoms / cm 3 ; The size of the pyramidal textured surface on the front is 1.0~1.2μm, the reflectivity without a passivation layer is 10~11%, and the texture density is 3×10⁻⁶. 4 ~5×10 4 pcs / mm 2 ; The textured surface of the large pyramid structure on the back has a size of 1.5~2.5μm, a reflectivity of 15~18% without a passivation layer, and a texture density of 1×10⁻⁶. 4 ~2×10 4 pcs / mm 2 The vertical height difference from the apex of the pyramid structure on the front and back sides to the crystalline silicon substrate is ≥0.5μm. The minority carrier lifetime of the crystalline silicon substrate is 500~800μs, which is ≥20% higher than that of the crystalline silicon substrate without phosphorus-rich getter treatment, and the light absorption efficiency of the cell in the long wavelength range of 800~1100nm is ≥3% higher.

[0008] The method for manufacturing the heterojunction differentiated textured solar cell includes the following steps: S1. Phosphorus-rich gettering: The original silicon substrate is placed in the quartz boat of the tube gettering furnace. Nitrogen gas is first introduced to purge the air in the furnace. Then the temperature is raised to 900~950℃, and a mixture of phosphorus source and oxygen gas is introduced. The gettering is carried out in a phosphorus-rich atmosphere for 30~60 minutes. After gettering, the temperature is naturally cooled to below 300℃ and then removed. This achieves the removal of impurities and the improvement of minority carrier lifetime of the silicon substrate. S2, First texturing: The crystalline silicon substrate after S1 gettering is placed in a tank texturing device, and a sodium hydroxide or potassium hydroxide solution with a mass concentration of 2-5% is added. After texturing, the residual alkaline solution on the silicon wafer surface is rinsed with deionized water. After draining, the silicon wafer is tested and found to have a reflectivity of 12-15% and a large-structure pyramid textured surface with a size of 1.5-2.5μm is formed on the back side. S3, Silicon Oxide Formation: The crystalline silicon substrate after S2 texturing is placed in a tube oxidation furnace, and a mixture of oxygen and nitrogen is introduced. The temperature is raised to 800~850℃ and held for 20~40 minutes. A silicon oxide layer with a thickness of 150~300nm is formed simultaneously on both sides of the crystalline silicon substrate. This silicon oxide layer serves as a mask layer for subsequent secondary texturing, with a side etching rate ≤5%. S4. Single-sided removal of phosphorus-rich silicon oxide layer: A chain cleaning method using a 3-5% hydrofluoric acid solution is employed to remove the phosphorus-rich silicon oxide layer from only one side of the silicon wafer, leaving the phosphorus-rich silicon oxide layer on the other side to prevent subsequent texturing reactions. The uniformity error of single-sided removal of the phosphorus-rich silicon oxide layer is ≤3%. S5. Second texturing: The substrate after S3 is subjected to a second texturing process. The solution used is a sodium hydroxide or potassium hydroxide solution with a mass concentration of 1-3%. The stirring rate is 150-250 r / min, the temperature is controlled at 70-85℃, and the etching time is 240-600s. Only the side not covered by the phosphorus-rich silicon oxide layer is etched to form a small-structure pyramid textured surface, and the lateral etching rate of the phosphorus-rich silicon oxide layer is ≤5%. S6. Acid washing and film removal: For the silicon wafers after S4 texturing, use a 3-5% hydrofluoric acid solution to clean them, control the temperature at 20-25℃, and the time at 60-200s to remove the residual phosphorus-rich silicon oxide layer. S7. Drying: Use hot air at a temperature of 60~90℃ and a wind speed of 1~3m / s to dry the silicon wafer to obtain a double-sided differentiated textured silicon wafer.

[0009] Furthermore, in S1, the nitrogen flow rate is 500~800 sccm, and the duration is 10~15 min; The phosphorus source flow rate is 50~100 sccm, and the oxygen flow rate is 100~200 sccm.

[0010] Furthermore, in S2, 0.1-0.3% isopropanol is added to the solution as a corrosion inhibitor; the stirring rate is controlled at 200-300 r / min, the temperature at 80-85℃, and the etching time at 120-360 s.

[0011] Furthermore, in S2, the resistivity of the solution obtained after texturing is ≥18.2 MΩ・cm.

[0012] Furthermore, in S3, the oxygen content in the mixed gas is 30%-50%, and the total flow rate is 400-600 sccm.

[0013] Furthermore, in S4, chain cleaning involves using a hydrofluoric acid solution with a temperature of 20-25°C and a mass concentration of 3-5% to clean the silicon wafers at a transmission rate of 1-2 m / min.

[0014] Furthermore, the alkaline solution used in the secondary texturing process described in S5 is a 1.5% sodium hydroxide solution at a temperature of 80°C and an etching time of 360s, with a dimensional deviation of ≤0.1μm for the small-structure pyramid textured surface.

[0015] Furthermore, the cleaning time of the hydrofluoric acid solution in S6 is 150~180s, and the residual amount of silicon oxide on the surface of the silicon wafer after cleaning is ≤2nm.

[0016] Furthermore, the temperature of the hot air drying in S7 is 75~85℃, the wind speed is 2~2.5m / s, and the moisture content on the surface of the silicon wafer after drying is ≤0.1%.

[0017] The beneficial effects of this invention are: 1. The main body of this invention adopts the mainstream trough texturing equipment in the photovoltaic industry to complete the two texturing processes, which is different from the existing chain texturing solution. It does not require enterprises to replace the texturing equipment, which significantly reduces the equipment investment cost of production line transformation. At the same time, the mature process system of trough texturing can be directly reused, reducing the process debugging cycle. The single-sided texturing effect is achieved by using a phosphorus-rich silicon oxide mask + trough texturing, avoiding the contact contamination problem caused by long-term use of rollers. In addition, the silicon oxide mask can be completely removed by acid washing in the process, without the introduction of residual impurities, ensuring the cleanliness of the silicon wafer surface.

[0018] 2. The silicon wafer produced by this invention has a high density of small pyramid textured surface on the front side, which greatly reduces the reflection loss of short-wavelength light; the large pyramid textured surface (1.5-2.5μm) on the back side achieves secondary reflection of long-wavelength (800-1100nm) light, with a long-wavelength absorption efficiency of 87%-89%, which is 12-14 percentage points higher, making full use of the long-wavelength part of the solar spectrum.

[0019] 3. The process parameters of this invention can be flexibly adjusted within a reasonable range. It can achieve rapid texturing through high-concentration alkaline solution (to meet high production capacity requirements) and can also achieve high-performance texturing preparation through parameter optimization (to meet high-efficiency battery requirements). The prepared differentiated texturing batteries have stable performance, and the core index deviation in the examples is ≤5%, which has the feasibility and economy for large-scale mass production. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0021] Figure 1 This is a schematic diagram of the overall process of an embodiment of the present invention; Figure 2 This is a schematic diagram of the silicon wafer substrate after the first texturing process according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the generation of a single-sided silicon oxide mask layer according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the process after removing single-sided silicon oxide according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after secondary texturing according to an embodiment of the present invention; Figure 6 This is a schematic diagram after removing the silicon nitride layer according to an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] like Figure 1 As shown, this invention specifically discloses a heterojunction differentiated textured solar cell and its manufacturing method. Through a combination of processes including phosphorus-rich gettering, primary texturing, silicon oxide mask layer generation, single-sided silicon oxide removal, secondary texturing, and acid washing to remove the film, a differentiated pyramidal textured surface on both sides of a crystalline silicon substrate is prepared, simultaneously improving the minority carrier lifetime of the crystalline silicon substrate and the long-wavelength absorption efficiency of the cell. The technical solution of this invention will be described in detail below with reference to specific embodiments and a blank control group.

[0024] The basic materials used in the embodiments of this invention are all mass-production grade raw materials for the photovoltaic industry. The crystalline silicon substrate is a P-type monocrystalline silicon wafer with a resistivity of 1~3 Ω·cm and a thickness of 150±5 μm. [The text abruptly ends here, likely due to an incomplete sentence or missing information.] <100> The original surface is a polished surface.

[0025] Example 1 This embodiment provides a method for manufacturing a heterojunction differentiated textured surface solar cell (based on sodium hydroxide-based differentiated textured surface preparation), the specific steps of which are as follows: S1. Phosphorus-rich gettering: The original silicon substrate is placed in a quartz boat and then into a tube getter furnace. Nitrogen gas (flow rate 600 sccm) is first introduced to purge the air from the furnace for 12 minutes. Then, the temperature is increased to 920°C at a rate of 6°C / min, and a mixture of POCl3 phosphorus source (flow rate 70 sccm) and oxygen (flow rate 150 sccm) is introduced. The wafer is then kept at this phosphorus-rich atmosphere for 45 minutes for gettering. After gettering, the temperature is decreased to 280°C at a rate of 8°C / min, and the silicon wafer is removed. At this point, the impurity content (such as Fe and Cu) on the silicon wafer is reduced by ≥30%, laying the foundation for subsequent texturing and performance improvement.

[0026] S2, First pile preparation (large-structure pile preparation): See details... Figure 2As shown, the original silicon substrate was placed in a tank texturing apparatus, and a 3.5% NaOH solution was added. The stirring rate was controlled at 250 r / min, the temperature at 80℃, and the etching time at 160 s. After texturing, the residual alkaline solution on the silicon wafer surface was rinsed with deionized water (resistivity 18.5 MΩ・cm). After draining, the silicon wafer was tested and found to have a reflectivity of 13% and an etching amount of 0.3 g. SEM observation showed that a large-structure pyramid textured surface with a size of 1.8~2.2 μm was formed on the back side.

[0027] S3. Formation of silicon oxide mask layer: The silicon wafer after S2 texturing is placed in a tube oxidation furnace, and a mixture of oxygen and nitrogen gas (oxygen content 40%, total flow rate 500 sccm) is introduced; the temperature is raised to 820℃ at a rate of 5℃ / min and held for 30min; a silicon oxide layer with a thickness of 220nm is formed simultaneously on both sides of the silicon wafer. The side etching rate of the silicon oxide layer is tested to be 3%, which can effectively block the subsequent texturing reaction.

[0028] S4. Single-sided removal of phosphorus-rich silicon oxide layer: Refer to... Figure 4 As shown, a chain cleaning device is used to clean the silicon wafer with an HF solution of 3% mass concentration and 23℃ at a transmission rate of 1.5m / min (spraying method can be used). Only the phosphorus-rich silicon oxide layer on the front side is removed. After cleaning, the residual amount of silicon oxide layer on the front side is ≤2nm, the uniformity error is 2%, and the silicon oxide layer on the back side is retained as a mask.

[0029] S5, Second Pile Making (Small Structure Pile Preparation): Refer to... Figure 5 As shown, the substrate treated with S4 was placed in a tank texturing apparatus, and a 1.5% (w / w) NaOH solution was added. The stirring rate was 200 r / min, the temperature was 80℃, and the etching time was 360 s. The front side not covered by silicon oxide was etched to form a small pyramid textured surface. SEM observation showed that the textured surface size on the front side was 1.1 μm, the size deviation was 0.08 μm, and the side etching rate of the silicon oxide layer was 3%. The alkali concentration was 1~3%, the etching time was 240-600 s, and it was necessary to ensure that the small textured surface size was 1.0~1.2 μm and the side etching rate of the silicon oxide mask was ≤5%.

[0030] S6. Pickling and film removal: Refer to... Figure 6 As shown, the silicon wafer after secondary texturing is placed in an acid washing tank and cleaned with an HF solution with a mass concentration of 3% and a temperature of 23°C for 160 seconds to remove the residual phosphorus-rich silicon oxide layer, with a residual silicon oxide content of 1 nm on the surface.

[0031] S7. Drying: The acid-washed silicon wafers are placed in a hot air drying oven and dried with hot air at 80°C and a wind speed of 2.2m / s. The surface moisture content is 0.08%, resulting in a double-sided differentiated textured silicon wafer. Subsequent processes such as depositing a passivation layer and preparing electrodes are then carried out to produce a heterojunction differentiated textured solar cell.

[0032] Example 2 This embodiment describes another set of process parameters for the preparation of a differentiated textured surface based on potassium hydroxide. The steps and principles are the same as in Example 1, with changes only to the following relevant parameters. The specific steps are as follows: S1. Phosphorus-rich gettering: The original silicon substrate is loaded into a quartz boat and placed in a tube gettering furnace; nitrogen flow rate is 700 sccm, and the purging time is 15 min; the temperature is raised to 930℃, phosphorus source flow rate is 80 sccm, oxygen flow rate is 180 sccm, and the gettering is carried out at this temperature for 50 min; the temperature is lowered to 290℃ and the wafer is removed, and the silicon wafer impurity removal rate is ≥32%.

[0033] S2. First texturing: The alkaline solution is a 4% KOH solution, and the isopropanol addition is 0.3%; the stirring rate is 280 r / min, the temperature is 83℃, and the etching time is 200 s; the resistivity of deionized water is 18.3 MΩ・cm, the reflectivity after texturing is 12.5%, and the size of the large texturing surface on the back is 2.0~2.3 μm.

[0034] S3. Formation of silicon oxide mask layer: The mixed gas contains 45% oxygen and has a total flow rate of 550 sccm; the temperature is raised to 830℃ and held for 35 min; the silicon oxide layer has a thickness of 240 nm and a side etching rate of 4%, which can effectively block the subsequent texturing reaction.

[0035] S4. Single-sided removal of phosphorus-rich silicon oxide layer: Using a chain cleaning device, the silicon wafer is cleaned with an HF solution with a mass concentration of 4% and a temperature of 22°C at a transmission rate of 1.8m / min. Only the phosphorus-rich silicon oxide layer on the front side is removed, with a uniformity error of 2.5%. The silicon oxide layer on the back side is retained as a mask.

[0036] S5. Second texturing (small structure texturing preparation): The substrate treated by S3 is placed in a tank texturing device, and a 2% KOH solution is added. The stirring rate is 220r / min, the temperature is 82℃, and the etching time is 400s. The front side not covered by silicon oxide is etched to form a small structure pyramid texturing surface with a size deviation of 0.09μm and a silicon oxide layer side etching rate of 4%.

[0037] S / 6, Acid Pickling and Film Removal: Clean the silicon wafer with HF solution at a mass concentration of 4% and a temperature of 22°C for 170 seconds to remove the residual phosphorus-rich silicon oxide layer, leaving a residual silicon oxide layer of 1.5 nm on the surface.

[0038] S7. Drying: The silicon wafer is dried with hot air at 85℃ and a wind speed of 2.4m / s, and the surface moisture content is 0.07%, resulting in a double-sided differentiated textured silicon wafer; the same subsequent processes are then used to produce a heterojunction differentiated textured solar cell.

[0039] Example 3 (Preparation of Differentiated Textured Surface with High-Concentration Alkali Solution): The steps and principles are the same as in Example 1, except for the following relevant parameters, which are changed. The specific steps are as follows: S1, Phosphorus-rich impurity removal: Nitrogen flow rate 500 sccm, purging time 10 min; heat to 950℃, phosphorus source flow rate 100 sccm, oxygen flow rate 200 sccm, heat and remove impurities for 30 min; cool to 270℃ and remove, impurity removal rate ≥28%.

[0040] S2. First texturing: The alkaline solution is a 5% NaOH solution, and the isopropanol addition is 0.1%; the stirring rate is 300r / min, the temperature is 85℃, and the etching time is 120s; the reflectivity after texturing is 12%, and the large textured surface size on the back is 2.2~2.5μm.

[0041] S3. Formation of silicon oxide mask layer: mixed gas with oxygen content of 30% and total flow rate of 400 sccm; heated to 850℃ and held for 20 min; silicon oxide layer thickness of 280 nm and lateral etching rate of 5%.

[0042] S4. Single-sided removal of phosphorus-rich silicon oxide layer: using 5% HF solution, with a chain cleaning machine transmission rate of 2m / min, the uniformity error of silicon oxide layer removal on the front side after cleaning is 3%.

[0043] S5. Second texturing: Using a 3% KOH solution, at a temperature of 85℃, an etching time of 240s, a stirring rate of 250r / min, a small texturing surface size of 1.2μm on the front side, and a silicon oxide layer side etching rate of 5%.

[0044] S6. Pickling: Use 5% HF solution for film removal, cleaning time 60s, silicon oxide residue on silicon wafer surface 2nm.

[0045] S7. Drying and subsequent processes: The silicon wafer was dried with hot air at 90°C and 3m / s for 8 minutes, resulting in a surface moisture content of 0.1%. The subsequent battery process was the same as in Example 1.

[0046] Blank control group To verify the technical effectiveness of the process of this invention, a blank control group was set up. Heterojunction solar cells were prepared using a conventional single-sided polishing + single-time texturing process (refer to CN113363349A). The specific steps are as follows: One side of the crystalline silicon substrate is polished, and the other side is texturized with a 3.5% NaOH solution at 80°C for 160 seconds to form a single-size pyramid textured surface.

[0047] Without phosphorus-rich gettering, passivation layer deposition and electrode fabrication were performed directly to obtain a conventional heterojunction solar cell.

[0048] Performance Testing and Results Analysis The performance of the batteries prepared in Examples 1, 2, 3 and the blank control group was tested. The test items included textured surface parameters, minority carrier lifetime, light absorption efficiency and photoelectric conversion efficiency. The results are shown in Tables 1 and 2.

[0049] Table 1 Comparison of Felt Surface Structure Parameters

[0050] Table 2 Comparison of Battery Performance Parameters

[0051] Textured surface structure: The batteries prepared in Examples 1, 2, and 3 formed a differentiated pyramid textured surface with a small front structure and a large back structure. The height difference between the front and back sides was ≥0.5μm, and the textured surface density showed a distribution characteristic of "high on the front and low on the back". The reflectivity was as low as 10.5~11.0%, which greatly reduced the short-wavelength light reflection loss. The large textured surface on the back side had a reflectivity of 16.5~18.0% due to its large size, while the blank control group only had a single textured surface + polished surface structure. The reflectivity of the polished surface was as high as 35%, which greatly reduced the light absorption efficiency.

[0052] After phosphorus-rich getter treatment, the minority carrier lifetimes of Examples 1-3 were all ≥650 μs, an improvement of over 116% compared to the blank control group (300 μs); the surface defect state density decreased to 2.2 × 10⁻⁶. 10 cm -2 Below, the value is significantly lower than the 5×10⁻⁶ in the blank control group. 10 cm -2 This indicates that the phosphorus-rich getter process effectively removes metallic impurities and lattice defects from the crystalline silicon substrate, optimizing the substrate's electrical properties.

[0053] The photoelectric conversion efficiency of Examples 1-3 was ≥24.8%, which was ≥1.8 percentage points higher than that of the blank control group (23.0%); the open-circuit voltage was ≥715mV, the fill factor was ≥82%, and the short-circuit current density was ≥42.0mA / cm². 2 The core performance indicators were all significantly better than those of the control group. Among them, Example 2 showed the best overall performance, with a photoelectric conversion efficiency of 25.5% and a long-wavelength absorption efficiency of 89%, demonstrating the technical value of the optimized process parameters of this invention.

[0054] In summary, this invention, through a combination of differentiated texturing and phosphorus-rich gettering processes, not only achieves the fabrication of differentiated textured surfaces on both sides of heterojunction solar cells, but also significantly improves the minority carrier lifetime of crystalline silicon substrates and the photoelectric conversion efficiency of the cells, demonstrating significant technical advantages compared to existing technologies.

[0055] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A heterojunction differentiated textured surface battery, characterized in that, The substrate includes a crystalline silicon substrate, wherein the front side of the substrate has a small-structure pyramid textured surface and the back side has a large-structure pyramid textured surface, and the residual phosphorus doping concentration inside the crystalline silicon substrate is 1×10⁻⁶. 18 ~5×10 19 atoms / cm 3 ; The size of the pyramidal textured surface on the front is 1.0~1.2μm, the reflectivity without a passivation layer is 10~11%, and the texture density is 3×10⁻⁶. 4 ~5×10 4 pcs / mm 2 ; The textured surface of the large pyramid structure on the back has a size of 1.5~2.5μm, a reflectivity of 15~18% without a passivation layer, and a texture density of 1×10⁻⁶. 4 ~2×10 4 pcs / mm 2 The vertical height difference from the apex of the pyramid structure on the front and back sides to the crystalline silicon substrate is ≥0.5μm. The minority carrier lifetime of the crystalline silicon substrate is 500~800μs, which is ≥20% higher than that of the crystalline silicon substrate without phosphorus-rich getter treatment, and the light absorption efficiency of the cell in the long wavelength range of 800~1100nm is ≥3% higher.

2. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 1, characterized in that, Includes the following steps: S1. Phosphorus-rich gettering: The original silicon substrate is placed in the quartz boat of the tube gettering furnace. Nitrogen gas is first introduced to purge the air in the furnace. Then the temperature is raised to 900~950℃, and a mixture of phosphorus source and oxygen gas is introduced. The gettering is carried out in a phosphorus-rich atmosphere for 30~60 minutes. After gettering, the temperature is naturally cooled to below 300℃ and then removed. This achieves the removal of impurities and the improvement of minority carrier lifetime of the silicon substrate. S2, First texturing: The crystalline silicon substrate after S1 gettering is placed in a tank texturing device, and a sodium hydroxide or potassium hydroxide solution with a mass concentration of 2-5% is added. After texturing, the residual alkaline solution on the silicon wafer surface is rinsed with deionized water. After draining, the silicon wafer is tested and found to have a reflectivity of 12-15% and a large-structure pyramid textured surface with a size of 1.5-2.5μm is formed on the back side. S3. Formation of silicon oxide mask layer: The crystalline silicon substrate after S2 texturing is placed in a tube oxidation furnace, and a mixture of oxygen and nitrogen is introduced. The temperature is raised to 800~850℃ and held for 20~40 minutes. A silicon oxide layer with a thickness of 150~300nm is formed simultaneously on both sides of the crystalline silicon substrate. This silicon oxide layer serves as a mask layer for subsequent secondary texturing, with a side etching rate ≤5%. S4. Single-sided removal of phosphorus-rich silicon oxide layer: A chain cleaning method using a 3-5% hydrofluoric acid solution is employed to remove the phosphorus-rich silicon oxide layer from only one side of the silicon wafer, leaving the phosphorus-rich silicon oxide layer on the other side to prevent subsequent texturing reactions. The uniformity error of single-sided removal of the phosphorus-rich silicon oxide layer is ≤3%. S5. Second texturing: The substrate after S3 is subjected to a second texturing process. The solution used is a sodium hydroxide or potassium hydroxide solution with a mass concentration of 1-3%. The stirring rate is 150-250 r / min, the temperature is controlled at 70-85℃, and the etching time is 240-600s. Only the side not covered by the phosphorus-rich silicon oxide layer is etched to form a small-structure pyramid textured surface, and the lateral etching rate of the phosphorus-rich silicon oxide layer is ≤5%. S6. Acid washing and film removal: For the silicon wafers after S4 texturing, use a 3-5% hydrofluoric acid solution to clean them, control the temperature at 20-25℃, and the time at 60-200s to remove the residual phosphorus-rich silicon oxide layer. S7. Drying: Use hot air at a temperature of 60~90℃ and a wind speed of 1~3m / s to dry the silicon wafer to obtain a double-sided differentiated textured silicon wafer.

3. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, In S1, the nitrogen flow rate is 500~800 sccm, and the duration is 10~15 min; The phosphorus source flow rate is 50~100 sccm, and the oxygen flow rate is 100~200 sccm.

4. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, In S2, 0.1-0.3% isopropanol is added to the solution as a corrosion inhibitor; the stirring rate is controlled at 200-300 r / min, the temperature at 80-85℃, and the etching time at 120-360 s.

5. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, In S2, the resistivity of the solution after texturing is ≥18.2 MΩ・cm.

6. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, In S3, the oxygen content in the mixed gas is 30%-50%, and the total flow rate is 400-600 sccm.

7. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, S4 Chain Cleaning: Use hydrofluoric acid solution with a temperature of 20~25℃ and a mass concentration of 3~5% to clean the silicon wafers at a transmission rate of 1~2m / min.

8. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, The alkaline solution used in the secondary texturing process described in S5 is a 1.5% sodium hydroxide solution at a temperature of 80°C and an etching time of 360s. The dimensional deviation of the small pyramid textured surface is ≤0.1μm.

9. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, The cleaning time of hydrofluoric acid solution in S6 is 150~180s, and the residual amount of silicon oxide on the surface of the silicon wafer after cleaning is ≤2nm.

10. The method for manufacturing a heterojunction differentiated textured surface battery according to claim 2, characterized in that, The temperature of the hot air drying in S7 is 75~85℃, the wind speed is 2~2.5m / s, and the moisture content of the silicon wafer surface after drying is ≤0.1%.

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