SFQ device bottom layer processing method and SFQ device bottom layer prepared by same

Abstract

The invention provides an SFQ device bottom layer processing method, and the SFQ device bottom layer comprises a first insulating layer and a superconducting layer wrapped in the first insulating layer. Comprising the following steps of performing atomic layer etching on the surface of the first insulating layer based on a mask to remove the first insulating layer on the superconducting layer so as to expose part of the superconducting layer; mechanically polishing the first insulating layer to completely expose the superconducting layer; depositing a second insulating layer above the completely exposed superconducting layer and the first insulating layer; and carrying out mechanical polishing on the surface of the second insulating layer to realize planarization of the bottom layer of the SFQ device. The first mechanical polishing is performed after atomic layer etching, the second insulating layer is deposited, and the second mechanical polishing is performed, so that the flatness of the bottom layer of the SFQ device is improved, and the stability of the SFQ device is further improved.

Description

Technical Field

[0001] This disclosure belongs to the field of SFQ device bottom layer fabrication technology, specifically relating to an SFQ device bottom layer processing method and an SFQ device bottom layer prepared by the processing method. Background Technology

[0002] A superconducting computer is a computer made of superconducting materials, in which the superconducting materials are in a superconducting state during operation, and the conductor is a superconductor. Superconducting computers offer advantages such as ultra-low power consumption and ultra-high frequency. While mainstream semiconductor computers use CMOS sensors, superconducting computers use Josephson junctions (JJs). The working principle and state of a Josephson junction are completely different from those of a CMOS transistor, possessing many superior characteristics. A Josephson junction is a current-controlled switching device. It has a current Ic; when the current flowing through it exceeds I(c), the junction is triggered, generating a voltage pulse and emitting a single-flux quantum (SFQ). The SFQ is induced by an inductor to obtain a stable current, thereby triggering the next Josephson junction or performing other functions.

[0003] Currently, single-flux quantum circuit (SFQ) technology is mainly divided into NEC (Niobium (Nb) Integrated Circuits) standard process (SDP) and advanced process (ADP). Specifically, the goal of the advanced process is to develop SFQ circuits that can contain junctions of over 100K and clock frequencies of around 80GHz, enabling SFQ circuits to operate at higher frequencies, achieve higher integration density compared to the standard process, and have higher reliability.

[0004] However, the main problem with using advanced processes is that, for the target parameters and device structure of advanced Nb processes, the characteristics of the Josephus junction are easily affected by the slight roughness of the underlying pattern of the SFQ device. Relying on several existing planarization techniques, such as Chemical Mechanical Planarization (CMP), Mechanical Polishing Planarization (MPP), and RF-biasputtering planarization, it is difficult to uniformly planarize patterns of different sizes, which further limits the stability of SFQ devices. Summary of the Invention The purpose of this disclosure is to propose a method for processing the underlying layer of an SFQ device and the underlying layer of the SFQ device, so as to solve the problem that the traditional planarization method still has a certain roughness and cannot guarantee the stability of the SFQ device.

[0005] To this end, in a first aspect, this disclosure provides a method for processing the bottom layer of an SFQ device, wherein the bottom layer of the SFQ device includes a first insulating layer and a superconducting layer encapsulated within the first insulating layer, comprising the following steps: Atomic layer etching is performed on the surface of the first insulating layer based on a mask to remove the first insulating layer on the superconducting layer and expose a portion of the superconducting layer. The first insulating layer is mechanically polished to fully expose the superconducting layer; A second insulating layer is deposited over the superconducting layer and the first insulating layer, which are completely included. The surface of the second insulating layer is mechanically polished to achieve planarization of the SFQ device substrate.

[0006] Optionally, when atomic layer etching is performed on the surface of the first insulating layer based on a mask to remove the first insulating layer on the superconducting layer, a first protrusion structure is formed at the unexposed superconducting layer and its edge locations.

[0007] Optionally, the second insulating layer is ion-etched to form a second protrusion structure, the vertical projection surface of the second protrusion structure covering the edge of the superconducting layer and a portion of the superconducting layer.

[0008] Optionally, before mechanically polishing the surface of the second insulating layer to achieve planarization of the SFQ device substrate, the method further includes: Reactive ion etching is performed on the surface of the second insulating layer to form a second protrusion structure.

[0009] Optionally, the mechanical polishing of the surface of the second insulating layer to achieve planarization of the SFQ device includes: The second protrusion structure on the surface of the second insulating layer is removed by mechanical polishing to achieve planarization of the SFQ device substrate.

[0010] Optionally, the step of performing atomic layer etching on the surface of the first insulating layer based on a mask to remove the first insulating layer on one side of the superconducting layer includes: A mask is formed on the surface of the first insulating layer using photoresist; The etchant is adsorbed onto the first insulating layer by a carrier gas inside the mask. After the exposure time, the temperature is raised to remove the silicon dioxide of the single atom layer of the first insulating layer, thus completing one etching cycle. Repeated etching cycles are performed to completely remove the first insulating layer on one side of the superconducting layer.

[0011] Optionally, the etching agent is a mixture of hydrofluoric acid and ammonia gas at a pressure of 50-200 mTorr.

[0012] Optionally, the exposure time is 1-5 seconds.

[0013] Optionally, depositing a second insulating layer over the first insulating layer and the superconducting layer, which are flush with each other on the surface, includes: Under vacuum conditions, the silicon dioxide is evaporated by bombarding a silicon dioxide target with an electron beam and then deposited on top of the first insulating layer and the superconducting layer, which are flush with the surface, to form a second insulating layer.

[0014] Optionally, the electron beam rate is 0.8-1.2 nm / s.

[0015] Optionally, the mechanical polishing is performed by polishing the first or second insulating layer with a rotating polishing head, wherein the polishing pressure of the polishing head is 3-6 psi and the rotation speed of the polishing head is 30-100 rpm.

[0016] Optionally, the first insulating layer is a silicon dioxide layer.

[0017] Optionally, the second insulating layer is a silicon dioxide layer.

[0018] Optionally, the superconducting layer is a niobium layer.

[0019] An SFQ device underlayer is also provided, the surface of which is planarized by the aforementioned SFQ device underlayer processing method.

[0020] Optionally, the global flatness of the bottom layer of the SFQ device is less than or equal to 1.5 nm.

[0021] Beneficial effects: This disclosure provides a method for processing the bottom layer of an SFQ device and the bottom layer of the SFQ device, which involves atomic layer etching followed by a first mechanical polishing, deposition of a second insulating layer, and then a second mechanical polishing. 1) Through the synergistic effect of two mechanical polishing and intermediate deposition steps, combined with the first and second protrusion structures formed by etching, the 'mode dependence' problem in traditional planarization processes is effectively solved, improving the flatness of the SFQ device substrate and the stability of the SFQ device. 2) At the same time, atomic layer etching, compared with traditional reactive ion etching, is beneficial to reduce damage to the underlying structure. Due to its isotropic nature, it can partially etch away the structure under the photoresist mask, reducing stress concentration and residue problems during mechanical polishing, and improving polishing yield and process consistency.

[0022] 3) By depositing a second insulating layer and performing secondary planarization, effective protection was provided for the underlying superconducting layer, and an ideal planar foundation was laid for further multilayer structure fabrication. It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating one embodiment of an SFQ device low-level processing method disclosed herein. Figure 2 This is a flowchart illustrating another embodiment of the SFQ device low-level processing method disclosed herein; Figure 3 This is an initial structural diagram of a low-level processing method for an SFQ device according to the present disclosure; Figure 4 This is a structural diagram of the overlay mask for a bottom-level processing method of an SFQ device according to the present disclosure; Figure 5 This is a structural diagram of an SFQ device after atomic layer etching, according to a bottom-layer processing method of this disclosure. Figure 6 This is a structural diagram of a mechanically polished SFQ device under-layer processing method according to this disclosure; Figure 7 This is a structural diagram of the deposition of the second insulating layer in an SFQ device bottom layer processing method according to the present disclosure; Figure 8 This is a structural diagram of the etching of the second protrusion structure in a bottom-layer processing method for an SFQ device according to the present disclosure; Figure 9 This is a structural diagram of the SFQ device after the second mechanical polishing in one of the underlying processing methods of this disclosure.

[0025] Figure 10 This is a structural diagram of the underlying layer of an SFQ device disclosed herein.

[0026] In the figure, 1-first insulating layer, 2-superconducting layer, 3-mask, 4-second insulating layer, 5-second protrusion structure, 6-first protrusion structure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The terms "first," "second," "third," "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be used interchangeably where appropriate. For example, without departing from the scope of this document, first information can also be referred to as second information, and similarly, second information can also be referred to as first information.

[0029] Depending on the context, the word "if" as used here can be interpreted as "when," "when," or "in response to determination."

[0030] Furthermore, as used herein, the singular forms “a,” “one,” and “the” are intended to also include the plural forms, unless the context indicates otherwise.

[0031] It should be further understood that the terms “comprising” or “including” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0032] The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, “A, B, or C” or “A, B, and / or C” means “any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C”. Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

[0033] The flatness of the SFQ device substrate is crucial to the stability of SFQ devices based on Josephson junctions. In related technologies, the surface of the SFQ device substrate is generally planarized directly through chemical polishing, mechanical polishing, or RF bias sputtering. However, these traditional planarization methods still have a certain degree of roughness, which makes it difficult to guarantee the stability of the SFQ device.

[0034] This disclosure provides, for example Figure 1 The illustrated low-level processing method for an SFQ device includes the following steps: The bottom layer of the SFQ device includes a first insulating layer 1 and a superconducting layer 2 encapsulated within the first insulating layer 1, and includes the following steps: S101. Based on the mask 3, atomic layer etching is performed on the surface of the first insulating layer 1 to remove the first insulating layer 1 on the superconducting layer 2 to expose part of the superconducting layer 2. Mask 3 is a photoresist used to predefine the shape of the areas to be retained and removed. It protects the areas covered by mask 3 and removes the areas not covered by mask 3 by atomic layer etching.

[0035] The purpose of atomic layer etching is to remove the first insulating layer 1 on one surface of the superconducting layer 2, exposing part of the surface of the superconducting layer 2. Atomic layer etching can precisely control the etching depth and range, ensuring that only the first insulating layer 1 on the surface of the superconducting layer 2 is removed, avoiding excessive etching that could damage the underlying superconducting layer 2. At the same time, through the isotropic etching characteristics, the insulating layer below the edge of the photoresist mask 3 is partially etched, forming the first protrusion structure 6, i.e., the hollow structure, which creates conditions for reducing stress concentration and residue problems in subsequent mechanical polishing.

[0036] S102. Mechanically polish the first insulating layer 1 to fully expose the superconducting layer, so that the surface of the first insulating layer 1 is flush with the surface of the superconducting layer 2. Because after atomic layer etching, there will be some areas below the area covered by mask 3 that cannot be etched, thus forming the first protrusion structure 6. The excess first protrusion structure 6 of the first insulating layer 1 is processed by mechanical polishing to eliminate the surface undulations generated during the deposition process, so that the surface of the first insulating layer 1 and the surface of the superconducting layer 2 are flush, achieving preliminary flatness and laying the foundation for subsequent deposition and second mechanical polishing.

[0037] S103. Deposit a second insulating layer over the fully exposed superconducting layer 2 and the first insulating layer 1, that is, deposit a second insulating layer 4 over the first insulating layer 1 and the superconducting layer 2 with their surfaces flush. After the preceding steps, the surfaces of the first insulating layer 1 and the superconducting layer 2 have reached a preliminary flush state. However, the exposed superconducting layer 2 will affect the stability of the superconducting performance. By depositing a uniform cover of the second insulating layer 4, the superconducting layer 2 is protected, reducing damage and oxidation to its surface, and laying the foundation for the subsequent second mechanical polishing.

[0038] S104. Mechanically polish the surface of the second insulating layer 4 to achieve planarization of the bottom layer of the SFQ device.

[0039] The surface of the second insulating layer 4 is flattened by a second mechanical polishing, thereby improving the smoothness of the surface of the second insulating layer 4.

[0040] This disclosure also provides, as Figure 2 The illustrated low-level processing method for an SFQ device includes the following steps: like Figure 3 As shown, the bottom layer of the SFQ device includes a first insulating layer 1 and a superconducting layer 2 encapsulated within the first insulating layer 1, and includes the following steps: S201. Based on the mask 3, atomic layer etching is performed on the surface of the first insulating layer 1 to remove the first insulating layer 1 on the superconducting layer 2 to expose part of the superconducting layer 2. S202, A first protrusion structure 6 is formed at the unexposed superconducting layer 2 and its edge positions; This includes: like Figure 4 As shown, a mask 3 is formed on the surface of the first insulating layer 1 using photoresist; Within the mask 3, the etchant is adsorbed onto the first insulating layer 1 using a carrier gas. After an exposure time, the temperature is raised to remove the silicon dioxide from the single atomic layer of the first insulating layer 1, completing one etching cycle. In some disclosed embodiments, the etchant is a mixture of hydrofluoric acid and ammonia in a 2:1 ratio, with a gas pressure of 50-200 mTorr (e.g., 50 mTorr, 100 mTorr, 150 mTorr, 200 mTorr), an exposure time of 1-5 seconds (e.g., 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds), and a temperature range of 60-80°C (e.g., 60°C, 65°C, 70°C, 75°C, 80°C). During atomic layer etching, if the exposure time is short (less than 1 second, e.g., 0.6 seconds), the adsorption of the first insulating layer 1 will be unsaturated, resulting in poor etching performance. An exposure time of 1-5 seconds ensures that the surface-adsorbed reactive species during the etching reaction are more fully and saturated, avoiding uneven or incomplete etching due to insufficient adsorption, thereby improving the atomic layer etching effect. A stable gas pressure of 50-200 mTorr ensures uniform distribution of the reactive gas within the etching chamber, avoiding gas diffusion obstruction due to excessively high pressure or insufficient reactive species concentration due to excessively low pressure. This ensures a stable etching rate and uniform etching area, providing a uniform foundation for subsequent mechanical polishing.

[0041] like Figure 5 As shown, multiple etching cycles are repeated to completely remove the first insulating layer 1 on one side of the superconducting layer 2.

[0042] Atomic layer etching allows for precise control of the etching depth and range, ensuring that only a portion of the first insulating layer 1 on the surface of the superconducting layer 2 is removed, avoiding excessive etching that could damage the underlying superconducting layer 2. During the removal of the first insulating layer 1, a first protrusion structure 6 is formed on the unexposed superconducting layer 2 and its edges. This first protrusion structure 6 helps reduce damage to the superconducting layer 2 structure, and due to its isotropic nature, it can partially etch away the structure under the photoresist mask, reducing stress concentration and residue issues during mechanical polishing. S203: Mechanical polishing is performed on the first protrusion structure 6 in the first insulating layer 1 to completely expose the superconducting layer, even if the surface of the first insulating layer 1 is flush with the surface of the superconducting layer 2. like Figure 6 As shown, the first insulating layer 1 is polished by a rotating polishing head until it is flush with the surface of the superconducting layer 2. The polishing pressure of the polishing head is 1-10 psi, for example, the polishing pressure can be selected as 3 psi, 4 psi, 5 psi, or 6 psi, and the rotation speed of the polishing head is 30-100 rpm, for example, the rotation speed of the polishing head can be selected as 30 rpm, 40 rpm, 50 rpm, 60 rpm, 70 rpm, 80 rpm, 90 rpm, or 100 rpm. The polishing platform has a rotational speed range of 80-150 rpm, for example, selectable speeds of 80 rpm, 90 rpm, 100 rpm, 110 rpm, 120 rpm, 130 rpm, 140 rpm, and 150 rpm. The polishing slurry flow rate is 150-300 mL / min, for example, selectable flow rates of 150 mL / min, 200 mL / min, 250 mL / min, and 300 mL / min. The polishing temperature range is 25-30℃, the polishing time is 25-30℃, the abrasive of the polishing head can be colloidal silica with a particle size of 30 nm, the polishing slurry concentration is 15-30 wt%, and the pH is 10-11. The polishing pressure of the polishing head can reduce damage to the superconducting layer 2 during mechanical polishing. A low pressure range of 3-6 psi balances polishing efficiency and structural protection. On the one hand, sufficient polishing pressure ensures that the abrasive in the polishing slurry effectively acts on the surface, removing uneven areas; on the other hand, low pressure avoids deformation or damage to the underlying superconducting layer 2 due to excessive mechanical stress, reducing residual defects caused by stress concentration. The design of the polishing head rotation speed being lower than the platform rotation speed allows the polishing slurry to evenly cover the surface to be polished through relative motion, ensuring consistent abrasive action intensity and avoiding localized over-polishing or under-polishing. This range guarantees sufficient polishing efficiency while improving overall smoothness through stable relative motion.

[0043] S204. Deposit a second insulating layer over the fully exposed superconducting layer 2 and the first insulating layer 1, that is, deposit a second insulating layer 4 over the first insulating layer 1 and the superconducting layer 2 with their surfaces flush. like Figure 7 As shown, under vacuum conditions, a silicon dioxide target is bombarded with an electron beam, causing the silicon dioxide to evaporate and deposited on top of the first insulating layer 1 and the superconducting layer 2, which are flush with each other, to form a second insulating layer 4. The electron beam voltage is 10 kV, and the electron beam speed is 0.3-1.2 nm / s, for example, 0.8 nm / s, 0.9 nm / s, 1 nm / s, 1.1 nm / s, and 1.2 nm / s. The vacuum level is 1*E. -10 Torr. If the electron beam rate is low, such as 0.5 nm / s, the gas molecule migration is poor, resulting in poor film quality and poor film thickness uniformity. Electron beam rates of 0.3–1.2 nm / s can improve film quality and increase the density of the SiO2 film; simultaneously, more stable deposition efficiency can reduce local film thickness differences caused by rate fluctuations, improving film thickness uniformity and laying the foundation for uniformity in subsequent etching and polishing. S205, perform ion etching on the second insulating layer 4 to form the second protrusion structure 5; like Figure 8 As shown, a second protrusion structure 5 is formed on the surface of the second insulating layer 4 by reactive ion etching. Directly performing a second mechanical polishing on the second insulating layer 4 would cause stress concentration, thus affecting the planarization effect and reducing flatness. The second protrusion structure 5 obtained by reactive ion etching has multiple protrusion structures (two protrusions are shown as an example in the figure). These convex structures can be preferentially removed by polishing, guiding the selective elimination of surface unevenness during the polishing process and avoiding stress concentration, over-polishing, or under-polishing caused by large areas of flat surfaces. Simultaneously, reactive ion etching can adjust the surface roughness distribution of the second insulating layer 4, making the contact between the abrasive and the surface more uniform in the subsequent second mechanical polishing process, thereby improving the flatness of the second mechanical polishing.

[0044] S206. The second protrusion structure 5 on the surface of the second insulating layer 4 is removed by mechanical polishing to achieve planarization of the SFQ device bottom layer.

[0045] like Figure 9 As shown, the second protrusion structure 5 on the surface of the second insulating layer 4 is removed by a second mechanical polishing. Compared with direct second mechanical polishing without reactive ion etching, it has a better polishing effect and the local flatness is significantly improved. Ultimately, the stability of the entire device is expected to be improved by more than 20%.

[0046] like Figure 10 As shown, an SFQ device underlayer is also provided, the surface of which is planarized by the above-described SFQ device underlayer processing method.

[0047] The bottom layer of the SFQ device includes a first insulating layer 1, a second insulating layer 4, and a superconducting layer 2. The superconducting layer 2 is located between the first insulating layer 1 and the second insulating layer 4. The surface of the second insulating layer 4 is planarized by the aforementioned SFQ device bottom layer processing method. The first and second insulating layers can be silicon dioxide layers, and the superconducting layer can be a niobium layer.

[0048] Finally, it should be noted that other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and alterations may be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for processing the bottom layer of an SFQ device, wherein the bottom layer of the SFQ device comprises a first insulating layer and a superconducting layer encapsulated within the first insulating layer, characterized in that, Includes the following steps: Atomic layer etching is performed on the surface of the first insulating layer based on a mask to remove the first insulating layer on the superconducting layer and expose a portion of the superconducting layer. The first insulating layer is mechanically polished to fully expose the superconducting layer; A second insulating layer is deposited over the fully exposed superconducting layer and the first insulating layer; The surface of the second insulating layer is mechanically polished to achieve planarization of the SFQ device substrate.

2. The method according to claim 1, characterized in that, When atomic layer etching is performed on the surface of the first insulating layer based on a mask to remove the first insulating layer on the superconducting layer, a first protrusion structure is formed at the unexposed superconducting layer and its edge locations.

3. The method according to claim 1, characterized in that, Before mechanically polishing the surface of the second insulating layer to achieve planarization of the SFQ device substrate, the following steps are also included: The second insulating layer is ion-etched to form a second protrusion structure, the vertical projection surface of the second protrusion structure covering the edge of the superconducting layer and part of the superconducting layer.

4. The method according to claim 3, characterized in that, The step of mechanically polishing the surface of the second insulating layer to achieve planarization of the SFQ device includes: The second protrusion structure on the surface of the second insulating layer is removed by mechanical polishing to achieve planarization of the SFQ device substrate.

5. The method according to claim 1, characterized in that, The method of performing atomic layer etching on the surface of the first insulating layer based on a mask to remove the first insulating layer on one side of the superconducting layer includes: A mask is formed on the surface of the first insulating layer using photoresist; The etchant is adsorbed onto the first insulating layer by a carrier gas inside the mask. After the exposure time, the temperature is raised to remove the silicon dioxide of the single atom layer of the first insulating layer, thus completing one etching cycle. Repeated etching cycles are performed to completely remove the first insulating layer on one side of the superconducting layer.

6. The method according to claim 5, characterized in that, The etching agent is a mixture of hydrofluoric acid and ammonia gas at a pressure of 50-200 mTorr.

7. The method according to claim 5, characterized in that, The exposure time is 1-5 seconds.

8. The method according to claim 1, characterized in that, The deposition of a second insulating layer above the first insulating layer and the superconducting layer, which are flush with each other on the surface, includes: Under vacuum conditions, the silicon dioxide is evaporated by bombarding a silicon dioxide target with an electron beam and then deposited on top of the first insulating layer and the superconducting layer, which are flush with the surface, to form a second insulating layer.

9. The method according to claim 8, characterized in that, The electron beam has a velocity of 0.8-1.2 nm / s.

10. The method according to claim 1, characterized in that, The mechanical polishing is performed by polishing the first or second insulating layer with a rotating polishing head. The polishing pressure of the polishing head is 3-6 psi, and the rotation speed of the polishing head is 30-100 rpm.

11. The method according to claim 1, characterized in that, The first insulating layer and the second insulating layer are silicon dioxide layers, and the thin film superlayer is a niobium layer.

12. An SFQ device underlying layer, characterized in that, The surface of the SFQ device bottom layer is planarized by an SFQ device bottom layer processing method according to any one of claims 1-11.

13. The underlying layer of the SFQ device according to claim 12, characterized in that, The global flatness of the bottom layer of the SFQ device is less than or equal to 1.5 nm.

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