Method for forming optical packages

Abstract

The invention relates to a method for forming an optical package. The present disclosure provides a method for forming an optical package. The method includes forming a patterned hard mask on a surface of a semiconductor wafer. Additionally, the method includes forming respective photoresist structures on the surface of the semiconductor wafer in the plurality of recesses. The size of the surface area covered by the corresponding photoresist structure in the corresponding groove depends on the position of the corresponding groove on the semiconductor wafer. The method further includes performing a first etch process. In the first etching process, the semiconductor wafer is etched in the recess at a location not covered by the photoresist structure. Further, the method includes removing the photoresist structure after performing the first etching process, and performing a second etching process after removing the photoresist structure. In the second etch process, the semiconductor wafer is etched in the recess to form a cavity by lowering the structure formed in the first etch process.

Description

Technical Field

[0001] This disclosure relates to the formation of optical packages. In particular, examples of this disclosure relate to methods for forming optical packages. Background Technology

[0002] Wafer-scale glass blowing constitutes a cost-effective method for fabricating optical wafer-level packages for microelectromechanical systems (MEMS) devices such as laser beam scanners. A silicon wafer is constructed using deep reactive ion etching (DRIE) to create a cavity, typically an elliptical or circular shape with a diameter of a few millimeters and a depth of several hundred micrometers. The structured silicon wafer is irreversibly bonded to a glass wafer under defined conditions. The bonded wafer stack is heated to temperatures near the glass softening point in a furnace tube process. At the elevated temperature, the glass viscosity decreases and the pressure of the gas encapsulated within the cavity increases. A dome-shaped glass structure is formed above the cavity. The dome structure serves as an optical wafer-level package for MEMS structures by either opening the cavity within the silicon wafer or completely removing the silicon wafer from the glass wafer, along with another wafer bonding process.

[0003] The depth of the DRIE cavity varies substantially across the wafer. This uniformity variation is typically tool / equipment-dependent (e.g., chamber geometry, nozzle configuration, bias-dependent chuck configuration). An increase in cavity depth at the wafer edge is generally observed compared to the wafer center. With the increasing volume of the cavity associated with the increased depth, the final height of the blow-out dome structure also increases by a similar relative amount from the wafer center to the edge. During subsequent processing steps, this dome height expansion causes collisions within the manufacturing tooling. Furthermore, the dome height affects the optical properties of the package. To minimize optical aberrations, the center of curvature of the dome at its apex should be equal to the distance from the dome apex to the MEMS mirror surface. With the expansion of the dome height across a single wafer, this condition is substantially violated for a large number of devices. This violation translates into significant yield losses.

[0004] Therefore, there may be a need for improving the formation of optical packages. Summary of the Invention

[0005] This requirement is satisfied by the subject matter of the independent claim. Advantageous embodiments are addressed by the dependent claims.

[0006] According to a first aspect, this disclosure provides a method for forming an optical package. The method includes: forming a patterned hard mask on a surface of a semiconductor wafer. The patterned hard mask includes a plurality of recesses defining the locations of cavities to be formed in the semiconductor wafer. Additionally, the method includes: forming corresponding photoresist structures in the plurality of recesses on the surface of the semiconductor wafer. The size of the surface area covered by the corresponding photoresist structure in the corresponding recess depends on the location of the corresponding recess on the semiconductor wafer. The method further includes: performing a first etching process. In the first etching process, the semiconductor wafer is etched in the recesses at locations not covered by the photoresist structure. Furthermore, the method includes: after performing the first etching process, removing the photoresist structure, and after removing the photoresist structure, performing a second etching process. In the second etching process, the semiconductor wafer is etched in the recesses to form cavities by reducing the structure formed in the first etching process.

[0007] According to a second aspect, this disclosure provides another method for forming an optical package. The method includes: forming a patterned mask layer on the surface of a semiconductor wafer. The patterned mask layer includes a plurality of recesses defining the locations of cavities to be formed in the semiconductor wafer. Furthermore, the method includes: performing a first etching process. In the first etching process, the semiconductor wafer is etched in the plurality of recesses to form voids in the surface of the semiconductor wafer. The method includes: removing the patterned mask layer. Furthermore, the method includes: after removing the patterned mask layer, forming a photoresist structure. The photoresist structure partially covers the surface of the semiconductor wafer in the voids. The size of the surface area covered by the photoresist structure in the respective voids depends on the location of the respective void in the semiconductor wafer. Additionally, the method includes: performing a second etching process. In the second etching process, the semiconductor wafer is etched in the voids at locations not covered by the photoresist structure to form cavities.

[0008] By varying the size of the photoresist structure in the method according to the first aspect, and by varying the size of the surface area covered by the photoresist structure in the corresponding voids in the method according to the second aspect, this method compensates for potential variations in etching depth on a semiconductor wafer, particularly from the center to the edge of the wafer, resulting in a (more) uniform cavity depth. This method allows for a (more) uniform cavity depth on the wafer, which is beneficial for the consistent performance of optical devices packaged within these cavities. Additionally, yield can be increased. In summary, this method allows for the creation of well-defined cavities in semiconductor wafers, which is beneficial for high-precision optical packages used in a variety of technological applications. Attached Figure Description

[0009] The following will describe some examples of apparatus and / or methods by way of example and with reference to the accompanying drawings, wherein:

[0010] Figure 1 The illustration shows a flowchart of an example of a first method for forming an optical package.

[0011] Figure 2 The illustration shows a semiconductor wafer during different stages of a first embodiment variant of the first method for forming an optical package;

[0012] Figure 3 The illustration shows a semiconductor wafer during different stages of a second embodiment variant of the first method for forming an optical package;

[0013] Figure 4 The illustration shows an example of a semiconductor wafer with formed cavities;

[0014] Figure 5 The diagram illustrates the formation of the dome-shaped structure;

[0015] Figure 6 The illustration compares the relative volume changes of cavities on a semiconductor wafer between the first method and the conventional method;

[0016] Figure 7 The flowchart illustrates an example of a second method for forming an optical package; and

[0017] Figure 8 The illustration shows a semiconductor wafer during different stages of a second method for optical packaging. Detailed Implementation

[0018] Some examples will now be described in more detail with reference to the accompanying drawings. However, other possible examples do not limit the features of these embodiments described in detail. Other examples may include modifications to features, as well as equivalents and alternatives to features. Furthermore, the terminology used herein to describe a particular example should not limit other possible examples.

[0019] Throughout the description of the accompanying drawings, the same or similar reference numerals refer to the same or similar elements and / or features, which may be implemented in the same or modified form while providing the same or similar function. For clarity, the thickness of lines, layers, and / or areas in the drawings may also be enlarged.

[0020] When two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e., only A, only B, and A and B, unless otherwise explicitly defined in individual cases. As alternative wording for the same combination, "at least one of A and B" or "A and / or B" may be used. This equivalent applies to combinations of more than two elements.

[0021] If the singular forms such as “a,” “an,” and “the” are used and the use of a single element is not explicitly or implicitly defined as mandatory, other examples may use several elements to achieve the same functionality. If the functionality is described below as being implemented using multiple elements, other examples may use a single element or a single processing entity to achieve the same functionality. It should also be understood that the terms “including,” “comprise,” and / or “comprising,” when used, describe the presence of the specified feature, integer, step, operation, process, element, component, and / or combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components, and / or combinations thereof.

[0022] Figure 1 The diagram illustrates a flowchart of a method 100 for forming an optical package.

[0023] Method 100 includes forming a patterned hard mask 102 on the surface of a semiconductor wafer. The patterned hard mask includes a plurality of grooves defining the locations of cavities to be formed in the semiconductor wafer.

[0024] A semiconductor wafer is a thin, typically circular, sheet of semiconductor material used as a base platform. The semiconductor material can be, for example, silicon. The diameter of the semiconductor wafer can be, for example, between about 100 mm and about 300 mm, particularly 200 mm. The thickness of the semiconductor wafer can be, for example, between 400 μm and 1000 μm, particularly 600 μm. It should be noted that this disclosure does not limit the aforementioned exemplary materials and dimensions of the semiconductor wafer. Other suitable semiconductor materials and dimensions may also be used.

[0025] A patterned hard mask is a layer of material used to pattern cavities on a substrate. A cavity is a recessed area (groove, void) to be formed in a semiconductor wafer. Multiple grooves indicate the location of the cavities to be formed (or to be formed) within the wafer. For example, a patterned hard mask can be made of durable materials, such as dielectric materials like silicon nitride (Si3N4) or silicon dioxide (SiO2), or metals like titanium or tungsten, making the patterned hard mask less photosensitive than a photoresist. Forming a patterned hard mask (102) can, for example, include: depositing a hard mask material onto a semiconductor wafer; applying a photoresist layer onto the hard mask material; patterning the photoresist using a photomask, the photomask including a desired pattern defining the location where a cavity will be formed; developing the photoresist to remove exposed or unexposed areas of the photoresist (depending on the type of photoresist) and revealing the pattern on the underlying hard mask material; etching away the exposed hard mask to transfer the pattern from the photoresist to the hard mask material; and stripping away the remaining photoresist, such that the patterned hard mask remains on the semiconductor wafer. The thickness of the patterned hard mask can be, for example, between 0.5 μm and 10 μm, particularly 2.5 μm.

[0026] Additionally, method 100 includes: forming 104 corresponding photoresist structures in a plurality of recesses on the surface of a semiconductor wafer. The size of the surface area covered by the corresponding photoresist structure in the corresponding recess depends on the location of the corresponding recess on the semiconductor wafer. In other words, the photoresist structure is formed on the surface of the semiconductor wafer within a recess of a hard mask. The size of each photoresist structure varies based on its location on the wafer. The photoresist structure is made of a photosensitive material that undergoes a chemical change when exposed to light. For example, a positive or negative photoresist can be used. Forming the 104 corresponding photoresist structures may include, for example: applying a photoresist material; soft baking the applied photoresist material; patterning the photoresist material using a photomask including a desired pattern defining the locations where the photoresist structures will be formed; developing the photoresist to remove exposed or unexposed areas of the photoresist (depending on the type of photoresist) and expose the areas of the semiconductor wafer to be etched.

[0027] Method 100 further includes performing 106 a first etching process (first etching process). In the first etching process, a semiconductor wafer is etched in a trench at locations not covered by the photoresist structure. The photoresist structure defines an area of ​​the semiconductor wafer exposed by the trench in a patterned hard mask and protected during the first etching process. In the first etching process, the area of ​​the semiconductor wafer surface not covered by the patterned hard mask and the photoresist structure is etched to a specific depth. For example, DRIE can be used in the first etching process for etching the semiconductor wafer.

[0028] Furthermore, method 100 includes removing the 108 photoresist structure after performing a first etching process. Various techniques such as chemical stripping, plasma ashing, or wet chemical etching can be used to remove the photoresist structure. After removing the 108 photoresist structure, the area of ​​the semiconductor wafer protected during the first etching process is exposed.

[0029] Method 100 includes performing a second etching process (second etching process) 110 after removing the photoresist structure. In the second etching process, the semiconductor wafer is etched in a trench to form a cavity by reducing the structure formed in the first etching process. In other words, the cavity is further etched into the semiconductor wafer during the second etching process based on the initial structure formed during the first etching process. For example, DRIE can be used in the second etching process for etching the semiconductor wafer.

[0030] By varying the size of the photoresist structure, method 100 compensates for potential variations in etching depth on a semiconductor wafer, particularly variations from the center (central region) to the edge (peripheral boundary or outermost portion) of the semiconductor wafer, resulting in a (more) uniform cavity depth. The cavity depth refers to the vertical distance from the surface of the semiconductor wafer to the bottom of the etched cavity. Method 100 allows for a (more) uniform cavity depth on the semiconductor wafer, which is beneficial for the consistent performance of optical devices packaged within these cavities. For example, the cavity depths may differ from each other by less than 15% or less than 10% on the semiconductor wafer. Specifically, the cavity depths may differ by less than 15% or less than 10% from the center to the edge of the semiconductor wafer. The cavity depth may be at least 20%, 25%, or 30% and at most 75%, 80%, or 85% of the thickness of the semiconductor wafer. For example, if the thickness of the semiconductor wafer is between 400 μm and 1000 μm, the depth of the cavity can be between 100 and 600 μm, particularly 400 μm, with a depth variation of less than 15% or less than 10% on the semiconductor wafer (especially from the center to the edge of the semiconductor wafer). In summary, method 100 allows for the creation of well-defined cavities in a semiconductor wafer, which is beneficial for high-precision optical packages used in a variety of technical applications.

[0031] Multiple recesses in a patterned hard mask can be of the same size. In other words, all recesses can have uniform dimensions in terms of form (shape), size, and depth. Therefore, cavities can be formed to have uniform dimensions in terms of shape and size. For example, multiple recesses can be circular or elliptical. However, this disclosure is not limited to this. Recesses can generally be of any form. The lateral extension (i.e., horizontal dimension or width) of the corresponding cavity in a semiconductor wafer can be between 3 mm and 10 mm, particularly 5 mm.

[0032] According to the examples of this disclosure, the size of the surface area covered by the corresponding photoresist structure in the corresponding groove can vary from the center to the edge of the semiconductor wafer. In other words, the size of the area covered by the photoresist is not uniform on the semiconductor wafer. Instead, it gradually changes on the semiconductor wafer (e.g., from the center of the semiconductor wafer to its edge). In particular, the size of the surface area covered by the corresponding photoresist structure in the corresponding groove can vary from the center to the edge of the semiconductor wafer to compensate for the variation in etching depth from the center to the edge of the semiconductor wafer in the first etching process and the second etching process. By varying the photoresist coverage, method 100 compensates for the variation in etching depth that occurs naturally from the center to the edge of the semiconductor wafer. This ensures a more uniform cavity depth throughout the semiconductor wafer. The size of the surface area covered by the corresponding photoresist structure in the corresponding groove can, for example, increase from the center to the edge of the semiconductor wafer. In other words, as it moves from the center to the edge of the semiconductor wafer, the surface area covered by the corresponding photoresist structure in the groove increases. This variation compensates for the typically faster etching rate at the edge of the semiconductor wafer, ensuring a uniform cavity depth.

[0033] The following will be referenced Figure 2 and Figure 3 Other details of method 100 are described. Figure 2 and Figure 3 The semiconductor wafer is shown during different stages of two different implementation variations of method 100.

[0034] Figure 2 The illustration shows a semiconductor wafer 200 during different stages of a first embodiment variant of method 100. Figure 2 The figure shows a cross-sectional view through one half of the semiconductor wafer 200. The dashed line 201 indicates the center of the semiconductor wafer 200 (with a radial distance R = 0). The other half of the semiconductor wafer 200 is symmetrical and therefore not shown.

[0035] As shown in sub-Figure (a), a patterned hard mask 210 is initially formed on the surface 205 of the semiconductor wafer 200. For simplicity, the patterned hard mask 210 includes only two recesses 211 and 212. However, it should be noted that this disclosure is not limited thereto. Any number of recesses ≥ 2 can be formed in the patterned hard mask 210. Recess 211 is closer to the center of the semiconductor wafer 200 than recess 212. Recess 212 is closer to the edge 202 of the semiconductor wafer 200 than recess 211. Figure 2 In the example, grooves 211 and 212 are circular in shape and of the same size. Specifically, the radius r of both grooves 211 and 212 is... c It is constant (the same).

[0036] Then, as shown in sub-figure (b), corresponding photoresist structures 221 and 222 are formed on the surfaces of the semiconductor wafer 200 in the recesses 211 and 212. Photoresist structures 221 and 222 are formed at the boundaries of the recesses 211 and 212. Photoresist structures 221 and 222 contact the patterned hard mask 210 along the entire respective boundaries. Photoresist structures 221 and 222 do not cover the semiconductor wafer 200 at the center of the recesses 211 and 212. The internal contours of photoresist structures 221 and 222 have the same shape as the boundaries of the recesses 211 and 212. Since the recesses 211 and 212 are circular, in Figure 2 In the example, photoresist structures 221 and 222 are toroidal rings.

[0037] As can be seen from sub-figure (b), the size of the surface area covered by the corresponding photoresist structures 221 and 222 in the corresponding grooves 211 and 212 depends on the position of the corresponding grooves 211 and 222 on the semiconductor wafer 200. Specifically, the size of the surface area covered by the corresponding photoresist structures 221 and 222 in the corresponding grooves 211 and 212 increases from the center to the edge of the semiconductor wafer 200. The photoresist structure 222 covers a larger surface area in groove 212 than the photoresist structure 221 in groove 211.

[0038] The surface area in the corresponding recesses 211, 212 that is not covered by the corresponding photoresist structures 221, 222 decreases from the center to the edge of the semiconductor wafer 200. The surface area A in the corresponding recesses 211, 212 that is not covered by the corresponding photoresist structures 221, 222... s It depends on the radial distance R to the center of the semiconductor wafer 200, and is defined as follows:

[0039]

[0040] r sThe surface area A in the corresponding grooves 211, 212 that is not covered by the corresponding photoresist structures 221, 222 is represented by the area A. s The radius.

[0041] Then, as further shown in sub-figure (b), a first etching process is performed to etch the semiconductor wafer 200 at the center location in recesses 211 and 212 that is not covered by photoresist structures 221 and 222. For example, DRIE can be used to etch the semiconductor wafer 200 in the first etching process. In the first etching process, a first portion of the corresponding cavity is formed by removing a portion of the semiconductor wafer 200 at the center location that is not covered by photoresist structures 221 and 222. The portion of the semiconductor wafer 200 etched away in the first etching process is indicated by reference numerals 231 and 232. In the first etching process, a cylindrical first sub-cavity is formed in each recess in recesses 211 and 212.

[0042] As indicated in sub-figure (b), the depth of the structure formed in the first etching process is non-uniform on the semiconductor wafer 200. The depth of the structure formed in the first etching process depends on the radial distance R to the center of the semiconductor wafer 200. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 200. The structure formed at the center of the groove 212 that is not covered by the photoresist structure 222 is deeper than the structure formed at the center of the groove 211 that is not covered by the photoresist structure 221. This can be represented as follows:

[0043] d1(R)=d 1，0 ·d etch (R) (2)

[0044] d1(R) represents the depth of the structure formed in the first etching process at a specific radial distance R from the center of the semiconductor wafer 200. 1，0 This represents a constant reference depth (i.e., d) at the center of a semiconductor wafer. 1，0 =d1(R=0)), and d etch (R) represents a scaling function that depends on the radial distance R to the center of the semiconductor wafer 200. The value of the scaling function increases as the radial distance R to the center of the semiconductor wafer 200 increases.

[0045] Then, after performing the first etching process, photoresist structures 221 and 222 are removed. After removing photoresist structures 221 and 222, a second etching process is performed. This is illustrated in sub-figure (c). For example, DRIE can be used to etch the semiconductor wafer 200 in the second etching process. In the second etching process, the semiconductor wafer 200 is etched in recesses 211 and 212 to form cavities by reducing the structures formed in the first etching process. Thus, in the second etching process, a second portion of the corresponding cavity is formed by removing a portion of the semiconductor wafer 200 in recesses 211 and 212. The portions of the semiconductor wafer 200 etched away in the second etching process are indicated by reference numerals 241 and 242. In the second etching process, a cylindrical second sub-cavity is formed in each recess of recesses 211 and 212.

[0046] As indicated in sub-figure (c), the depth of the structure formed in the second etching process is non-uniform on the semiconductor wafer 200. The depth of the structure formed in the second etching process depends on the radial distance R to the center of the semiconductor wafer 200. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 200. The structure formed in groove 212 is deeper than the structure formed in groove 211. This can be represented as follows:

[0047] d2(R)=d 2，0 ·d etch (R) (3)

[0048] Where d2(R) represents the depth of the structure formed in the second etching process at a specific radial distance R from the center of the semiconductor wafer 200, and d 2，0 This represents a constant reference depth (i.e., d) at the center of a semiconductor wafer. 2,0 =d2(R=0)).

[0049] The resulting cavities 251 and 252 are shown in subgraph (d). Cavity 252 is deeper than cavity 251. The volume V of each cavity can be represented as follows:

[0050]

[0051] This can be rewritten based on mathematical expressions (3) and (4) as follows:

[0052]

[0053] Parameters V and r c These are predefined target parameters. Parameter d 1,0 d 2,0 and d etch(R) can be measured. Therefore, the mathematical expression (10) allows for the determination of the corresponding surface area A in the corresponding grooves 211, 212 that is not covered by the corresponding photoresist structures 221, 222. s The radius.

[0054] exist Figure 2 In the example, variations in etching depth are compensated for by constructing cavities with smaller diameters. The cavity structure formed in the first etching step is radius-dependent. Figure 2 In the example, the etched stepped structure creates cavities of varying diameters after the cavity is opened from the back of the wafer. The fact that no structure is released during the opening process reduces defect density.

[0055] Figure 3 The illustration shows a semiconductor wafer 300 during different stages of an alternative second embodiment variant of method 100. Figure 3 The figure shows a cross-sectional view through one half of the semiconductor wafer 300. The dashed line 301 indicates the center of the semiconductor wafer 300 (with a radial distance R = 0). The other half of the semiconductor wafer 300 is symmetrical and therefore not shown.

[0056] As shown in sub-figure (a), a patterned hard mask 310 is initially formed on the surface 305 of the semiconductor wafer 300. For simplicity, the patterned hard mask 310 includes only two recesses 311 and 312. However, it should be noted that this disclosure is not limited thereto. Any number of recesses ≥ 2 can be formed in the patterned hard mask 310. Recess 311 is closer to the center of the semiconductor wafer 300 than recess 312. Recess 312 is closer to the edge 302 of the semiconductor wafer 300 than recess 311. Figure 3 In the example, grooves 311 and 312 are circular in shape and of the same size. Specifically, the radius r of both grooves 311 and 312 is... c It is constant (the same).

[0057] As can be seen from sub-figure (b), the size of the surface area covered by the corresponding photoresist structures 321 and 322 in the corresponding grooves 311 and 312 depends on the position of the corresponding grooves 311 and 322 on the semiconductor wafer 300. In particular, the size of the surface area covered by the corresponding photoresist structures 321 and 322 in the corresponding grooves 311 and 312 increases from the center to the edge of the semiconductor wafer 300. The photoresist structure 322 covers a larger surface area in the groove 312 than the photoresist structure 321 covers in the groove 311.

[0058] The surface area in the corresponding recesses 311, 312 that is not covered by the corresponding photoresist structures 321, 322 decreases from the center to the edge of the semiconductor wafer 200. The surface area A in the corresponding recesses 311, 312 that is not covered by the corresponding photoresist structures 321, 322... p It depends on the radial distance R to the center of the semiconductor wafer 200, and is defined as follows:

[0059]

[0060] Where r p This represents the radius of the surface area covered by the corresponding photoresist structures 221 and 222 in the corresponding grooves 211 and 212.

[0061] Then, as further shown in sub-figure (b), a first etching process is performed to etch the semiconductor wafer 300 at locations in recesses 311 and 312 that are not covered by photoresist structures 321 and 322. For example, DRIE can be used to etch the semiconductor wafer 300 in the first etching process. In the first etching process, a first portion of a corresponding cavity is formed by removing a portion of the semiconductor wafer 300 at locations in recesses not covered by photoresist structures 321 and 322. The portions of the semiconductor wafer 300 etched away in the first etching process are indicated by reference numerals 331 and 332. In the first etching process, an annular first sub-cavity is formed in each of the recesses 311 and 212. The annular first sub-cavity surrounds a corresponding pillar at the center of each of the recesses 311 and 312.

[0062] As indicated in subfigure (b), the depth of the structure formed in the first etching process is non-uniform on the semiconductor wafer. The depth of the structure formed in the first etching process depends on the radial distance R to the center of the semiconductor wafer 300. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 300. The annular structure formed at the boundary of the groove 312 not covered by the photoresist structure 322 is deeper than the annular structure formed at the boundary of the groove 311 not covered by the photoresist structure 321. The depth can be represented similarly to the mathematical expression (2) above.

[0063] Then, after performing the first etching process, photoresist structures 321 and 322 are removed. After removing photoresist junctions 321 and 322, a second etching process is performed. This is illustrated in sub-figure (c). For example, DRIE can be used to etch semiconductor wafer 300 in the second etching process. In the second etching process, semiconductor wafer 300 is etched in recesses 311 and 312 to form cavities by reducing the structures formed in the first etching process. Thus, in the second etching process, a second portion of the corresponding cavity is formed by removing a portion of semiconductor wafer 300 in recesses 311 and 312. The portions of semiconductor wafer 200 etched away in the second etching process are indicated by reference numerals 341 and 342. In the second etching process, a cylindrical second sub-cavity is formed in each recess of recesses 311 and 312.

[0064] As indicated in sub-figure (c), the depth of the structure formed in the second etching process is non-uniform on the semiconductor wafer 300. The depth of the structure formed in the second etching process depends on the radial distance R to the center of the semiconductor wafer 300. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 300. The structure formed in the groove 312 is deeper than the structure formed in the groove 311. The depth can be represented similarly to the mathematical expression (2) above.

[0065] The resulting cavities 351 and 352 are shown in subgraph (d). Cavity 352 is deeper than cavity 351. The volume V of each cavity can be represented as follows:

[0066]

[0067] This can be rewritten based on the simulation of mathematical expressions (3) and (4) as follows:

[0068]

[0069] Similar mathematical expressions (10) and (19) allow for the determination of the radius of the corresponding surface area covered by the corresponding photoresist structures 321 and 322 in the corresponding grooves 311 and 312.

[0070] exist Figure 3 In the example, a hard mask is used in two etching steps to define the shape of the cavity at the wafer surface. In the first etching step, a circular resist spot defines a cylindrical structure at the center of a circle not covered by the hard mask. This is determined by the etching depth d. etchThe spatial dependence of (R) means that the radius of these cylinders depends on their position on the wafer to create cavities that are volumetrically uniform. After the resist is removed, a second etching stage reduces the structure created in the first stage. The second stage ensures the shape of the cavities at the silicon interface, and later defines the shape of the dome structure independently of the structure compensating for variations in spatial etch depth. One advantage of using cylindrical structures at the bottom of the cavities is that all cavities on the wafer have the same diameter after the cavities are opened from the back side of the wafer by wet or dry etching. Furthermore, the alignment of the mask defining the resist spots with the circular gaps in the hard mask is not critical.

[0071] exist Figure 4 The Chinese illustration has the above reference. Figure 3 A perspective view of a wafer 400 with multiple cavities 410 as described.

[0072] Back Figure 2 and Figure 3 , Figure 2 and Figure 3 Sub-figure (b) of each figure also highlights that method 100 may optionally further include: removing the patterned hard mask 210 / 310 112 after performing the second etching process. Various techniques such as wet chemical etching, dry etching (plasma etching), or stripping techniques can be used to remove the patterned hard mask. Removing the hard mask 112 leaves a clean semiconductor wafer surface for subsequent manufacturing steps.

[0073] The following will be referenced Figure 1 and Figure 5 Exemplary subsequent manufacturing steps of method 100 are described. Method 100 may further include: forming a 114-bonded wafer stack by bonding a semiconductor wafer to a glass wafer after removing a patterned hard mask. This is in Figure 5 The left portion is illustrated exemplarily. A semiconductor wafer 510 is bonded to a glass wafer 520 to form a bonded wafer stack 500. For simplicity, only a single cavity 515 is shown in the semiconductor wafer 510. The glass wafer 520 is a thin, typically circular sheet of glass material.

[0074] Bonding the semiconductor wafer 510 to the glass wafer 520 may include, for example, aligning the semiconductor wafer 510 to the glass wafer 520 and bonding it to the glass wafer 520. Bonding can be achieved using various techniques such as anodic bonding, adhesive bonding, or thermocompression bonding. This produces a composite wafer stack with the semiconductor wafer 510 on one side and the glass wafer 520 on the other side. The glass material can be any type of glass material having a CTE similar to that of the semiconductor wafer 510. For example, the glass material can be a sodium-containing glass, such as borosilicate glass. The diameter of the glass wafer 520 can be the same as the diameter of the semiconductor wafer 510 (e.g., between approximately 100 mm and approximately 300 nm), however, it is not necessarily the same. The thickness of the glass wafer 520 can be the same as or different from the thickness of the semiconductor wafer 510. It should be noted that this disclosure is not limited to the foregoing exemplary materials and dimensions of the glass wafer 520. Other suitable glass materials and dimensions may also be used. The pressure used to bond the semiconductor wafer 510 to the glass wafer 520 can be, for example, between 0 bar and 3 bar, particularly 2 bar. The semiconductor wafer 510 can be bonded to the glass wafer 520 at a temperature, for example, between 300°C and 500°C, particularly 330°C.

[0075] Method 100 may further include: forming 116 dome-shaped structures in a glass wafer at the location of the cavity by performing a furnace tube process on the bonded wafer stack. The dome-shaped structures are convex structures, meaning they curve outwards to form a dome shape protruding from the surface of the glass wafer, and thus forming the bonded wafer stack. The dome-shaped structures are positioned directly above the cavity in the semiconductor wafer. The size and curvature of each dome-shaped structure correspond to the size of the cavity below. This is in Figure 5 The right portion is illustrated exemplary. In a furnace tube process, controlled heating causes the glass wafer 510 to soften and increases the pressure of the gas encapsulated in a cavity such as cavity 515. The encapsulated gas deforms the soft glass wafer at a location corresponding to the cavity 515 in the semiconductor wafer 510 to form a dome-shaped structure. Figure 5 The diagram shows an exemplary dome-shaped structure 525 at the location of cavity 515. The furnace tube process can be used at temperatures between 700°C and 900°C, particularly 750°C.

[0076] Uniform cavity depth on the semiconductor wafer results in a more consistent height for the dome-shaped structure. With a more consistent height for the dome-shaped structure, the physical dimensions of the optical package are within a narrower specification. Additionally, optical aberrations introduced by the optical package are reduced and minimized. This can increase yield.

[0077] These dome-shaped structures can be used as lenses or protective covers for potential features of devices such as MEMS devices or other photonic or optical devices. References will be made below. Figure 1 Two exemplary methods for further processing the bonded wafer stacks are described.

[0078] According to the first method, method 100 further includes removing the semiconductor wafer 118 from the glass wafer after forming the dome structure. In other words, the two wafers are carefully separated without damaging the dome structure in the glass wafer. Techniques such as chemical etching, material separation, or other processes designed to release bonding without damaging the glass wafer or the dome structure can be used.

[0079] Method 100 further includes: in the first method, after removing the semiconductor wafer from the glass wafer, bonding the optical MEMS device 120 to the glass wafer. A dome-shaped structure covers the optical MEMS device. For example, the optical MEMS device can be aligned and bonded to the glass wafer. The bonding process ensures precise placement and secure attachment of the optical MEMS device under the dome-shaped structure. The dome-shaped structure provides a robust physical barrier, protecting the delicate optical MEMS device from mechanical damage and environmental contaminants such as dust or moisture. Furthermore, the dome-shaped structure can serve as a lens, focusing or guiding light onto or from the optical MEMS device, thereby enhancing its optical performance.

[0080] Forming a dome-shaped structure and attaching optical MEMS devices in sequential steps can streamline the manufacturing process, allowing for easy control.

[0081] In an alternative second method, method 100 may further include: after forming the dome-shaped structure, forming an opening 122 in the semiconductor wafer at the location of the cavity. The opening in the semiconductor wafer extends from a second surface of the semiconductor wafer to the cavity. The second surface is opposite to the surface of the semiconductor wafer. The opening may be formed, for example, in another etching process (e.g., using DRIE) or by laser drilling, such that a precise opening is formed in the semiconductor wafer, extending from the second surface (back side) of the wafer to the pre-formed cavity.

[0082] Method 100 may further include: in the second method, after forming an opening in the semiconductor wafer, bonding 124 of the optical MEMS device to a second surface of the semiconductor wafer. A dome-shaped structure covers the optical MEMS device. For example, the optical MEMS device can be aligned and bonded to the semiconductor wafer. Also according to the second method, the dome-shaped structure provides a robust physical barrier, protecting the delicate optical MEMS device from mechanical damage and environmental contaminants such as dust or moisture. Furthermore, the dome-shaped structure can serve as a lens, focusing or guiding light onto or from the optical MEMS device, thereby enhancing its optical performance.

[0083] The main difference between the first and second methods lies in the placement and integration of the optical MEMS devices. In the first method, the optical MEMS devices are bonded to a glass wafer after the semiconductor wafer is removed, while in the second method, the optical MEMS devices are bonded to a second surface of the semiconductor wafer through openings extending into the cavity, wherein dome-shaped structures in the glass wafer cover these devices.

[0084] Optical MEMS devices can be any type of miniaturized system that combines optical components with microelectromechanical elements. These optical MEMS devices integrate photonic and mechanical functions at the microscale to manipulate light and perform various optical functions. For example, an optical MEMS device can be a MEMS laser beam scanning device. MEMS laser beam scanning devices are miniature devices that use microfabricated mechanical structures to guide and manipulate laser beams (e.g., with high precision). These MEMS laser beam scanning devices integrate optical components with MEMS technology to achieve precise control over the position, orientation, and movement of the laser beam for various applications (e.g., light detection and ranging, lidar, or medical imaging).

[0085] As described above, method 100 allows for more uniform cavity depth to be achieved on a semiconductor wafer. This in Figure 6 This is further highlighted in Figure 600, which illustrates a comparison of the relative volume changes of cavities on a semiconductor wafer between Method 100 and the conventional method. The horizontal axis represents the distance from the corresponding cavity to the center of the semiconductor wafer in arbitrary units. The vertical axis represents the relative volume of the corresponding cavity.

[0086] Data point 610 represents the relative volume of a cavity formed in a semiconductor wafer according to method 100 described above. For reference, data point 620 represents the relative volume of a cavity formed in a semiconductor wafer according to a conventional method. The semiconductor wafer is the same for both methods.

[0087] from Figure 6It can be seen that when formed using method 100, the relative volume change (different) of the cavities on the semiconductor wafer is smaller. This is due to the more uniform cavity depth on the semiconductor wafer achieved using method 100.

[0088] The following will be referenced Figure 7 An alternative method 700 for forming a semiconductor package is described.

[0089] Method 700 includes forming a patterned mask layer 702 on the surface of a semiconductor wafer. The patterned mask layer includes a plurality of grooves defining the locations of cavities to be formed in the semiconductor wafer.

[0090] A patterned mask layer is a patterned material layer applied to the surface of a semiconductor wafer to pattern cavities to be formed in the semiconductor wafer. For example, the patterned mask layer may be a patterned hard mask used in method 100 described above. In an alternative example, the patterned mask layer may be a patterned photoresist. The patterned photoresist is made of a photosensitive material that undergoes a chemical change when exposed to light. For example, a positive or negative photoresist may be used. The patterned photoresist may be formed, for example, by spin coating. Forming a patterned photoresist by spin coating may include, for example, dispensing (a predefined amount) of liquid photoresist material onto the center of a semiconductor wafer, rotating the semiconductor wafer (e.g., at a rotational speed of 1000 to 6000 revolutions per minute) to uniformly distribute the photoresist material on the semiconductor wafer, soft-baking the distributed photoresist material, patterning the photoresist material using a photomask comprising a desired pattern defining the location of the patterned photoresist to be formed, developing the photoresist to remove exposed or unexposed areas of the photoresist (depending on the type of photoresist) and revealing the areas of the semiconductor wafer to be etched.

[0091] Method 700 further includes performing a first etching process (first etching process) 704 after forming a patterned mask layer. In the first etching process, the semiconductor wafer is etched in a plurality of grooves to form voids (deepenings, gaps, recesses) in the surface of the semiconductor wafer. The patterned mask layer covers areas of the semiconductor wafer protected during the first etching process. In the first etching process, areas of the surface of the semiconductor wafer not covered by the patterned mask layer are etched to a specific depth such that voids are formed in the surface of the semiconductor wafer. For example, DRIE can be used in the first etching process for etching the semiconductor wafer.

[0092] Furthermore, method 700 includes removing the 706 patterned mask layer after performing the first etching process. Various techniques such as chemical stripping, plasma ashing, (wet) chemical etching, dry etching (plasma etching), or stripping techniques can be used to remove the patterned mask layer. After removing the 706 patterned mask layer, the area of ​​the semiconductor wafer protected during the first etching process is exposed.

[0093] Method 700 includes forming a 708 photoresist structure after removing a patterned mask layer. The photoresist structure partially covers the surface of a semiconductor wafer within a cavity. The size of the surface area covered by the photoresist structure in the corresponding cavity depends on the location of the corresponding cavity in the semiconductor wafer. In other words, the photoresist structure is applied such that it partially covers the surface of the wafer within the previously etched cavity. The photoresist structure extends to the boundary of the cavity. The photoresist structure does not cover the semiconductor wafer at the center of the cavity. That is, the edges of the cavity are covered (protected) by the photoresist structure, but the central area remains exposed. For example, the internal contour of the photoresist structure in the cavity can have the same shape as the boundary of the cavity. This means that the pattern of the photoresist within the cavity can closely match the shape of the cavity itself, thereby ensuring accurate and consistent coverage. The size of the area covered by photoresist in each cavity is controlled and varies according to the cavity on the wafer. Different voids can have different amounts of photoresist coverage.

[0094] The photoresist structure is made of a photosensitive material that undergoes a chemical change when exposed to light. For example, positive or negative photoresists can be used. The photoresist structure can be formed by spraying. Forming a 708 photoresist structure by spraying may include, for example: spraying liquid photoresist material onto the surface of a semiconductor wafer under controlled pressure through a nozzle; soft-bake sprayed photoresist material; patterning the photoresist material using a photomask that includes a desired pattern defining the location where the photoresist structure will be formed; developing the photoresist to remove exposed or unexposed areas of the photoresist (depending on the type of photoresist) and expose the areas of the semiconductor wafer to be etched.

[0095] Method 700 includes performing a second etching process (second etching process) 710 after forming the photoresist structure. In the second etching process, the semiconductor wafer is etched into voids to form cavities at locations not covered by the photoresist structure. In other words, the semiconductor wafer is further etched within the voids, but only in the areas exposed by the photoresist structure. This additional etching deepens the voids to form the final cavities. The photoresist is used as a protective mask during this second etching process to prevent further etching of specific areas within the voids. For example, DRIE can be used in the second etching process to etch the semiconductor wafer.

[0096] By varying the size of the surface area covered by the photoresist structure within the corresponding cavities, method 700 compensates for potential variations in etch depth on the semiconductor wafer, particularly variations in etch depth from the center to the edge of the semiconductor wafer, resulting in a (more) uniform cavity depth. Similar to method 100, method 700 allows for a (more) uniform cavity depth on the semiconductor wafer, which benefits the consistent performance of optical devices encapsulated within these cavities. For example, the cavity depths may differ from each other by less than 15% or less than 10% on the semiconductor wafer. Specifically, the cavity depths may differ by less than 15% or less than 10% from the center to the edge of the semiconductor wafer. The cavity depth may be at least 20%, 25%, or 30% and at most 75%, 80%, or 85% of the thickness of the semiconductor wafer. For example, if the thickness of the semiconductor wafer is between 400 μm and 1000 μm, the depth of the cavity can be between 100 and 600 μm, particularly 400 μm, with a depth variation of less than 15% or less than 10% on the semiconductor wafer (especially from the center to the edge of the semiconductor wafer). In summary, method 700 allows for the creation of well-defined cavities on a semiconductor wafer, which is beneficial for high-precision optical packages used in a variety of technical applications.

[0097] Photoresist structures can cover another part of a semiconductor wafer. For example, photoresist structures can be formed to cover the sidewalls of a cavity. Sidewalls are the vertical or sloping surfaces of cavities etched into the semiconductor wafer during a first etching process. If the sidewalls of the cavity are covered with photoresist (i.e., through a photoresist structure), the surface is protected during a second etching process. Therefore, only the bottom of the cavity will be further etched, rather than the sides. This helps maintain the shape and integrity of the cavity sidewalls.

[0098] Alternatively or additionally, the photoresist structure can be formed to cover the surface of the semiconductor wafer at locations covered by a patterned mask layer in the first etching process. Essentially, this means that the photoresist structure is applied to areas of the semiconductor wafer that were not etched in the first etching step. This helps protect these areas from unwanted etching.

[0099] Similar to the description of method 100 above, multiple recesses in a patterned mask layer can be of the same size. In other words, all recesses can have uniform dimensions in terms of form (shape), size, and depth. Therefore, cavities can be formed to have uniform dimensions in terms of shape and size. For example, multiple recesses can be circular or elliptical. However, this disclosure is not limited to this. Recesses can generally be of any form. The lateral extension (i.e., horizontal dimension or width) of the corresponding cavity in the semiconductor wafer can be between 3 mm and 10 mm, particularly 5 mm.

[0100] According to the examples of this disclosure, the size of the surface area covered by the photoresist structure in the corresponding cavity can vary from the center to the edge of the semiconductor wafer. In other words, the size of the photoresist-covered area is non-uniform on the semiconductor wafer. Instead, it varies gradually on the semiconductor wafer (e.g., from the center to the edge). Specifically, the size of the surface area covered by the photoresist structure in the corresponding cavity can vary from the center to the edge of the semiconductor wafer to compensate for the variation in etching depth from the center to the edge of the semiconductor wafer in the first and second etching processes. By changing the photoresist coverage, method 700 compensates for the naturally occurring variation in etching depth from the center to the edge of the semiconductor wafer, similar to method 100. This ensures a more uniform cavity depth on the semiconductor wafer. The size of the surface area covered by the photoresist structure in the corresponding cavity can, for example, increase from the center to the edge of the semiconductor wafer. In other words, the size of the surface area covered by the photoresist structure in the corresponding cavity increases as one moves from the center of the semiconductor wafer toward its edge. This variation compensates for the typically faster etching rate at the edges of the semiconductor wafer, thereby ensuring a uniform cavity depth.

[0101] The following will be referenced Figure 8 Other details of method 700, Figure 8 Semiconductor wafer 800 is shown during different stages of method 700. Figure 8 The diagram shows a cross-sectional view through semiconductor wafer 800. The dashed line 801 indicates the center of semiconductor wafer 800 (with a radial distance R = 0).

[0102] As shown in sub-figure (a), a patterned mask layer 810 is initially formed on the surface 805 of the semiconductor wafer 800. For simplicity, the patterned mask layer 810 includes only four recesses 811, ..., 814. However, it should be noted that this disclosure is not limited thereto. Any number of recesses K ≥ 2 can be formed in the patterned mask layer 810. Recesses 811 and 813 are located at the center of the semiconductor wafer 800. Recess 811 is closer to the center of the semiconductor wafer 800 than recess 812. Recess 812 is closer to the edge 802 of the semiconductor wafer 800 than recess 811. Similarly, recess 813 is closer to the center of the semiconductor wafer 800 than recess 814. Figure 8 In the example, grooves 811, ..., 814 are circular in shape and have the same size. In particular, the radii of grooves 811, ..., 814 are constant (the same).

[0103] Then, as shown in sub-figure (b), a first etching process is performed to etch the semiconductor wafer 800 in the recesses 811, ..., 814, i.e., at locations not covered by the patterned mask layer 810. For example, DRIE can be used to etch the semiconductor wafer 800 in the first etching process. In the first etching process, by removing portions of the semiconductor wafer 800 in the recesses 811, ..., 814, voids are formed as first portions of corresponding cavities. The portions of the semiconductor wafer 800 etched away in the first etching process are indicated by reference numerals 821, ..., 824. In the first etching process, cylindrical first sub-cavities are formed in each of the recesses 811, ..., 814.

[0104] As indicated in sub-figure (b), the depths of the voids 821, ..., 824 formed in the first etching process are non-uniform on the semiconductor wafer 800. The depths of the voids 821, ..., 824 formed in the first etching process depend on the radial distance R to the center of the semiconductor wafer 800. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 800. The void 822 formed in the groove 812 is deeper than the void 821 formed in the groove 811. Similarly, the void 824 formed in the groove 814 is deeper than the void 823 formed in the groove 813. Since the grooves 811 and 813 are located at the same radial distance to the center of the semiconductor wafer 800, the depths of the voids 821 and 823 are substantially the same. Similarly, since the grooves 812 and 814 are located at the same radial distance to the center of the semiconductor wafer 800, the depths of the voids 822 and 824 are substantially the same.

[0105] Then, after performing the first etching process, the patterned mask layer 810 is removed. This is illustrated in sub-figure (c).

[0106] After the patterned mask layer 810 is removed, a photoresist structure 830 is formed. This is illustrated in sub-figure (d). The photoresist structure 830 covers the surface 805 of the semiconductor wafer 800 at the location covered by the patterned mask layer 810 during the first etching process. In other words, the photoresist structure 830 covers the portions of the surface 805 of the semiconductor wafer 800 where voids 821, ..., 824 are not formed.

[0107] A photoresist structure 830 partially covers the surface 805 of the semiconductor wafer 800 within the cavities 821, ..., 824. The photoresist structure 830 covers the boundaries of the cavities 821, ..., 824. In other words, the photoresist structure 830 extends to the boundaries of the cavities 821, ..., 824. The photoresist structure 830 also covers the sidewalls of the cavities 821, ..., 824. The photoresist structure 830 does not cover the semiconductor wafer 800 at the center of the cavities 821, ..., 824. The internal contour of the photoresist structure 830 within the cavities 821, ..., 824 exhibits the same shape as the boundaries of the cavities 821, ..., 824. Because in Figure 8 In the example, the grooves 811, ..., 814 and therefore the cavities 821, ..., 824 are circular, and the photoresist structure 830 forms annular rings in the cavities 821, ..., 824.

[0108] As can be seen from sub-figure (d), the size of the surface area covered by the photoresist structure 830 in the corresponding voids 821, ..., 824 depends on the position of the corresponding voids 821, ..., 824 in the semiconductor wafer 800. Specifically, the size of the surface area covered by the photoresist structure 830 in the corresponding voids 821, ..., 824 increases from the center to the edge of the semiconductor wafer 800. The photoresist structure 830 covers more surface area in void 822 than in void 821. Similarly, the photoresist structure 830 covers more surface area in void 824 than in void 823. Since the grooves 811 and 813, and therefore the voids 821 and 823, are located at the same radial distance from the center of the semiconductor wafer 800, the surface areas covered by the photoresist structure 830 in voids 822 and 824 are substantially the same.

[0109] As illustrated in sub-figure (e), a second etching process is performed after the photoresist structure 830 is formed. For example, DRIE can be used to etch the semiconductor wafer 800 in the second etching process. In the second etching process, the semiconductor wafer 800 is etched in the voids 821, ..., 824 at locations not covered by the photoresist structure 830. Therefore, in the second etching process, a second portion of the corresponding cavity is formed by removing a portion of the semiconductor wafer 800 in the recesses 821, ..., 824. The portions of the semiconductor wafer 800 etched away in the second etching process are indicated by reference numerals 841, ..., 844. In the second etching process, a cylindrical second sub-cavity is formed in each of the recesses 811, ..., 814.

[0110] As illustrated in sub-figure (e), the depth of the structure (second sub-cavity) formed in the second etching process is non-uniform on the semiconductor wafer 800. The depth of the structure formed in the second etching process depends on the radial distance R to the center of the semiconductor wafer 800. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 800.

[0111] The resulting cavities 851, ..., 854 are shown in sub-figure (f). Cavity 852 is deeper than cavity 851. Similarly, cavity 854 is deeper than cavity 853. Since recesses 811 and 813, and therefore cavities 821 and 823, are located at the same radial distance from the center of semiconductor wafer 800, the depths of cavities 852 and 854 are substantially the same.

[0112] exist Figure 8 In the example, variations in etching depth are compensated for by constructing cavities with smaller dimensions. The cavity structure formed in the second etching step is radius-dependent. After opening the cavity from the back side of the wafer, in Figure 8 In the example, the etched stepped structure creates cavities of varying diameters. The fact that no structure is released during the opening process reduces defect density.

[0113] Similar to Figure 2 and Figure 3 The removal of the patterned hard mask 210 / 310 in the example. Figure 8 Sub-figure (f) highlights that method 700 may optionally further include: removing the 712 photoresist structure 830 after performing the second etching process. Various techniques such as chemical stripping, plasma ashing, or wet chemical etching can be used to remove the photoresist structure 830. Removing the 712 photoresist structure 830 leaves a clean semiconductor wafer surface for subsequent manufacturing steps.

[0114] For example, method 700 may further include: after removing the photoresist structure, forming a 714 bonded wafer stack by bonding a semiconductor wafer to a glass wafer, and forming a 716 dome-shaped structure in the glass wafer at the location of the cavity by performing a furnace tube process on the bonded wafer stack. This can be done similarly to what has been described above for method 100.

[0115] Method 700 may include other features of method 100 described above. For example, method 700 may further include: removing a semiconductor wafer 718 from a glass wafer after forming the dome structure, and bonding an optical MEMS device 720 to the glass wafer after removing the semiconductor wafer from the glass wafer. The dome structure covers the optical MEMS device. Alternatively, method 700 may further include: forming an opening 722 in the semiconductor wafer at the location of the cavity after forming the dome structure. The opening in the semiconductor wafer extends from a second surface of the semiconductor wafer to the cavity. The second surface is opposite to the surface of the semiconductor wafer. Method 700 may then additionally include: bonding an optical MEMS device 724 to the second surface of the semiconductor wafer after forming the opening in the semiconductor wafer. The dome structure covers the optical MEMS device. Details of these optional other features of method 700 are given above with reference to method 100.

[0116] The aspects and features described in a particular example from the previous examples can also be combined with one or more examples from other examples to replace the same or similar features of those other examples, or additionally introduce features into those other examples.

[0117] It should also be understood that the disclosure of several steps, processes, operations, or functions in the specification or claims should not be construed as implying that these operations must depend on the described order, unless expressly stated in a single case or necessary for technical reasons. Therefore, the preceding description does not limit the execution of several steps or functions to a particular order. Furthermore, in other examples, a single step, function, process, or operation may include and / or be decomposed into several sub-steps, sub-functions, sub-processes, or sub-operations.

[0118] If aspects of a device or system have already been described, these aspects should also be understood as descriptions of the corresponding methods. For example, a block, device, or functional aspect of a device or system may correspond to a feature of the corresponding method, such as method steps. Therefore, aspects describing a method should also be understood as descriptions of corresponding blocks, elements, characteristics, or functional features of the corresponding device or system.

[0119] The following claims are thus incorporated into the detailed description, wherein each claim may be considered an independent example. It should also be noted that, although in the claims, dependent claims relate to a particular combination with one or more other claims, other examples may also include combinations of dependent claims with the subject matter of any other dependent or independent claim. Such combinations are expressly stated herein unless it is indicated in a single case that a particular combination is not intended. Furthermore, the features of a claim should also be included in any other independent claim, even if that claim is not directly defined as dependent on that other independent claim.

Claims

1. A method (100) for forming an optical package, the method (100) comprising: forming (102) a patterned hardmask on a surface of a semiconductor wafer, wherein the patterned hardmask comprises a plurality of grooves, the plurality of grooves defining locations of cavities to be formed in the semiconductor wafer; forming (104) a respective photoresist structure on the surface of the semiconductor wafer in a respective one of the plurality of grooves, wherein a size of a surface area covered by the respective photoresist structure in the respective groove depends on a location of the respective groove on the semiconductor wafer; performing (106) a first etching process, wherein, in the first etching process, the semiconductor wafer is etched in the grooves at locations not covered by the photoresist structures; after performing the first etching process, removing (108) the photoresist structures; and after removing the photoresist structures, performing (110) a second etching process, wherein, in the second etching process, the semiconductor wafer is etched in the grooves to form the cavities by reducing structures formed in the first etching process.

2. The method (100) of claim 1, wherein the size of the surface area covered by the respective photoresist structure in the respective groove varies from a center to an edge of the semiconductor wafer.

3. The method (100) of claim 1 or 2, wherein the size of the surface area covered by the respective photoresist structure in the respective groove varies from a center to an edge of the semiconductor wafer to compensate for a variation in etch depth from the center to the edge of the semiconductor wafer in the first etching process and the second etching process.

4. The method (100) of any one of claims 1 to 3, wherein the size of the surface area covered by the respective photoresist structure in the respective groove increases from a center to an edge of the semiconductor wafer.

5. The method (100) of any one of claims 1 to 4, wherein the photoresist structure exhibits a same shape as the grooves.

6. The method (100) of any one of claims 1 to 5, wherein the photoresist structure is formed at a center of the groove.

7. The method (100) of any one of claims 1 to 6, wherein the photoresist structure is spaced apart from a boundary of the groove formed by the patterned hardmask.

8. The method (100) of any one of claims 1 to 4, wherein the photoresist structure is formed at a boundary of the groove and contacts the patterned hardmask along an entirety of the respective boundary, and wherein the photoresist structure does not cover the semiconductor wafer at a center of the groove.

9. The method (100) of claim 8, wherein an inner profile of the photoresist structure exhibits a same shape as the boundary of the groove.

10. The method (100) of any of claims 1 to 9, further comprising: removing (112) the patterned hard mask after performing the second etch process.

11. The method (100) of claim 10, further comprising: forming (114) a bonded wafer stack by bonding the semiconductor wafer to a glass wafer after removing the patterned hard mask; and forming (116) a dome-shaped structure in the glass wafer at the location of the cavity by performing a tube furnace process on the bonded wafer stack.

12. A method (700) for forming an optical package, the method (700) comprising: forming (702) a patterned mask layer on a surface of a semiconductor wafer, wherein the patterned mask layer comprises a plurality of grooves defining locations of cavities to be formed in the semiconductor wafer; performing (704) a first etch process, wherein, in the first etch process, the semiconductor wafer is etched in a plurality of the grooves to form voids in the surface of the semiconductor wafer; removing (706) the patterned mask layer; forming (708) a photoresist structure after removing the patterned mask layer, wherein the photoresist structure partially covers the surface of the semiconductor wafer in the voids, wherein a size of a surface area covered by the photoresist structure in a respective void depends on a location of the respective void in the semiconductor wafer; and performing a second etch process, wherein, in the second etch process, the semiconductor wafer is etched in the voids at locations not covered by the photoresist structure to form the cavities.

13. The method (700) of claim 12, wherein the patterned mask layer is a patterned hard mask.

14. The method (700) of claim 12, wherein the patterned mask layer is a patterned photoresist.

15. The method (700) of claim 14, wherein the patterned photoresist is formed by spin coating.

16. The method (700) of any of claims 12 to 15, wherein the photoresist structure is formed to cover sidewalls of the voids.

17. The method (700) of any of claims 12 to 15, wherein the photoresist structure is formed to cover the surface of the semiconductor wafer at locations covered by the patterned mask layer in the first etch process.

18. The method (700) of any of claims 12 to 17, wherein the photoresist structure is formed by spray coating.

19. The method (700) of any of claims 12 to 18, wherein the size of the surface area covered by the photoresist structure in a respective void varies from a center to an edge of the semiconductor wafer.

20. The method (700) of any of claims 12-19, wherein the size of the surface area covered by the photoresist structure in the respective void varies from a center to an edge of the semiconductor wafer to compensate for a variation in etch depth from the center to the edge of the semiconductor wafer in the first etch process and the second etch process.

21. The method (700) of any of claims 12-20, wherein the size of the surface area covered by the photoresist structure in the respective void increases from a center to an edge of the semiconductor wafer.

22. The method (700) of any of claims 12-21, wherein the photoresist structure extends to a boundary of the void, and wherein the photoresist structure does not cover the semiconductor wafer at a center of the void.

23. The method (700) of claim 22, wherein an inner profile of the photoresist structure in the void exhibits a same shape as the boundary of the void.

24. The method (700) of any of claims 12-23, further comprising: removing (712) the photoresist structure after performing the second etch process.

25. The method (700) of claim 24, further comprising: forming (714) a bonded wafer stack by bonding the semiconductor wafer to a glass wafer after removing the photoresist structure; and forming (716) a dome-shaped structure in the glass wafer at a location of the cavity by performing a tube process on the bonded wafer stack.

26. The method (100, 700) of claim 11 or 25, further comprising: removing (118, 718) the semiconductor wafer from the glass wafer after forming the dome-shaped structure; and bonding (120, 720) an optical MEMS device to the glass wafer after removing the semiconductor wafer from the glass wafer, wherein the dome-shaped structure covers the optical MEMS device.

27. The method (100, 700) of claim 11 or 25, further comprising: forming (122, 722) an opening in the semiconductor wafer at a location of the cavity after forming the dome-shaped structure, wherein the opening in the semiconductor wafer extends from a second surface of the semiconductor wafer to the cavity, and wherein the second surface is opposite the surface of the semiconductor wafer; and bonding (124, 724) the optical MEMS device to the second surface of the semiconductor wafer after forming the opening in the semiconductor wafer, wherein the dome-shaped structure covers the optical MEMS device.

28. The method (100, 700) of claim 26 or 27, wherein the optical MEMS device is a MEMS laser beam scanning device.

29. The method (100, 700) according to any of claims 1 to 28, wherein deep reactive ion etching is used in the first etching process and the second etching process for etching the semiconductor wafer.

30. The method (100, 700) according to any of claims 1 to 29, wherein a plurality of the recesses exhibit the same size.

31. The method (100, 700) according to any of claims 1 to 30, wherein a plurality of the recesses exhibit a circular or elliptical form.

32. The method (100, 700) according to any of claims 1 to 31, wherein the depth of the cavities is at least 25% and at most 80% of the thickness of the semiconductor wafer.

33. The method (100, 700) according to any of claims 1 to 32, wherein the depth of the cavities differs from each other by less than 15% on the semiconductor wafer.

34. The method (100, 700) according to any of claims 1 to 33, wherein the lateral extension of the respective cavities in the semiconductor wafer is at most 10 mm.

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