Communication method of baseboard management controller and processor

Abstract

The invention discloses a communication method for a substrate management controller and a processor, and relates to the technical field of server hardware management, and the method comprises the steps: employing a peripheral component interconnect express (PCIe) link to replace multiple links, transmitting data through the PCIe link in a unified manner, and reducing the pin occupation amount; the PCIe protocol is uniformly adopted for interaction between the processor and the baseboard management controller, multi-protocol adaptation and time sequence conflict processing are reduced, the development period is shortened, and the maintenance cost is reduced; after the substrate management controller receives the service data returned by the processor, the corresponding operation instruction is determined, and then the operation instruction is issued to the processor for execution through the PCIe link, so that an integrated link of data acquisition and control instruction issuing is realized, instruction format conversion among multiple protocols is also avoided, and the compatibility risk is reduced.

Description

Technical Field

[0001] This application relates to the field of server hardware management technology, and in particular to a communication method between a baseboard management controller and a processor. Background Technology

[0002] In the hardware management system of AMD platform servers, the Baseboard Management Controller (BMC), as a dedicated control unit independent of the main central processing unit (CPU) and operating system, needs to acquire real-time operating data from core components such as the CPU and Dual In-Line Memory Modules (DIMMs) and perform fault diagnosis and other operations to ensure stable server operation. Currently, the industry generally adopts a multi-hardware link and corresponding protocol combination scheme to realize CPU-BMC interaction, with multiple links working together to form the core communication architecture.

[0003] However, this multi-link interaction architecture has significant technical flaws, making it difficult to meet the requirements of efficiency, scalability, and stability: First, the complex link combination occupies a large number of general-purpose input / output (GPIO) pin resources on the motherboard, limiting the flexibility of subsequent functional expansion; second, the parallel operation of multiple protocols increases the complexity of hardware design and software adaptation, not only increasing R&D costs and time, but also easily causing compatibility issues; third, the superposition of multiple links and multiple protocols reduces the stability and reliability of data transmission, easily leading to problems such as link preemption, data frame loss, or verification errors, affecting the timeliness of BMC data acquisition and fault diagnosis, and posing a potential risk to the stable operation of the server. Summary of the Invention

[0004] This application provides a communication method between a baseboard management controller and a processor, which at least solves the defects of related technologies, such as occupying a large number of GPIO pin resources, limiting the expansion of motherboard functions, increasing the difficulty of hardware and software design adaptation due to multiple protocols running in parallel, and easily causing signal interference and compatibility problems, as well as reducing the stability and reliability of data transmission.

[0005] This application provides a communication method between a baseboard management controller and a processor, applied to a baseboard management controller, wherein a high-speed peripheral component interconnect (PSI) link is established between the baseboard management controller and the processor. The method includes: in response to a pre-coded instruction, sending a data request message to the processor via the PSI link; obtaining a data response message returned by the processor via the PSI link, the data response message carrying the processor's service data; analyzing the service data, and determining an operation instruction from an instruction set based on the analysis results of the service data; wherein the instruction set is defined based on a high-speed PSI protocol, and the operation instruction is used to instruct the processor to perform a corresponding operation; and sending the operation instruction to the processor via the PSI link.

[0006] This application provides another communication method between a baseboard management controller and a processor, applied to a processor, wherein a high-speed peripheral component interconnect link is established between the baseboard management controller and the processor. The method includes: receiving a data request message sent by the baseboard management controller through the high-speed peripheral component interconnect link; in response to the data request message, acquiring service data; packaging the service data according to the high-speed peripheral component interconnect protocol to generate a service data response message; sending the service data response message to the baseboard management controller through the high-speed peripheral component interconnect link; receiving an operation instruction sent by the baseboard management controller through the high-speed peripheral component interconnect link; and performing a corresponding operation in response to the operation instruction.

[0007] This application also provides a communication device between a baseboard management controller and a processor, comprising: a baseboard management controller and a processor, wherein a high-speed peripheral component interconnection link is established between the baseboard management controller and the processor; The baseboard management controller is used to send data request messages to the processor via a high-speed peripheral component interconnect link in response to pre-coded instructions; The processor is used to receive data request messages sent by the baseboard management controller through the high-speed peripheral component interconnect link; in response to the data request message, acquire service data; package the service data according to the high-speed peripheral component interconnect protocol to generate a service data response message; and send the service data response message to the baseboard management controller through the high-speed peripheral component interconnect link. The baseboard management controller is used to acquire data response messages returned by the processor through the high-speed peripheral component interconnection link. The data response messages carry the processor's service data; analyze the service data, and determine operation instructions from the instruction set based on the analysis results; wherein, the instruction set is defined based on the high-speed peripheral component interconnection protocol, and the operation instructions are used to instruct the processor to perform corresponding operations; and send the operation instructions to the processor through the high-speed peripheral component interconnection link.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the communication method between the baseboard management controller and the processor when executing the computer program.

[0009] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described communication method between the baseboard management controller and the processor.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described communication method between the baseboard management controller and the processor.

[0011] This application uses a high-speed peripheral component interconnect (PCIe) link to transmit all data uniformly through the PCIe link, reducing the number of pins occupied and freeing up pin resources for server function expansion. The interaction between the processor and the baseboard management controller uniformly adopts the PCIe protocol, eliminating the parallel implementation of multiple link protocol stacks, thereby reducing multi-protocol adaptation and timing conflict handling, which helps to shorten the development cycle and reduce maintenance costs. After receiving the service data returned by the CPU, the BMC determines the corresponding operation instructions, which are then sent to the CPU for execution through the PCIe link. This realizes an integrated link for data acquisition and control instruction issuance, and also avoids instruction format conversion between multiple protocols, reducing compatibility risks. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic diagram of the specific hardware architecture on which the communication method between a baseboard management controller and a processor provided in the embodiments of this application depends; Figure 2 A schematic flowchart illustrating a communication method between a baseboard management controller and a processor, provided in an embodiment of this application; Figure 3 A schematic flowchart illustrating another communication method between a baseboard management controller and a processor provided in an embodiment of this application; Figure 4 An interactive schematic diagram illustrating a communication method between a baseboard management controller and a processor, provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To more clearly illustrate the embodiments of this application, the technical terms used in the embodiments will be briefly introduced below: A board management controller is a dedicated microcontroller that is independent of the main central processing unit and operating system. It is usually integrated on the motherboard (board) of a server or high-end computer. Its core function is to realize out-of-band management of hardware devices, that is, to remotely / locally monitor and control the hardware status without relying on the host operating system.

[0017] Static Random-Access Memory (SRAM) is a type of volatile memory that uses flip-flops to store data. Its key characteristic is that as long as power is continuously supplied, the stored data will not be lost, unlike dynamic memory which requires periodic refreshes to maintain the data.

[0018] Cyclic Redundancy Check (CRC) is an error detection algorithm based on polynomial division. Its core purpose is to detect whether bit errors occur in data during transmission / storage due to noise, interference, etc.

[0019] Dual In-Line Memory Module (DIMM) is a standardized hardware package for computer memory. Its core is to solder multiple memory chips onto a printed circuit board and design metal pins on both sides of the board for physical connection and signal transmission with the motherboard's memory slots.

[0020] General Purpose Input / Output (GPIO) is a universal digital signal pin interface provided by a chip. Its core feature is programmability. Through software configuration, a single GPIO pin can be flexibly switched to input or output mode to achieve simple control or status acquisition of external hardware without the need for dedicated interface circuits.

[0021] The Enhanced Serial Peripheral Interface (eSPI) is a high-speed serial communication protocol designed to replace traditional low-pin-count interfaces for low-speed data transmission between the southbridge chip on the computer motherboard and peripheral devices (such as the BMC).

[0022] Inter-Integrated Circuit (I2C) is a low-speed serial communication bus protocol whose core purpose is to simplify the hardware connection for short-distance data transmission between chips. It enables bidirectional communication between multiple devices and multiple slave devices using only two signal lines.

[0023] The Enhanced Inter-Integrated Circuit (I3C) is a physical communication link based on the I3C protocol. The core goal of the I3C protocol is to be compatible with I2C while improving speed, simplifying design, and enhancing functionality.

[0024] Peripheral Component Interconnect Express (PCIe Express) is a high-speed serial computer expansion bus standard. Its core features are serial differential signal transmission and point-to-point interconnection. Serial differential signal transmission transmits data using differential signal pairs, offering stronger anti-interference capabilities and supporting higher transmission rates. Point-to-point interconnection allows each PCIe device to connect to the CPU or chipset via an independent bus, with each device having its own dedicated channel bandwidth, eliminating bandwidth contention and improving the efficiency of concurrent device operation.

[0025] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] The specific application environment architecture or specific hardware architecture on which the execution of the communication method between the baseboard management controller and the processor depends is described here.

[0027] like Figure 1 As shown, Figure 1 This is a schematic diagram of the specific hardware architecture on which the communication method between a baseboard management controller and a processor provided in this application embodiment depends.

[0028] The baseboard management controller includes a main control chip, an intelligent data processing module, a PCIe interface controller, on-chip cache, and on-board cache. The intelligent data processing module has functions such as packing, unpacking, and priority scheduling, responsible for data processing and scheduling; it is also used to generate pre-encoded instructions, determine data request priorities, and schedule them accordingly; it supports lightweight symmetric encryption algorithms for encrypting sensitive request information. The PCIe interface controller can be a dual PCIe interface controller, corresponding to the primary and backup PCIe links respectively, supporting PCIe 4.0 and above to meet high-speed transmission requirements. The baseboard management controller also includes a link performance monitoring module for real-time acquisition of metrics such as transmission rate, latency, and frame error rate.

[0029] The processor includes a processor core, an intelligent data processing module, a PCIe interface controller, on-chip cache, and on-board cache. The intelligent data processing module is used to divide memory into high, medium, and low priority queues, supporting priority-based instruction reading; it also stores encryption keys and verifies device identity, preventing communication security risks caused by key leakage. The PCIe interface controller corresponds one-to-one with the BMC's dual PCIe controllers, supporting transaction layer packet parsing of the PCIe protocol. The processor also includes a PCIe parameter management module, used to receive link optimization commands, adjust power and signal compensation parameters, or switch links.

[0030] The baseboard management controller (BMC) and the processor are connected via a PCIe link, which can be a 4-channel (Lanex4) PCIe 4.0 link. Two PCIe links (primary and backup) must be physically connected independently, and both must support the transmission of transaction layer data packets according to the PCIe protocol specification, including header construction, CRC check, priority scheduling, and other functions. Simultaneously, the link must integrate a signal strength monitoring unit deployed at the PCIe physical layer on the BMC side. This unit can collect signal amplitude, signal-to-noise ratio, and eye diagram parameters and convert them into a comprehensive signal strength value. A rate negotiation interface must be deployed to support dynamic adjustment of the transmission frequency based on the bit error rate, ensuring that the link can maintain communication through parameter optimization during signal attenuation or minor anomalies, and triggering primary / backup switching only in the event of severe anomalies.

[0031] To ensure stable data transmission, a high-speed cache module is integrated into the PCIe link to temporarily store bursty data, preventing data loss and transmission congestion. The cache module is connected in series within the PCIe link to guarantee stable and smooth data transmission. The cache module is divided into a shared memory area for primary and backup links. This area is further subdivided into a common data area for storing instructions and request messages to be sent by the BMC, accessible to both primary and backup links; a response data area for storing response data returned by the CPU, accessible to the primary and backup link controllers of the BMC; a link status marker area for recording the real-time status of the primary and backup links, such as "normal," "abnormal," and "active," identified using hexadecimal encoding; a performance metric cache area for storing metrics such as transmission rate, latency, and error rate of the primary and backup links; and a tiered pending-transmission cache area, divided into high, medium, and low sub-cache areas according to request priority. A queue overflow cache area is configured on the CPU side to temporarily store requests that cannot be written immediately due to a full message queue, preventing data loss or scheduling chaos.

[0032] In some embodiments, the BMC includes an application layer, an interaction logic layer, and a hardware driver layer. The application layer interacts with the processor by calling the interface of the interaction logic layer; the hardware driver layer is used for data transmission with hardware devices; and the interaction logic layer is used to construct corresponding instructions and data according to different requests.

[0033] The CPU layer consists of an application layer, a processing logic layer, and a driver layer. After receiving data, the driver layer passes it to the processing logic layer; after processing, the processing logic layer returns the processing result to the BMC layer through the driver layer.

[0034] The embodiments of this application provide a storage space management method, and the method is described in detail in conjunction with the execution flow of the communication method between the baseboard management controller and the processor.

[0035] Figure 2 This is a flowchart illustrating a communication method between a baseboard management controller (BMC) and a processor, as provided in an embodiment of this application. The method is applied to the BMC. A high-speed peripheral component interconnect (PCIe) link is established between the BMC and the CPU. Figure 2 As shown, the method includes the following steps: S201, in response to a pre-coded instruction, sends a data request message to the processor via a high-speed peripheral component interconnect link.

[0036] The pre-encoded instructions use a specific encoding format, enabling them to be quickly recognized and executed on the AMD platform. Data request messages are used to request CPU temperature data, status data, and fault information. For example, when the BMC needs to obtain CPU temperature data, the pre-encoded instruction is "AMD_GET_CPU_TEMP".

[0037] In some embodiments, in response to a precoding instruction, a data request message is sent to the processor via the High-Speed ​​Peripheral Component Interconnect (PCIe) link. This includes: first, determining request information in response to the precoding instruction; then, packaging the request information according to the PCIe protocol to generate a data request message; and finally, sending the data request message to the CPU via the PCIe link.

[0038] Combination Figure 1 The BMC responds to the pre-encoded instructions through the intelligent data processing module, first determining the request information, then packaging the request information according to the PCIe protocol, and finally sending the packaged information to the CPU through the PCIe link.

[0039] Specifically, the BMC responds to pre-encoded instructions, identifying which business data the instruction requests and defining the scope of the requested data, such as which CPU core it targets and whether real-time sampling values ​​are needed. Because the pre-encoded instructions have a predefined format, the BMC does not need additional interpretation and can directly extract the core parameters required to construct the data request message, laying the foundation for subsequent packaging operations. For example, the request information includes the type identifier of the CPU temperature data, the target CPU identifier, and the length of the temperature data.

[0040] As a high-speed peripheral component interconnection protocol, PCIe has strict packet format specifications, including headers, data segments, and checksums. If these specifications are not met, data request messages will be rejected or lost by the CPU. Therefore, during the packet packaging process, the request information is first reassembled according to the protocol version corresponding to the PCIe link. The target device address and request type identifier are added to the packet header. The target device address specifies which interface to send to the CPU, and the request type identifier informs the CPU that this is a data read request. Then, the core request parameters are filled into the data segment, and finally, a checksum field is added to ensure data integrity.

[0041] The packaged data request message is passed to the BMC's PCIe physical layer interface. This interface converts the data request message into electrical or optical signals suitable for high-speed transmission and transmits it to the CPU via the PCIe bus. Because the PCIe link itself has the characteristics of "point-to-point high-speed transmission" and "low latency," and the data packets are pre-packaged according to the protocol specifications without additional conversion, the data request message can reach the CPU's PCIe controller at an extremely high rate. After receiving the data packet, the CPU controller first verifies its format and integrity. Only after confirming that it is correct does it parse the request content, preparing for the subsequent data return.

[0042] In the above embodiments, under the BMC and CPU communication architecture, the pre-encoded instructions are based on the format conventions of AMD platform and other platforms. The BMC can quickly extract core requirements and avoid instruction misjudgment; the request information is packaged according to the PCIe protocol to ensure that the generated data request message can be accurately parsed by the CPU side.

[0043] In some embodiments, after the request information is packaged according to the PCIe protocol, the subsequent request information in the package can be encrypted, and then a data request message can be generated based on the encrypted request information.

[0044] After the BMC completes the PCIe protocol packaging and generates an initial data packet containing a header, data segment, and checksum, it first determines whether the current request information belongs to the category of highly sensitive data, such as requests involving the underlying hardware operating status, such as obtaining CPU core voltage or cache access logs. If so, it triggers the encryption process, selecting a lightweight symmetric encryption algorithm, such as the Galois / Counter mode (GCM mode) of the Advanced Encryption Standard (AES-128 / 256). The hardware encryption module is then invoked to use the core request parameter segment (such as CPU core number, data sampling timestamp, sensitive instruction code, etc.) as plaintext, combining it with a preset key and generating ciphertext according to the selected algorithm. Simultaneously, a MAC value is generated and bound to the ciphertext to form the encrypted core data segment. After encryption, the encrypted core data segment is re-integrated with the header and checksum of the initial data packet, retaining the original header and replacing the original data segment with the encrypted core data segment. An encryption identifier field is added to the end of the data packet to inform the CPU that the data request message has been encrypted and the type of encryption algorithm used. Subsequently, the encrypted data request information is converted into a high-speed signal transmission through the PCIe physical layer interface. After receiving it, the CPU's PCIe controller first identifies the "encryption identifier field", calls the corresponding decryption module (using the same key as the encryption end) to decrypt the core data segment, and verifies the MAC value to ensure that the data has not been tampered with. Finally, it parses out the request information and performs subsequent operations.

[0045] In some embodiments, after generating a data request message, if there are multiple data request messages, they are merged to form a request transaction, which is then sent to the CPU via PCIe. This reduces the transaction overhead of link transmission and improves the overall data request efficiency.

[0046] During merging, the system first determines whether the target objects of multiple data request messages are consistent, whether they are of the same type, and whether their timeliness is consistent. This allows non-real-time data request messages with the same target and type to be included in the merging queue. After filtering out multiple data request messages that meet the merging criteria, they are merged into a single multi-request transaction data packet according to the PCIe transaction layer protocol specification. Specifically, a unified header containing a batch request identifier is generated, and a request quantity field and a unified target device address are added to the header. The request quantity field informs the CPU that the transaction contains N requests, and the unified target device address is a consistent target address after multiplexing and filtering. The request type identifier is also retained. Then, the core data segments of each data request message are sequentially concatenated according to the order of the merging queue during filtering, forming a continuous data block. A request separator is added before each data segment to facilitate accurate splitting by the CPU after reception. A global checksum field is generated for the entire transaction data packet to ensure data integrity while reducing the length of the checksum.

[0047] For the merged transaction data packet, its total length is first verified to ensure it meets the maximum transmission unit (MTU) limit of the current PCIe link. If the limit is exceeded, the transaction data packet is split into multiple segmented data packets that meet the MTU limit, and a segment identifier and segment sequence number are added to the header to ensure that the CPU can correctly reassemble them after receiving them. If the limit is not exceeded, the transaction data packet is transmitted to the PCIe physical layer, converted into a high-speed differential signal, and transmitted to the CPU via the PCIe link. After receiving the transaction data packet, the CPU's PCIe controller first parses the unified header, identifies the "batch request identifier" and "request quantity field," and clarifies that it is currently receiving a multi-request transaction. Then, it splits the merged data segments using the "request separator flag" to obtain each independent data request message. Finally, it executes the operation of each request in the order after splitting and returns the response results in batches, further reducing the number of interactions between the CPU and the control unit.

[0048] S202. Obtain the data response message returned by the processor through the high-speed peripheral component interconnection link.

[0049] On the processor side, after receiving a data request message from the BMC, the CPU first acquires the service data, then packages the service data according to the PCIe protocol to generate a data response message. The data response message is then returned to the BMC via the PCIe link. The data response message carries the CPU's service data.

[0050] In some embodiments, after obtaining the data acknowledgment message sent by the CPU via the PCIe link, the CPU's service data carried in the data acknowledgment message is first verified. If the verification fails, a data retransmission request message is sent to the CPU via the PCIe link, thereby obtaining the data acknowledgment message retransmitted by the CPU via the PCIe link.

[0051] After receiving the service data from the CPU, the BMC unpacks and analyzes it for verification, including but not limited to CRC check. If the verification fails, the BMC will resend a data request message to the CPU via the PCIe link to retransmit the service data until the verification succeeds.

[0052] For example, the following is a portion of the code that validates business data:

[0053] This code snippet demonstrates the implementation of the CRC32 check mechanism when the AMD platform CPU and BMC transmit data via the PCIe link. It primarily includes the definition of the CRC32 table and the checksum calculation function, providing integrity verification capabilities for the defined PCIeDataFrame. First, let's look at the definition of the "CRC32 table." The code declares a static constant array containing 256 unsigned integers using `static const unsigned int crc32_table

[256] `. This array is the core "lookup table" in the CRC32 algorithm. The CRC32 table stores the intermediate CRC32 calculation results corresponding to different bytes (0-255) in advance. In actual use, there's no need to derive the results through complex polynomial operations each time; the corresponding value can be quickly obtained by directly looking up the table, improving the efficiency of checksum calculation. For example, when processing data in a PCIeDataFrame, there's no need to perform polynomial operations bit by bit; simply look up the corresponding table entry based on the data byte. This is crucial for the low-latency data transmission required by the PCIe link. The code indicates that "specific values ​​are omitted here". In actual application, it is necessary to use professional tools to generate and fill the complete 256 entries. When generating, it is necessary to ensure that the polynomial rule is consistent with the receiving end (usually using the standard CRC32 polynomial 0xEDB88320), otherwise it will lead to deviation in the verification result.

[0054] Next is the "CRC32 checksum calculation function" `calculate_crc32`, which takes two parameters: `constunsigned char *data`, representing the starting address of the data to be checked, such as the starting address of the data identifier field and the data content field in a PCIeDataFrame; and `size_t length`, representing the total length of the data to be checked, which is 1 byte of data identifier plus 128 bytes of data content, totaling 129 bytes. Internally, the function first initializes `unsigned int crc = 0xFFFFFFFF`, which is the standard initial value for the CRC32 algorithm, used to ensure the accuracy of the check in the initial state. Then, it iterates through each byte of the data to be checked using a for loop: `(crc>>8)` in the loop means shifting the current CRC value 8 bits to the right, and `(crc&0xFF)^data[i]` performs an XOR operation between the lower 8 bits of the current CRC value and the currently iterated data byte. The result is used as an index in the CRC32 table. The corresponding value is retrieved from the table and then XORed with the right-shifted CRC value, finally updating the current CRC value. After all data bytes have been traversed, the function performs an XOR operation on the final intermediate result using `returncrc^0xFFFFFFFF` to obtain the final CRC32 checksum. This value is the content that needs to be filled into the `crc32` field of the `PCIeDataFrame`. For example, when the CPU sends service data to the BMC, it calls this function to calculate the checksum values ​​for the `data_identifier` and `data_content` fields of the `PCIeDataFrame`. After receiving the data, the BMC calls the same function again to recalculate the checksum values ​​for these two fields and compares them with the values ​​in the `crc32` field to determine whether the data is complete.

[0055] The above embodiments, by verifying and identifying anomalies in data response messages, ensure that every piece of CPU service data acquired by the BMC is authentic and valid. If verification fails, a retransmission request is sent, providing a fault-tolerant solution for transmission anomalies in the PCIe link and improving the success rate of data acquisition. It also reduces hardware management service interruptions caused by data anomalies, thus improving service continuity.

[0056] During the validation of business data, the data content is first obtained, then a validation value is calculated, and finally, the validation value is compared with a reference value for the data content. The source of the reference value depends on the generation scenario of the business data: if the business data is being generated for the first time (e.g., CPU temperature collected in real-time by a sensor), the reference value is usually a validation value calculated and appended synchronously when the business data is generated (e.g., by a sensor controller), and this reference value needs to be extracted from the appended fields received from the business data; if the business data is read from a storage device (e.g., historical hardware status data), the reference value is a validation value pre-calculated and associated with the business data during data storage, and this reference value needs to be obtained by querying the storage address.

[0057] If the checksum is the same as the reference value of the data content, the checksum is successful, and step S203 continues; if the checksum is different from the reference value of the data content, the checksum is unsuccessful, and a data retransmission request message is sent to the CPU through the PCIe link.

[0058] Specifically, redundant identifiers from the transmission process are removed from the data response message to extract the pure data content. A verification algorithm then converts this data content into fixed-length feature values ​​to determine if the business data has been tampered with or corrupted. During calculation, the BMC divides the business data content into blocks according to the algorithm's required block size, verifies each block, and obtains the final verification value through iterative calculation. The currently calculated verification value is compared byte-by-byte with the extracted reference value. If all bytes are completely identical, the verification is considered successful, and subsequent data processing can proceed. If any byte difference exists, the verification is considered a failure, triggering a data retransmission request process. Simultaneously, key information regarding verification failures can be recorded for subsequent troubleshooting.

[0059] After verification fails, a data retransmission request message is constructed according to the PCIe protocol. This message includes the original data identifier, the reason for verification failure, and the original request number. The original data identifier informs the CPU of the data object that needs to be retransmitted. The reason for verification failure may be a mismatch in the checksum or an abnormal data length. The original request number is used to associate the data with a historical request. The retransmission request message is then packaged into a Transaction Layer Packet (TLP) according to the PCIe transaction layer specification. The header must include a retransmission request type identifier, the target CPU address, and a high-priority flag to prioritize transmission over ordinary requests and prevent data loss due to queuing delays. The packaged retransmission request packet is converted into a high-speed signal by the PCIe physical layer and sent to the CPU via the PCIe link. Upon receiving the packet, the CPU's PCIe controller parses the "retransmission request content," locates the corresponding original data generation module (such as a sensor or storage chip), and re-triggers the data generation and transmission process until the received data stream is successfully verified.

[0060] During the process of sending a data retransmission request message to the CPU via the PCIe link, the bit error rate (BER) of the PCIe link is first obtained. If the BER of the PCIe link is less than a first preset threshold, a data retransmission request message is sent to the CPU via the PCIe link for a first preset number of retransmissions. The first preset threshold is a pre-set BER threshold for the PCIe link, for example, 0.1%. The first preset number of retransmissions corresponds to the first preset threshold, for example, 2 times.

[0061] If the bit error rate of the PCIe link is greater than or equal to a first preset threshold and less than or equal to a second preset threshold, the transmission frequency of the PCIe link is first reduced, and then a data retransmission request message is sent to the CPU according to the second preset retransmission number. The second preset threshold is a pre-set bit error rate threshold for the PCIe link, which is greater than the first preset threshold (e.g., 1%), and the second preset retransmission number corresponds to the second preset threshold (e.g., 5 times).

[0062] Specifically, the BMC reads statistical data on error events during PCIe link transmission through the PCIe link's management interface or hardware monitoring registers. This data includes the number of erroneous bits per unit time and the total number of transmitted bits. The real-time bit error rate (BER) of the current PCIe link is calculated using the formula: BER = (Number of erroneous bits / Total number of transmitted bits). To ensure data accuracy, a sliding time window is used in the BER calculation to avoid misjudgments caused by single instantaneous errors. The real-time BER is compared with a first preset threshold and a second preset threshold. If the real-time BER is less than the first preset threshold, the PCIe link is considered to be in a stable state. In this case, the error probability of the PCIe link is extremely low, and the risk of retransmission request loss is small. A low-redundancy retransmission strategy can be adopted, sending retransmission requests to the CPU according to the first preset number of retransmissions. If the first preset threshold is less than or equal to the real-time BER and less than or equal to the second preset threshold, the PCIe link is considered to be in a slightly abnormal state. In this case, the error probability of the PCIe link is relatively high. If transmission continues at the original frequency, retransmission requests may be repeatedly lost. Therefore, the link parameters need to be adjusted before sending retransmission requests to the CPU according to the second preset number of retransmissions. If the real-time bit error rate exceeds the second preset threshold, the link is determined to be in a severely abnormal state. At this time, a higher priority link repair process will be triggered, such as re-initializing the PCIe link to avoid unnecessary resource consumption.

[0063] The above embodiments use the bit error rate as the basis for judging the PCIe link status, divide different link scenarios by hierarchical thresholds, adjust the number of retransmissions and optimize the transmission frequency, thereby avoiding excessive retransmissions when the link is stable to save resources, and solving the problem of retransmission failure when the link is abnormal, thus improving reliability.

[0064] In some embodiments, after obtaining the data response message sent by the CPU via the PCIe link, the data frame structure of the service data carried in the data response message is identified to obtain the data identifier field, data content field, and verification field of the service data. Then, the data type of the service data is determined based on the data identifier field.

[0065] The data identifier field indicates the data type of the business data, including but not limited to: temperature data, status data, and fault information. For example, the data identifier field "0x01" indicates that the business data is temperature data.

[0066] The following is a portion of the code related to the data frame structure of business data:

[0067] This code primarily defines the data identification rules and data transmission format when the AMD platform CPU and BMC interact via the PCIe link, providing a foundation for efficient data identification, content delivery, and integrity verification between the two. First, the code defines three types of core data identifier constants using the "#define" statement. "DATA_TYPE_TEMPERATURE0x01" indicates that the hexadecimal value 0x01 is used as the exclusive identifier for "temperature data," "DATA_TYPE_STATUS0x02" sets 0x02 as the identifier for "status data," and "DATA_TYPE_ERROR0x03" uses 0x03 to correspond to "fault data." These fixed identifiers allow the receiver (such as the BMC or CPU) to quickly determine the data type by reading the identifiers after receiving data, enabling them to determine subsequent processing logic without parsing the complete content, thus improving data identification efficiency.

[0068] Next, the code defines a data frame structure named "PCIeDataFrame" using "typedefstruct". This structure is a standard "container" for data transmission between the CPU and BMC via the PCIe link. It contains three key fields: the first field "unsigned char data_identifier" is a 1-byte data identifier field, whose value corresponds to the three types of data identifier constants (0x01 / 0x02 / 0x03) defined earlier, used to specify the specific data type carried by the current data frame; the second field "unsigned char data_content

[128] " is a 128-byte data content field, used to store actual business data, such as the temperature data field storing the CPU core temperature value, the status data field storing the link connection status identifier, and the fault data field storing the fault code, etc. The length of 128 bytes can be flexibly adjusted according to actual transmission requirements (such as whether longer log information needs to be transmitted); the third field "unsigned int "crc32" is a 4-byte CRC32 check field used to store the CRC32 check value calculated for the "data identifier field and data content field". After receiving the data frame, the receiver will recalculate the CRC32 value for the first two fields and compare it with the check value of this field. If they match, it means that the data has not been tampered with or damaged during transmission, thus ensuring the integrity of data transmission.

[0069] S203. Analyze the business data and determine the operation instructions from the instruction set based on the analysis results of the business data.

[0070] The instruction set is defined based on the PCIe protocol, and the operation instructions are used to instruct the processor to perform corresponding operations. The instruction set includes, but is not limited to, data read instructions, status set instructions, and fault diagnosis instructions.

[0071] The code snippet below shows the part of the code that analyzes business data:

[0072] The unpack_data function defined in this code is the core tool for parsing the received PCIeDataFrame standard data frame when the CPU and BMC transmit data through the PCIe link on the AMD platform. Its function is to verify the integrity of the data frame and extract the core business data in it, providing a basis for subsequent business processing (such as BMC analyzing CPU status and CPU executing BMC instructions). Together with the pack_data function, it forms a complete data processing closed loop of packing and unpacking.

[0073] From the function parameters, it contains three input / output parameters and one return value: The first parameter, `PCIeDataFrame*frame`, is a pointer to the received `PCIeDataFrame` type data frame, representing the "complete data frame" to be parsed. This data frame is usually received from the PCIe link and stored in memory, containing the filled `data_identifier` (data identifier), `data_content` (data content), and `crc32` (checksum) fields; The second parameter, `unsigned char**target_data`, is a double pointer used to store the address of the core business data extracted after unpacking, essentially passing the memory address of the `data_content` field to the caller for easy access to the business data later; The third parameter, `size_t*data_length`, is a pointer type used to store the length of the unpacked core business data. Here, the fixed size of the `data_content` field (128 bytes) is used directly to let the caller specify the range of accessible data.

[0074] The function's execution logic can be divided into two steps: The first step is CRC32 integrity verification. First, the `calculate_crc32` function is called to recalculate the CRC32 checksum for the entire content of the `data_content` field in the data frame and store the result in the `calculated_crc` variable. Since `data_content` is a 128-byte array, the checksum length is `sizeof(frame->data_content)`. Then, the recalculated checksum is compared with the `crc32` field value inherent in the data frame using the `if(calculated_crc!=frame->crc32)` method. If the two are inconsistent, it indicates that the data may have been lost, tampered with, or interfered with during transmission through the PCIe link. In this case, -1 is returned, indicating that the verification failed and no data will be extracted subsequently to avoid using incorrect data and causing system abnormalities. The second step is to extract the core data. If the CRC check passes, the frame->data_content (the address of the field storing the business data in the data frame) is assigned to *target_data, allowing the caller to directly access the unpacked business data through this pointer. At the same time, sizeof(frame->data_content) (i.e., 128 bytes) is assigned to *data_length to explicitly inform the caller of the length of the business data and prevent access from exceeding the memory range.

[0075] The function also returns two values: if the CRC check passes and data extraction is complete, it returns 0, indicating successful unpacking, and the caller can use the business data normally through the target_data pointer and data_length; if the CRC check fails, it returns -1, indicating that the data is invalid and error handling is required (such as requesting resending the data). For example, when the BMC receives a data acknowledgment message sent by the CPU through the PCIe link, it calls the unpack_data function, passing in the received data frame pointer, a secondary pointer for storing the temperature data address, and a pointer for storing the data length; if the check passes, that is, the recalculated CRC value is consistent with the one in the data frame, the BMC can read the temperature value in data_content through the returned target_data pointer, and then combine it with the data_identifier field (0x01) to confirm that it is temperature data, finally completing the parsing of the temperature information and subsequent monitoring processing.

[0076] In some embodiments, if the data type of the business data is determined to be fault information based on the data identifier field, a fault diagnosis instruction corresponding to the fault information is determined from the instruction set. This fault diagnosis instruction is used to instruct the CPU to perform fault detection.

[0077] S204: Send operation instructions to the processor via the high-speed peripheral component interconnection link.

[0078] The BMC sends operation commands to the CPU via the PCIe link.

[0079] In some embodiments, the BMC sends operation instructions to the CPU's message queue via the PCIe link, allowing the processor to read and execute the instructions from the message queue when idle. The CPU's message queue is a pre-defined circular buffer in memory, such as 4KB in size, capable of storing 16 24-byte instruction units. The CPU pre-informs the BMC of the message queue's memory region address via the PCIe configuration space to ensure accurate BMC location.

[0080] Specifically, the BMC first constructs the header of the operation instruction according to the PCIe Transaction Layer Protocol (TLP) specification, specifying the message queue mapping address used by the CPU to receive the instruction. A checksum is appended to the end of the operation instruction for the CPU to verify data integrity upon reception. Then, the BMC sends the operation instruction to the CPU via the PCIe link.

[0081] The asynchronous scheduling logic in the above embodiments, which sends operation instructions to the CPU message queue, avoids interference from operation instructions on CPU core tasks and makes full use of CPU idle resources to perform management operations. The existence of the message queue provides a protection mechanism for operation instructions to prevent loss and ensure ordering. The message queue temporarily stores operation instructions, which can be executed in batches when the CPU is idle, thus meeting the management needs of the BMC without affecting the CPU's response speed to real-time tasks.

[0082] In some embodiments, when the BMC sends a data request message to the CPU via the PCIe link, it first determines the priority of the data request message, and then sends the data request message to the CPU's message queue via the PCIe link according to the priority, so that the CPU can read the data request message from the message queue according to the priority and respond when idle.

[0083] The priority of data request messages is related to the type of business data, and priority determination rules can be specified according to the economic value and scope of impact of the business data. For example, if the request involves hardware fault handling or real-time security monitoring, such as "urgent query for CPU temperature exceeding threshold" or "voltage anomaly detection request", it is determined to be high priority and marked with priority identifier 0x01; if the request is for routine hardware status collection, such as "CPU power consumption statistics every 5 minutes" or "normal firmware version query", it is determined to be medium priority and marked with 0x02; if the request is for non-critical data interaction, such as "historical log backup request" or "non-real-time configuration parameter reading", it is determined to be low priority and marked with 0x03.

[0084] Data request messages from the BMC are transmitted to the CPU's PCIe controller via the PCIe bus in a high-priority, medium-priority, and low-priority manner. High-priority TLP packets skip the queue of low-priority packets in the link, reducing transmission latency. The CPU pre-divides "hierarchical message queues" in memory, corresponding to the high, medium, and low priorities of the BMC. For example, queue a is a high-priority queue, queue b is a medium-priority queue, and queue c is a low-priority queue. Each queue is an independent circular buffer. After receiving a data request message, the CPU extracts the priority field from the header to determine the target queue. If it is a high-priority message (0x01), the message is written to queue a; medium-priority messages (0x02) are written to queue b; and low-priority messages (0x03) are written to queue c. During writing, the idle status of the target queue is checked. If there is an idle unit, the request is written directly and the queue pointer and count are updated. If the target queue is full, high-priority requests will temporarily occupy the idle units of the low-priority queue and be marked as "high-priority temporary storage" to avoid losing high-priority requests. At the same time, a high-priority queue full response is returned to the BMC. When the medium and low-priority queues are full, the request is temporarily stored in the corresponding priority overflow buffer and a queue busy response is returned to the BMC. The request will be written after the queue has an idle unit.

[0085] When the CPU detects that it is in an idle state, it first queries the hierarchical queue management module to see if there are any unexecuted requests in the high-priority queue (queue a). If the high-priority queue is empty, it then queries the medium-priority queue (queue b) and the low-priority queue (queue c) in sequence. If there are unexecuted requests, it extracts the request message from the queue header, parses the request type and parameters in the message, converts them into micro-operations that the CPU can execute, and adds them to the idle task execution queue for priority execution. After the response is generated, the CPU returns a priority response message to the BMC via the PCIe link according to the priority of the original request. The response message header also carries a priority identifier to facilitate the BMC to match the original request. At the same time, it updates the head pointer of the corresponding message queue and releases the queue unit.

[0086] The above embodiments implement request priority determination and PCIe link priority transmission on the BMC side, and on the CPU side, through hierarchical message queues and tiered read responses, which not only ensures low latency and high reliability of high-priority data requests, but also avoids resource preemption issues of low-priority requests.

[0087] In some embodiments, the PCIe link includes a primary PCIe link and a backup PCIe link, which share memory. The primary PCIe link is used by default for communication between the BMC and the CPU. During communication between the BMC and the CPU, performance metrics of the primary PCIe link are collected, and the system is then used to determine if the primary PCIe link is malfunctioning. If so, the system switches to the backup PCIe link.

[0088] This application deploys a primary PCIe link and a backup PCIe link simultaneously at the hardware level. The two links independently connect the BMC's dual PCIe controller to the CPU's dual PCIe interface, ensuring that the backup link can transmit independently in the event of a primary link failure. Both links share a common memory area. The core function of this shared memory is to achieve data synchronization between the primary and backup links: the BMC writes the communication data to be sent into the common data area of ​​the shared memory. The primary link reads data directly from this area during transmission, while the backup link monitors updates to the shared memory in real time through a memory address mapping mechanism, ensuring seamless data transmission takeover in the event of a primary link failure. Simultaneously, the response data returned by the CPU is also first written into the response data area of ​​the shared memory, which can be read by both the primary and backup link controllers of the BMC, preventing data loss. Furthermore, a link status marking area is partitioned within the shared memory to record the current status of the primary and backup links. For example, a normal primary link is marked as 0x01, and an abnormal primary link as 0x00; the backup link is marked similarly, providing a basis for subsequent switchover decisions.

[0089] The BMC communicates with the CPU via the main PCIe link. The BMC needs to collect key performance indicators of the main link in real time to assess the link health. The collected performance indicators include link transmission rate, transmission latency, frame error rate, and number of interruptions. A weighted algorithm is used to calculate a comprehensive score for the main link performance indicators, such as transmission rate accounting for 30%, transmission latency for 25%, frame error rate for 35%, and number of interruptions for 10%. Pre-set thresholds for main link performance anomalies include individual indicator thresholds and a comprehensive score threshold. For example, if the transmission rate is below 90% of the theoretical value, the transmission latency exceeds 50μs, the frame error rate exceeds 1e-6, the number of interruptions exceeds 2 per minute, and the comprehensive score is below 60, the main link is considered abnormal. If any individual indicator exceeds the preset threshold, the main link is considered abnormal. If all individual indicators are within limits, but the comprehensive score is below 60, the main link is also considered abnormal. The main link status in the shared memory link status marker area is then updated to abnormal. Simultaneously, the status indicators of the backup link are read. If the backup link is currently "normal" (0x01), the real-time performance of the backup link in the shared memory "performance indicator cache" is read (although the backup link is not transmitting, it will periodically check its performance) to ensure that the backup link's transmission rate, latency and other indicators meet the communication requirements. If the backup link status is "abnormal", a "dual link failure alarm" is immediately sent to the system administrator, and the primary link is restarted. If the restart is successful, the primary link communication is restored.

[0090] If the backup link's transmission rate, latency, and other indicators meet the communication requirements, first shut down the primary link's data transmission, then configure the backup link's parameters to be consistent with the primary link, and simultaneously update the shared memory's "link status flag area," setting the backup link status to "normal (active)" (0x02) and the primary link status to "fault (disabled)" (0x00). Read any incomplete communication data (such as commands not sent when the primary link failed) from the shared memory's "common data area" and continue sending it to the CPU in the primary link's transmission order. After receiving the data transmitted from the backup link, the CPU returns a response through the shared memory's "response data area," and the BMC's backup link controller reads the response and updates the data status.

[0091] The above embodiments utilize primary and backup link hardware redundancy, collect link performance indicators to identify whether the primary link is abnormal, and in the event of an abnormality, the backup link takes over, ensuring the availability and continuity of communication between the BMC and the CPU. Data loss is avoided through shared memory, thus improving the overall reliability of the system.

[0092] In some embodiments, during communication between the BMC and the CPU, the signal strength of the PCIe link is detected. If the signal strength is less than a preset strength, a link optimization command is sent to the CPU via the PCIe link. The link optimization command is used to instruct the CPU to adjust the power or signal compensation parameters of the PCIe link.

[0093] The preset signal strength is determined by combining the PCIe link version and hardware design parameters; if the signal strength is lower than the preset strength, the probability of signal distortion will increase.

[0094] Optionally, the BMC collects the signal amplitude, signal-to-noise ratio (SNR), and eye diagram parameters of the PCIe link, and calculates the signal strength of the PCIe link using a weighted algorithm. The signal amplitude is the difference between the peak and trough values ​​of the signal voltage, reflecting the strength of the signal; the SNR is the ratio of the effective signal component to noise, affecting the accuracy of signal analysis; and eye diagram parameters, such as eye height and eye width, reflect the timing stability of the signal. A smaller eye opening indicates a higher risk of signal distortion. For example, the signal strength is calculated by weighting the signal amplitude (40%), SNR (40%), and eye diagram parameters (20%).

[0095] If the signal strength is greater than or equal to the preset strength, the link signal is considered stable and no optimization is needed; normal monitoring continues. If the combined value is less than the preset strength, the link signal is considered to be attenuating. The transmission of non-urgent data request messages is paused, the signal attenuation index is recorded, and the adjustment direction is determined based on the attenuation index. If the signal amplitude is insufficient (e.g., below 0.6V), the command must include power boosting parameters, such as requesting the CPU to increase the PCIe link transmitter power from the default 12dBm to 15dBm. If the signal-to-noise ratio is too low (e.g., below 12dB), the command must include signal compensation parameters, such as requesting the CPU to enable pre-emphasis compensation or adjust the equalizer coefficients to enhance signal anti-interference capabilities. If the eye diagram parameters are abnormal, a coordinated adjustment scheme for both power and compensation parameters must be included. The link optimization command is sent to the CPU via the PCIe link.

[0096] Upon receiving a link optimization command, the CPU performs parameter adjustments as required. If the adjustment is for power, a control signal is sent to the power control unit of the CPU's PCIe physical layer to adjust the transmitter power from the current value to the target value, while simultaneously monitoring energy consumption changes after the power adjustment to avoid excessive power consumption. If the adjustment is for signal compensation parameters, the gain coefficient of the CTLE equalizer is adjusted to enhance high-frequency signal components, or the amplitude is increased at the signal rising edge to compensate for high-frequency attenuation during transmission. After parameter adjustment, the CPU returns an optimization confirmation command to the BMC via the PCIe link, including the adjusted parameter values ​​and feedback on the current link signal strength. Upon receiving the confirmation command, the BMC re-monitors the link signal strength. If the combined value rises above the preset strength, the optimization is considered successful, and normal data transmission resumes. If it remains below the threshold, a second optimization is triggered to further increase power or adjust other compensation parameters. If multiple optimizations are ineffective, a link fault alarm is sent to the system administrator, indicating potential hardware physical damage.

[0097] In the above embodiments, the BMC captures signal changes in real time. When the signal strength is lower than a preset threshold, it triggers an optimization instruction to adjust the power enhancement signal strength of the PCIe link or optimize the signal compensation parameters to reduce transmission attenuation, thereby fundamentally improving signal quality, reducing the probability of communication interruption caused by signal problems, and ensuring stable transmission of instructions and data between the BMC and the CPU.

[0098] In the communication method between the baseboard management controller (BMC) and the processor provided in this application, a pre-encoding instruction indicates that the BMC needs to obtain service data from the CPU. The BMC responds to the pre-encoding instruction to determine the request information, packages the request information according to the PCIe protocol, and then sends the packaged data request to the processor via the PCIe link. The PCIe protocol assigns different data identifiers to different types of data to enable rapid identification and processing of the data. The data request is sent to the processor's message queue.

[0099] When the processor is idle after receiving a data request, it reads the data request from the message queue, unpacks and parses it to determine the data type of the request. The asynchronous transmission mechanism based on the message queue avoids the problem of long response wait times, improving the efficiency of the interaction. Then, it retrieves the requested service data from memory registers or sensors, packages the service data according to the PCIe protocol, and returns the packaged service data to the BMC via the PCIe link. To ensure the reliability of data transmission, the PCIe protocol incorporates cyclic redundancy check (CRC) and retransmission mechanisms to verify and protect important data.

[0100] When the CPU returns service data to the BMC via PCIe, the CPU (sender) calculates a CRC32 checksum for the service data and appends it to the data. After receiving the data, the BMC (receiver) recalculates the CRC32 value of the service data and compares it with the checksum appended by the CPU to confirm whether the data is complete.

[0101] After receiving the service data, the BMC unpacks and analyzes the service data to determine the operation instructions from the instruction set, and then sends the operation instructions to the processor through the PCIe link so that the CPU can respond to the operation instructions and execute the corresponding operation.

[0102] In summary, the embodiments of this application provide a communication method between a baseboard management controller and a processor. Compared with related technologies, this application can achieve the following beneficial effects: In the multi-link architecture of related technologies, I3C, eSPI, and I2C each need to occupy independent GPIO pins (each link requires dedicated signal pins to achieve communication), resulting in the dispersed consumption of GPIO resources. This solution uses only a single PCIe link to realize the full-scenario interaction between the CPU and BMC, including business data acquisition, fault diagnosis, and operation command issuance. The PCIe link does not need to rely on multiple sets of GPIO pins. It only needs to complete all data transmission through its standardized differential signal channels (such as the x1 channel which only requires 4 pins: 2 for transmitting and 2 for receiving), reducing the GPIO pin occupation. The freed pin resources can be used for motherboard function expansion (such as adding sensors, expanding interfaces, etc.).

[0103] The multi-link architecture of related technologies needs to be compatible with three protocols: I3C, eSPI, and I2C. At the hardware level, independent signal conditioning circuits need to be designed for each protocol. At the software level, multiple protocol drivers need to be developed and timing coordination between protocols needs to be handled, resulting in high design and adaptation complexity. This solution uniformly adopts the PCIe protocol as the only interaction protocol: at the hardware level, only one PCIe interface circuit needs to be deployed, without the need for multi-protocol circuits. At the software level, only one PCIe protocol driver needs to be developed, without the need to adapt to multi-protocol logic. At the same time, the PCIe protocol assigns exclusive data identifiers to different types of data (business data, operation instructions), enabling rapid data identification and classification, reducing the complexity of hardware and software design and adaptation costs.

[0104] In the multi-link architecture of related technologies, the signal characteristics (such as level and rate) of I3C, eSPI, and I2C differ, which can easily lead to signal interference during parallel transmission. Furthermore, the compatibility of different protocols requires additional debugging, resulting in poor data transmission stability. This solution transmits all data through only one PCIe link, eliminating the problem of parallel interference from multiple links. Moreover, PCIe uses a differential signal design, which inherently has a much stronger anti-interference capability than single-ended signal links such as I2C / I3C. Relying on the "Cyclic Redundancy Check (CRC) mechanism" (to verify data integrity) and "retransmission mechanism" (to retransmit lost / erroneous data) built into the PCIe protocol, important data such as business data and operation instructions are doubly protected. No additional reliability logic needs to be designed, which improves the stability and reliability of data transmission and avoids the problem of debugging for multi-protocol compatibility.

[0105] Figure 3 This is a flowchart illustrating another communication method between a baseboard management controller and a processor, provided as an embodiment of this application. The method is applied to the processor. Figure 3 As shown, the method includes the following steps: S301, Receive data request messages sent by the baseboard management controller through the high-speed peripheral component interconnection link.

[0106] The CPU receives data request messages sent by the BMC via the PCIe link. These data request messages are used to request the service data needed by the BMC.

[0107] S302. Respond to the data request message and obtain business data.

[0108] Unpack the data request message to determine the data type of the business data; retrieve the corresponding business data based on the data type. Business data includes, but is not limited to: temperature data, status data, and fault information.

[0109] S303. Package the business data according to the high-speed peripheral component interconnection protocol and generate a data response message.

[0110] For example, the following is a partial code snippet showing how to package service data and generate a data response message according to the PCIe protocol:

[0111] The pack_data function defined in this code is the core tool for encapsulating raw business data into standard PCIeDataFrame data frames when the AMD platform CPU and BMC transmit data through the PCIe link. Its function is to ensure that the data to be transmitted can be packaged according to the preset format specifications, so as to prepare for subsequent transmission and integrity verification through the PCIe link.

[0112] From the function parameters, it contains four input parameters and one return value: The first parameter, `PCIeDataFrame*frame`, is a pointer to a `PCIeDataFrame` type data frame, representing an "empty data frame container" to be filled with data. All subsequent packaged data will be stored in this container. The second parameter, `unsigned char data_type`, is a data type identifier. Its value must correspond to previously defined constants such as `DATA_TYPE_TEMPERATURE` (0x01) and `DATA_TYPE_STATUS` (0x02) to specify the specific type of the currently packaged data. The third parameter, `const unsigned char *source_data`, is a pointer to the original business data, such as temperature values ​​collected by the CPU and hardware status information. These are the core contents that need to be packaged and transmitted. The fourth parameter, `size_tdata_length`, is the length of the original business data, used to determine the amount of data to be copied into the data frame.

[0113] The function's execution logic can be divided into three steps: The first step is data length verification. It checks if the length of the original business data exceeds the maximum capacity of the `data_content` field in the PCIeDataFrame using the `if(data_length>sizeof(frame->data_content))` method. This field is defined as a 128-byte array, hence its maximum capacity is 128 bytes. If it exceeds this capacity, it returns -1, indicating that the data is too long to be fully packed, thus preventing memory overflow. The second step is filling the data frame field. First, `data_type` is assigned to `frame->data_identifier` to clarify the type identifier of the current data frame. Then, the `memcpy` function copies the original business data pointed to by `source_data` to `frame->data_content` according to the length of `data_length`, completing the core data filling. The third step is calculating and filling the CRC32 checksum. It calls the defined `calculate_crc32` function to calculate the checksum for the original business data `source_data` according to the length of `data_length`, and then assigns the result to the `frame->crc32` field, providing a basis for data transmission integrity verification.

[0114] The function returns two values: If all steps in the data packaging process are completed normally (data length is compliant, fields are filled completely, and checksum calculation is successful), it returns 0, indicating that the data frame is successfully packaged and can be used for subsequent PCIe link transmission; if the data length exceeds the capacity of the data_content field, it returns -1 as an error indicator, prompting the caller to handle the data overlength issue, such as splitting the data or adjusting the length of the data_content field. For example, when the CPU needs to send temperature data to the BMC, it calls the pack_data function, passing in an empty data frame pointer, DATA_TYPE_TEMPERATURE (0x01), a temperature data pointer, and the temperature data length. If the temperature data length is 4 bytes (not exceeding 128 bytes), the function will generate a complete data frame containing a temperature type identifier, 4 bytes of temperature data, and the corresponding CRC32 checksum, returning 0 to indicate that packaging is complete. Subsequently, the data frame can be sent to the BMC via the PCIe link.

[0115] S304. Send a data response message to the board management controller via the high-speed peripheral component interconnection link.

[0116] The CPU sends a data response message to the BMC via the PCIe link.

[0117] S305 Receives operation commands sent by the baseboard management controller through the high-speed peripheral component interconnect link.

[0118] S306. Execute the corresponding operation in response to the operation command.

[0119] The operation instructions include, but are not limited to: data read instructions, status setting instructions, and fault diagnosis instructions.

[0120] After receiving the operation instruction, the CPU first verifies whether the CRC checksum matches to determine if there is a data transmission error. It then checks whether the "destination address" in the data packet header is a valid mapped address of the message queue to avoid writing to illegal memory areas. If the verification fails, the data packet is discarded and a transmission failure response is returned to the BMC, triggering a retransmission. If the verification succeeds, the CPU enters the message queue writing process. The CPU first checks if there are any free units in the message queue: if there are, the instruction unit is extracted from the operation instruction and written to the memory address pointed to by the tail pointer, while updating the tail pointer and the free unit count; if the queue is full, the instruction data packet is temporarily stored in the "queue overflow buffer" and a "queue busy response" is returned to the BMC. Once there are free units in the queue (the CPU reads the instruction and releases it), the instruction is read from the overflow buffer and written to the queue, ensuring that no instructions are lost.

[0121] The CPU monitors its own load status in real time. When an idle state is detected, it first checks if there are any unexecuted operation instructions in the message queue. If so, it retrieves the instruction unit pointed to by the head pointer; otherwise, the reading process terminates and returns to a no-instruction state. The CPU then parses the type identifier and parameters of the unexecuted operation instructions, converts them into CPU-executable operations, and executes them sequentially. After the operation instruction is executed, the CPU updates the head pointer of the message queue, releases the queue unit occupied by the operation instruction, and returns the instruction execution result response to the BMC.

[0122] Assume the CPU receives a fault diagnosis command from the BMC via the PCIe link and performs internal fault detection in response. Then, according to the PCIe protocol, it sends the detection results back to the BMC via the PCIe link.

[0123] On the BMC side, after receiving the detection results, the BMC performs a diagnosis based on the fault analysis algorithm and takes corresponding measures according to the diagnosis results, such as sending alarm information and adjusting server operating parameters.

[0124] Figure 4 This is an interactive schematic diagram illustrating a communication method between a baseboard management controller (BMC) and a processor, provided in an embodiment of this application. A PCIe link is established between the BMC and the CPU. Figure 4 As shown, the method includes: S401 and BMC respond to the pre-encoding instruction to determine the request information.

[0125] S402 and BMC package the request information according to the PCIe protocol to generate a data request message.

[0126] S403 and BMC send data request messages to the CPU via the PCIe link.

[0127] For example, when the BMC receives an externally triggered pre-coded instruction (such as a monitoring request from a remote management terminal), it parses the service type of the request and generates request information containing fields such as opcode, data identifier, and length. Subsequently, the BMC packages the request information according to the TLP (Transaction Layer Packet) format, adds a PCIe header (including routing information, packet type, length, etc.), generates a data request message, and sends it to the CPU through the PCIe link.

[0128] S404: The CPU responds to the data request message and obtains the business data.

[0129] S405: The CPU unpacks the data request message to determine the data type of the business data.

[0130] S406, the CPU obtains the corresponding business data according to the data type.

[0131] S407: The CPU packages the service data according to the PCIe protocol and generates a data response message.

[0132] S408, the CPU returns a data response message to the BMC via the PCIe link.

[0133] For example, after receiving a data request message, the CPU notifies the CPU kernel to process it via interrupt or polling. The CPU first unpacks the TLP packet, extracts the service type field from the request information, and then calls the corresponding data acquisition module to obtain the service data, such as obtaining temperature values ​​through a sensor driver or reading memory statistics through the kernel interface. Afterward, the CPU encapsulates the service data into a completion packet (CompletionTLP) according to the PCIe protocol, adds a status code (such as success / failure) and a data payload, and returns it to the BMC via the PCIe link.

[0134] S409 and BMC analyze business data and determine operation instructions from the instruction set based on the analysis results.

[0135] The S410 and BMC send operation commands to the CPU via the PCIe link.

[0136] S411, The CPU responds to the operation instruction and executes the corresponding operation.

[0137] S412, the CPU returns the execution result to the BMC via the PCIe link.

[0138] For example, after receiving a data response message, the BMC processes the business data, such as determining whether the temperature exceeds a threshold or whether memory usage is too high; and matches the corresponding operation instruction from the instruction set according to preset rules. Subsequently, the BMC packages the operation instruction into a PCIe message and sends it to the CPU via the PCIe link. Upon receiving the operation instruction, the CPU parses the specific operation type, calls the corresponding execution module to complete the specified operation, such as a driver to adjust fan speed or a system call to trigger an alarm, and can return the execution result to the BMC via the PCIe link.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0140] Embodiments of this application provide a communication device between a baseboard management controller and a processor. The device includes a baseboard management controller and a processor, and a high-speed peripheral component interconnect link is established between the baseboard management controller and the processor.

[0141] The baseboard management controller is used to send data request messages to the processor via a high-speed peripheral component interconnect link in response to pre-coded instructions; The processor is used to receive data request messages sent by the baseboard management controller through the high-speed peripheral component interconnect link; in response to the data request message, acquire service data; package the service data according to the high-speed peripheral component interconnect protocol to generate a service data response message; and send the service data response message to the baseboard management controller through the high-speed peripheral component interconnect link. The baseboard management controller is used to acquire data response messages returned by the processor through the high-speed peripheral component interconnection link. The data response messages carry the processor's service data; analyze the service data, and determine operation instructions from the instruction set based on the analysis results; wherein, the instruction set is defined based on the high-speed peripheral component interconnection protocol, and the operation instructions are used to instruct the processor to perform corresponding operations; and send the operation instructions to the processor through the high-speed peripheral component interconnection link.

[0142] As an optional implementation provided in this application, the baseboard management controller is used to determine request information in response to pre-encoded instructions; package the request information according to the high-speed peripheral component interconnection protocol to generate a data request message; and send the data request message to the processor through the high-speed peripheral component interconnection link.

[0143] As an optional implementation provided in this application, the baseboard management controller is further configured to: verify service data; if the verification fails, send a data retransmission request message to the processor via the high-speed peripheral component interconnection link; and obtain a data response message retransmitted by the processor via the high-speed peripheral component interconnection link.

[0144] As an optional implementation provided in this application, when the baseboard management controller verifies the service data, it is specifically used to: obtain the data content of the service data; calculate the verification value of the data content; and compare whether the verification value is the same as the reference value of the data content.

[0145] As an optional implementation provided in this application, if the baseboard management controller fails the verification, it sends a data retransmission request message to the processor through the high-speed peripheral component interconnection link. Specifically, it is used to: if the verification fails, obtain the bit error rate of the high-speed peripheral component interconnection link; if the bit error rate is less than a first preset threshold, send a data retransmission request message to the processor through the high-speed peripheral component interconnection link according to the first preset number of retransmissions.

[0146] As an optional implementation provided in this application, if the baseboard management controller fails to verify, after obtaining the bit error rate of the high-speed peripheral component interconnection link, it is further configured to: reduce the transmission frequency of the high-speed peripheral component interconnection link when the bit error rate is greater than or equal to a first preset threshold and less than or equal to a second preset threshold; and after the transmission frequency is reduced, send a data retransmission request message to the processor according to a second preset number of retransmissions.

[0147] As an optional implementation provided in this application, the baseboard management controller is further configured to: identify the data frame structure of the service data to obtain the data identifier field, data content field, and verification field of the service data; and determine the data type of the service data based on the data identifier field.

[0148] As an optional implementation provided in this application, when the baseboard management controller analyzes service data and determines operation instructions from the instruction set based on the analysis results of the service data, it is specifically used to: determine the fault diagnosis instruction corresponding to the fault information from the instruction set when the data type is fault information; wherein, the fault diagnosis instruction is used to instruct the processor to perform fault detection.

[0149] As an optional implementation provided in this application, when the baseboard management controller sends an operation instruction to the processor through the high-speed peripheral component interconnect link, it is specifically used to: send the operation instruction to the processor's message queue through the high-speed peripheral component interconnect link, so that the processor can read the operation instruction from the message queue and execute it when idle.

[0150] As an optional implementation provided in this application, when the baseboard management controller sends a data request message to the processor through the high-speed peripheral component interconnect link, it is specifically used to: determine the priority of the data request message; send the data request message to the processor's message queue through the high-speed peripheral component interconnect link according to the priority, so that the processor can read the data request message from the message queue according to the priority and respond when idle.

[0151] As an optional implementation provided in this application, the high-speed peripheral component interconnect link includes a primary high-speed peripheral component interconnect link and a backup high-speed peripheral component interconnect link, which share memory; the baseboard management controller is also used to: collect performance indicators of the primary high-speed peripheral component interconnect link; determine whether the primary high-speed peripheral component interconnect link is abnormal based on the performance indicators; and switch to the backup high-speed peripheral component interconnect link when the primary high-speed peripheral component interconnect link is abnormal.

[0152] As an optional implementation provided in this application, the substrate management controller is further configured to: detect the signal strength of the high-speed peripheral component interconnect link; and when the signal strength is less than a preset strength, send a link optimization instruction to the processor through the high-speed peripheral component interconnect link, wherein the link optimization instruction is used to instruct the processor to adjust the power or signal compensation parameters of the high-speed peripheral component interconnect link.

[0153] As an optional implementation provided in this application, when the baseboard management controller sends a data request message to the processor via the high-speed peripheral component interconnect link in response to a pre-encoding instruction, it is specifically configured to: determine request information in response to the pre-encoding instruction; package the request information according to the high-speed peripheral component interconnect protocol to generate a data request message; when there are multiple data request messages, merge the multiple data request messages to generate a request transaction; and send the request transaction to the processor via the high-speed peripheral component interconnect link.

[0154] As an optional implementation provided in this application, when the baseboard management controller sends a data request message to the processor via the high-speed peripheral component interconnect link in response to a pre-encoding instruction, it is specifically configured to: determine request information in response to the pre-encoding instruction; package the request information according to the high-speed peripheral component interconnect protocol; encrypt the packaged request information; generate a data request message based on the encrypted request information; and send the data request message to the processor via the high-speed peripheral component interconnect link.

[0155] For a description of the features in the embodiment corresponding to the communication device between the baseboard management controller and the processor, please refer to the relevant description in the embodiment corresponding to the communication method between the baseboard management controller and the processor, which will not be repeated here.

[0156] like Figure 5 As shown, embodiments of this application also provide an electronic device, including a memory 501 and a processor 502. The memory 501 stores a computer program, and the processor 502 is configured to run the computer program to perform the steps in any of the above embodiments of the communication method between a baseboard management controller and a processor.

[0157] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the communication method between a baseboard management controller and a processor when it is run.

[0158] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0159] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the communication method between a baseboard management controller and a processor.

[0160] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the communication method between the baseboard management controller and the processor.

[0161] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0162] The communication method between a baseboard management controller and a processor provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for communication between a baseboard management controller and a processor, the method comprising: The application is applied to a substrate management controller, a high-speed peripheral component interconnect link is established between the substrate management controller and the processor, and the method comprises the following steps: In response to a pre-encoding instruction, a data request message is sent to the processor through the high-speed peripheral component interconnect link; A data response message returned by the processor through the high-speed peripheral component interconnect link is acquired, and the data response message carries service data of the processor; The service data is analyzed, and an operation instruction is determined from an instruction set according to an analysis result of the service data; wherein the instruction set is defined based on a high-speed peripheral component interconnect protocol, and the operation instruction is used to instruct the processor to perform a corresponding operation; The operation instruction is sent to the processor through the high-speed peripheral component interconnect link.

2. The method of claim 1, wherein, The method further comprises the following steps after the data response message returned by the processor through the high-speed peripheral component interconnect link is acquired and before the service data is analyzed and the operation instruction is determined from the instruction set according to the analysis result of the service data: The service data is checked; If the check fails, a data retransmission request message is sent to the processor through the high-speed peripheral component interconnect link; The data response message retransmitted by the processor through the high-speed peripheral component interconnect link is acquired.

3. The method of claim 1, wherein, If the check fails, the method further comprises the following steps: If the check fails, the bit error rate of the high-speed peripheral component interconnect link is acquired; If the bit error rate is less than a first preset threshold, a data retransmission request message is sent to the processor through the high-speed peripheral component interconnect link according to a first preset retransmission number. The method further comprises the following steps after the bit error rate of the high-speed peripheral component interconnect link is acquired if the check fails:

4. The method of claim 3, wherein, If the bit error rate is greater than or equal to the first preset threshold and less than or equal to a second preset threshold, the transmission frequency of the high-speed peripheral component interconnect link is reduced; the first preset threshold is less than the second preset threshold; After the transmission frequency is reduced, a data retransmission request message is sent to the processor according to a second preset retransmission number. The method further comprises the following steps after the data response message returned by the processor through the high-speed peripheral component interconnect link is acquired and before the service data is analyzed and the operation instruction is determined from the instruction set according to the analysis result of the service data:

5. The method of claim 4, wherein, The data frame structure of the service data is identified to obtain a data identification field, a data content field and a check field of the service data; The data type of the service data is determined according to the data identification field. ​ 6. The method of claim 1, wherein, ​ ​ ​ 7. The method of claim 6, wherein, The business data is analyzed, and operation instructions are determined from an instruction set according to an analysis result of the business data. In a case where the data type is fault information, a fault diagnosis instruction corresponding to the fault information is determined from the instruction set. The fault diagnosis instruction is used to instruct the processor to perform fault detection.

8. The method of claim 2, wherein, The data request message is sent to the processor through the high-speed peripheral component interconnect link, including: A priority of the data request message is determined; The data request message is sent to a message queue of the processor through the high-speed peripheral component interconnect link according to the priority, so that the processor reads the data request message from the message queue according to the priority and responds when idle.

9. The method of claim 1, wherein, The high-speed peripheral component interconnect link includes a main high-speed peripheral component interconnect link and a backup high-speed peripheral component interconnect link, and the main high-speed peripheral component interconnect link and the backup high-speed peripheral component interconnect link share a memory; The method further includes: Performance indicators of the main high-speed peripheral component interconnect link are collected; Whether the main high-speed peripheral component interconnect link is abnormal is determined according to the performance indicators; In a case where the main high-speed peripheral component interconnect link is abnormal, the backup high-speed peripheral component interconnect link is switched to.

10. The method of claim 1, wherein, The data request message is sent to the processor through the high-speed peripheral component interconnect link in response to the pre-encoding instruction, including: Request information is determined in response to the pre-encoding instruction; The request information is packaged according to a high-speed peripheral component interconnect protocol to generate the data request message; In a case where the number of data request messages is multiple, multiple data request messages are merged to generate a request transaction; The request transaction is sent to the processor through the high-speed peripheral component interconnect link.

11. The method of claim 1, wherein, The data request message is sent to the processor through the high-speed peripheral component interconnect link in response to the pre-encoding instruction, including: Request information is determined in response to the pre-encoding instruction; The request information is packaged according to a high-speed peripheral component interconnect protocol; The packaged request information is encrypted; The data request message is generated according to the encrypted request information; The data request message is sent to the processor through the high-speed peripheral component interconnect link.

12. A method of communication between a baseboard management controller and a processor, the method comprising: The high-speed peripheral component interconnect link is established between the substrate management controller and the processor, The method includes: A data request message sent by the substrate management controller through the high-speed peripheral component interconnect link is received; Business data is acquired in response to the data request message; The business data is packaged according to a high-speed peripheral component interconnect protocol to generate a business data response message; The business data response message is sent to the substrate management controller through the high-speed peripheral component interconnect link; An operation instruction sent by the substrate management controller through the high-speed peripheral component interconnect link is received; A corresponding operation is performed in response to the operation instruction.

13. An electronic device, comprising: It includes: A memory is used to store a computer program; A processor for implementing the steps of the communication method between the baseboard management controller and the processor as claimed in any one of claims 1 to 11 when the computer program is executed, or the steps of the communication method between the baseboard management controller and the processor as claimed in claim 12.

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