Parasitic capacitance calculation method and system and computer equipment

Abstract

The invention provides a stray capacitance calculation method and system and computer equipment, and relates to the technical field of integrated circuit design. The design layout is divided into a plurality of subunits according to the processing range, comprehensive three-dimensional solving of the whole design layout is avoided, and the calculated amount is remarkably reduced; key geometrical relationship and interlayer coupling information are reserved in the local subunits, so that an extraction result is close to three-dimensional numerical simulation precision; the subunits are classified in advance, and the corresponding pattern matching tables are matched according to categories, so that the retrieval and query efficiency is improved; off-line precipitation is carried out on a common structure and a parameter interval through a preset pattern library, the complexity of pre-generation and maintenance is controlled within an acceptable range while the capacitance extraction accuracy is guaranteed, and finally rapid and accurate calculation of the parasitic capacitance of the whole design layout is achieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a method, system and computer device for calculating parasitic capacitance. Background Technology

[0002] Parasitic capacitance in integrated circuits has a critical impact on circuit timing, integrity, and power consumption. As manufacturing nodes evolve towards smaller linewidths, interconnect structures exhibit characteristics such as increased layer count, diverse material types, and complex geometries. The acquisition of parasitic capacitance has gradually evolved from analytical estimation of a few typical structures to a comprehensive process relying on large-scale numerical calculations and data-driven methods.

[0003] Traditional methods for calculating parasitic capacitance face a core contradiction: the difficulty of balancing computational efficiency and result accuracy. While point-by-point solutions based on 3D numerical simulation offer high accuracy, the computational load increases dramatically with the number of structural combinations, resulting in low efficiency and difficulty in completing within project timeframes. On the other hand, fast methods based on simple empirical rules or coarse-grained table lookups, while quick, cannot provide reliable results for complex proximity couplings and interlayer relationships, exhibiting uncontrollable errors and lacking clear applicability boundaries. Summary of the Invention

[0004] The purpose of this application is to provide a parasitic capacitance calculation method, system, and computer device to overcome the shortcomings of traditional parasitic capacitance calculation methods, such as low efficiency, uncontrollable errors, and lack of clear applicable boundaries.

[0005] In a first aspect, this application proposes a method for calculating parasitic capacitance, the method comprising: Iterate through all conductors on the design layout; During the traversal, any conductor is taken as the dominant body, and based on each dominant body, the processing range is determined according to the preset rules. All conductors within the processing range are divided into the same sub-unit. Extract the feature information of each sub-unit, and cluster each sub-unit into different types of unit sets based on the feature information; Match the corresponding pattern matching table for each unit set from the preset pattern library; The capacitance data of each conductor in each sub-unit is obtained by querying the pattern matching table, and the parasitic capacitance of each sub-unit is calculated based on the capacitance data. The parasitic capacitance of each sub-unit is combined to obtain the parasitic capacitance of the design layout.

[0006] In one embodiment, the step of taking any one conductor as the dominant conductor and determining the processing range according to a preset rule based on each dominant conductor includes: Using the circumscribed rectangle of any dominant conductor as a reference, the planar projection range is obtained by extending it outwards by a predetermined distance within the layout plane; wherein, the predetermined distance is proportional to the minimum spacing of the layer in which the conductor is located; The layer containing the dominant entity and the n layers above and below it are considered as the vertical layer domain; where n is a positive integer. The planar projection range and the vertical layer domain constitute the processing range.

[0007] In one embodiment, the step of extracting feature information of each sub-unit and clustering each sub-unit into different types based on the feature information includes: The feature information is categorized, and a classification label is generated based on the categorization result. The feature information includes at least one of the following: the number of conductors in the same layer as the dominant body, the number of layers above the dominant body, the number of layers below the dominant body, and the spatial overlap relationship between the dominant body and the conductors above and below it. Sub-units with the same classification identifier are grouped into the same type.

[0008] In one embodiment, the preset pattern library includes multiple pre-built pattern matching tables, and the method for constructing each pattern matching table includes: Obtain the interconnect process format file corresponding to the process node; Based on the coverage area of ​​each conductor and the spatial overlap relationship between the dominant conductor and the upper and lower conductors, a set of feature structures is determined, and at least one pattern matching table is configured for each feature structure; the coverage area is used to define the topological boundary of the feature structure. The range of conductor parameters is set according to the geometric constraints in the interconnect process format file; the conductor parameters include the spacing between conductors in the same layer, the spacing between upper and lower layer conductors and the main conductor, and the width of each conductor; Within the specified value range, multiple discrete simulation points are selected according to a preset step size; the finite element method is used to solve for the capacitance of the characteristic structure corresponding to each simulation point to obtain parasitic capacitance data; A pattern matching table is generated based on the search information and parasitic capacitance data; the search information includes layer attributes and conductor width.

[0009] In one embodiment, matching the corresponding pattern matching table for each unit set from a preset pattern library includes: For each unit set, the retrieval information is determined based on the classification identifier corresponding to that unit set; Based on the retrieval information, a matching process is performed in a preset database to obtain the pattern matching table corresponding to the unit set.

[0010] In one embodiment, querying the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, and calculating the parasitic capacitance of each sub-unit based on the capacitance data, includes: For a given sub-unit, based on the retrieval information of the unit set to which the sub-unit belongs, locate the corresponding entry in the pattern matching table of the unit set to which it belongs; If the search information completely corresponds to the entry, the parasitic capacitance data of all conductors in the sub-unit is obtained based on the entry; the parasitic capacitance data includes mutual capacitance. The parasitic capacitance data of each conductor is added to the total capacitance of the main body of the sub-unit to obtain the parasitic capacitance of the sub-unit. If the search information does not completely correspond to an entry, multiple entries with the smallest difference from the search information are selected as candidate entries from the pattern matching table according to preset parameter differences and priorities. The parasitic capacitance data of each candidate item is obtained and interpolated to obtain the parasitic capacitance data of each conductor.

[0011] In one embodiment, adding the parasitic capacitance data of each conductor to the total capacitance of the sub-unit master body includes: Establish a conductor pair index to record each conductor pair combination that appears in each sub-unit and its corresponding parasitic capacitance data; For multiple parasitic capacitance data obtained for the same conductor pair in multiple sub-units, a weighted sum is performed to obtain the final parasitic capacitance of the conductor pair; for conductor pairs that appear only in a single sub-unit, the single result is used as the final parasitic capacitance. The total capacitance of the dominant conductor is obtained by summing up the final parasitic capacitances of the conductor pairs associated with the dominant conductor in each sub-unit.

[0012] In one embodiment, querying the pattern matching table to obtain the parasitic capacitance of each sub-unit further includes: When a unit set corresponds to multiple pattern matching tables, locate the corresponding entry in the multiple pattern matching tables; Obtain the parasitic capacitance data for each entry; The parasitic capacitance data of the same conductor is obtained by weighted summation of the parasitic capacitance data in different pattern matching tables.

[0013] Secondly, this application proposes a parasitic capacitance calculation system, the system comprising: The partitioning module is used to traverse all conductors on the design layout. During the traversal, for any conductor, the main conductor is used as the reference, and the processing range is determined according to the preset rules. All conductors within the processing range are divided into the same sub-unit. The classification module is used to extract feature information of each sub-unit and cluster each sub-unit into different types of unit sets based on the feature information; The matching module is used to match the corresponding pattern matching table for each unit set from the preset pattern library; The calculation module is used to query the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, calculate the parasitic capacitance of each sub-unit based on the capacitance data, and combine the parasitic capacitances of each sub-unit to obtain the parasitic capacitance of the design layout.

[0014] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method steps in the first aspect.

[0015] The above-mentioned method, system, and computer equipment for calculating parasitic capacitance have at least the following advantages: This application iterates through all conductors on the design layout. During the traversal, for any conductor, it takes that conductor as the main conductor and as the reference, determines the processing range according to preset rules, and divides all conductors within the processing range into the same sub-unit. It extracts the feature information of each sub-unit and clusters each sub-unit into different types of unit sets based on the feature information. It matches the corresponding pattern matching table for each unit set from the preset pattern library. It queries the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, calculates the parasitic capacitance of each sub-unit based on the capacitance data, and combines the parasitic capacitance of each sub-unit to obtain the parasitic capacitance of the design layout. By adopting the above scheme, this application divides the design layout into several sub-units according to the processing scope, avoiding a comprehensive three-dimensional solution for the entire design layout and significantly reducing the amount of computation. Key geometric relationships and inter-layer coupling information are preserved within local sub-units, making the extraction results close to the accuracy of three-dimensional numerical simulation. Each sub-unit is first classified and matched with the corresponding pattern matching table according to the category, improving retrieval and query efficiency. Common structures and parameter ranges are offline stored through a preset pattern library, ensuring the accuracy of capacitance extraction while keeping the complexity of pre-generation and maintenance within an acceptable range, ultimately achieving rapid and accurate calculation of parasitic capacitance for the entire design layout. Attached Figure Description

[0016] Figure 1 This is a diagram illustrating the application environment of the parasitic capacitance calculation method in one embodiment. Figure 2 This is a flowchart illustrating a parasitic capacitance calculation method in one embodiment; Figure 3 This is a schematic diagram of the structure of each conductor in a design layout of one embodiment; Figure 4 This is a structural schematic diagram of a sub-unit in one embodiment; Figure 5(a) is a schematic diagram of the feature structure corresponding to pattern matching table A in one embodiment; Figure 5(b) is a schematic diagram of the feature structure corresponding to pattern matching table B in one embodiment; Figure 6 This is a block diagram of a parasitic capacitance calculation system in one embodiment; Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0017] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0018] Some exemplary embodiments of this application have been described for illustrative purposes. It should be understood that this application may be implemented in other ways not specifically shown in the accompanying drawings.

[0019] The parasitic capacitance calculation method provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on another network server.

[0020] Terminal 102 can send the integrated circuit design layout to server 104, enabling server 104 to process the design layout. For example, server 104 traverses all conductors on the design layout; during the traversal, it takes any conductor as the dominant conductor and, based on each dominant conductor, determines the processing range according to preset rules, dividing all conductors within the processing range into the same sub-unit; it extracts the feature information of each sub-unit, and clusters each sub-unit into different types of unit sets based on the feature information; it matches the corresponding pattern matching table for each unit set from a preset pattern library; it queries the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, and calculates the parasitic capacitance of each sub-unit based on the capacitance data; it combines the parasitic capacitances of each sub-unit to obtain the parasitic capacitance of the design layout. Server 104 then feeds back the parasitic capacitance result to terminal 102.

[0021] The parasitic capacitance calculation method described above traverses all conductors on the design layout. During the traversal, for any given conductor, it is used as the main conductor and as a reference. The processing range is determined according to preset rules, and all conductors within the processing range are divided into the same sub-unit. Feature information of each sub-unit is extracted, and each sub-unit is clustered into different types of unit sets based on the feature information. A corresponding pattern matching table is matched for each unit set from a preset pattern library. The pattern matching table is queried to obtain the capacitance data of each conductor in each sub-unit, and the parasitic capacitance of each sub-unit is calculated based on the capacitance data. The parasitic capacitance of each sub-unit is combined to obtain the parasitic capacitance of the design layout. By adopting the above scheme, this application divides the design layout into several sub-units according to the processing scope, avoiding the need for comprehensive three-dimensional solution of the entire design layout and significantly reducing the amount of computation; it retains key geometric relationships and inter-layer coupling information within local sub-units, making the extraction results close to the accuracy of three-dimensional numerical simulation; it classifies each sub-unit first and matches the corresponding pattern matching table according to the category, improving the efficiency of retrieval and query; it offline accumulates common structures and parameter ranges through a preset pattern library, ensuring the accuracy of capacitance extraction while keeping the complexity of pre-generation and maintenance within an acceptable range, ultimately achieving fast and accurate calculation of parasitic capacitance of the entire design layout.

[0022] The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, and smart in-vehicle systems. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted devices. The server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0023] In one exemplary embodiment, this application provides a method for calculating parasitic capacitance, which will be applied to the following embodiments. Figure 1 We will use server 104 as an example to illustrate this.

[0024] Please see Figure 2 , Figure 2 This is a flowchart illustrating a parasitic capacitance calculation method according to this embodiment, which specifically includes the following steps: Step 202: Traverse all conductors on the design layout.

[0025] Specifically, the design layout of an integrated circuit is a complex structure composed of multiple types of layers, ranging from several to dozens of layers depending on its complexity. Typically, the design layout mainly includes: conductor layers, isolation layers, and process layers. Conductor layers define the paths for current flow, such as transistors and interconnects; isolation layers define and isolate different conductor regions; and process layers assist in manufacturing and inspection.

[0026] Conductors on a design layout refer to areas that are electrically conductive after fabrication. These include metal interconnect patterns, contacts and vias, device electrodes, metal fillers connected to the network, and pads. Conductors can consist of single-layer patterns or multi-layer through-structures and are identified and summarized based on the electrical connection network.

[0027] Furthermore, for a design layout, this application embodiment extracts all conductors from a preset layout database, merges cross-layer interconnected structures according to electrical connection networks, and forms a set of conductor entries.

[0028] Following a preset order, each conductor in the conductor entry set is traversed until all conductors have been scanned. For example, the preset order can be sorted by network priority, with higher priority networks scanned first; within the same network, scanning proceeds from bottom to top according to the hierarchy; within the same hierarchy, scanning proceeds from smallest to largest according to the minimum coordinates of the outer boundary.

[0029] Step 204: During the traversal, any conductor is taken as the dominant body, and based on each dominant body, the processing range is determined according to the preset rules. All conductors within the processing range are divided into the same sub-unit.

[0030] Specifically, during the traversal scan, each conductor is treated as a dominant entity. The processing range is determined based on this dominant entity, and all conductors within the processing range are then divided into sub-units. That is, each sub-unit corresponds to a dominant entity. By constructing the processing range based on the dominant entity, conductor pair indexes can be subsequently built based on this dominant entity. This avoids duplicate counting and prevents coupling omissions caused by overly fine division, ensuring that the summarized full-map capacitance results are closed-loop and traceable.

[0031] Step 206: Extract the feature information of each sub-unit, and cluster each sub-unit into different types of unit sets based on the feature information.

[0032] Specifically, the feature information is an abstract description of the key structural and geometric relationships related to parasitic capacitance within a sub-unit. For example, in embodiments of this application, the feature information includes at least one of the following: the number of conductors in the same layer as the dominant conductor, the number of layers above the dominant conductor, the number of layers below the dominant conductor, and the spatial overlap between the dominant conductor and the conductors above and below it.

[0033] Parasitic capacitance is primarily determined by relative position, overlap, spacing, width, and interlayer dielectric. Subunits with the same or similar characteristics exhibit similar coupling paths and field distributions, and their capacitance values ​​vary smoothly within a small range with the parameters. Therefore, they can be grouped into the same type and subjected to controlled interpolation within that type. After classification, subunits of the same type are uniformly linked to the corresponding pattern matching table, significantly narrowing the search scope and improving retrieval and query efficiency during subsequent queries.

[0034] Step 208: Match the corresponding pattern matching table for each unit set from the preset pattern library, query the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, calculate the parasitic capacitance of each sub-unit based on the capacitance data, and combine the parasitic capacitances of each sub-unit to obtain the parasitic capacitance of the design layout.

[0035] Specifically, the preset pattern library is a pre-set data warehouse that can be retrieved and called. It stores multiple pattern matching tables built based on the feature structure of the design layout. Each pattern matching table has an entry and its corresponding parasitic capacitance data. Each entry can correspond to a set of parameters.

[0036] The parasitic capacitance calculation method described above traverses all conductors on the design layout. During the traversal, for any given conductor, it is used as the main conductor and as a reference. The processing range is determined according to preset rules, and all conductors within the processing range are divided into the same sub-unit. Feature information of each sub-unit is extracted, and each sub-unit is clustered into different types of unit sets based on the feature information. A corresponding pattern matching table is matched for each unit set from a preset pattern library. The pattern matching table is queried to obtain the capacitance data of each conductor in each sub-unit, and the parasitic capacitance of each sub-unit is calculated based on the capacitance data. The parasitic capacitance of each sub-unit is combined to obtain the parasitic capacitance of the design layout. By adopting the above scheme, this application divides the design layout into several sub-units according to the processing scope, avoiding the need for comprehensive three-dimensional solution of the entire design layout and significantly reducing the amount of computation; it retains key geometric relationships and inter-layer coupling information within local sub-units, making the extraction results close to the accuracy of three-dimensional numerical simulation; it classifies each sub-unit first and matches the corresponding pattern matching table according to the category, improving the efficiency of retrieval and query; it offline accumulates common structures and parameter ranges through a preset pattern library, ensuring the accuracy of capacitance extraction while keeping the complexity of pre-generation and maintenance within an acceptable range, ultimately achieving fast and accurate calculation of parasitic capacitance of the entire design layout.

[0037] Optionally, any one conductor can be taken as the dominant conductor, and the processing range can be determined according to preset rules based on each dominant conductor, including: Using the circumscribed rectangle of any dominant conductor as a reference, the planar projection range is obtained by extending it outwards by a preset distance within the layout plane; wherein, the preset distance is proportional to the minimum spacing of the layer where the conductor is located; the layer where the dominant conductor is located and the n layers above and below it are taken as the vertical layer domain; wherein, n is a positive integer; the planar projection range and the vertical layer domain constitute the processing range.

[0038] Specifically, the bounding rectangle of a dominant body refers to the smallest rectangle on the map plane that is aligned with the coordinate axes and completely encloses the two-dimensional outline of the dominant body.

[0039] For a complete design layout, each conductor is treated as a dominant conductor. Each conductor is scanned sequentially, and several conductors near the dominant conductor are considered as a small unit based on preset rules. When formulating these preset rules, the spatial distance between the dominant conductor and other conductors should be considered. If a conductor is too far from the dominant conductor, its influence on the dominant conductor is considered small, and its capacitance can be ignored. For other conductors on the same layer as the dominant conductor, the preset distance is proportional to the minimum spacing of the layer containing that conductor. It should be understood that this proportional relationship can be determined based on accuracy requirements and the function of the layer. For example, for a general layout, two to three times the minimum spacing can be selected; for a high-precision layout, or where the dominant conductor's layer is adjacent to a complete reference layer, one to two times the minimum spacing can be selected. For conductors on layers above and below the dominant conductor, conductors exceeding n layers above and below are also considered too far from the dominant conductor and are not considered. For example, in this embodiment, n is 1, meaning only conductors on the layer above and below the dominant conductor are considered.

[0040] Please see Figure 3 , Figure 3 The diagram shows the structural schematics of the conductors in the design layout. When conductor 2 is the dominant conductor, conductors within the processing range may be assigned to the same unit as conductor 2. Among the conductors in the same layer, conductor 3 is within the preset distance range from conductor 2, while conductor 4 is not. Conductor 5 is within the processing range and is only one layer above conductor 2. Conductor 6 is within the processing range but extends beyond the layer above it. Conductor 1 is only one layer below conductor 2 but is not within the processing range. Therefore, only conductors 3 and 5 will ultimately be assigned to the same unit as conductor 2.

[0041] The above scheme expands the circumscribed rectangle of the dominant conductor according to the minimum spacing ratio, which can adapt to the linewidth and spacing scale of different process nodes, and prioritizes the inclusion of adjacent conductors and interlayer conductors that contribute the most to the dominant conductor, reducing the risk of coupling omissions. At the same time, the processing range formed by combining the planar projection range with the vertical layer domain restricts the solution to the necessary local area, significantly reducing the number of conductors to be calculated and the number of paired combinations, thus greatly reducing the computational load. In addition, the processing range boundary determined by the above-mentioned preset rules is clear and applicable to various design layouts.

[0042] Optionally, feature information of each sub-unit is extracted, and each sub-unit is clustered into different types based on the feature information, including: The feature information is categorized and a classification label is generated based on the categorization results. The feature information includes at least one of the following: the number of conductors in the same layer as the dominant body, the number of layers above the dominant body, the number of layers below the dominant body, and the spatial overlap between the dominant body and the conductors above and below. Subunits with the same classification label are classified into the same type.

[0043] Specifically, after dividing the complete design layout into multiple sub-units, each sub-unit is categorized into different types based on its characteristics. The pattern matching table and interpolation algorithm used for sub-units of the same type are consistent. This classification method and the interpolation algorithm for each type are universal for all layouts, requiring no special processing based on the layout.

[0044] The purpose of grading is to convert chaotic and varying geometric and interlayer information into a small number of stable, searchable grade labels. For example, the preset grading levels for the number of conductors in the same layer as the dominant element are: one, two, three, or more; in this embodiment, the number of upper and lower layers is only one, but in other embodiments, the number of layers can be set as needed; the grading levels for the spatial overlap relationship between the dominant element and the upper and lower layer conductors are: complete overlap, partial overlap, and no overlap. Thus, based on the characteristic information of each sub-unit, sub-units with the same grading level are classified into one type and assigned a classification identifier.

[0045] By adopting the above scheme, the type and pattern matching tables are matched, the search range is significantly narrowed, the matching and interpolation speed is improved, and the retrieval and query efficiency is increased.

[0046] Optionally, the preset pattern library includes multiple pre-built pattern matching tables, and the methods for constructing each pattern matching table include: Obtain the interconnect process format file corresponding to the process node; determine the set of feature structures based on the coverage of each conductor and the spatial overlap relationship between the dominant conductor and the upper and lower layer conductors, and configure at least one pattern matching table for each feature structure; the coverage is used to limit the topological boundary of the feature structure. Set the range of conductor parameters according to the geometric constraints in the interconnect process format file; conductor parameters include the spacing between conductors in the same layer, the spacing between conductors in the upper and lower layers and the main conductor, and the width of each conductor; Within the range of values, multiple discrete simulation points are selected according to a preset step size; the finite element method is used to solve the capacitance of the characteristic structure corresponding to each simulation point to obtain parasitic capacitance data; A pattern matching table is generated based on the retrieval information and parasitic capacitance data; the retrieval information includes layer attributes and conductor width.

[0047] Specifically, the interconnect process format file corresponding to a process node is a standardized, machine-readable description of the metal layers, dielectric stack-ups, and interconnect parameters of the process node. This file is used to drive simulation, extraction, and approval, and is typically provided by the foundry or a process design kit (PDK). The interconnect process format file includes information such as layer attributes, layer stack order, material and dielectric parameters, layer thickness, minimum width and minimum spacing geometric constraints, as well as the file's identifier and version.

[0048] The pattern matching tables in the preset database are set up according to the feature structures in the design layout. This application first determines the set of feature structures based on the coverage area and spatial overlap relationship of each conductor. In this embodiment, the coverage structure is determined based on the number of conductors in the same layer as the dominant conductor, the number of layers above the dominant conductor, the number of layers below the dominant conductor, and the spatial overlap relationship between the dominant conductor and the conductors above and below it; the spatial overlap relationship includes complete overlap, partial overlap, and no overlap. Based on the above information, a different pattern matching table is designed for each feature structure.

[0049] Furthermore, the retrieval information in the embodiments of this application includes layer attributes and conductor width. In practical applications, the corresponding retrieval information can be selected for each pattern matching table according to the feature structure. The retrieval information may also include spatial overlap level, same-layer spacing, inter-layer distance, same-layer conductor spacing of different layers from the dominant body, specified capacitance, number of upper and lower layers of the dominant body, etc.

[0050] Based on the geometric constraints of minimum spacing and minimum width in the interconnect process format file, the range of conductor parameters is set in integer multiples of these constraints. Within the range of values, a number of discrete simulation points are selected according to a preset step size, and parasitic capacitance data is generated only for these simulation points. The parasitic capacitance data in each pattern matching table is obtained by solving the capacitance of the characteristic structure corresponding to each simulation point using the finite element method based on the file information of the interconnect process format file. For example, this application constructs a three-dimensional geometric model consistent with its characteristic structure at each discrete simulation point based on the file information of the interconnect process format file, and configures electrical characteristic parameters consistent with the target process for this three-dimensional geometric model. These electrical characteristic parameters include material parameters, operating conditions, boundary and reference settings, and mesh and convergence control. The solver is started to calculate the electric field distribution of the three-dimensional geometric model and the equivalent parameters corresponding to each conductor. The equivalent parameters include the equivalent charge and flux under a specified excitation. Each conductor is selected as the test object in sequence, while other conductors are kept under preset reference or floating conditions. In each solution, the response of the tested conductor and the responses of other conductors to the excitation are read from the equivalent parameters, thereby obtaining the coupling information between the tested conductor and surrounding conductors, i.e., mutual capacitance.

[0051] Using the retrieved information as entries, write the corresponding parasitic capacitance data to generate a pattern matching table.

[0052] The program takes an interconnect process format file as input; different process nodes have their own corresponding interconnect process format files. The pattern matching table only needs to be generated once and can be used by all layouts with the same interconnect process format file.

[0053] The above scheme first configures a pattern matching table according to the feature structure set, then performs discrete simulation within the controlled value range and writes the table. Subsequent data extraction only requires table lookup and interpolation, avoiding point-by-point 3D solution of the entire layout, significantly reducing computational load and time. Furthermore, the conductor parameter value range is derived from the geometric constraints of the process file, and parasitic capacitance data in the pattern matching table is obtained offline using the finite element method. During the lookup phase, interpolation is only performed within the same spatial overlap level and value range; extrapolation is not performed beyond the limits, ensuring predictable errors and clear applicable boundaries. Furthermore, different process nodes have their own corresponding interconnect process format files. The pattern matching table only needs to be generated once for use by all layouts with the same interconnect process format file, and can be directly reused under the same process identifier and version, significantly reducing the cost of repetitive modeling and solving.

[0054] Optionally, a pattern matching table is matched for each unit set from a preset pattern library, including: For each unit set, the retrieval information is determined based on the classification identifier corresponding to that unit set; based on the retrieval information, a matching is performed in a preset database to obtain the pattern matching table corresponding to that unit set.

[0055] Specifically, the retrieval information includes multiple parameters, such as layer attributes, conductor width, spatial overlap level, interlayer spacing, interlayer distance, interlayer conductor spacing in layers different from the dominant material, specified capacitance, and the number of layers above and below the dominant material. When classifying the unit set, its corresponding retrieval information is also determined accordingly. Matching is performed using the determined retrieval information as the key to obtain at least one pattern matching table consistent with the target process.

[0056] Optionally, the capacitance data of each conductor in each sub-unit is obtained by querying the pattern matching table, and the parasitic capacitance of each sub-unit is calculated based on the capacitance data, including: For a given sub-unit, based on the retrieval information of the unit set to which the sub-unit belongs, locate the corresponding entry in the pattern matching table of the unit set to which it belongs; When the retrieved information completely matches the entry, the parasitic capacitance data of all conductors in the sub-unit is obtained based on the entry; the parasitic capacitance data includes mutual capacitance; the parasitic capacitance data of each conductor is added to the total capacitance of the main body of the sub-unit to obtain the parasitic capacitance of the sub-unit. If the retrieved information does not completely correspond to an entry, multiple entries with the smallest difference from the retrieved information are selected as candidate entries from the pattern matching table according to the preset parameter difference and priority; the parasitic capacitance data of each candidate entry is obtained and interpolated to obtain the parasitic capacitance data of each conductor.

[0057] Specifically, based on the search information, a search is performed in the corresponding pattern matching table. First, the search is filtered by layer attributes and spatial overlap level; then, each item is matched according to geometric level to finally locate the target item.

[0058] If the retrieved information perfectly matches an entry in the table, the parasitic capacitance data provided by that entry is directly read, including the mutual capacitance between the dominant conductor and each adjacent conductor within the sub-unit. Following established aggregation rules, all parasitic capacitances related to the dominant conductor are added to the total capacitance of the dominant conductor to obtain the parasitic capacitance result for that sub-unit. The parasitic capacitance results for all sub-units constitute the parasitic capacitance of the design layout.

[0059] If the retrieved information does not perfectly match a single entry, several candidate entries closest to the retrieved information are selected from the pattern matching table based on preset parameter differences and priorities. The parasitic capacitance data of each candidate entry is read, and interpolation is performed within the interval according to the positional relationship of the candidate entries in each parameter dimension to obtain the mutual capacitance of each conductor within the sub-unit. The parasitic capacitances related to the dominant body are added to the total capacitance of the dominant body, and the parasitic capacitance calculation of the sub-unit is completed. For example, if the parameter value of a parameter in the retrieved information is D, but the pattern matching table does not find parameter value D, but instead finds two parameter values ​​D1 and D2 that differ smallest from parameter value D, the capacitance values ​​C1 and C2 corresponding to parameter values ​​D1 and D2 are interpolated to obtain the capacitance value C. Capacitance value C is the capacitance value obtained by searching the pattern matching table.

[0060] Furthermore, if there are multiple parameters in the pattern matching table, the search proceeds sequentially according to the order of the parameters in the table. For example, if the parameter values ​​in the pattern matching table are W and S, and the actual layout has parameter values ​​w and s, the search first looks for parameter values ​​W1 and W2 with the smallest difference from w in the column corresponding to parameter value W. To facilitate the search, in this embodiment, the parameter values ​​in the pattern matching table are arranged in ascending order. After determining parameter values ​​W1 and W2, the search continues in the column corresponding to parameter value D among all points where W=W1, yielding parameter values ​​D11 and D12. Similarly, D21 and D22 corresponding to parameter value W2 can be found. When the number of parameters is n, a total of 2n points need to be searched.

[0061] Furthermore, due to the diverse and complex nature of actual design layouts, the feature structures corresponding to the pattern matching table are often not entirely consistent. This can lead to a discrepancy between the number of parameters in the design layout and the number of parameters in the selected pattern matching table. When the number of parameters in the design layout is less than that in the pattern matching table—for example, if the dominant conductor in the design layout has no adjacent conductors on the same layer, but the pattern matching table contains such a conductor—an additional parameter S representing the distance between the two conductors will be added. In this case, when looking up the table, S can be specified as the maximum value from the simulation point. When the number of parameters in the design layout is greater than that in the pattern matching table, it is possible to decide which information to ignore to reduce the number of parameters used for matching, based on actual needs.

[0062] Optionally, the parasitic capacitance data of each conductor is added to the total capacitance of the dominant body of the sub-unit, including: Establish a conductor pair index to record each conductor pair and its corresponding parasitic capacitance data in each sub-unit; for the same conductor pair, the multiple parasitic capacitance data obtained in multiple sub-units are weighted and summed to obtain the final parasitic capacitance of the conductor pair; for conductor pairs that appear only in a single sub-unit, the single result is used as the final parasitic capacitance; the final parasitic capacitance of the conductor pairs related to the dominant body in each sub-unit is accumulated one by one to obtain the total capacitance of the dominant body.

[0063] Specifically, when scanning the design layout, each conductor acts as the master body. By querying the parasitic capacitance data of each conductor in the sub-unit, and adding them to the master body, the capacitance value of each conductor can be obtained after scanning the entire design layout.

[0064] A conductor pair refers to two conductors that are coupled together. The parasitic capacitance data of a conductor pair refers to the mutual capacitance between the two conductors, excluding the self-capacitance of each conductor. Since the same conductor pair may appear in multiple sub-cells, a conductor pair index can be established to avoid duplicate calculations, giving each conductor pair a unique identifier.

[0065] For example, conductors 2 and 3 form a conductor pair. Subunit a includes conductors 2 and 3, with conductor 2 being the dominant conductor. Subunit b includes conductor 2, conductor 3, and conductor 4, with conductor 3 being the dominant conductor. When calculating the parasitic capacitance of subunit a, the capacitance values ​​of conductors 2 and 3 consist of two parts: c23 when conductor 2 is the dominant conductor and c32 when conductor 3 is the dominant conductor. Therefore, the final result for conductors 2 and 3 is c23 / 2 + c32 / 2. Dividing by 2 here is equivalent to a weighted average. In other embodiments, each conductor can be assigned a corresponding weight based on the geometric relationship between the conductors.

[0066] In another embodiment, if subunit c includes conductor 2 and conductor 5, and conductor 5 is the main conductor, since subunit a does not include conductor 5, when processing subunit a, it is only necessary to add c52 (when conductor 5 is the main conductor) to the total capacitance of conductor 2, without needing to divide by 2.

[0067] Optionally, the process of obtaining the parasitic capacitance of each sub-unit by querying the pattern matching table above also includes: When there are multiple pattern matching tables corresponding to a unit set, locate the corresponding entry in the multiple pattern matching tables; obtain the parasitic capacitance data of each entry; and perform a weighted summation of the parasitic capacitance data of the same conductor in different pattern matching tables to obtain the parasitic capacitance data of the conductor.

[0068] Please see Figure 4 , Figure 4 The diagram shown is a structural schematic of a subunit. Figure 4 The sub-units include conductor 1, conductor 2 and conductor 3, wherein conductor 2 is the main conductor.

[0069] Please refer to Figures 5(a) and 5(b). Figure 5(a) shows the feature structure corresponding to pattern matching table A, and Figure 5(b) shows the feature structure corresponding to pattern matching table B. In Figure 5(a), the dominant conductor 2 is not covered by the conductor of the next higher layer, while in Figure 5(b), the dominant conductor 2 is completely covered by conductor 3. Therefore, according to... Figure 4 The sub-unit shown can be matched to both pattern matching table A and pattern matching table B. By looking up the values ​​in pattern matching table A and pattern matching table B respectively, and then interpolating the obtained capacitance values, the capacitance extraction value of this layout can be obtained.

[0070] In another embodiment, if a sub-unit has a characteristic structure similar to that in Figure 5(b), where conductor 2 is on the metal1 layer and conductor 3 is on the metal4 layer, then searching for the values ​​of conductors 2 and 3 in the pattern matching table B will result in a matching failure. This is because pattern matching table B only stores data where the layer number difference between conductors 2 and 3 is within 2 layers. If the difference exceeds 2 layers, it means that conductors 2 and 3 are too far apart and have little influence on each other; in this case, the lookup result is 0.

[0071] The parasitic capacitance calculation method described above traverses all conductors on the design layout. During the traversal, for any given conductor, it is used as the main conductor and as a reference. The processing range is determined according to preset rules, and all conductors within the processing range are divided into the same sub-unit. Feature information of each sub-unit is extracted, and each sub-unit is clustered into different types of unit sets based on the feature information. A corresponding pattern matching table is matched for each unit set from a preset pattern library. The pattern matching table is queried to obtain the capacitance data of each conductor in each sub-unit, and the parasitic capacitance of each sub-unit is calculated based on the capacitance data. The parasitic capacitance of each sub-unit is combined to obtain the parasitic capacitance of the design layout. By adopting the above scheme, this application divides the design layout into several sub-units according to the processing scope, avoiding the need for comprehensive three-dimensional solution of the entire design layout and significantly reducing the amount of computation; it retains key geometric relationships and inter-layer coupling information within local sub-units, making the extraction results close to the accuracy of three-dimensional numerical simulation; it classifies each sub-unit first and matches the corresponding pattern matching table according to the category, improving the efficiency of retrieval and query; it offline accumulates common structures and parameter ranges through a preset pattern library, ensuring the accuracy of capacitance extraction while keeping the complexity of pre-generation and maintenance within an acceptable range, ultimately achieving fast and accurate calculation of parasitic capacitance of the entire design layout.

[0072] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0073] Based on the same inventive concept, this application also provides a parasitic capacitance calculation system. This system is applicable to the above-described parasitic capacitance calculation method. The solution provided by this system is similar to the solution described in the above-described method. Therefore, the specific limitations of one or more system embodiments provided below can be found in the limitations of the method above, and will not be repeated here.

[0074] Please see Figure 6 In one embodiment, the parasitic capacitance calculation system includes: a partitioning module, a classification module, a matching module, and a calculation module.

[0075] The partitioning module is used to traverse all conductors on the design layout. During the traversal, for any conductor, the main conductor is used as the reference, and the processing range is determined according to the preset rules. All conductors within the processing range are divided into the same sub-unit. The classification module is used to extract the feature information of each sub-unit and cluster each sub-unit into different types of unit sets based on the feature information; The matching module is used to match the corresponding pattern matching table for each unit set from the preset pattern library; The calculation module is used to query the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, calculate the parasitic capacitance of each sub-unit based on the capacitance data, and combine the parasitic capacitances of each sub-unit to obtain the parasitic capacitance of the design layout.

[0076] Optionally, the partitioning module takes any conductor as the dominant body and uses each dominant body as a reference to determine the processing range according to preset rules, including: taking the outer rectangle of any dominant body as a reference, extending it outwards by a preset distance in the layout plane to obtain the planar projection range; wherein, the preset distance is proportional to the minimum spacing of the layer where the conductor is located; taking the layer where the dominant body is located and the n layers above and below it as the vertical layer domain; wherein, n is a positive integer; the planar projection range and the vertical layer domain constitute the processing range.

[0077] Optionally, the classification module extracts feature information of each sub-unit and clusters each sub-unit into different types based on the feature information, including: performing grading processing on the feature information and generating classification labels based on the grading processing results; the feature information includes at least one of the following: the number of conductors in the same layer of the dominant body, the number of layers above the dominant body, the number of layers below the dominant body, and the spatial overlap relationship between the dominant body and the conductors above and below; and classifying sub-units with the same classification label into the same type.

[0078] Optionally, the parasitic capacitance calculation system described above also includes a pattern library construction module.

[0079] The pattern library construction module is used to pre-build and store multiple pattern matching tables to form a preset pattern library. The construction of each pattern matching table includes: obtaining the interconnect process format file corresponding to the process node; determining the set of feature structures based on the coverage of each conductor and the spatial overlap relationship between the dominant conductor and the upper and lower layer conductors, and configuring at least one pattern matching table for each feature structure; the coverage is used to define the topological boundary of the feature structure; setting the value range of conductor parameters according to the geometric constraints in the interconnect process format file; conductor parameters include the spacing between conductors in the same layer, the spacing between upper and lower layer conductors and the dominant conductor, and the width of each conductor; selecting multiple discrete simulation points within the value range according to a preset step size; using the finite element method to solve for the capacitance of the feature structure corresponding to each simulation point to obtain parasitic capacitance data; and generating a pattern matching table based on the retrieved information and the parasitic capacitance data; the retrieved information includes layer attributes and conductor width.

[0080] Optionally, the matching module matches a corresponding pattern matching table for each unit set from a preset pattern library, including: for each unit set, determining retrieval information based on the classification identifier corresponding to the unit set; and performing matching in a preset database based on the retrieval information to obtain the pattern matching table corresponding to the unit set.

[0081] Optionally, the calculation module queries the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, and calculates the parasitic capacitance of each sub-unit based on the capacitance data. This includes: for a sub-unit, locating the corresponding entry in the pattern matching table corresponding to the unit set to which the sub-unit belongs, based on the retrieval information; if the retrieval information completely matches the entry, obtaining the parasitic capacitance data of all conductors in the sub-unit based on the entry; the parasitic capacitance data includes mutual capacitance; adding the parasitic capacitance data of each conductor to the total capacitance of the dominant body of the sub-unit to obtain the parasitic capacitance of the sub-unit; if the retrieval information does not completely match an entry, selecting multiple entries with the smallest difference from the retrieval information as candidate entries from the pattern matching table according to preset parameter differences and priorities; obtaining the parasitic capacitance data of each candidate entry and performing interpolation calculations to obtain the parasitic capacitance data of each conductor. If there are multiple pattern matching tables corresponding to a unit set, locating the corresponding entry in multiple pattern matching tables; obtaining the parasitic capacitance data of each entry; and performing a weighted summation of the parasitic capacitance data of the same conductor in different pattern matching tables to obtain the parasitic capacitance data of the conductor.

[0082] Optionally, the calculation module adds the parasitic capacitance data of each conductor to the total capacitance of the dominant body of the sub-unit, including: establishing a conductor pair index, recording each pair of conductors appearing in each sub-unit and its corresponding parasitic capacitance data; for the same conductor pair, the multiple parasitic capacitance data obtained in multiple sub-units are weighted and summed to obtain the final parasitic capacitance of the conductor pair; for conductor pairs that appear only in a single sub-unit, the single result is used as the final parasitic capacitance; and the final parasitic capacitance of the conductor pairs related to the dominant body in each sub-unit is accumulated one by one to obtain the total capacitance of the dominant body.

[0083] The parasitic capacitance calculation system described above traverses all conductors on the design layout. During the traversal, for any given conductor, it uses that conductor as the main conductor and as a reference, determines the processing range according to preset rules, and divides all conductors within the processing range into the same sub-unit. It extracts the feature information of each sub-unit and clusters each sub-unit into different types of unit sets based on the feature information. It matches the corresponding pattern matching table for each unit set from a preset pattern library. It queries the pattern matching table to obtain the capacitance data of each conductor in each sub-unit, calculates the parasitic capacitance of each sub-unit based on the capacitance data, and combines the parasitic capacitances of each sub-unit to obtain the parasitic capacitance of the design layout. By adopting the above scheme, this application divides the design layout into several sub-units according to the processing scope, avoiding the need for comprehensive three-dimensional solution of the entire design layout and significantly reducing the amount of computation; it retains key geometric relationships and inter-layer coupling information within local sub-units, making the extraction results close to the accuracy of three-dimensional numerical simulation; it classifies each sub-unit first and matches the corresponding pattern matching table according to the category, improving the efficiency of retrieval and query; it offline accumulates common structures and parameter ranges through a preset pattern library, ensuring the accuracy of capacitance extraction while keeping the complexity of pre-generation and maintenance within an acceptable range, ultimately achieving fast and accurate calculation of parasitic capacitance of the entire design layout. Each module in the aforementioned parasitic capacitance calculation system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0084] In one feasible embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements the parasitic capacitance calculation method described above. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0085] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0086] In one feasible embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method steps in the parasitic capacitance calculation method described above.

[0087] In one feasible embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method steps in the parasitic capacitance calculation method described above.

[0088] In one feasible embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the method steps in the parasitic capacitance calculation method described above.

[0089] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of calculating parasitic capacitance, characterized by, The method comprises: traversing all conductors on a design layout; during the traversal, taking any conductor as a main conductor, and determining a processing range according to a preset rule with each main conductor as a reference, and dividing all conductors located in the processing range into a same subunit; extracting feature information of each subunit, and clustering each subunit into a unit set of different types based on the feature information; matching a corresponding mode matching table for each unit set from a preset mode library; querying the mode matching table to obtain capacitance data of each conductor in each subunit, and calculating parasitic capacitance of each subunit according to each capacitance data, and combining parasitic capacitance of each subunit to obtain parasitic capacitance of the design layout.

2. The method of claim 1, wherein, The method comprises: taking a circumscribed rectangle of any main conductor as a reference, expanding a preset distance in all directions on the layout plane to obtain a planar projection range; wherein the preset distance is in proportional relationship with the minimum spacing of the layer where the conductor is located; taking the layer where the main conductor is located and n layers above and below it as a vertical layer domain; wherein n is a positive integer; the planar projection range and the vertical layer domain constitute the processing range.

3. The method of claim 1, wherein, The method comprises: performing grading processing on the feature information, and generating a classification identifier according to the grading processing result; the feature information comprises at least one of the number of conductors on the same layer as the main conductor, the number of layers above the main conductor, the number of layers below the main conductor, and the spatial overlap relationship between the main conductor and the conductors above and below it; subunits with the same classification identifier are divided into the same type.

4. The method of claim 1, wherein, The preset mode library comprises a plurality of mode matching tables constructed in advance, and the mode matching tables are constructed in the following manner: obtain an interconnection process format file corresponding to a process node; determine a set of feature structures according to the coverage range of each conductor and the spatial overlap relationship between the main conductor and the conductors above and below it, and configure at least one mode matching table for each feature structure; the coverage range is used to define the topological boundary of the feature structure; set the value range of the conductor parameters according to the geometric constraint conditions in the interconnection process format file; the conductor parameters include the spacing between conductors on the same layer, the spacing between the conductors above and below and the main conductor, and the width of each conductor; select a plurality of discrete simulation points in the value range according to a preset step size; use the finite element method to solve the capacitance of the feature structure corresponding to each simulation point to obtain parasitic capacitance data; generate a mode matching table based on the search information and the parasitic capacitance data; the search information includes layer attributes and conductor width.

5. The method of claim 4, wherein, The method comprises: for each unit set, determine the search information according to the classification identifier corresponding to the unit set; match the search information in the preset database to obtain the mode matching table corresponding to the unit set.

6. The method of claim 5, wherein, The method comprises: For a subunit, according to retrieval information of a unit set to which the subunit belongs, a corresponding entry is located in a pattern matching table corresponding to the unit set; In a case where the retrieval information completely corresponds to the entry, parasitic capacitance data of all conductors in the subunit are obtained based on the entry; the parasitic capacitance data include mutual capacitance; The parasitic capacitance data of each conductor are added to total capacitance of a main conductor of the subunit, to obtain parasitic capacitance of the subunit; In a case where the retrieval information fails to completely correspond to an entry, according to a preset parameter difference and priority, multiple entries with the smallest difference from the retrieval information are selected from the pattern matching table as candidate entries; Parasitic capacitance data of each candidate entry are obtained and interpolation calculation is performed, to obtain parasitic capacitance data of each conductor.

7. The method of claim 6, wherein, The adding of the parasitic capacitance data of each conductor to the total capacitance of the main conductor of the subunit includes: An index of conductor pairs is established, to record each pair of conductor combination appearing in each subunit and corresponding parasitic capacitance data thereof; For multiple parasitic capacitance data of a same conductor pair obtained in multiple subunits, weighted summation is performed thereon, to obtain final parasitic capacitance of the conductor pair; for a conductor pair appearing only in a single subunit, the single result is used as final parasitic capacitance; Final parasitic capacitance of conductor pairs related to a main conductor in each subunit is accumulated one by one, to obtain total capacitance of the main conductor.

8. The method of claim 6, wherein, The querying of the pattern matching table for parasitic capacitance of each subunit further includes: In a case where the pattern matching table corresponding to a unit set is multiple, corresponding entries are located in multiple pattern matching tables; Parasitic capacitance data of each entry are obtained; For parasitic capacitance data of a same conductor in different pattern matching tables, weighted summation is performed, to obtain parasitic capacitance data of the conductor.

9. A parasitic capacitance calculation system characterized by comprising: The system includes: A division module, configured to traverse all conductors on a design layout; in the traversal process, for any conductor, the conductor is taken as a main conductor and a reference, a processing range is determined according to a preset rule, and all conductors located in the processing range are divided into a same subunit; A classification module, configured to extract feature information of each subunit, and cluster each subunit into different types of unit sets based on the feature information; A matching module, configured to match a corresponding pattern matching table for each unit set from a preset pattern library; A calculation module, configured to query the pattern matching table for capacitance data of each conductor in each subunit, and calculate parasitic capacitance of each subunit according to the capacitance data, combine parasitic capacitance of each subunit, and obtain parasitic capacitance of the design layout. 10.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-9. The processor, when executing the computer program, implements steps of the method in any one of claims 1-8.

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