Method and device for refreshing dynamic random access memory based on DDR5, electronic equipment and storage medium

Abstract

The invention discloses a DDR5-based dynamic random access memory refreshing method and device, electronic equipment and a storage medium, and the refreshing method comprises the steps: presetting a transmission address mapping logic circuit, and integrating the transmission demands of the same bank and the same page of different bank groups into a continuous transmission task in a centralized manner; the DRAM refresh mode is divided into a DRAM self-refresh mode and a normal working mode, and the DRAM refresh mode is switched according to a command of a user command interface of the DRAM controller; wherein in the normal working mode, one-time activation, one-time pre-charging and one-time refreshing operation need to be carried out when transmission tasks of all the same banks and the same pages in each bank group are completed, and only read-write operation is carried out on a DRAM interface in the transmission process; and the switching between the bank groups follows a polling arbitration logic according to a certain rule. According to the refreshing method, on the premise that the transmission efficiency of the solid state disk is guaranteed, the DDR5 regular refreshing requirement is met, and it is guaranteed that DRAM particles stably work under various working conditions.

Description

Technical Field

[0001] This invention relates to the field of memory, and more particularly to a refresh method, apparatus, electronic device, and storage medium for a DDR5-based dynamic random access memory. Background Technology

[0002] In the enterprise-grade solid-state drive (SSD) field, high performance and high reliability are core technical indicators. Dynamic random access memory (DRAM) chips, as the key storage medium for storing flash memory address-mapped data, have become an indispensable component for achieving the high performance of enterprise-grade SSDs due to their high bandwidth, low latency, and high reliability. Specifically, the fast access to flash memory address-mapped data directly determines the SSD's response efficiency to host read / write requests. The aforementioned characteristics of DRAM chips can effectively shorten the access time for address-mapped data, thereby significantly improving the overall read / write performance of enterprise-grade SSDs and meeting the stringent data transfer speed requirements of enterprise-level application scenarios.

[0003] According to the latest JEDEC79-5 protocol standard developed by JEDEC (Joint Electron Device Engineering Council), the current mainstream fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5) has reached a maximum operating speed of 6400 MTps, further enhancing the data transfer efficiency advantage of DRAM chips. However, DRAM chips are volatile storage media, and their stored data relies on the charge of internal capacitors. Capacitors inevitably experience charge leakage, and if the charge is not replenished in time, the stored data will be lost. Therefore, the SSD controller needs to periodically send refresh commands to the DRAM chips to maintain stable capacitor charge and ensure data integrity. It is worth noting that with the iterative updates of the JEDEC79 standard, from DDR4 to DDR5, the refresh interval of DRAM chips has been shortened from 7.9 microseconds (μs) to 3.9 microseconds (μs), significantly increasing the frequency of refresh operations.

[0004] In current enterprise-level solid-state drive (SSD) applications, although the high bandwidth and low latency characteristics of DRAM chips support improved drive performance, there are still pressing technical issues to be addressed regarding the coordination between DRAM refresh operations and hard drive data transmission. On one hand, DRAM chips need to enter an idle state before performing a refresh operation, making simultaneous data read / write transmission impossible. Furthermore, existing DRAM controllers mostly employ autonomous timed refresh strategies, which only perform refreshes based on preset time intervals. This lacks interoperability with actual SSD business scenarios (such as read / write load intensity and data transmission rhythm), and cannot dynamically adjust refresh timing according to business needs. During hard drive data read / write transmission, even if a concentrated refresh operation is implemented by delaying individual refresh operations to reduce the proportion of the hard drive's business window occupied by refresh operations, urgent refresh requests from DRAM chips may still occur within the concentrated refresh interval. Failure to respond immediately to these requests will increase the risk of data loss, necessitating the suspension of ongoing hard drive transmission services and prioritizing the refresh command. This operation directly causes a significant drop in overall hard drive transmission bandwidth, severely impacting the hard drive's steady-state transmission performance.

[0005] On the other hand, as mentioned earlier, with the updates to the JEDEC 79 standard, the refresh interval of DRAM chips is constantly decreasing, and refresh operations are becoming more frequent. Especially when enterprise-level solid-state drives (SSDs) face complex environmental factors such as external temperature fluctuations and electromagnetic interference, the charge leakage rate of the capacitors inside the DRAM chips may accelerate. In this case, meeting the timed refresh requirements of DRAM chips is crucial for ensuring the operational stability of DRAM chips and reducing the bit error rate of data storage. If the timing and method of refresh operations cannot adapt to the above requirements, it will not only exacerbate the problem of transmission bandwidth fluctuations, but may also lead to data integrity damage, affecting the reliable operation of enterprise-level SSDs.

[0006] The disclosure of the above background technical content is only for the purpose of assisting in understanding the concept and technical solution of this application, and does not necessarily provide technical instruction. Summary of the Invention

[0007] The purpose of this invention is to provide a refresh method, apparatus, electronic device, and storage medium for DDR5-based dynamic random access memory, which meets the timed refresh requirements of DDR5 while ensuring the transmission efficiency of solid-state drives and ensures that DRAM chips work stably under various operating conditions.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A refresh method for DDR5-based dynamic random access memory includes: pre-setting a transfer address mapping logic circuit to integrate the transfer requests of the same page in the same bank of different bank groups into a single continuous transfer task; DRAM refresh modes are divided into DRAM self-refresh mode and normal working mode, and the DRAM refresh mode is switched according to the commands of the DRAM controller's user command interface. In the normal working mode, the completion of the transmission task of all the same page in the same bank in each bank group requires one activation, one precharge and one refresh operation. During the transmission process, only read and write operations are performed on the DRAM interface. The switching between the bank groups follows a polling arbitration logic based on certain rules.

[0009] As described above, in the normal operating mode, the completion of transmission tasks for all identical pages in the same bank within each bank group requires one activation, one precharge, and one refresh operation. During the transmission process, only read and write operations occur on the DRAM interface. When the transmission address mapping logic circuit integrates the transmission requirements of the same page in the same bank of different bank groups into a continuous task, the DRAM controller will perform a unified activation operation on the same bank. After activation, the continuous transmission phase begins, where the DRAM interface is responsible for transmitting the integrated read and write data, and activation, precharge, or refresh operations are no longer inserted. Once the integrated continuous transmission task is completed, the DRAM controller will perform a unified precharge operation on the same page of the same bank, shut down the activated bank, release the hardware resources it occupies, and return the bank to the waiting state to prepare for the next transmission. Once the pre-charging is complete, a refresh operation is immediately performed. A refresh command is issued to the same page of the same bank that was just pre-charged to replenish the capacitor charge.

[0010] Based on any one or a combination of the aforementioned technical solutions, the DRAM controller's self-refresh function is disabled throughout the process. The DRAM self-refresh mode is a low-power state that occurs when the DRAM is in an idle state and the user command interface sends a command to enter the DRAM self-refresh mode.

[0011] Based on any one or a combination of the aforementioned technical solutions, the transmission address mapping logic circuit is located in the cache control unit of the solid-state drive main controller chip, and when the circuit integrates transmission requirements, the size of a single continuous transmission task is determined by the bandwidth of the solid-state drive's access to DRAM, so as to adapt to the transmission efficiency requirements under different read and write load scenarios.

[0012] As described above, in the normal operating mode, the user command interface of the DRAM controller periodically sends refresh commands along with the read / write business process of the solid-state drive. The refresh command is executed during DRAM transmission, and during execution, it selects to refresh all banks or refresh some pages of banks with the same sequence number to ensure that the refresh operation does not interrupt the current transmission service or reduce the DRAM transmission bandwidth.

[0013] Based on any one or a combination of the aforementioned technical solutions, the autonomous refresh function of the DRAM controller is disabled. The solid-state drive main controller firmware completely controls the DRAM refresh operation timing through the user command interface, including the refresh command issuance interval and refresh range selection, to avoid conflicts between autonomous refresh and service transmission. Based on any one or a combination of the aforementioned technical solutions, when the solid-state drive controller responds to a sudden surge in large data volume from the host, the execution of the current DRAM refresh operation is postponed to extend the DRAM single burst transmission time window, ensuring that the refresh operation is only executed after the transmission task corresponding to the burst service is fully completed, thus maintaining the steady-state transmission performance of the solid-state drive.

[0014] Based on any one or a combination of the aforementioned technical solutions, when the DRAM switches from an idle state to a working state with service requirements, the user command interface first sends a command to exit the DRAM self-refresh mode, waking the DRAM from a low-power state to a normal working mode. Then, a refresh operation is issued to ensure the integrity of the data stored in the DRAM before executing subsequent read / write transmission tasks.

[0015] Following any or a combination of the aforementioned technical solutions, in the normal operating mode, when the solid-state drive controller detects a sudden surge in large data volume from the host, it performs the following operations through the user command interface: Temporarily postpone the currently pending DRAM refresh operation to extend the single burst transfer time window of the DRAM; The transmission address mapping logic circuit is triggered to prioritize the integration of transmission requirements of the same page in the same bank in all different bank groups related to the burst of large data volume, forming a continuous transmission task adapted to the burst of large data volume. The DRAM interface is controlled to perform only read and write operations during the execution of the continuous transmission task, until all transmission tasks corresponding to the large data burst service are fully completed. After the large data burst is completed, a centralized refresh operation is performed on all bank-pages involved in the transmission to meet the DRAM's timed refresh requirements and avoid data loss.

[0016] Based on any one or a combination of the aforementioned technical solutions, the identification criteria for the sudden surge in large data volume include at least one of the following: the amount of data in a single read / write request issued by the host exceeds a preset threshold, the frequency of host read / write requests received by the solid-state drive per unit time exceeds a preset frequency threshold, and the bandwidth of the solid-state drive accessing DRAM reaches a preset high load threshold.

[0017] According to another aspect of the present invention, the present invention provides a refresh device for a DDR5-based dynamic random access memory, including a transfer address mapping logic circuit for integrating the transfer requests of the same page in the same bank of different bank groups into a single continuous transfer task. The user command interface is used to control the switching of DRAM refresh modes, which are divided into DRAM self-refresh mode and normal working mode. The normal working mode refresh module is used to complete the transmission task of all the same page of the same bank in each bank group in the normal working mode. It requires one activation, one precharge and one refresh operation. During the transmission process, there are only read and write operations on the DRAM interface. The DRAM self-refresh mode module is used to ensure that the DRAM is in an idle state during the DRAM self-refresh mode, and that the DRAM enters a low-power state after the user command interface sends a command to enter the DRAM self-refresh mode.

[0018] According to another aspect of the present invention, an electronic device is provided, comprising: Memory, used to store computer programs; When a processor executes a computer program stored in the memory, it performs the steps of the method described above.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, the steps of the method described above are performed.

[0020] The beneficial effects of the technical solution provided by this invention are as follows: a. Balancing transmission performance and data security, resolving the core conflict between DRAM refresh and service transmission: Through hardware and software co-design, at the hardware level, a transmission address mapping logic circuit is set in the SSD main controller cache control unit to integrate the transmission needs of the same bank and the same page in different bankgroups into a continuous task, realizing batch transmission with "one activation + one precharge + one refresh", avoiding interruption by refresh during transmission; at the software level, the firmware flexibly controls the refresh timing through the user command interface, and can refresh during burst transmission gaps and trigger self-refresh during idle periods, which not only meets the timing requirements of DDR5-3.9μs short refresh interval (preventing data loss and reducing bit error rate), but also avoids the bandwidth drop caused by the forced suspension of services by traditional self-refresh, ensuring the steady-state transmission performance of SSD; b. Reduce power consumption and development costs, and improve scenario adaptability: On the one hand, when idle, the DRAM enters self-refresh mode, and the internal circuitry completes the data refresh autonomously without the need for continuous intervention from the main controller, which greatly reduces the proportion of DRAM power consumption, reduces the overall heat generation of the SSD, and improves device stability; on the other hand, the main controller chip has a hardened hardware mechanism of "allocating burst data by address mapping", which eliminates the need for the firmware to repeatedly debug the DRAM controller address optimization logic and shortens the development cycle of different firmware versions; at the same time, the firmware can dynamically adjust the refresh strategy (such as delaying refresh or switching self-refresh mode) according to external operating conditions (such as temperature) and business load (such as sudden large data volume requests from the host), adapting to complex application scenarios of enterprise-level SSDs. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a refresh method provided as an exemplary embodiment of the present invention; Figure 2 A schematic diagram of a refresh method in normal working mode provided as an exemplary embodiment of the present invention; Figure 3 A schematic diagram of a refresh method for handling large amounts of data, provided as an exemplary embodiment of the present invention; Figure 4 A schematic diagram of a refresh device provided for an exemplary embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0025] In one embodiment of the present invention, a refresh method for DDR5-based dynamic random access memory is provided, including: pre-setting a transmission address mapping logic circuit to integrate the transmission requirements of the same page in the same bank of different bank groups into a single continuous transmission task; the DRAM refresh mode is divided into DRAM self-refresh mode and normal working mode, and the DRAM refresh mode is switched according to the command of the user command interface of the DRAM controller. In the normal operating mode, the completion of transmission tasks for all pages in the same bank within each bank group requires one activation, one precharge, and one refresh operation. During the transmission process, only read and write operations occur on the DRAM interface. For example, the execution process is as follows: When the transmission address mapping logic circuit integrates the transmission requirements of the same page in the same bank of different bank groups (such as Bank0-page0 of Group1, Bank0-page0 of Group2, and Bank0-page0 of Group3) into a continuous task, the DRAM controller will perform a unified activation operation on the same bank. After activation, the continuous transmission phase begins, where the DRAM interface is responsible for transmitting the integrated read and write data, and activation, precharge, or refresh operations are no longer inserted. Once the integrated continuous transmission task is completed, the DRAM controller will perform a unified precharge operation on the same bank, shut down the activated bank, release the hardware resources it occupies, and return the bank to the waiting state to prepare for the next transmission. After precharging is completed, a refresh operation is immediately performed, issuing a refresh command to the same bank that was just precharged to replenish the capacitor charge.

[0026] The logical advantage of "one activation + one precharge + one refresh" in normal working mode is based on the underlying hardware rules of DDR5: any bank must be "activated" (opened) before it can read or write data, and "precharged" (closed) after it is used up. Moreover, the refresh operation can only be performed on "precharged banks" or "banks in the transmission gap". The design of this invention conforms to this rule and achieves "uninterrupted transmission and uninterrupted refresh".

[0027] In one embodiment of the present invention, the switching between the bank groups follows a polling arbitration logic based on certain rules.

[0028] The switching process based on the polling arbitration logic can be understood as switching tasks on the same page of the same bank group in a fixed order, one batch at a time. For example: Assuming there are four bank groups: Group1, Group2, Group3, and Group4, the polling order is as follows: Group1's Bank0-pageX → Group2's Bank0-pageX → Group3's Bank0-pageX → Group4's Bank0-pageX (first batch: Bank0-pageX of all groups) → Group1's Bank1 → Group2's Bank1 → Group3's Bank1 → Group4's Bank1 (second batch: the same page of Bank1 of all groups)... and so on. Each batch can first activate the same page of the same bank in four different groups, and then perform continuous read and write transmissions on these four activated pages.

[0029] The switching is triggered only after the current batch of integrated transmission loops (activation → transmission → precharging → refresh) for the same bank and page in different groups is completely completed.

[0030] The essence of switching is not random switching between individual bank groups, but batch switching according to the same bank + page + polling order. This is because each batch of tasks has already integrated the same bank and the same page in different groups. When switching, it is only necessary to repeat the closed loop of "activation → transmission → precharging → refresh" for the new same bank and the same page. There is no need to frequently switch groups, which reduces the overhead of hardware operations.

[0031] In one embodiment of the present invention, the DRAM self-refresh mode is a low-power state that is entered after the user command interface sends a command to enter the DRAM self-refresh mode when the DRAM is in an idle state.

[0032] Understandably, DRAM idle state means that the solid-state drive (SSD) has no read / write requests from the host, and the DRAM is temporarily not in use (such as when the server is not running at night or the computer is in standby).

[0033] User command interface sends commands: The SSD controller chip sends a "enter self-refresh mode" instruction to the DRAM through a dedicated "user command interface" - this is the "switch" for the DRAM to switch working modes.

[0034] Upon receiving the command, the DRAM will perform the following operations: Shut down unnecessary circuits: such as data transmission channels and some logic control units, leaving only the "self-refresh circuit" and the most basic power supply.

[0035] Start the internal refresh timer: The DRAM's own small circuitry starts to refresh the data periodically, eliminating the need for the SSD controller to send refresh commands.

[0036] Ultimately, this approach preserves data while saving power. No data loss: Although DRAM enters low power mode, the internal self-refresh circuit will refresh the data on time, the capacitor charge will not leak, and the stored flash memory address mapping table and other critical data will remain safe.

[0037] Significantly reduced power consumption: Compared to normal operating mode, self-refresh mode can significantly reduce power consumption, thereby reducing SSD heat generation and extending device lifespan.

[0038] In one embodiment of the present invention, the transmission address mapping logic circuit is disposed in the cache control unit of the solid-state drive main controller chip, and when the circuit integrates transmission requirements, the size of a single continuous transmission task is determined by the bandwidth of the solid-state drive's access to DRAM, so as to adapt to the transmission efficiency requirements under different read and write load scenarios.

[0039] In one embodiment of the present invention, in the normal operating mode, the user command interface of the DRAM controller periodically sends refresh commands along with the read / write business process of the solid-state drive. The refresh command is executed during DRAM transmission, and during execution, it selects to refresh all banks or refresh some banks with the same sequence number to ensure that the refresh operation does not interrupt the current transmission service or reduce the DRAM transmission bandwidth.

[0040] It is worth noting that in both the normal working mode and the DRAM self-refresh mode of this invention, the autonomous refresh in the DRAM controller is disabled, and firmware is used to control the DRAM refresh operation as well as the self-refresh entry and exit operations.

[0041] In one embodiment of the present invention, in the normal operating mode, the autonomous refresh function of the DRAM controller is disabled, and the solid-state drive main controller firmware completely controls the DRAM refresh operation timing through the user command interface, including the refresh command issuance interval and refresh range selection, so as to avoid conflicts between autonomous refresh and service transmission.

[0042] In one embodiment of the present invention, when the solid-state drive controller responds to a sudden surge in large data volume from the host, the execution of the current DRAM refresh operation is postponed to extend the single burst transmission time window of the DRAM, ensuring that the refresh operation is performed only after the transmission task corresponding to the burst service is fully completed, thereby maintaining the steady-state transmission performance of the solid-state drive.

[0043] In one embodiment of the present invention, when the DRAM switches from an idle state to a working state with service requirements, the user command interface first sends a command to exit the DRAM self-refresh mode, so that the DRAM wakes up from the low power state to the normal working mode, and then issues a refresh operation to ensure the integrity of the data stored in the DRAM before executing subsequent read and write transmission tasks.

[0044] For example, a server initiates a 128KB sequential write request to an enterprise-grade SSD. The SSD controller needs to write this data to the NAND flash memory. This process relies on DDR5 DRAM to store a "flash memory address mapping table" (i.e., recording crucial data of "host logical address → NAND physical address"). The execution steps are as follows: Figure 3 As shown: Step 1: Integration of Address Mapping Logic Circuits The SSD controller's address mapping logic circuit recognizes that this write request involves updating the address mapping data for bank0-page0 (i.e., the same page in the same bank of different bank groups) in multiple bank groups (let's say bank group0, bank group2, and bank group3). Leveraging the shortest switching latency between the same page in the same bank of different bank groups, the circuit integrates the dispersed transmission needs into a single continuous transmission task (e.g., "updating the address mapping entries in bank0-page0 of bank group0, bank0-page0 of bank group1, and bank0-page0 of bank group2 all at once").

[0045] Step 2: Polling Arbitration and Activation Operation Following a polling arbitration logic, the DRAM controller sequentially confirms the transmission permissions of each bank group and then performs an activation operation on the same bank. Activation commands are sent to bank0-page0 of bank group0, bank0-page0 of bank group1, and bank0-page0 of bank group2 respectively to open the storage arrays of these banks and prepare for subsequent data writing.

[0046] Step 3: Pure read / write transfer, without interference from other operations. After activation, the DRAM interface enters the pure read / write phase: The SSD controller updates the address mapping data corresponding to the 128KB write request and writes it continuously to bank0-page0 of the above three bank groups.

[0047] During this process, the DRAM interface only transmits read and write data, without inserting activation, precharge, or refresh operations, ensuring the continuity and high bandwidth of data transmission.

[0048] Step 4: Pre-charge + refresh, completing the task loop. After all 128KB of data has been written, two key operations are performed: One precharge: Send a precharge command to bank0-page0 of bank group1, bank0-page0 of bank group2, and bank0-page0 of bank group3 to close these bank-page0s and release hardware resources.

[0049] One refresh: For these banks0 that have just been pre-charged, send a refresh command to replenish the charge of the storage capacitors and ensure that data is not lost.

[0050] Step 5: Switch to the next task (if applicable) If there are new transmission tasks (such as the host initiating another read request), the DRAM controller will switch to the next batch of tasks in the same bank and page (such as bank1-pagex of bank group4 and bank group5) according to the polling arbitration logic, and repeat the process of activation → transmission → precharge → refresh; if there are no tasks temporarily, the DRAM self-refresh mode can be triggered by the user command interface to enter a low-power state.

[0051] In this process, the design of "integrating the same bank and same page transmission + one-time activation / precharge / refresh" not only avoids the transmission interruption caused by frequent bank group switching in the traditional mode, but also completes the refresh by utilizing the transmission gap, ensuring the bandwidth stability of 128KB write requests (without speed drop caused by refresh), while meeting the DDR5-3.9μs refresh interval requirement and eliminating the risk of data loss.

[0052] In one embodiment of the present invention, when the solid-state drive controller responds to a sudden surge in large data volume from the host, it postpones the execution of the current DRAM refresh operation to extend the single burst transmission time window of the DRAM, ensuring that the refresh operation is performed only after the transmission task corresponding to the burst service is fully completed, thereby maintaining the steady-state transmission performance of the solid-state drive.

[0053] When the solid-state drive controller detects a sudden surge in large data volumes from the host, it performs the following operations through the user command interface: Temporarily postpone the currently pending DRAM refresh operation to extend the single burst transfer time window of the DRAM; The transmission address mapping logic circuit is triggered to prioritize the integration of transmission requirements of the same page in the same bank in all different bank groups related to the burst of large data volume, forming a continuous transmission task adapted to the burst of large data volume. The DRAM interface is controlled to perform only read and write operations during the execution of the continuous transmission task, until all transmission tasks corresponding to the large data burst service are fully completed. After the large data burst is completed, a centralized refresh operation is performed on all bank pages involved in the transmission to meet the DRAM's timed refresh requirements and prevent data loss. In addition, the procedures for handling emergencies such as large-scale data processing are as follows: Figure 3 As shown, the exemplary execution process is as follows: If a database server initiates a 1GB sequential read request to an enterprise-grade SSD, requiring the reading of a large amount of data from the flash memory, this process requires frequent access to the "flash address mapping table" in the DDR5 DRAM (a single read operation requires multiple lookups of the mapping relationship).

[0054] Step 1: Business Surge Identification and Refresh Strategy Adjustment The SSD controller's firmware layer recognizes that the "1GB continuous read" is a burst of large data volume and immediately sends a command to the DRAM controller through the user command interface: Temporarily postpone the execution of the current DRAM refresh operation; At the same time, the transmission address mapping logic circuit is notified: relying on the characteristic of the shortest switching delay between the same bank and the same page in different bank groups, it prioritizes the integration of multiple transmission requirements of "the same bank and the same page in different bank groups" in all bank groups (such as bank groups 0~4) related to the burst read request, forming a continuous transmission task with ultra-large capacity.

[0055] Step 2: Batch activation and enabling ultra-long transmission window The DRAM controller performs a batch activation operation on the same page of the same bank in all involved bank groups according to the polling arbitration logic, and then enters the ultra-long continuous transmission phase: The SSD controller continuously reads address mapping table data from these bakn-pages, and the DRAM interface only performs pure read and write operations without any activation, precharge, or refresh operations being inserted. This phase's duration fully utilizes the extra-large transmission window created by the delayed refresh.

[0056] Step 3: Perform a refresh after the emergency service is completed. Once all address mapping queries for the 1GB sequential read request are completed (i.e., the burst service ends), the SSD controller immediately sends a command through the user command interface: Perform a centralized refresh operation on the same page of the same bank in all bank groups participating in this transmission (covering all banks that need to be refreshed); After the refresh is complete, a pre-charging operation is performed to shut down the hardware resources of these banks.

[0057] Step 4: Restore normal scheduling and self-refresh If no new services are initiated, the user command interface can trigger the DRAM self-refresh mode, allowing the DRAM to enter a low-power state.

[0058] In this process, the strategy of delaying refresh and using an ultra-long transmission window ensures that the bandwidth of 1GB burst read requests is always kept at a high level (without performance drop due to mid-process refresh), perfectly adapting to the stringent requirements for bandwidth stability during business bursts in enterprise-level scenarios; at the same time, the refresh operation executed in a concentrated manner after the burst ends also fully meets the DDR5 refresh interval specification, eliminating the risk of data loss.

[0059] In one embodiment of the present invention, such as Figure 4 As shown, a refresh device for a DDR5-based dynamic random access memory is provided, including a transfer address mapping logic circuit, which is used to integrate the transfer requirements of the same page of the same bank in different bank groups into a single continuous transfer task. The user command interface is used to control the switching of DRAM refresh modes, which are divided into DRAM self-refresh mode and normal working mode. The normal working mode refresh module is used to complete the transmission task of all the same page of the same bank in each bank group in the normal working mode. It requires one activation, one precharge and one refresh operation. During the transmission process, there are only read and write operations on the DRAM interface. The DRAM self-refresh mode module is used to ensure that the DRAM is in an idle state during the DRAM self-refresh mode, and that the DRAM enters a low-power state after the user command interface sends a command to enter the DRAM self-refresh mode.

[0060] In one embodiment of the present invention, an electronic device is provided, comprising: Memory, used to store computer programs; When a processor executes a computer program stored in the memory, it performs the steps of the method described above.

[0061] In one embodiment of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored therein, and the computer program performs the steps of the method described above when executed by a processor.

[0062] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0063] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A refresh method of a DDR5-based dynamic random access memory, characterized by, The application relates to a DRAM (Dynamic Random Access Memory) control method and device. The DRAM refresh mode is divided into a DRAM self-refresh mode and a normal working mode, and the DRAM refresh mode is switched according to a command of a user command interface of a DRAM controller. In the normal working mode, the completion of transmission tasks of all same banks and same pages in each bank group needs to be carried out once, precharged and refreshed, and only read-write operations exist on a DRAM interface during transmission. The switching between the bank groups follows a polling arbitration logic according to certain rules. In the normal working mode, the completion of transmission tasks of all same banks and same pages in each bank group needs to be carried out once, precharged and refreshed, and only read-write operations exist on a DRAM interface during transmission.

2. The DDR5-based dynamic random access memory refresh method of claim 1, wherein, When the transmission address mapping logic circuit integrates transmission requirements of same banks and same pages of different bank groups into a continuous task, the DRAM controller carries out a unified activation operation on the same banks and same pages. After the activation is completed, a continuous transmission stage is entered, the DRAM interface is responsible for transmitting the integrated read-write data, and no activation, precharge or refresh operation is inserted. When the integrated continuous transmission task is completed, the DRAM controller carries out a unified precharge operation on the same banks and same pages, closes the activated banks, releases the occupied hardware resources and lets the banks return to the activated state, thereby preparing for the next transmission. After the precharge is completed, a refresh operation is immediately carried out, a refresh command is issued for the precharged same banks and same pages, and capacitor charge is supplemented. The self-refresh function of the DRAM controller is disabled, the DRAM self-refresh mode is that, after a DRAM enters a low-power state by sending an entering DRAM self-refresh mode command through the user command interface, the DRAM enters the low-power state.

3. The DDR5-based dynamic random access memory refresh method of any one of claims 1 or 2, wherein, When the DRAM is switched from an idle state to a working state with business requirements, the user command interface first sends an exiting DRAM self-refresh mode command, so that the DRAM is woken up from the low-power state to the normal working mode, then a refresh operation is issued, the integrity of data stored in the DRAM is ensured, and then subsequent read-write transmission tasks are executed.

4. The DDR5-based dynamic random access memory refresh method of claim 3, wherein, The transmission address mapping logic circuit is arranged in a cache control unit of a solid state disk master control chip, and the size of a single continuous transmission task is determined by the access business bandwidth of the solid state disk to the DRAM when the circuit integrates transmission requirements, so as to adapt to the transmission efficiency requirement in different read-write load scenes.

5. The DDR5-based dynamic random access memory refresh method of any one of claims 1 or 2, wherein, In the normal working mode, the user command interface of the DRAM controller issues a refresh command along with a solid state disk read-write business process.

6. The DDR5-based dynamic random access memory refresh method of claim 1, wherein, ​ The refresh command is executed during DRAM transmission, and all banks or banks with the same sequence number and the same page are selected for refresh to ensure that the refresh operation does not interrupt the current transmission service and does not reduce the DRAM transmission bandwidth.

7. The DDR5-based dynamic random access memory refresh method of claim 1 or 5, wherein, In the normal working mode, the self-refresh function of the DRAM controller is disabled, and the refresh operation timing of the DRAM is completely controlled by the solid state disk master firmware through the user command interface, including the refresh command issuing interval and the refresh range selection, to avoid the conflict between the self-refresh and the service transmission.

8. The DDR5-based dynamic random access memory refresh method of claim 1, wherein, When the solid state disk master responds to the host large data burst service, the execution of the current DRAM refresh operation is delayed to expand the single burst transmission time window of the DRAM, ensure that the transmission task corresponding to the burst service is completed before the refresh operation is executed, and maintain the steady-state transmission performance of the solid state disk.

9. The DDR5-based dynamic random access memory refresh method of claim 8, wherein, When the solid state disk master identifies the large data burst service issued by the host, the following operations are performed through the user command interface: temporarily delaying the execution of the current DRAM refresh operation to expand the single burst transmission time window of the DRAM; triggering the transmission address mapping logic circuit to preferentially integrate the transmission requirements of the same bank and the same page in all different bank groups related to the large data burst service to form a continuous transmission task adapted to the large data burst service; controlling the DRAM interface to only perform read and write operations during the execution of the continuous transmission task until all transmission tasks corresponding to the large data burst service are completed; after the completion of the large data burst service, performing centralized refresh operation on all banks and pages participating in this transmission to meet the timing refresh requirement of the DRAM and avoid data loss.

10. The DDR5-based dynamic random access memory refresh method of claim 8, wherein, The identification of the large data burst service is based on at least one of the following: the amount of read and write request data issued by the host at a time exceeds a preset threshold, the frequency of read and write requests received by the solid state disk within a unit time exceeds a preset frequency threshold, and the access bandwidth of the solid state disk to the DRAM reaches a preset high load threshold.

11. A DDR5-based dynamic random access memory refresh apparatus, characterized by, It includes: a transmission address mapping logic circuit for integrating the transmission requirements of the same bank and the same page in different bank groups into a continuous transmission task; a user command interface for controlling the switching of the DRAM refresh mode, wherein the DRAM refresh mode includes a DRAM self-refresh mode and a normal working mode; a normal working mode refresh module for, in the normal working mode, performing one activation, one pre-charge and one refresh operation for each transmission task of the same bank and the same page in each bank group, and only read and write operations on the DRAM interface during transmission; a DRAM self-refresh mode module for, in the DRAM self-refresh mode, the DRAM being in an idle state, and after the user command interface sends a command to enter the DRAM self-refresh mode, the DRAM entering a low power state.

12. An electronic device, comprising: It includes: a memory for storing a computer program; a processor for executing steps of the method according to any one of claims 1 to 10 when executing a computer program stored on the memory.

13. A computer-readable storage medium, characterized in that, a computer program stored in the computer readable storage medium, the computer program being executed by a processor to perform steps of the method according to any one of claims 1 to 10.

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