Semiconductor power device and preparation method thereof

Abstract

The invention relates to a semiconductor power device and a preparation method thereof, and relates to the technical field of semiconductors, in the semiconductor power device, the depth of a gate trench is greater than the depth of a source region and less than the depth of a well region, so that the corner of a formed first gate part is surrounded by the well region, the maximum electric field intensity at the corner is reduced, and the reliability of the semiconductor power device is improved. In addition, at the moment, the first gate portion forms a side face conducting channel in the first direction, an L-shaped conducting channel is formed in the corner, surrounding the first gate portion, of the well region, the density of the conducting channel is increased, and the conduction capacity of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor power device and a method for fabricating the same. Background Technology

[0002] Silicon carbide (SiC) power devices have shown great potential in high-voltage and high-temperature power electronics applications due to their excellent material properties, such as wide bandgap, high critical electric field, high electron saturation velocity and high thermal conductivity.

[0003] While silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) can achieve higher switching speeds and lower switching losses than conventional silicon power devices, traditional SiC planar MOSFETs still exhibit relatively high specific on-resistance due to their low channel mobility. Traditional SiC trench MOSFETs, on the other hand, offer the potential for lower specific on-resistance due to the absence of a JFET region, smaller cell spacing, and higher channel mobility on the trench sidewalls. However, in the off state, SiC trench MOSFETs are subjected to a high electric field in the gate oxide at the trench corners, which can lead to reliability issues in semiconductor power devices.

[0004] Therefore, improving the reliability of semiconductor power devices has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor power device and its fabrication method to address the issue of how to improve the reliability of semiconductor power devices.

[0006] To achieve the above objectives, in one aspect, the present invention provides a semiconductor power device, comprising:

[0007] The substrate has a first type of conductivity;

[0008] An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, a doped region, and a gate trench. The drift region and the source region have a first conductivity type, and the well region and the doped region have a second conductivity type. The well regions are located within the drift regions and are spaced apart from each other in a first direction. The doped regions surround the well regions and the drift regions spaced apart along the first direction to form a cell region. The source region is located within the well regions and covers the periphery and bottom of the source region. The gate trench spans the drift regions spaced apart in the first direction and extends into the source region. In a direction perpendicular to the substrate, the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region. The first direction is parallel to the substrate.

[0009] A gate structure, the gate structure including a first gate portion located within the gate trench.

[0010] In one embodiment, the gate structure further includes:

[0011] The second gate portion covers the first gate portion and a portion of the source region on the side away from the substrate.

[0012] In one embodiment, the semiconductor power device includes at least two cell regions arranged along a second direction; the gate structure further includes:

[0013] The third gate portion is located on the side of the epitaxial structure away from the substrate. The second gate portion covers each cell region. The third gate portion extends along the second direction and connects adjacent second gate portions. The second direction is parallel to the substrate and perpendicular to the first direction.

[0014] In one embodiment, in a direction perpendicular to the substrate, the well region includes a first sub-region, a second sub-region, and a third sub-region, wherein the first sub-region is located on the side closer to the drift region, the third sub-region is located on the surface of the epitaxial structure away from the substrate, and the second sub-region is located between the first sub-region and the second sub-region.

[0015] The doping concentration of the second sub-region is greater than that of the third sub-region and the first sub-region, and the doping concentration of the third sub-region is greater than that of the first sub-region.

[0016] In one embodiment, the doping concentration ratio of the first sub-region, the second sub-region, and the third sub-region is 1:2:5.

[0017] In one embodiment, the semiconductor power device further includes:

[0018] A dielectric layer covers the side of the epitaxial structure and the gate structure away from the substrate, and exposes a portion of the doped region;

[0019] The source electrode covers the dielectric layer and a portion of the exposed doped region;

[0020] The drain is located on the side of the substrate away from the epitaxial structure.

[0021] On the other hand, this application also provides a method for fabricating a semiconductor power device, comprising:

[0022] A substrate having a first conductivity type is provided;

[0023] An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, a doped region, and a gate trench. The drift region and the source region have a first conductivity type, and the well region and the doped region have a second conductivity type. The well regions are located within the drift regions and are spaced apart from each other in a first direction. The doped regions surround the well regions and the drift regions spaced apart along the first direction to form a cell region. The source region is located within the well regions and covers the periphery and bottom of the source region. The gate trench spans the drift regions spaced apart in the first direction and extends into the source region. In a direction perpendicular to the substrate, the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region. The first direction is parallel to the substrate.

[0024] A gate structure is formed on the side of the epitaxial structure away from the substrate, the gate structure including a first gate portion located within the gate trench.

[0025] In one embodiment, forming an epitaxial structure on one side of the substrate includes:

[0026] An epitaxial layer is formed on one side of the substrate;

[0027] A first ion implantation is performed on the side of the epitaxial layer away from the substrate to form an initial well region;

[0028] A second ion implantation is performed on the side of the initial well region away from the substrate to form a source region;

[0029] A third ion implantation is performed on the side of the epitaxial layer away from the substrate to form a doped region;

[0030] The epitaxial layer located between adjacent source regions in the first direction is etched to form the gate trench, the remaining initial well region is used as the well region, and the remaining epitaxial layer is used as the drift region.

[0031] In one embodiment, the semiconductor power device includes at least two cell regions arranged along a second direction; the formation of a gate structure on the side of the epitaxial structure away from the substrate includes:

[0032] A gate oxide layer is formed on the side of the epitaxial structure away from the substrate, and the gate oxide layer covers the bottom and sidewalls of the gate trench;

[0033] A gate material layer is formed on the side of the gate oxide material layer away from the epitaxial structure, and the gate material layer fills the gate trench;

[0034] Based on the first patterned mask layer, the gate material layer and the gate oxide material layer are etched to form a gate structure. The gate structure includes a first gate portion, a second gate portion and a third gate portion. The first gate portion is connected to the second gate portion, and the third gate portion is connected to the second gate portions of two adjacent cells.

[0035] In one embodiment, after forming the gate structure on the side of the epitaxial structure away from the substrate, the method further includes:

[0036] A dielectric layer is formed on the side of the gate structure away from the epitaxial structure, and the dielectric layer exposes a portion of the doped region;

[0037] A source electrode is formed, the source electrode covering the dielectric layer and exposing a portion of the doped region in the dielectric layer;

[0038] A drain electrode is formed on the side of the substrate away from the epitaxial structure.

[0039] Compared with existing technologies, the above technical solution has the following advantages:

[0040] The semiconductor power device includes a substrate, an epitaxial structure, and a gate structure. The substrate has a first conductivity type. The epitaxial structure includes a drift region, a well region, a source region, a doped region, and a gate trench. The drift region and the source region have the first conductivity type, and the well region and the doped region have a second conductivity type. The well regions are located within the drift regions and are spaced apart from each other in a first direction. The doped regions surround the well regions and the drift regions between the well regions spaced apart along the first direction to form a cell region. The source region is located within the well regions and covers the periphery and bottom of the source region. The gate trench spans the drift regions between the well regions spaced apart in the first direction and extends into the source region. In a direction perpendicular to the substrate, the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region. The first direction is parallel to the substrate. The gate structure includes a first gate portion that fills the gate trench.

[0041] At this time, since the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region, the corner of the first gate portion is surrounded by the well region, which reduces the maximum electric field strength at the corner and significantly improves the device reliability. In addition, the first gate portion not only forms a side conductive channel in the first direction, but also forms an L-shaped conductive channel at the corner of the well region surrounding the first gate portion, which increases the density of conductive channels and improves the device's conductivity. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This application provides a schematic diagram of the structure after the initial well region is formed, as shown in the embodiment of the present application.

[0044] Figure 2 This is a schematic diagram of the structure after the source region is formed, as provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of the structure after forming a doped region and a gate trench, provided in an embodiment of this application;

[0046] Figure 4 A schematic diagram of a planar conductive channel and a side conductive channel provided for embodiments of this application;

[0047] Figure 5 This is a schematic diagram of a structure for forming a gate structure provided in an embodiment of this application;

[0048] Figure 6This is a schematic diagram of a structure for forming a dielectric layer and a source electrode, provided in an embodiment of this application.

[0049] Figure 7 This is a partial structural diagram of a gate structure sidewall provided in an embodiment of this application;

[0050] Figure 8 for Figure 6 A schematic diagram of the cross-sectional structure along DD;

[0051] Figure 9 A schematic diagram of an L-shaped conductive channel provided for an embodiment of this application;

[0052] Figure 10 This is a schematic flowchart illustrating a method for fabricating a semiconductor power device according to an embodiment of this application.

[0053] Explanation of reference numerals in the attached figures: Substrate 01; Epitaxial structure 02; Drift region 021; Well region 022; Source region 023; Doped region 024; Gate trench 025; Gate structure 03; First gate portion 031; Second gate portion 032; Third gate portion 033; Dielectric layer 04; Source 05; Side conductive channel AA; Planar conductive channel CC; L-shaped conductive channel BB; Epitaxial layer 0211; Initial well region 0221. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0056] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.

[0057] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0058] Based on the background information, in traditional single-trench SiC MOSFET device designs, a significant electric field concentration occurs at the corner of the bottom gate oxide layer during reverse breakdown, with the maximum electric field strength exceeding 5 MV / cm. A common method to address this issue is to add a P-type injection protection layer at the bottom of the trench, using the depletion region generated during reverse breakdown to protect the corner. However, this method affects the conduction path during forward conduction, increasing the forward resistance. Furthermore, if the P-type injection protection layer at the bottom of the trench lacks an effective injection shielding layer, it will significantly impact the trench channel, leading to noticeable fluctuations in device performance.

[0059] Based on this, this application provides a semiconductor power device and a method for fabricating the same. The semiconductor power device includes a substrate, an epitaxial structure, and a gate structure. The substrate has a first conductivity type. The epitaxial structure includes a drift region, a well region, a source region, a doped region, and a gate trench. The drift region and the source region have the first conductivity type, and the well region and the doped region have the second conductivity type. The well regions are located within the drift regions and are spaced apart from each other in a first direction. The doped regions surround the well regions and the drift regions spaced apart along the first direction to form a cell region. The source region is located within the well regions and covers the periphery and bottom of the source regions. The gate trench spans the drift regions spaced apart in the first direction and extends into the source region. In a direction perpendicular to the substrate, the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region. The first direction is parallel to the substrate. The gate structure includes a first gate portion that fills the gate trench.

[0060] At this time, since the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region, the corner of the first gate portion is surrounded by the well region, which reduces the maximum electric field strength at the corner and significantly improves the device reliability. In addition, the first gate portion not only forms a side conductive channel in the first direction, but also forms an L-shaped conductive channel at the corner of the well region surrounding the first gate portion, which increases the density of conductive channels and improves the device's conductivity.

[0061] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] refer to Figures 1-9 , Figures 1-9 This is a partial structural schematic diagram of the semiconductor power device formation process provided in an embodiment of this application; the semiconductor power device includes:

[0063] Substrate 01 has a first conductivity type (such as...) Figure 1 (as shown)

[0064] Epitaxial structure 02 is located on one side of substrate 01. Epitaxial structure 02 includes drift region 021, well region 022, source region 023, doped region 024, and gate trench 025. Drift region 021 and source region 023 have a first conductivity type, and well region 022 and doped region 024 have a second conductivity type. Well region 022 is located within drift region 021 and is spaced apart from adjacent well regions 022 in the first direction X. Doped region 024 is arranged around well region 022 and spaced apart along the first direction X. A drift region 021 is formed between well regions 022 to form a cell region; a source region 023 is located within the well region 022, and the well region 022 covers the periphery and bottom of the source region 023; a gate trench 025 is located across the drift region 021 between the well regions 022 spaced apart in the first direction X, and extends into the source region 023. In a direction perpendicular to the substrate 01, the depth of the gate trench 025 is greater than the depth of the source region 023 and less than the depth of the well region 022. The first direction X is parallel to the substrate 01 (e.g., ...). Figure 2 (as shown)

[0065] Gate structure 03, gate structure 03 includes a first gate portion 031, the first gate portion 031 is located within the gate trench 025 (e.g. Figure 3 (As shown).

[0066] Specifically, substrate 01 can be a Si substrate, SiC substrate, Ga2O3 substrate, GaN substrate, etc., without any specific limitation. Substrate 01 can have a first conductivity type, for example, the first conductivity type can be N-type.

[0067] The epitaxial structure 02 is located on one side of the substrate 01. The epitaxial structure 02 includes a drift region 021, a well region 022, a source region 023, a doped region 024, and a gate trench 025. Among them, the drift region 021 and the source region 023 have a first conductivity type, which can be N-type. The well region 022 and the doped region 024 have a second conductivity type, which can be P-type.

[0068] The epitaxial structure 02 may include at least one cell region, a doped region 024 surrounds the cell region to form isolation, and a cell region includes well regions 022 spaced apart in the first direction X. The well regions 022 are located on the side of the drift region 021 away from the substrate 01, and the drift region 021 is included between the two well regions 022. The source region 023 is located in the well region 022. It should be noted that in the same cell region, the well region 022 covers the periphery and bottom of the source region 023. For example, the well region 022 is extended outward by 0.4 μm relative to the source region 023 to form a conductive channel in the first direction X.

[0069] The gate trench 025 spans the drift region 021 between the well regions 022 spaced apart in the first direction X and extends into the source region 023. In the direction perpendicular to the substrate 01 (Z direction), the depth of the gate trench 025 is greater than the depth of the source region 023 and less than the depth of the well region 022. That is, the gate trench 025 exposes at least the sidewalls of the source region 023, part of the sidewalls of the well region 022, and part of the bottom of the well region 022 (e.g., ...). Figure 3 (As shown).

[0070] It should be noted that the well region 022 covers the periphery and bottom of the source region 023, and the width of the gate trench 025 in the second direction Y can be smaller than the width of the source region 023 in the second direction Y to ensure that a conductive channel can be formed. In some embodiments, the second direction Y can be parallel to the plane where the substrate 01 is located and perpendicular to the first direction X. In some embodiments, in the direction perpendicular to the substrate 01 (Z direction), the depth of the well region 022 can be 0.8 μm, and the gate trench 025 can be rectangular. In this case, the depth of the gate trench 025 can be 0.6 μm, the length is 2.8 μm, and the width is 0.6 μm, which is only for illustrative purposes.

[0071] When the gate structure 03 is formed, the first gate portion 031 fills the gate trench 025. At this time, the first gate portion 031 forms a side conductive channel AA in the first direction X (e.g., Figure 4 As shown), an L-shaped conductive channel BB is formed at the corner between the well region 022 and the source region 023 (as shown). Figure 9 (As shown).

[0072] In this embodiment, since the depth of the gate trench 025 is greater than the depth of the source region 023 and less than the depth of the well region 022, the corner of the first gate portion 031 is surrounded by the well region 022, which reduces the maximum electric field strength at the corner and significantly improves the device reliability. In addition, at this time, the first gate portion 031 not only forms a side conductive channel AA in the first direction X, but also forms an L-shaped conductive channel BB at the corner of the well region 022 surrounding the first gate portion 031, which increases the density of conductive channels and improves the conductivity of the device.

[0073] In another embodiment of this application, such as Figure 5 As shown, the gate structure 03 also includes:

[0074] The second gate portion 032 covers the side of the first gate portion 031 and a portion of the source region 023 that is away from the substrate 01.

[0075] Specifically, the second gate portion 032 has the same structure as the first gate portion 031 and can be integrally fabricated. The second gate portion 032 covers the side of the first gate portion 031 and part of the source region 023 away from the substrate 01. At this time, the second gate portion 032 is located on the upper side of the surface of the epitaxial structure 02, and a planar conductive channel CC is formed on the surface of the epitaxial structure 02.

[0076] In this embodiment, forming a second gate portion 032 further increases the conductive channel density of the semiconductor power device, thereby further increasing its conductivity.

[0077] In another embodiment of this application, such as Figure 5 As shown, the semiconductor power device includes at least two cell regions, which are arranged along the second direction Y; the gate structure 03 also includes:

[0078] The third gate portion 033 is located on the side of the epitaxial structure 02 away from the substrate 01. The second gate portion 032 covers each cell region. The third gate portion 033 extends along the second direction Y and connects to the adjacent second gate portion 032. The second direction Y is parallel to the substrate 01 and perpendicular to the first direction X.

[0079] Specifically, when a semiconductor power device includes at least two cell regions, the gate structure 03 of two adjacent cell regions can be controlled simultaneously. In this case, the second gate portion 032 covers each cell region. The gate structure 03 may also include a third gate portion 033, which extends along the second direction Y on the surface of the epitaxial structure 02 and connects to the second gate portion 032 of the adjacent cell regions to achieve simultaneous control of the gate structure 03.

[0080] It should be noted that the first gate portion 031, the second gate portion 032, and the third gate portion 033 can be integrally formed at this time.

[0081] In this embodiment, the third gate portion 033 can provide gate drive synchronization, reduce parasitic parameters of the gate structure 03, and optimize the high-frequency switching performance and reliability of the device.

[0082] In another embodiment of this application, in a direction perpendicular to the substrate 01 (Z direction), the well region 022 includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region is located on the side close to the drift region 021, the third sub-region is located on the surface of the epitaxial structure 02 away from the substrate 01, and the second sub-region is located between the first sub-region and the second sub-region.

[0083] The doping concentration of the second sub-region is greater than that of the third sub-region and the first sub-region, and the doping concentration of the third sub-region is greater than that of the first sub-region (not shown in the figure).

[0084] Specifically, because the gate structure 03 is provided with a first gate portion 031 and a second gate portion 032, the device forms a side conductive channel AA, an L-shaped conductive channel BB, and a planar conductive channel CC (e.g., Figure 4 (As shown). To ensure the proper opening of conductive channels at different locations, the doping distribution of the well region 022 can be divided into a first sub-region, a second sub-region, and a third sub-region. The first sub-region is located on the side closer to the drift region 021, the third sub-region is located on the surface of the epitaxial structure 02 away from the substrate 01, and the second sub-region is located between the first and second sub-regions. The doping concentration of the second sub-region is greater than that of the third and first sub-regions, and the doping concentration of the third sub-region is greater than that of the first sub-region. This can prevent premature punch-through of the device.

[0085] In another embodiment of this application, the doping concentration ratio of the first sub-region, the second sub-region, and the third sub-region is 1:2:1.5.

[0086] Specifically, the doping concentration ratio of the first, second, and third sub-regions can be 1:2:1.5. For example, the doping concentration of the first sub-region of well region 022 can be 1e17cm. -3 The doping concentration of the second sub-region can be 2e17cm. -3 The doping concentration of the third sub-region can be 1.5e17cm. -3 No specific limitations are imposed.

[0087] In another embodiment of this application, such as Figure 6 , Figure 7 , Figure 8 As shown, semiconductor power devices also include:

[0088] The dielectric layer 04 covers the side of the epitaxial structure 02 and the gate structure 03 away from the substrate 01, and exposes part of the doped region 024.

[0089] Source 05, covering dielectric layer 04 and exposed part of doped region 024;

[0090] The drain is located on the side of substrate 01 away from epitaxial structure 02 (not shown).

[0091] Specifically, the dielectric layer 04 can be made of silicon dioxide. The dielectric layer 04 is located on the side of the gate structure 03 away from the substrate 01, covering the gate structure 03 and preventing the gate structure 03 from contacting the subsequently formed source 05. At this time, at least part of the doped region 024 is exposed to facilitate the subsequent formation of ohmic contacts.

[0092] The source electrode 05 can be made of metal. The source electrode 05 is located on the side of the dielectric layer 04 away from the substrate 01, and covers the dielectric layer 04 and the exposed doped region 024.

[0093] The drain material can be a metal material. To form the drain, the side of the substrate 01 away from the epitaxial structure 02 can be thinned first, and then nickel can be sputtered to form an ohmic contact. After that, metals such as titanium, nickel, and silver can be used for the evaporation of the drain.

[0094] In another embodiment of this application, a method for fabricating a semiconductor power device is also provided, referring to... Figure 10 , Figure 10 This application provides a schematic flowchart of a method for fabricating a semiconductor power device; the fabrication method includes:

[0095] S10: Provides a substrate 01 having a first conductivity type (e.g., ... Figure 1 (As shown).

[0096] In this step, substrate 01 can be a Si substrate, SiC substrate, Ga2O3 substrate, GaN substrate, etc., without specific limitations. Substrate 01 can have a first conductivity type, for example, the first conductivity type can be N-type. At this time, the thickness of substrate 01 can be set to 150μm-180μm, including the endpoint values, to facilitate thinning during the fabrication of the drain electrode.

[0097] S20: An epitaxial structure 02 is formed on one side of the substrate 01 (e.g., Figure 3 (As shown).

[0098] The epitaxial structure 02 includes a drift region 021, a well region 022, a source region 023, a doped region 024, and a gate trench 025. The drift region 021 and the source region 023 have a first conductivity type, and the well region 022 and the doped region 024 have a second conductivity type. The well region 022 is located within the drift region 021 and is spaced apart from adjacent well regions 022 in the first direction X. The doped region 024 surrounds the well region 022 and the well regions 022 spaced apart along the first direction X. A drift region 021 is formed between the well regions 022 to form a cell region; a source region 023 is located within a well region 022, which covers the periphery and bottom of the source region 023; a gate trench 025 is located across the drift region 021 between the well regions 022 spaced apart in the first direction X, and extends into the source region 023. In a direction perpendicular to the substrate 01, the depth of the gate trench 025 is greater than the depth of the source region 023 and less than the depth of the well region 022. The first direction X is parallel to the substrate 01 (e.g., ...). Figure 2 (As shown).

[0099] In this step, an epitaxial structure 02 is formed on one side of the substrate 01. The required drift region 021, well region 022, source region 023 and doped region 024 can be implanted sequentially by ion implantation. The drift region 021 and source region 023 have a first conductivity type, which can be N-type. The well region 022 and doped region 024 have a second conductivity type, which can be P-type. The epitaxial structure 02 may include at least one cell region, a doped region 024 surrounds the cell region to form isolation, and a cell region includes well regions 022 spaced apart in the first direction X. The well regions 022 are located on the side of the drift region 021 away from the substrate 01, and the drift region 021 is included between the two well regions 022. The source region 023 is located in the well region 022. It should be noted that in the same cell region, the well region 022 covers the periphery and bottom of the source region 023. For example, the well region 022 is extended outward by 0.4 μm relative to the source region 023 to form a conductive channel in the first direction X.

[0100] The gate trench 025 spans the drift region 021 between the well regions 022 spaced apart in the first direction X and extends into the source region 023. In the direction perpendicular to the substrate 01 (Z direction), the depth of the gate trench 025 is greater than the depth of the source region 023 and less than the depth of the well region 022. That is, the gate trench 025 exposes at least the sidewall of the source region 023, part of the sidewall of the well region 022 and part of the bottom of the well region 022.

[0101] The well region 022 covers the periphery and bottom of the source region 023. The width of the gate trench 025 in the second direction Y can be smaller than the width of the source region 023 in the second direction Y to ensure that a conductive channel can be formed. In some embodiments, the second direction Y can be parallel to the plane where the substrate 01 is located and perpendicular to the first direction X. In some embodiments, in the direction perpendicular to the substrate 01 (Z direction), the depth of the well region 022 can be 0.8 μm, and the gate trench 025 can be rectangular. In this case, the depth of the gate trench 025 can be 0.6 μm, the length is 2.8 μm, and the width is 0.6 μm. This is only an example.

[0102] It should be noted that the depth of the gate trench 025 needs to be matched with the depth of the well region 022, so as to achieve the effect of the well region 022 surrounding the corner of the gate structure 03.

[0103] S30: A gate structure 03 is formed on the side of the epitaxial structure 02 away from the substrate 01. The gate structure 03 includes a first gate portion 031, which is located within the gate trench 025 (e.g., ...). Figure 5 (As shown).

[0104] In this step, a gate structure 03 can be formed by deposition and etching. The gate structure 03 may include a first gate portion 031, which fills a gate trench 025. At this time, the first gate portion 031 forms a side conductive channel AA in the first direction X, and an L-shaped conductive channel BB is formed at the corner between the well region 022 and the source region 023.

[0105] In this embodiment, since the depth of the gate trench 025 is greater than the depth of the source region 023 and less than the depth of the well region 022, the corner of the first gate portion 031 is surrounded by the well region 022, which reduces the maximum electric field strength at the corner and significantly improves the device reliability. In addition, at this time, the first gate portion 031 not only forms a side conductive channel AA in the first direction X, but also forms an L-shaped conductive channel BB at the corner of the well region 022 surrounding the first gate portion 031, which increases the density of conductive channels and improves the conductivity of the device.

[0106] In another embodiment of this application, an epitaxial structure 02 is formed on one side of the substrate 01, including:

[0107] An epitaxial layer 0211 is formed on one side of substrate 01 (e.g. Figure 1 (as shown)

[0108] A first ion implantation is performed on the side of the epitaxial layer 0211 away from the substrate 01 to form an initial well region 0221 (e.g., ...). Figure 1 (as shown)

[0109] A second ion implantation is performed on the side of the initial well region 0221 away from the substrate 01 to form the source region 023 (e.g., Figure 2 (as shown)

[0110] A third ion implantation is performed on the side of the epitaxial layer 0211 away from the substrate 01 to form a doped region 024;

[0111] The epitaxial layer 0211 located between adjacent source regions 023 in the first direction is etched to form a gate trench 025. The remaining initial well region 0221 serves as well region 022, and the remaining epitaxial layer 0211 serves as drift region 021 (e.g., ...). Figure 3 (As shown).

[0112] Specifically, an epitaxial layer 0211 can be formed on one side of the substrate 01. This epitaxial layer 0211 can be an N-type SiC epitaxial layer 0211 with a thickness of 11 μm and a doping concentration of 1e16 cm⁻¹. -3 No specific limitations are imposed.

[0113] Subsequently, a first ion implantation is performed on the side of the epitaxial layer 0211 away from the substrate 01 to form an initial well region 0221. The first ion implantation can be Al ion implantation. It should be noted that when performing the first ion implantation, a second patterned mask layer can be formed first, and then the epitaxial layer 0211 can be implanted based on the second patterned mask layer.

[0114] It should be noted that the initial well region 0221 can be formed into first, second, and third initial sub-regions with different concentrations through multiple directional ion implantations and stepwise annealing. In this case, the doping thickness of the initial well region 0221 can be 0.8 μm.

[0115] Subsequently, a second ion implantation is performed on the side of the initial well region 0221 away from the substrate 01 to form the source region 023. The second ion implantation can be N ion implantation. It should be noted that during the first ion implantation, a third patterned mask layer can be formed first, and then the initial well region 0221 can be implanted based on the third patterned mask layer.

[0116] At this time, in the first direction X, the source region 023 is shrunken inward relative to the initial well region 0221 to form a planar conductive channel CC on the surface of the epitaxial layer 0211. At this time, the source region 023 is shrunken inward by at least 0.2 μm relative to the initial well region 0221. For example, the source region 023 can also be shrunken inward by 0.4 μm relative to the initial well region 0221, etc. There is no specific limitation. It is only necessary to form a planar conductive channel CC.

[0117] Subsequently, a third ion implantation is performed on the side of the epitaxial layer 0211 away from the substrate 01 to form a doped region 024. The third ion implantation can be Al ion implantation. It should be noted that when performing the third ion implantation, a fourth patterned mask layer can be formed first, and then the epitaxial layer 0211 can be implanted based on the fourth patterned mask layer.

[0118] The doped region 024 formed at this point can form an ohmic contact and a depletion region during reverse breakdown. The third ion implantation can use an energy of up to 1800 keV to implant Al ions, and the doping thickness of the formed doped region 024 can be 2 μm. At this point, the surface doping concentration of the doped region 024 furthest from the substrate 01 can be 1 / 20 cm⁻¹. -3 No specific limitations are imposed.

[0119] The remaining initial well region 0221 is used as well region 022, and the remaining epitaxial layer 0211 is used as drift region 021.

[0120] Subsequently, the epitaxial layer 0211 located between adjacent source regions 023 in the first direction X is etched using plasma etching technology to form the gate trench 025.

[0121] In another embodiment of this application, the semiconductor power device includes at least two cell regions arranged along a second direction Y; a gate structure 03 is formed on the side of the epitaxial structure 02 away from the substrate 01, including:

[0122] A gate oxide layer is formed on the side of the epitaxial structure 02 away from the substrate 01, and the gate oxide layer covers the bottom and sidewalls of the gate trench 025.

[0123] A gate material layer is formed on the side of the gate oxide material layer away from the epitaxial structure 02, and the gate material layer fills the gate trench 025;

[0124] Based on the first patterned mask layer, the gate material layer and the gate oxide material layer are etched to form a gate structure 03. The gate structure 03 includes a first gate portion 031, a second gate portion 032 and a third gate portion 033. The first gate portion 031 is connected to the second gate portion 032, and the third gate portion 033 is connected to the second gate portion 032 of two adjacent cells.

[0125] Specifically, the gate structure 03 includes a gate oxide layer 034 and a gate 035. The gate oxide layer 034 can be made of silicon dioxide, and the gate 035 can be made of polysilicon. It should be noted that the first gate portion 031, the second gate portion 032, and the third gate portion 033 all include a gate oxide layer 034 and a gate 035.

[0126] When fabricating the gate oxide layer 034, a gate oxide material layer can be formed using a chemical vapor deposition process. This gate oxide material layer covers the sidewalls and bottom of the gate trench 025 and also covers the surface of the epitaxial structure 02. Then, a low-pressure chemical vapor deposition process is used to fill the gate trench 025 with the gate material layer. The gate material layer also covers the surface of the gate oxide material layer furthest from the epitaxial structure 02.

[0127] Next, a first patterned mask layer is provided. It should be noted that the first patterned mask layer can be set as needed. Then, based on the first patterned mask layer, photolithography and dry etching processes are used to remove part of the gate oxide material layer and gate material layer on the outside of the epitaxial structure 02. At this time, the remaining gate structure 03 may include a first gate portion 031, a second gate portion 032, and a third gate portion 033.

[0128] In this embodiment, the well region 022 surrounds the bottom corner of the gate trench 025, reducing the electric field strength of the gate oxide layer 034 and improving the reliability of the gate oxide layer 034. The maximum electric field strength can be reduced to below 3MV / cm.

[0129] In another embodiment of this application, after forming the gate structure 03 on the side of the epitaxial structure 02 away from the substrate 01, the method further includes:

[0130] A dielectric layer 04 is formed on the side of the gate structure 03 away from the epitaxial structure 02, and the dielectric layer 04 exposes part of the doped region 024;

[0131] A source electrode 05 is formed, which covers the dielectric layer 04 and a portion of the doped region 024 exposed by the dielectric layer 04;

[0132] A drain electrode is formed on the side of substrate 01 away from epitaxial structure 02.

[0133] Specifically, a dielectric layer 04 is formed on the side of the gate structure 03 away from the epitaxial structure 02. After the gate structure 03 is formed, a dielectric material layer (not shown) can be formed on the side of the gate structure 03 away from the epitaxial structure 02 using a chemical vapor deposition process. Then, the dielectric material layer is planarized by reflow to facilitate subsequent etching. After that, a photolithography process is used to etch and form the dielectric layer 04.

[0134] The source electrode 05 can be formed using physical vapor deposition (PVD), for example, Al metal as the source electrode 05. The source electrode 05 is located on the side of the dielectric layer 04 away from the substrate 01, and covers the dielectric layer 04 and the exposed doped region 024.

[0135] The drain material can be a metal material. To form the drain, the side of the substrate 01 away from the epitaxial structure 02 can be thinned first, and then nickel can be sputtered to form an ohmic contact. After that, metals such as titanium, nickel, and silver can be used for the evaporation of the drain.

[0136] It should be noted that the embodiments of this application do not require the introduction of additional masks and processes, and have strong compatibility.

[0137] It should be understood that, although Figure 10 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 10 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0138] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor power device, characterized by, The semiconductor power device comprises: a substrate having a first conductivity type; an epitaxial structure located on one side of the substrate, the epitaxial structure comprising a drift region, a well region, a source region, a doped region and a gate trench, the drift region and the source region having the first conductivity type, the well region and the doped region having a second conductivity type; the well region is located within the drift region and is spaced apart from the well region in a first direction; the doped region surrounds the well region and the drift region between the well regions spaced apart in the first direction to form a cell region; the source region is located within the well region, the well region surrounds the source region on all sides and the bottom; the gate trench crosses the drift region between the well regions spaced apart in the first direction and extends into the source region, and in a direction perpendicular to the substrate, the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region, the first direction being parallel to the substrate; a gate structure, the gate structure comprising a first gate portion, the first gate portion being located within the gate trench.

2. The semiconductor power device of claim 1, wherein, The gate structure further comprises: a second gate portion, the second gate portion covering the first gate portion and part of the source region away from the substrate.

3. The semiconductor power device of claim 2, wherein, The semiconductor power device comprises at least two cell regions, at least two of the cell regions being arranged in a second direction; the gate structure further comprises: a third gate portion, the third gate portion being located on a side of the epitaxial structure away from the substrate, the second gate portion covering each cell region, the third gate portion extending in the second direction and connecting adjacent second gate portions, the second direction being parallel to the substrate and perpendicular to the first direction.

4. The semiconductor power device of claim 2, wherein, In a direction perpendicular to the substrate, the well region comprises a first sub-region, a second sub-region and a third sub-region, the first sub-region being located on a side close to the drift region, the third sub-region being located on a surface of the epitaxial structure away from the substrate, the second sub-region being located between the first sub-region and the second sub-region; the doping concentration of the second sub-region is greater than the doping concentration of the third sub-region and the first sub-region, the doping concentration of the third sub-region is greater than the doping concentration of the first sub-region.

5. The semiconductor power device of claim 4, wherein, The ratio of the doping concentrations of the first sub-region, the second sub-region and the third sub-region is 1:2:1.

5.

6. The semiconductor power device of claim 1, wherein, The semiconductor power device further comprises: a dielectric layer covering a side of the epitaxial structure and the gate structure away from the substrate and exposing part of the doped region; a source electrode covering the dielectric layer and the exposed part of the doped region; a drain electrode located on a side of the substrate away from the epitaxial structure.

7. A method of manufacturing a semiconductor power device, characterized by, The semiconductor power device comprises: providing a substrate having a first conductivity type; forming an epitaxial structure on one side of the substrate, the epitaxial structure comprising a drift region, a well region, a source region, a doped region and a gate trench, the drift region and the source region having a first conductivity type, the well region and the doped region having a second conductivity type; the well region is located in the drift region and is spaced apart from the well region in a first direction; the doped region surrounds the well region and the drift region between the well regions spaced apart in the first direction to form a cell region; the source region is located in the well region, the well region covering the source region around and bottom; the gate trench across the drift region between the well regions spaced apart in the first direction and extends into the source region, and in a direction perpendicular to the substrate, the depth of the gate trench is greater than the depth of the source region and less than the depth of the well region, the first direction is parallel to the substrate; forming a gate structure on a side of the epitaxial structure away from the substrate, the gate structure comprising a first gate part, the first gate part is located in the gate trench.

8. The method of manufacturing a semiconductor power device according to claim 7, wherein The forming an epitaxial structure on one side of the substrate comprises: forming an epitaxial layer on one side of the substrate; performing a first ion implantation on a side of the epitaxial layer away from the substrate to form an initial well region; performing a second ion implantation on a side of the initial well region away from the substrate to form a source region; performing a third ion implantation on a side of the epitaxial layer away from the substrate to form a doped region; performing etching on the epitaxial layer between the source regions in the first direction to form the gate trench, the remaining initial well region as the well region, and the remaining epitaxial layer as the drift region.

9. The method of manufacturing a semiconductor power device according to claim 7, wherein The semiconductor power device comprises at least two cell regions, and the at least two cell regions are arranged along a second direction; and the forming a gate structure on a side of the epitaxial structure away from the substrate comprises: forming a gate oxide material layer on a side of the epitaxial structure away from the substrate, the gate oxide material layer covering the bottom and the sidewall of the gate trench; forming a gate material layer on a side of the gate oxide material layer away from the epitaxial structure, the gate material layer filling the gate trench; based on a first patterned mask layer, etching the gate material layer and the gate oxide material layer to form a gate structure, the gate structure comprising a first gate part, a second gate part and a third gate part, the first gate part and the second gate part are connected, and the third gate part connects the second gate parts of two adjacent cell regions.

10. The method of manufacturing a semiconductor power device according to claim 7, wherein After the forming a gate structure on a side of the epitaxial structure away from the substrate, the method further comprises: forming a dielectric layer on a side of the gate structure away from the epitaxial structure, the dielectric layer exposing part of the doped region; forming a source electrode, the source electrode covering the dielectric layer and the dielectric layer exposing part of the doped region; forming a drain electrode on a side of the substrate away from the epitaxial structure.

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