Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, the solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a first area and a second area, the first area is provided with a first tunneling passivation contact structure, and the second area is provided with a second tunneling passivation contact structure. The first region and the second region are provided with a second passivation structure, the second passivation structure on the first region is laminated on the first tunneling passivation contact structure, the height difference H1 of the surface of one side, deviating from the silicon substrate, of the second passivation structure on the first region and the second region is 0.01-8 [mu] m, and / or the height difference H1 of the surface of one side, deviating from the silicon substrate, of the second passivation structure on the first region and the second region is 0.01-8 [mu] m. And the height difference H2 of the surface of one side, facing the silicon substrate, of the second passivation structure on the first region and the second region is 0.01-8 microns. The silicon substrate can be ensured not to be damaged, the tunneling passivation contact structure on the first region is not affected, the passivation effect can be considered, parasitic absorption can be reduced, and the cell efficiency and the double-sided rate are remarkably improved while the process window is improved.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically relating to a solar cell and its preparation method. Background Technology

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international photovoltaic markets are constantly increasing, prompting industry manufacturers to focus on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells improve surface passivation performance and reduce metal contact recombination current by sequentially fabricating an ultrathin tunnel oxide layer and a doped polycrystalline silicon layer on the back of a silicon substrate, effectively increasing the cell's open-circuit voltage and short-circuit current. In recent years, the market share of TOPCon cells has risen rapidly, gradually surpassing PERC cells to become the mainstream technology for solar cells.

[0003] The back of the TOPCon cell uses a tunneling oxide layer and a doped polysilicon layer to form a tunneling passivation contact structure, which significantly improves the cell efficiency. The thicker the doped polysilicon on the back, the larger the window for metal paste burn-through, but the higher the parasitic absorption. Therefore, one of the solutions to improve the efficiency of TOPCon cells is the back polyfin structure, which reduces or completely eliminates the thickness of the doped polysilicon in the non-metallic region, thereby reducing parasitic absorption in the long wavelength range on the back. Therefore, it is necessary to control the thickness of the polysilicon in the metallic and non-metallic regions.

[0004] If the polysilicon doping layer on the back metal region is too thin, the sintering paste will penetrate the doped polysilicon, damaging the underlying tunnel oxide layer and resulting in poor passivation and low cell efficiency. If the polysilicon doping layer on the back non-metal region is too thick, parasitic absorption will be high, leading to low cell efficiency. If the polysilicon doping layer on the back non-metal region is too thin, field passivation will be poor, also resulting in low cell efficiency. Currently, the thickness of the polysilicon doped layer on the back of mass-produced TOPCon cells is generally between 100nm and 150nm, and the inability to reduce it further is mainly limited by the sintering window of the sintering paste.

[0005] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a solar cell and a method for its fabrication. Summary of the Invention

[0006] The purpose of this invention is to provide a solar cell and its preparation method, which takes into account both passivation effect and reduction of parasitic absorption, and significantly improves cell efficiency and bifaciality while improving the process window.

[0007] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0008] A solar cell includes a silicon substrate, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including a first region and a second region, the first region having a first tunneling passivation contact structure, the first region and the second region having second passivation structures, the second passivation structure on the first region being stacked on the first tunneling passivation contact structure, wherein...

[0009] The height difference H1 of the side surface of the second passivation structure facing away from the silicon substrate in the first and second regions is 0.01 μm to 8 μm, and / or the height difference H2 of the side surface of the second passivation structure facing the silicon substrate in the first and second regions is 0.01 μm to 8 μm.

[0010] In one embodiment, the second passivation structure on the second region is in contact with the second surface of the silicon substrate, the first tunneling passivation contact structure on the first region includes a tunneling layer and a second doped layer stacked sequentially, and the solar cell further includes a second electrode located on the first region and in contact with the second doped layer.

[0011] In one embodiment, the height difference H1 between the surface of the second passivation structure facing away from the silicon substrate in the first region and the second region is 0.05 μm to 8 μm or 3 μm to 6 μm; and / or,

[0012] The height difference H2 of the side surface of the second passivation structure facing the silicon substrate in the first region and the second region is 0.05μm to 8μm or 3μm to 6μm.

[0013] In one embodiment, the tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0014] The thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0015] The second doped layer is a doped polycrystalline silicon layer with a thickness of 1 nm to 150 nm or 50 nm to 100 nm; and / or,

[0016] The second doped layer has the same doping type as the silicon substrate, with a surface doping concentration of 2E20cm⁻¹. -3 ~3E21cm -3 Or 5E20cm -3 ~2E21cm -3 .

[0017] In one embodiment, the silicon substrate is recessed in the second region.

[0018] In one embodiment, the first region and the second region in the second surface of the silicon substrate are both polished surfaces after being textured and polished with a pyramid structure, and the pyramid base size in the first region is smaller than the pyramid base size in the second region.

[0019] In one embodiment, the tower base size in the first region is 3μm to 20μm, and the tower base size in the second region is 3μm to 50μm; or,

[0020] The tower base size in the first region is 8μm to 15μm, and the tower base size in the second region is 15μm to 30μm.

[0021] In one embodiment, a second tunneling passivation contact structure is provided on the second region, the second passivation structure on the second region is stacked on the second tunneling passivation contact structure, and the thickness of the second tunneling passivation contact structure is less than the thickness of the first tunneling passivation contact structure.

[0022] In one embodiment, the first region is provided with a tunneling layer, a second doped layer, a barrier layer, and a third doped layer, the second region is provided with a tunneling layer and a second doped layer, and the solar cell further includes a second electrode located in the first region and in contact with the third doped layer.

[0023] In one embodiment, the first region is provided with a tunneling layer, a second doped layer, a barrier layer, and a third doped layer, and the second region is provided with a tunneling layer and a second doped layer; or,

[0024] The first region has a tunneling layer, a second doped layer, a barrier layer, and a third doped layer; the second region has a tunneling layer, a second doped layer, a barrier layer, and a third doped layer; the thickness of the third doped layer in the second region is less than the thickness of the third doped layer in the second region; or,

[0025] The first region has a tunneling layer, at least two alternately stacked second doped layers and at least two barrier layers, and a third doped layer; the second region has a tunneling layer, at least two alternately stacked second doped layers and at least one barrier layer; or,

[0026] The first region is provided with a tunneling layer, at least two alternately stacked second doped layers and at least two barrier layers, and a third doped layer. The second region is provided with a tunneling layer, at least two alternately stacked second doped layers and at least two barrier layers, and a third doped layer. The thickness of the third doped layer in the second region is less than the thickness of the third doped layer in the second region.

[0027] In one embodiment, the height difference H1 between the surface of the second passivation structure facing away from the silicon substrate in the first region and the second region is 0.01 μm to 0.153 μm or 0.048 μm to 0.102 μm; and / or,

[0028] The height difference H2 of the side surface of the second passivation structure facing the silicon substrate in the first region and the second region is 0.01 μm to 0.153 μm or 0.048 μm to 0.102 μm.

[0029] In one embodiment, the tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0030] The thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0031] The barrier layer is any one or more combinations of silicon oxide layer and silicon carbide layer; and / or,

[0032] The thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2 nm; and / or,

[0033] The second doped layer has the same doping type as the silicon substrate, with a surface doping concentration of 1E20cm⁻¹. -3 ~9E20cm -3 Or 3E20cm -3 ~5E20cm -3 ; and / or,

[0034] The third doped layer has the same doping type as the silicon substrate, with a surface doping concentration of 2E20cm⁻¹. -3 ~3E21cm -3 Or 5E20cm -3 ~2E21cm -3 ; and / or,

[0035] The second doped layer is a doped polycrystalline silicon layer with a thickness of 1 nm to 100 nm or 1 nm to 50 nm; and / or,

[0036] The third doped layer is a doped polycrystalline silicon layer with a thickness of 1 nm to 150 nm or 50 nm to 100 nm; and / or,

[0037] The total thickness of the second and third doped layers in the first region is 50 nm to 150 nm or 60 nm to 100 nm.

[0038] In one embodiment, the first region includes a plurality of parallel and equally spaced first sub-regions, and the second region includes a plurality of parallel and equally spaced second sub-regions. The first and second sub-regions are alternately distributed, and the width of the first sub-region is 20μm to 600μm, and the width of the second sub-region is 100μm to 800μm.

[0039] In one embodiment, the second passivation structure includes one or more of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0040] In one embodiment, the second passivation structure includes a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer stacked sequentially, wherein the thickness of the silicon oxide layer is 0.1 nm to 3 nm, the thickness of the aluminum oxide layer is 3 nm to 10 nm or 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm; or,

[0041] The second passivation structure includes a silicon oxide layer and a silicon nitride layer stacked sequentially, wherein the thickness of the silicon oxide layer is 1 nm to 30 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm.

[0042] In one embodiment, a first doped layer and a first electrode in contact with the first doped layer are provided on the first surface of the silicon substrate.

[0043] In one embodiment, the doping type of the first doped layer is opposite to that of the silicon substrate, and the surface doping concentration is 1E18cm⁻¹. -3 ~5E19cm -3 The thickness is 10nm to 100nm; and / or,

[0044] A first passivation structure is stacked on the first doped layer. The first passivation structure includes an aluminum oxide layer and a silicon nitride layer stacked sequentially. The thickness of the aluminum oxide layer is 3nm to 10nm or 4nm to 8nm, and the thickness of the silicon nitride layer is 60nm to 100nm or 70nm to 90nm.

[0045] Another embodiment of the present invention provides the following technical solution:

[0046] A method for preparing a solar cell, the method comprising the following steps:

[0047] A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including a first region and a second region;

[0048] A tunneling passivation contact structure and a mask layer are fabricated on the second surface;

[0049] The mask layer on the second region is patterned and opened using laser technology;

[0050] Wet etching process is used to remove all or part of the tunneling passivation contact structure on the second region, while retaining the tunneling passivation contact structure on the first region;

[0051] Remove the mask layer on the first region to expose the tunneling passivated contact structure on the first region;

[0052] A second passivation structure is prepared on the second surface;

[0053] Wherein, the height difference H1 of the side surface of the second passivation structure facing away from the silicon substrate in the first region and the second region is 0.01μm to 8μm, and / or the height difference H2 of the side surface of the second passivation structure facing the silicon substrate in the first region and the second region is 0.01μm to 8μm.

[0054] In one embodiment, the preparation method further includes:

[0055] A pyramidal textured structure is prepared on the first and second surfaces of the silicon substrate using an alkaline texturing process, with the pyramid size ranging from 0.5 μm to 3 μm; and,

[0056] Before preparing the tunneling passivation contact structure, the second surface of the silicon substrate is polished with an alkaline solution to form several tower bases on the second surface, with tower base dimensions of 3μm to 20μm or 8μm to 15μm.

[0057] In one embodiment, the tunneling passivation contact structure includes a tunneling layer and a second doped layer stacked sequentially; the wet etching process includes:

[0058] The second doped layer, tunneling layer and part of the silicon substrate on the second region are removed by alkaline etching. After alkaline etching, the tower base size on the second region of the silicon substrate is 3μm to 50μm or 15μm to 30μm. Alternatively, all or part of the second doped layer on the second region is removed by alkaline etching.

[0059] In one embodiment, the tunneling passivation contact structure includes a tunneling layer, a second doped layer, a barrier layer, and a third doped layer stacked sequentially; the wet etching process includes:

[0060] The third doped layer on the second region is removed by alkaline etching; or, the third doped layer, the barrier layer, and at least part of the second doped layer on the second region are removed by alkaline etching.

[0061] In one embodiment, the tunneling passivation contact structure includes a tunneling layer, at least two alternately stacked second doped layers and at least two barrier layers, and a third doped layer; the wet etching process includes:

[0062] The third doped layer on the second region is removed by alkaline etching; or, the third doped layer, the outermost barrier layer, and at least part of the outermost second doped layer on the second region are removed by alkaline etching.

[0063] In one embodiment, the laser used in the laser process is a green picosecond laser or a violet picosecond laser, with a laser power of 0.3W to 25W or 0.3W to 5W, a laser frequency of 100kHz to 1000kHz or 300kHz to 600kHz, a laser scanning rate of 10000mm / s to 100000mm / s or 10000mm / s to 60000mm / s, and a laser processing number of 1 to 100 times or 1 to 10 times.

[0064] In one embodiment, the mask layer is any one or more combinations of silicon oxide, silicon oxynitride, and silicon nitride, with a thickness of 1 nm to 100 nm or 5 nm to 30 nm; and / or,

[0065] The mask layer in the first region was removed using an acid solution.

[0066] In one embodiment, preparing a second passivation structure on the second surface includes:

[0067] A silicon oxide layer and an aluminum oxide layer are deposited on the second surface using the ALD process. The silicon oxide layer is deposited at a temperature of 180℃ to 300℃ with a thickness of 0.1nm to 3nm, and the aluminum oxide layer is deposited at a temperature of 180℃ to 300℃ with a thickness of 3nm to 10nm or 4nm to 8nm. Then, a silicon nitride layer is deposited on the aluminum oxide surface using the PECVD process with a thickness of 60nm to 100nm or 70nm to 90nm; or...

[0068] A silicon oxide layer and a silicon nitride layer are deposited on the second surface using a PECVD process. The thickness of the silicon oxide layer is 0.1 nm to 3 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm.

[0069] In one embodiment, the preparation method further includes:

[0070] A first doped layer is formed on a first surface, wherein the doping type of the first doped layer is opposite to that of the silicon substrate; and,

[0071] A first electrode in contact with a first doped layer is prepared on a first surface, and a second electrode in contact with a tunneling passivation contact structure is prepared on a first region.

[0072] In one embodiment, the preparation method further includes:

[0073] A first passivation structure is prepared on a first surface of a silicon substrate. An aluminum oxide layer with a thickness of 3 nm to 10 nm or 4 nm to 8 nm is deposited on the first surface using an ALD process. Then, a silicon nitride layer with a thickness of 60 nm to 100 nm or 70 nm to 90 nm is deposited on the aluminum oxide surface using a PECVD process.

[0074] Compared with the prior art, the present invention has the following beneficial effects:

[0075] This invention removes the mask layer on the non-metallic area on the back side using laser technology, and then removes or thins the tunneling passivation contact structure on the second area on the back side using chemical etching. This ensures that the silicon substrate is not damaged and the tunneling passivation contact structure on the first area is not affected. It can balance passivation effect and reduce parasitic absorption, and significantly improve cell efficiency and bifaciality while increasing the process window.

[0076] The chemical etching process can further polish the silicon substrate on the second region, thereby increasing the height difference between the first and second regions and forming a larger tower base on the second region, thereby further improving the battery efficiency.

[0077] By introducing a barrier layer on the back of the battery, the doping concentration variation of the doped layer can be effectively improved during the laser process, avoiding damage to the tunneling layer and further improving the passivation effect. At the same time, the barrier layer has a certain ability to block the piercing of the back slurry, which helps to reduce the total thickness of the back doped layer and increase the open circuit voltage (Voc) of the battery. Attached Figure Description

[0078] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0079] Figure 1 This is a schematic diagram of the structure of the solar cell in Embodiment 1 of the present invention;

[0080] Figure 2 for Figure 1 A schematic diagram of the local structure at point M;

[0081] Figure 3 This is a planar schematic diagram of the second surface of the silicon substrate in Embodiment 1 of the present invention;

[0082] Figure 4 This is a planar schematic diagram of the second surface and the second electrode in Embodiment 1 of the present invention;

[0083] Figures 5a-5j This is a flowchart illustrating the fabrication process of the solar cell in Embodiment 1 of the present invention;

[0084] Figure 6 This is a schematic diagram of the structure of the solar cell in Embodiment 2 of the present invention;

[0085] Figure 7 for Figure 6 A schematic diagram of the local structure at point N;

[0086] Figure 8 This is a planar schematic diagram of the second surface of the silicon substrate in Embodiment 3 of the present invention;

[0087] Figure 9 for Figure 8 A partial structural diagram at point A in the middle;

[0088] Figures 10a-10j This is a flowchart illustrating the fabrication process of the solar cell in Embodiment 3 of the present invention;

[0089] Figure 11 This is a schematic diagram of the structure of the solar cell in Embodiment 4 of the present invention;

[0090] Figure 12 for Figure 11 A schematic diagram of the local structure at point B;

[0091] Figure 13 This is a schematic diagram of the structure of the solar cell in Embodiment 5 of the present invention;

[0092] Figure 14 for Figure 13 A schematic diagram of the local structure at point C;

[0093] Figure 15 This is a schematic diagram of the structure of the solar cell in Embodiment 6 of the present invention;

[0094] Figure 16 for Figure 15 A schematic diagram of the local structure at point D;

[0095] Figure 17 This is a SEM image of the pyramid-structured textured surface in Embodiment 1 of the present invention;

[0096] Figure 18 This is a SEM image of the first region on the backlight surface of the silicon substrate in Embodiment 1 of the present invention;

[0097] Figure 19 This is a SEM image of the second region on the backlight surface of the silicon substrate in Embodiment 1 of the present invention. Detailed Implementation

[0098] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0099] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0100] This invention discloses a solar cell, including a silicon substrate. The silicon substrate includes a first surface and a second surface disposed opposite to each other. The second surface includes a first region and a second region. A first tunneling passivation contact structure is provided on the first region, and a second passivation structure is provided on the first region and the second region. The second passivation structure on the first region is stacked on the first tunneling passivation contact structure. The height difference H1 of the side surface of the second passivation structure facing away from the silicon substrate on the first region and the second region is 0.01 μm to 8 μm, and / or the height difference H2 of the side surface of the second passivation structure facing the silicon substrate on the first region and the second region is 0.01 μm to 8 μm.

[0101] This invention also discloses a method for preparing a solar cell, comprising the following steps:

[0102] A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including a first region and a second region;

[0103] A tunneling passivation contact structure and a mask layer are fabricated on the second surface;

[0104] The mask layer on the second region is patterned and opened using laser technology;

[0105] Wet etching process is used to remove all or part of the tunneling passivation contact structure on the second region, while retaining the tunneling passivation contact structure on the first region;

[0106] Remove the mask layer on the first region to expose the tunneling passivated contact structure on the first region;

[0107] Prepare a second passivation structure on the second surface;

[0108] Wherein, the height difference H1 between the surfaces of the second passivation structure facing away from the silicon substrate in the first region and the second region is 0.01 μm to 8 μm, and / or, the height difference H2 between the surfaces of the second passivation structure facing the silicon substrate in the first region and the second region is 0.01 μm to 8 μm.

[0109] In the present invention, the mask layer on the back non-metal region is removed by a laser process, and then all or part of the tunneling passivation contact structure on the back non-metal region is removed by a chemical etching process, which can take into account the passivation effect and reduce parasitic absorption, and significantly improve the cell efficiency and bifaciality while increasing the process window.

[0110] The present invention will be further described below in conjunction with specific examples.

[0111] Example 1:

[0112] Refer Figure 1 、 Figure 2 The structure diagram of the solar cell in this embodiment is shown. This solar cell is a TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 which are oppositely arranged. The second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e., the backlight surface) of the silicon substrate 10, the first region S21 is the back metal region, and the second region S22 is the back non-metal region.

[0113] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0114] Furthermore, a pyramid-structured textured surface is formed on the first surface S1 of the silicon substrate 10 by alkaline texturing. The pyramid structure is in the shape of a frustum, such as a triangular frustum, a quadrangular frustum, etc. The pyramid size is defined as the average value of the width of the bottom of the frustum. For example, taking a quadrangular frustum as an example, the bottom is roughly square, and the pyramid size is the side length of this square.

[0115] In this embodiment, the pyramid size ranges from 0.5 μm to 3 μm. Refer Figure 17 The SEM image of the pyramid-structured textured surface in this embodiment is shown. The three marked pyramid sizes are 2.67 μm, 2.60 μm, and 2.75 μm respectively, and the average value of all pyramid sizes is about 2.7 μm.

[0116] Both the first region S21 and the second region S22 of the second surface S2 are polished surfaces after pyramid-structured suede polishing. Among them, in this embodiment, the silicon substrate 10 is recessed on the second region S22, and the base size of the pyramids on the first region S21 is smaller than the base size of the pyramids on the second region S22. During the alkaline polishing process, the pyramid-structured suede on the back of the silicon substrate is polished to form a base, and the base is the pedestal left after the pyramid-shaped suede is polished. The shape of the base can be triangular, quadrilateral, etc. The base size is defined as the average value of the width of the base pattern. Taking a square base as an example, the base size is the average value of the side length of the square.

[0117] Among them, the base size formed during the alkaline polishing process is larger than the pyramid size. The deeper the etching depth, the larger the base size. In this embodiment, the base size on the first region S21 is 3 μm to 20 μm, preferably 8 μm to 15 μm, and the base size on the second region is 3 μm to 50 μm, preferably 15 μm to 30 μm.

[0118] See Figure 18 Shown is the SEM image of the first region S21 in this embodiment. The marked base sizes are 11.37 μm, 11.52 μm, 11.44 μm, 11.53 μm, 11.13 μm respectively. The average size of the bases on the first region S21 is about 11.4 μm. See Figure 19 Shown is the SEM image of the second region S22 in this embodiment. The etching depth of the second region S22 is deeper, and the formed base size is larger. As shown by the marked base sizes of 20.30 μm, 20.23 μm, 19.29 μm respectively, the average size of the bases on the second region S22 is about 20 μm.

[0119] In this embodiment, a first doped layer 11 is formed on the first surface S1 of the silicon substrate 10 by diffusion process or PECVD process. Exemplarily, the first doped layer 11 is a P-type doped layer (i.e., P+ emitter) formed by boron doping process, with a doping concentration of 1E18 cm -3 ~5E19 cm -3 , and the sheet resistance is 100 Ω / sq to 500 Ω / sq, preferably 200 Ω / sq to 400 Ω / sq.

[0120] See Figure 1 And in combination with Figure 2 Shown, on the first region S21 of the second surface S2 of the silicon substrate 10 in this embodiment, a first tunneling passivation contact structure is provided, and the first tunneling passivation contact structure includes a tunneling layer 12 and a second doped layer 13 stacked in sequence.

[0121] Among them, the tunneling layer 12 is a silicon oxide (SiO X ) layer, a silicon oxynitride (SiO X NY The second doped layer 13 is a combination of one or two of the following layers, preferably a silicon oxide layer with a thickness of 0.5 nm to 3 nm, more preferably 1.5 nm to 2.5 nm; the second doped layer 13 is a phosphorus-doped polycrystalline silicon layer with a doping concentration of 2E20cm⁻¹. -3 ~3E21cm -3 The preferred size is 5E20cm. -3 ~2E21cm -3 The thickness is 1nm to 150nm, preferably 50nm to 100nm.

[0122] In addition, in this embodiment, a first passivation structure and a second passivation structure are respectively stacked on the first surface S1 and the second surface S2 of the silicon substrate.

[0123] Specifically, the first passivation structure is stacked on the first doped layer 11, comprising sequentially stacked aluminum oxide (SiO2). X Layer 21 and silicon nitride (SiN) X The aluminum oxide layer 21 has a thickness of 3nm to 10nm, preferably 4nm to 8nm, and the silicon nitride layer 31 has a thickness of 60nm to 100nm, preferably 70nm to 90nm.

[0124] The second passivation structure is stacked on the surface of the second region S22 and the second doped layer 13, including silicon oxide (SiO2). X ) layer, aluminum oxide (AlO) X ) layer and silicon nitride (SiO) X One or more layers of a combination of layers. For example, in this embodiment, the second passivation structure includes sequentially stacked silicon oxide (SiO2) layers. X Layer 22 and silicon nitride (SiO) X Layer 32, wherein the thickness of the silicon oxide layer is 1nm to 30nm, and the thickness of the silicon nitride layer is 60nm to 100nm, preferably 70nm to 90nm.

[0125] Since the silicon substrate 10 is recessed in the second region S22 in this embodiment, there is a height difference between the first region S21 and the second region S22. Figure 2 As shown, the height difference between the surface of the second passivation structure facing away from the silicon substrate (i.e., the outer surface of the silicon nitride layer 32) in the first region S21 and the second region S22 is H1, and the height difference between the surface of the second passivation structure facing the silicon substrate (i.e., the inner surface of the silicon oxide layer 22) in the first region S21 and the second region S22 is H2.

[0126] In the first region S21, a tunneling layer 12 and a second doping layer 13 are stacked. Therefore, the height difference H2 is the sum of the depression depth of the second region S22 and the thicknesses of the tunneling layer 12 and the second doping layer 13, and its value is 0.05 μm to 8 μm, preferably 3 μm to 6 μm. For example, in this embodiment, the sum of the thicknesses of the tunneling layer 12 and the second doping layer 13 is about 100 nm (0.1 μm), the height difference H2 is about 4 μm, and the depression depth of the second region S22 is about 3.9 μm.

[0127] In this embodiment, the silicon oxide layer 22 and the silicon nitride layer 32 are deposited on the front side by the PECVD process. Therefore, the silicon oxide layer 22 and the silicon nitride layer 32 on the first region S21 and the second region S22 have equal thicknesses, and thus the height difference H1 is equal to the height difference H2. In other embodiments, when the thicknesses of the second passivation structures on the first region S21 and the second region S22 are not equal, the height difference H1 and the height difference H2 are also not equal.

[0128] In another embodiment of the present invention, the second passivation structure includes a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer stacked in sequence. Among them, the thickness of the silicon oxide layer is 0.1 nm to 3 nm, the thickness of the aluminum oxide layer is 3 nm to 10 nm, preferably 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0129] In addition, in this embodiment, the first electrode 41 is located on the first surface S1 of the silicon substrate 10 and is in contact with the first doping layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically in the first region S21 of the second surface S2, and is in contact with the second doping layer 13.

[0130] Refer Figure 3 As shown, the first region S21 in this embodiment includes a plurality of first sub-regions 101 that are parallel and equally spaced apart, the second region S22 includes a plurality of second sub-regions 102 that are parallel and equally spaced apart, and the first sub-regions 101 and the second sub-regions 102 are交错分布. The width of the first sub-region 101 is less than the width of the second sub-region 102. For example, the width ratio between the two can be 1:(5 to 20). Preferably, the width of the first region S21 is 20 μm to 600 μm, and the area of the first region S21 accounts for about 10% of the area of the entire second surface S2.

[0131] Combined Figure 4 As shown, the second electrode 42 is a gate line electrode, which at least includes a plurality of parallel and distributed thin gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the thin gate lines 421. Optionally, the second electrode 42 may further include a plurality of main gate lines (not shown) that are perpendicular to the thin gate lines 421.

[0132] Taking the 210 TOPCon cell as an example, the cell size is 203.396 ± 15 mm, the number of fine grid lines 421 is 230, the width is 15 μm to 100 μm, and the distance between adjacent fine grid lines is 0.907 ± 0.015 mm. The distance between adjacent first sub-regions 101 is equal to the distance between adjacent fine grid lines. One fine grid line 421 is distributed on each first sub-region 101, and the width of the first sub-region 101 is greater than the width of the fine grid line 421. The width of the first sub-region is 50 μm to 150 μm. For example, if the width of the fine grid line is 40 μm, the width of the first sub-region is 80 μm.

[0133] The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0134] 1. Double-sided texturing

[0135] Refer Figure 5a As shown, a silicon substrate 10 is provided. The silicon substrate includes a first surface S1 and a second surface S2 arranged oppositely. The second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e., the backlight surface) of the silicon substrate 10, the first region S21 is the back metal region, and the second region S22 is the back non-metal region.

[0136] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0137] Refer Figure 5b As shown, a pyramid-structured textured surface is formed on the first surface S1 and the second surface S2 of the silicon substrate 10 in this embodiment by an alkaline texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0138] 2. Boron diffusion

[0139] Refer Figure 5c As shown, a first doped layer (i.e., P+ emitter) 11 doped with P-type is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, diffusion is carried out in a high-temperature furnace tube by a boron source deposition and propulsion method. After diffusion, the doping concentration of the first doped layer is 1E18 cm -3 ~5E19 cm -3 , the sheet resistance is 100 Ω / sq to 500 Ω / sq, preferably 200 Ω / sq to 400 Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0140] In other embodiments, the first doping layer 11 can also be prepared by PECVD process. First, a boron-doped amorphous silicon layer with a thickness of 10 nm to 100 nm is deposited on the first surface S1 by PECVD process, and then a P-type doped polysilicon layer is formed after high-temperature oxidation annealing.

[0141] 3. Backside polishing

[0142] As shown in the figure Figure 5d The silicon substrate after boron diffusion is first passed through a single-sided chain equipment, and the backside silicon oxide is removed by hydrofluoric acid solution, and then the backside is polished with alkali to remove the edge junction and backside plating (BSG), and finally cleaned.

[0143] During the alkali polishing process, the pyramid-shaped texture on the backside of the silicon substrate is polished to form a pedestal, which is the pedestal left after the pyramid-shaped texture is polished. In this embodiment, the size of the pedestal on the backside of the silicon substrate after alkali polishing is 3 μm to 20 μm, preferably 8 μm to 15 μm.

[0144] 4. Preparation of backside tunneling passivation contact structure

[0145] As shown in the figure Figure 5e A tunneling layer 12, a second doping layer 13 and a mask layer 15 are sequentially stacked on the second surface S2.

[0146] Exemplarily, in this embodiment, a silicon oxide tunneling layer with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm, is deposited on the backside by PECVD process;

[0147] Then a phosphorus-doped amorphous silicon layer is deposited by PECVD process, with a doping concentration of 2E20 cm -3 ~3E21 cm -3 , preferably 5E20 cm -3 ~2E21 cm -3 , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm;

[0148] Finally, a mask layer 15 is deposited, which is any one or a combination of a silicon oxide (SiO X ), silicon oxynitride (SiO X N Y ), and silicon nitride (SiN X ) layer, with a thickness of 1 nm to 100 nm, preferably 5 nm to 30 nm.

[0149] 5. Annealing

[0150] The silicon substrate with a tunneling passivation contact structure deposited on the back surface is placed in a high-temperature annealing furnace for high-temperature annealing. The annealing temperature is 850°C to 950°C, preferably 890°C to 920°C. During the annealing process, phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0151] 6. Laser opening of the mask

[0152] Refer Figure 5f As shown, a laser process is used to perform pattern opening of the mask layer 15 on the second region (non-metal region) S22.

[0153] The energy required for laser opening of the mask is affected by the thickness of the mask layer. In this embodiment, the laser can be a green picosecond laser or a violet picosecond laser. The laser power is 0.3W to 25W, preferably 0.3W to 5W. The laser frequency is 100kHz to 1000kHz, preferably 300kHz to 600kHz. The laser scanning rate is 10000mm / s to 100000mm / s, preferably 10000mm / s to 60000mm / s. The number of laser processing times is 1 to 100 times, preferably 1 to 10 times.

[0154] 7. Wet etching

[0155] Refer Figure 5g As shown, a wet etching process is used to remove the second doping layer 13, the tunneling layer 12, and a part of the silicon substrate 10 on the second region S22, and the tunneling layer 12 and the second doping layer 13 on the first region S21 are retained.

[0156] First, hydrofluoric acid is used to remove the front surface and edge PSG;

[0157] Then, an alkali etching process is used to remove the front surface and edge plating, as well as the tunneling layer 12, the second doping layer 13, and a part of the silicon substrate 10 on the second region S22. The etching solution composition is sodium hydroxide / potassium hydroxide + additive + pure water. The etching temperature is 50°C to 90°C, preferably 60°C to 80°C. The etching time is 100s to 500s, preferably 200s to 300s. The base size on the second region of the silicon substrate after alkali etching is 3μm to 50μm, preferably 15μm to 30μm;

[0158] Finally, hydrofluoric acid is used to remove the front surface BSG and the mask layer 15 on the back surface first region S21, and RCA cleaning is performed.

[0159] After the wet etching process, the height difference between the surface of the second doping layer 13 away from the silicon substrate and the second surface in the second region S22 is 0.05μm to 8μm, preferably 3μm to 6μm.

[0160] 8. Preparation of the first passivation structure

[0161] As shown Figure 5h first, an alumina layer 21 is deposited on the first surface by ALD process, with a thickness of 3 nm to 10 nm, preferably 4 nm to 8 nm, and then a silicon nitride layer 31 is deposited on the alumina surface by PECVD process, with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0162] 9. Preparation of the second passivation structure

[0163] As shown Figure 5i first, a silicon oxide layer 22 and a silicon nitride layer 32 are deposited on the surface of the second region and the second doped layer by PECVD process. The thickness of the silicon oxide layer 22 is 0.1 nm to 3 nm, and the thickness of the silicon nitride layer 32 is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0164] In other embodiments, a silicon oxide layer and an alumina layer can also be deposited on the surface of the second region S22 and the second doped layer 13 by ALD process first. During the deposition of the silicon oxide layer, H2O is introduced, the deposition temperature is 180 °C to 300 °C, and the thickness is 0.1 nm to 3 nm. During the deposition of the alumina layer, TMA and H2O are introduced, the deposition temperature is 180 °C to 300 °C, and the thickness is 3 nm to 10 nm, preferably 4 nm to 8 nm. Then, a silicon nitride layer is deposited on the alumina surface by PECVD process, with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0165] It should be understood that in this embodiment, when the second passivation structure is prepared on the surface of the second region S22 and the second doped layer 13, the second passivation structure will be formed synchronously on the sidewalls of the tunneling layer 12 and the second doped layer 13 during the deposition process. The thickness of the second passivation structure on the sidewalls (about 90 nm) is much smaller than the width of the tunneling layer 12 and the second doped layer 13 (20 μm to 600 μm).

[0166] 10. Printing metal electrodes

[0167] As shown Figure 5j first, the first electrode 41 and the second electrode 42 are printed on the front and back surfaces respectively by screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form an ohmic contact.

[0168] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, usually including main gate lines and fine gate lines. It should be noted that since the fine gate lines in the second electrode 42 need to be printed on the first region, the width of the first sub-region needs to be greater than the width of the fine gate lines in the second electrode 42, so as to achieve the alignment of the fine gate lines.

[0169] The TOPCon cell can be prepared through the above steps, and finally, the cell wafers are tested, sorted, and stored in the warehouse.

[0170] Example 2:

[0171] Refer Figure 6 、 Figure 7 The structure schematic diagram of the solar cell in this example is shown. The structure and preparation process of the solar cell in this example are roughly the same as those in the example. The differences are as follows:

[0172] In this example, the first region S21 and the second region S22 on the second surface S2 of the silicon substrate 10 are flush. The tower base sizes on both regions are 3 μm to 20 μm, preferably 8 μm to 15 μm. Thus, the height differences H1 and H2 on the first region S21 and the second region S22 are both the sum of the thicknesses of the tunneling layer 12 and the second doping layer 13, and the value is preferably 0.05 μm to 0.1 μm.

[0173] Correspondingly, in the preparation method of the solar cell in this example, in the alkali etching process of the wet etching process, by controlling the process parameters, only the second doping layer 13 on the second region S22 is removed, and the silicon substrate 10 is not removed. In addition, when the mask layer is removed by hydrofluoric acid, the tunneling layer 12 on the second region S22 is removed synchronously.

[0174] Example 3:

[0175] Refer Figure 8 、 Figure 9 The structure schematic diagram of the solar cell in this example is shown. This solar cell is a TOPCon cell. The structure of the silicon substrate 10 and its first surface S1 (i.e., the front or light-receiving surface) is exactly the same as that in the example, and will not be elaborated here.

[0176] Different from Example 1, in this example, a first tunneling passivation contact structure and a second tunneling passivation contact structure are respectively provided on the first region S21 and the second region S22 on the second surface S2 of the silicon substrate 10.

[0177] The first tunneling passivation contact structure above the first region S21 includes a tunneling layer 12, a layer of second doping layer 131, a layer of blocking layer 14, and a third doping layer 132 stacked in sequence. Specifically, the tunneling layer 12 is a layer of silicon oxide (SiO X ) layer, a layer of silicon oxynitride (SiO X N Y ) layer, or a combination of one or two of them, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; the blocking layer 14 is a layer of silicon oxide (SiO X ) layer, a silicon carbide layer, or a combination of one or two of them, preferably a silicon oxide (SiOX The layer has a thickness of 0.5nm to 3nm, preferably 1.5nm to 2nm.

[0178] In this embodiment, the doping type of the second doped layer 131 and the third doped layer 132 is the same as the doping type of the silicon substrate. Preferably, the surface doping concentration of the third doped layer 132 is greater than the surface doping concentration of the second doped layer 131. At the same time, the thickness of the third doped layer 132 is greater than the thickness of the second doped layer 131. The total thickness of the second doped layer 131 and the third doped layer 132 is 50nm to 150nm, preferably 60nm to 100nm.

[0179] For example, in this embodiment, the second doped layer 131 is a phosphorus-doped polycrystalline silicon layer with a surface doping concentration of 1E20cm⁻¹. -3 ~9E20cm -3 The preferred size is 3E20cm. -3 ~5E20cm -3 The thickness is 1nm to 100nm, preferably 1nm to 50nm; the third doped layer 132 is a phosphorus-doped polycrystalline silicon layer with a surface doping concentration of 2E20cm⁻¹. -3 ~3E21cm -3 The preferred size is 5E20cm. -3 ~2E21cm -3 The thickness is 1nm to 150nm, preferably 50nm to 100nm.

[0180] The second tunneling passivation contact structure above the second region S22 includes a tunneling layer 12 and a second doped layer 131 stacked sequentially. The tunneling layer 12 and the second doped layer 131 are exactly the same as the tunneling layer 12 and the second doped layer 131 on the first region S21, and will not be described again here.

[0181] In this embodiment, a first passivation structure and a second passivation structure are respectively stacked on the first surface S1 and the second surface S2 of the silicon substrate 10. The first passivation structure and the second passivation structure are exactly the same as those in Embodiment 1, and will not be described again here.

[0182] In addition, in this embodiment, the first electrode 41 is located on the first surface S1 of the silicon substrate 10 and is in contact with the first doped layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically in the first region S21 of the second surface S2 and is in contact with the third doped layer 132.

[0183] Since in this embodiment, the first region S21 and the second region S22 are respectively provided with a first tunneling passivation contact structure and a second tunneling passivation contact structure, and the heights of the two tunneling passivation contact structures are different, the height differences H1 and H2 on the first region S21 and the second region S22 are both the sum of the thicknesses of the third doping layer 132 and the blocking layer 14, and the value is 0.01 μm to 0.153 μm, that is, 10 nm to 153 nm, preferably 0.048 μm to 0.102 μm, that is, 48 nm to 102 nm. In this embodiment, when the thickness of the blocking layer 14 is 2 nm and the thickness of the third doping layer 132 is 98 nm, the height differences H1 and H2 are both 100 nm.

[0184] The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0185] 1. Double-sided texturing

[0186] Refer Figure 10a As shown, a silicon substrate 10 is provided. The silicon substrate includes a first surface S1 and a second surface S2 arranged oppositely. The second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e., the backlight surface) of the silicon substrate 10, the first region S21 is the back metal region, and the second region S22 is the back non-metal region.

[0187] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0188] Refer Figure 10b As shown, the first surface S1 and the second surface S2 of the silicon substrate 10 in this embodiment are formed with a pyramid-structured matte surface through an alkaline texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0189] 2. Boron diffusion

[0190] Refer Figure 10c As shown, a P-type doped first doping layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 through a boron diffusion process. Specifically, diffusion is carried out by using a boron source deposition and propulsion method in a high-temperature furnace tube. After diffusion, the doping concentration of the first doping layer is 1E18 cm -3 ~5E19 cm -3 , the sheet resistance is 100 Ω / sq to 500 Ω / sq, preferably 200 Ω / sq to 400 Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0191] In other embodiments, the first doping layer 11 can also be prepared by PECVD process. First, a boron-doped amorphous silicon layer with a thickness of 10 nm to 100 nm is deposited on the first surface S1 by PECVD process, and then a P-type doped polycrystalline silicon layer is formed after high-temperature oxidation annealing.

[0192] 3. Backside polishing

[0193] As shown Figure 10d in the figure, the silicon substrate after boron diffusion is first passed through a single-sided chain equipment, the backside silicon oxide is removed by using hydrofluoric acid solution, and then the backside is polished with alkali to remove the edge junction and backside plating (BSG), and finally cleaned.

[0194] During the alkali polishing process, the pyramid-shaped texture on the backside of the silicon substrate is polished to form a pedestal, which is the pedestal left after polishing the pyramid-shaped texture. In this embodiment, the size of the pedestal on the backside of the silicon substrate after alkali polishing is 3 μm to 20 μm, preferably 8 μm to 15 μm.

[0195] 4. Preparation of backside tunneling passivation contact structure

[0196] As shown Figure 10e in the figure, a tunneling layer 12, a second doping layer 131, a barrier layer 14, a third doping layer 132 and a mask layer 15 are sequentially stacked on the second surface S2.

[0197] Exemplarily, in this embodiment, a silicon oxide tunneling layer with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm, is deposited on the backside by PECVD process;

[0198] then a phosphorus-doped amorphous silicon layer with a surface doping concentration of 1E20 cm -3 to 9E20 cm -3 , preferably 3E20 cm -3 to 5E20 cm -3 , and a thickness of 1 nm to 100 nm, preferably 1 nm to 50 nm, is deposited by PECVD process;

[0199] then a silicon oxide barrier layer with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2 nm, is deposited by PECVD process;

[0200] then a phosphorus-doped amorphous silicon layer with a surface doping concentration of 2E20 cm -3 to 3E21 cm -3 , preferably 5E20 cm -3 to 2E21 cm -3 , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm, is deposited by PECVD process;

[0201] Finally, a mask layer is deposited again. The mask layer is any one or a combination of multiple layers of silicon oxide (SiO X ), silicon oxynitride (SiO X N Y ), and silicon nitride (SiN X ). The thickness is 1 nm to 100 nm, preferably 5 nm to 30 nm.

[0202] 5. Annealing

[0203] The silicon substrate with the tunneling passivation contact structure deposited on the back is placed in a high-temperature annealing furnace for high-temperature annealing. The annealing temperature is 850 °C to 950 °C, preferably 890 °C to 920 °C. During the annealing process, phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0204] 6. Laser film opening

[0205] As shown in Figure 10f , a laser process is used to perform pattern film opening on the mask layer 15 in the second region (non-metal region) S22.

[0206] The energy required for laser film opening is affected by the thickness of the mask layer. In this embodiment, the laser can be a green picosecond laser or a violet picosecond laser. The laser power is 0.3 W to 25 W, preferably 0.3 W to 5 W. The laser frequency is 100 kHz to 1000 kHz, preferably 300 kHz to 600 kHz. The laser scanning rate is 10000 mm / s to 100000 mm / s, preferably 10000 mm / s to 60000 mm / s. The number of laser processing times is 1 to 100 times, preferably 1 to 10 times.

[0207] 7. Wet etching

[0208] As shown in Figure 10g , a wet etching process is used to remove the third doped layer 132 and the barrier layer 14 in the second region S22, and the third doped layer 132 and the barrier layer 14 in the first region S21 are retained.

[0209] First, hydrofluoric acid is used to remove the front and edge PSG;

[0210] Then, an alkali etching process is used to remove the front and edge plating and the third doped layer 132 in the second region S22. The etching solution composition is sodium hydroxide / potassium hydroxide + additive + pure water;

[0211] Finally, hydrofluoric acid is used to remove the front BSG, the mask layer on the back first region S21, and the barrier layer 14 in the second region S22, and RCA cleaning is performed.

[0212] After the wet etching process, the height difference between the surface of the third doping layer 132 away from the silicon substrate in the first region S21 and the surface of the second doping layer 131 away from the silicon substrate in the second region S22 is 0.01 μm to 0.153 μm, that is, 10 nm to 153 nm.

[0213] 8. Preparation of the first passivation structure

[0214] Refer Figure 10h As shown, first, an alumina layer 21 with a thickness of 3 nm to 10 nm, preferably 4 nm to 8 nm, is deposited on the first surface by ALD process, and then a silicon nitride layer 31 with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm, is deposited on the surface of the alumina by PECVD process.

[0215] 9. Preparation of the second passivation structure

[0216] Refer Figure 10i As shown, first, a silicon oxide layer 22 and a silicon nitride layer 32 are deposited on the surfaces of the first region S21 and the second region S22 by PECVD process. The thickness of the silicon oxide layer 22 is 0.1 nm to 3 nm, and the thickness of the silicon nitride layer 32 is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0217] In other embodiments, a silicon oxide layer and an alumina layer can also be deposited on the surfaces of the first region S21 and the second region S22 by ALD process. During the deposition of the silicon oxide layer, H2O is introduced, the deposition temperature is 180 °C to 300 °C, and the thickness is 0.1 nm to 3 nm. During the deposition of the alumina layer, TMA and H2O are introduced, the deposition temperature is 180 °C to 300 °C, and the thickness is 3 nm to 10 nm, preferably 4 nm to 8 nm. Then, a silicon nitride layer is deposited on the surface of the alumina by PECVD process, and the thickness is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0218] It should be understood that in this embodiment, when the second passivation structure is prepared on the surfaces of the first region S21 and the second region S22, the second passivation structure will be formed synchronously on the sidewalls of the first tunneling passivation contact structure. The thickness of the second passivation structure on the sidewalls (about 90 nm) is much smaller than the width of the first tunneling passivation contact structure (20 μm to 600 μm).

[0219] 10. Printing metal electrodes

[0220] Refer Figure 10j As shown, the first electrode 41 and the second electrode 42 are printed on the front and back surfaces respectively by screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form ohmic contacts.

[0221] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, usually including main gate lines and fine gate lines. It should be noted that since the fine gate lines in the second electrode 42 need to be printed on the first region, the width of the first sub-region needs to be greater than the width of the fine gate lines in the second electrode 42, so that the alignment of the fine gate lines can be achieved.

[0222] Through the above steps, the TOPCon battery can be prepared, and finally the battery wafers are tested, sorted and stored in the warehouse.

[0223] Example 4:

[0224] Refer Figure 11 and in combination with Figure 12 As shown, the solar cell in this embodiment is substantially the same as that in Example 3. The difference is that on the second region S22 of the second surface S2 of the silicon substrate 10 in this embodiment, a tunneling layer 12, a layer of second doping layer 131, a layer of blocking layer 14, and a third doping layer 132' are sequentially stacked. The tunneling layer 12, the second doping layer 131, and the blocking layer 14 on the second region S22 are exactly the same as those on the first region S21. The thickness of the third doping layer 132' is less than the thickness of the third doping layer 132.

[0225] The preparation method of the solar cell in this embodiment is also substantially the same as that in Example 3. The difference is that the wet etching step in Step 7 is different. In this embodiment, an alkali etching process is used to remove part of the third doping layer on the second region S22 and the mask layer on the first region S21, and the third doping layer 132 on the first region S21 is retained. By controlling the parameters of the alkali etching process, the third doping layer on the second region S22 is thinned rather than completely removed.

[0226] In this embodiment, since part of the third doping layer 132' on the second region S22 is retained, when the pickling process is carried out, the acid solution will not corrode the blocking layer 14 on the second region S22. Therefore, the blocking layer 14 and part of the third doping layer 132' are retained on the second region.

[0227] Corresponding to the thickness ranges of the blocking layer 14 and the third doping layer 132 in Example 3, the height differences H1 and H2 between the first region S21 and the second region S22 are both the height difference between the third doping layers 132 and 132', and its value is less than the thickness of the third doping layer 132, which is 0.01 μm to 0.149 μm, that is, 10 nm to 149 nm, preferably 0.05 μm to 0.09 μm, that is, 50 nm to 90 nm.

[0228] Exemplarily, in this embodiment, the thickness of the blocking layer 14 on the first region S21 is about 2 nm, the thickness of the third doping layer 132 is 100 nm, and the thickness of the remaining side third doping layer 132' on the second region S22 is about 40 nm. Then, the height differences H1 and H2 between the first region S21 and the second region S22 are about 60 nm (i.e., 0.06 μm).

[0229] Embodiment 5:

[0230] Refer Figure 13 and in combination with Figure 14 as shown, the solar cell in this embodiment is substantially the same as that in Embodiment 3, except that an alternating stack of a second doping layer 131 and a blocking layer 14 is provided on the tunneling layer 11 of the second surface S2 of the silicon substrate 10 in this embodiment.

[0231] Specifically, on the first region S21 of the second surface S2 of the silicon substrate 10 in this embodiment, a tunneling layer 12, a second doping layer 131, a blocking layer 14, a second doping layer 131, a blocking layer 14, and a third doping layer 132 are sequentially stacked. On the second region S22 of the second surface S2 of the silicon substrate 10, a tunneling layer 12, a second doping layer 131, a blocking layer 14, and a second doping layer 131 are sequentially stacked.

[0232] The preparation method of the solar cell in this embodiment is also substantially the same as that in Embodiment 3, except that the wet etching step in Step 7 is different. In this embodiment, an alkaline etching is used to remove the third doping layer 132 on the second region S22, and an acid solution is used to remove the outermost blocking layer 14 on the second region S22 and the mask layer on the first region S21.

[0233] Similar to Embodiment 3, the height differences H1 and H2 between the first region S21 and the second region S22 in this embodiment depend on the thickness ranges of the third doping layer 132 and the outermost blocking layer 14, which will not be elaborated here.

[0234] Embodiment 6:

[0235] Refer Figure 15 and in combination with Figure 16 as shown, the solar cell in this embodiment is substantially the same as that in Embodiment 5, except that on the second region S22 of the second surface S2 of the silicon substrate 10 in this embodiment, a tunneling layer 12, a second doping layer 131, a blocking layer 14, a second doping layer 131, a blocking layer 14, and a third doping layer 132' are sequentially stacked, and the thickness of the third doping layer 132' is less than the thickness of the third doping layer 132 on the first region S21.

[0236] The fabrication method of the solar cell in this embodiment is roughly the same as that in Embodiment 5, except that the wet etching step in step 7 is different. In this embodiment, an alkaline etching process is used to remove part of the third doped layer on the second region S22 and the mask layer on the first region S21, while retaining the third doped layer 132 on the first region S21. By controlling the parameters of the alkaline etching process, the third doped layer on the second region S22 is thinned, rather than completely removed.

[0237] In this embodiment, since part of the third doped layer 132' on the second region S22 is retained, the acid solution will not corrode the barrier layer 14 on the second region S22 during the acid washing process. Therefore, the barrier layer 14 and part of the third doped layer 132' are retained on the second region.

[0238] Similar to Example 4, the height differences H1 and H2 between the first region S21 and the second region S22 in this example depend on the thickness range of the third doped layer 132 and the outermost barrier layer 14, which will not be described in detail here.

[0239] Based on the existing TOPCon battery structure, this invention deposits a tunneling passivation contact structure and a mask layer on the back side, then uses a laser process to pattern the second region (non-metallic region) and then uses a wet etching process to remove or thin the tunneling passivation contact structure on the second region (non-metallic region), providing a new solution for improving the efficiency of TOPCon batteries.

[0240] The main deposition methods for polysilicon (PECVD) are LPCVD and PECVD. Considering production capacity and the cost of quartz components, PECVD is more suitable for mass production. However, compared to LPCVD, the mask on the outer layer of PE polysilicon requires higher energy to open. Laser processes can remove the mask in non-metallic areas and the underlying polysilicon. However, as laser power increases, the degree to which the back mask is opened changes from completely unable to open → a loose mask structure → complete mask vaporization → mask + partial polysilicon vaporization. At a certain power level, this can damage the silicon substrate, thereby reducing cell efficiency.

[0241] This invention removes the mask layer on the non-metallic area on the back side using laser technology, and then removes or thins the tunneling passivation contact structure on the second area on the back side using chemical etching. This ensures that the silicon substrate is not damaged and the tunneling passivation contact structure on the first area is not affected. It can balance passivation effect and reduce parasitic absorption, and significantly improve cell efficiency and bifaciality while increasing the process window.

[0242] In Example 1, the chemical etching process can further polish the silicon substrate on the second region, thereby increasing the height difference between the first region and the second region, and forming a larger tower base on the second region, thereby further improving the battery efficiency.

[0243] In Examples 3-6, the introduction of a barrier layer on the back of the battery can effectively improve the doping concentration change of the doped layer during the laser process, avoid damage to the tunneling layer, and further improve the passivation effect. At the same time, the barrier layer has a certain ability to block the puncture of the back slurry, which helps to reduce the total thickness of the back doped layer and increase the open circuit voltage (Voc) of the battery.

[0244] Tests have shown that, compared to using lasers to directly remove the second doped layer and tunneling layer on the second region, the efficiency of the solar cell in this invention can be improved by more than 0.15%.

[0245] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0246] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized by, The solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface arranged oppositely, the second surface comprises a first region and a second region, the first region is provided with a first tunneling passivation contact structure, the first region and the second region are provided with a second passivation structure, and the second passivation structure on the first region is stacked on the first tunneling passivation contact structure, wherein, A height difference H1 of a side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01 μm-8 μm, and / or a height difference H2 of a side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01 μm-8 μm.

2. The solar cell according to claim 1, characterized in that, The second passivation structure on the second region is in contact with the second surface of the silicon substrate, the first tunneling passivation contact structure on the first region comprises a tunneling layer and a second doped layer which are stacked in sequence, and the solar cell further comprises a second electrode located on the first region and in contact with the second doped layer.

3. The solar cell according to claim 2, characterized in that, The height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.05 μm-8 μm or 3 μm-6 μm; and / or, The height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.05 μm-8 μm or 3 μm-6 μm.

4. The solar cell of claim 2, wherein The tunneling layer is any one or a combination of a plurality of silicon oxide layers and silicon nitride oxide layers; and / or, The thickness of the tunneling layer is 0.5 nm-3 nm or 1.5 nm-2.5 nm; and / or, The second doped layer is a doped polysilicon layer, and the thickness is 1 nm-150 nm or 50 nm-100 nm; and / or, The second doped layer has the same doping type as the silicon substrate and a surface doping concentration of 2E20 cm -3 ~ 3E21 cm -3 or 5E20 cm -3 ~ 2E21 cm -3 .

5. The solar cell of claim 2, wherein The silicon substrate is recessed on the second region.

6. The solar cell according to claim 1 or 5, characterized in that, The first region and the second region in the second surface of the silicon substrate are both polished surfaces after pyramid structure texturing and polishing, and the size of the tower base on the first region is smaller than the size of the tower base on the second region.

7. The solar cell according to claim 6, characterized in that The size of the tower base on the first region is 3 μm-20 μm, and the size of the tower base on the second region is 3 μm-50 μm; or, The size of the tower base on the first region is 8 μm-15 μm, and the size of the tower base on the second region is 15 μm-30 μm.

8. The solar cell of claim 1, wherein, The second region is provided with a second tunneling passivation contact structure, the second passivation structure on the second region is stacked on the second tunneling passivation contact structure, and the thickness of the second tunneling passivation contact structure is smaller than the thickness of the first tunneling passivation contact structure.

9. The solar cell of claim 8, wherein, The first region is provided with a tunneling layer, a second doped layer, a barrier layer and a third doped layer, the second region is provided with a tunneling layer and a second doped layer, and the solar cell further comprises a second electrode located on the first region and in contact with the third doped layer.

10. The solar cell of claim 9, wherein, The first region is provided with a tunneling layer, a second doped layer, a barrier layer and a third doped layer, and the second region is provided with a tunneling layer and a second doped layer; or, the first region is provided with a tunneling layer, a second doped layer, a barrier layer, and a third doped layer, the second region is provided with a tunneling layer, a second doped layer, a barrier layer, and a third doped layer, the thickness of the third doped layer in the second region is less than that in the first region; or, the first region is provided with a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer, the second region is provided with a tunneling layer, at least two second doped layers and at least one barrier layer which are alternately stacked; or, the first region is provided with a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer, the second region is provided with a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer, the thickness of the third doped layer in the second region is less than that in the first region.

11. The solar cell of claim 8, wherein, the height difference H1 of the side surface of the second passivation structure away from the silicon substrate in the first region and the second region is 0.01 μm-0.153 μm or 0.048 μm-0.102 μm; and / or, the height difference H2 of the side surface of the second passivation structure toward the silicon substrate in the first region and the second region is 0.01 μm-0.153 μm or 0.048 μm-0.102 μm.

12. The solar cell of claim 9, wherein, the tunneling layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer; and / or, the thickness of the tunneling layer is 0.5 nm-3 nm or 1.5 nm-2.5 nm; and / or, the barrier layer is any one or a combination of a silicon oxide layer and a silicon carbide layer; and / or, the thickness of the barrier layer is 0.5 nm-3 nm or 1.5 nm-2 nm; and / or, The second doped layer has the same doping type as the silicon substrate and a surface doping concentration of 1E20 cm -3 ~ 9E20 cm -3 or 3E20 cm -3 ~ 5E20 cm -3 ; and / or, The third doped layer has the same doping type as the silicon substrate and a surface doping concentration of 2E20 cm -3 ~ 3E21 cm -3 or 5E20 cm -3 ~ 2E21 cm -3 and / or, the second doped layer is a doped polysilicon layer, and the thickness is 1 nm-100 nm or 1 nm-50 nm; and / or, the third doped layer is a doped polysilicon layer, and the thickness is 1 nm-150 nm or 50 nm-100 nm; and / or, the total thickness of the second doped layer and the third doped layer in the first region is 50 nm-150 nm or 60 nm-100 nm.

13. The solar cell according to claim 2 or 9, characterized in that, the first region comprises a plurality of first sub-regions which are parallel and equally spaced, the second region comprises a plurality of second sub-regions which are parallel and equally spaced, the first sub-regions and the second sub-regions are alternately distributed, and the width of the first sub-region is 20 μm-600 μm, and the width of the second sub-region is 100 μm-800 μm.

14. The solar cell of claim 1, wherein, the second passivation structure comprises a combination of one or more of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

15. The solar cell of claim 14, wherein, the second passivation structure comprises a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer which are sequentially stacked, wherein the thickness of the silicon oxide layer is 0.1 nm-3 nm, the thickness of the aluminum oxide layer is 3 nm-10 nm or 4 nm-8 nm, and the thickness of the silicon nitride layer is 60 nm-100 nm or 70 nm-90 nm; or, The second passivation structure comprises a silicon oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the silicon oxide layer is 1-30 nm, and the thickness of the silicon nitride layer is 60-100 nm or 70-90 nm.

16. The solar cell of claim 1, wherein, The first surface of the silicon substrate is provided with a first doped layer and a first electrode in contact with the first doped layer.

17. The solar cell of claim 16, wherein, The first doped layer has a doping type opposite to that of the silicon substrate, a surface doping concentration of 1E18 cm -3 ~5E19 cm -3 a thickness of 10 nm~100 nm; and / or, The first doped layer is stacked with a first passivation structure, and the first passivation structure comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3-10 nm or 4-8 nm, and the thickness of the silicon nitride layer is 60-100 nm or 70-90 nm.

18. A method for preparing a solar cell, characterized in that, The preparation method comprises the following steps: A silicon substrate is provided, which comprises a first surface and a second surface arranged oppositely, and the second surface comprises a first region and a second region; A tunneling passivation contact structure and a mask layer are prepared on the second surface; The mask layer on the second region is patterned and opened by a laser process; All or part of the tunneling passivation contact structure on the second region is removed by a wet etching process, and the tunneling passivation contact structure on the first region is reserved; The mask layer on the first region is removed to expose the tunneling passivation contact structure on the first region; A second passivation structure is prepared on the second surface; The height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01-8 μm, and / or the height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01-8 μm.

19. The method of claim 18, wherein, The preparation method further comprises: Pyramid texture structures are prepared on the first surface and the second surface of the silicon substrate by an alkali texturing process, and the pyramid size is 0.5-3 μm; and Before the tunneling passivation contact structure is prepared, the second surface of the silicon substrate is polished by an alkali solution to form a plurality of tower bases on the second surface, and the tower base size is 3-20 μm or 8-15 μm.

20. The method of claim 19, wherein, The tunneling passivation contact structure comprises a tunneling layer and a second doped layer stacked in sequence; the wet etching process comprises: The second doped layer, the tunneling layer and part of the silicon substrate on the second region are removed by an alkali etching process, and the tower base size on the second region of the silicon substrate after alkali etching is 3-50 μm or 15-30 μm, or all or part of the second doped layer on the second region is removed by an alkali etching process.

21. The method of claim 19, wherein, The tunneling passivation contact structure comprises a tunneling layer, a second doped layer, a barrier layer and a third doped layer stacked in sequence; the wet etching process comprises: All or part of the third doped layer on the second region is removed by an alkali etching process, or all of the third doped layer, the barrier layer and at least part of the second doped layer on the second region are removed by an alkali etching process.

22. The method of claim 19, wherein, The tunneling passivation contact structure comprises a tunneling layer, at least two second doped layers and at least two barrier layers stacked alternately, and a third doped layer; the wet etching process comprises: The third doped layer on the second region is removed by an alkali etching process; or, the third doped layer on the second region and the outermost blocking layer and at least part of the second doped layer of the outermost layer are removed by an alkali etching process.

23. The preparation method according to claim 18, characterized in that, The laser in the laser process is a green picosecond laser or a purple picosecond laser, the laser power is 0.3W-25W or 0.3W-5W, the laser frequency is 100kHz-1000kHz or 300kHz-600kHz, the laser scanning rate is 10000mm / s-100000mm / s or 10000mm / s-60000mm / s, and the laser processing times is 1-100 times or 1-10 times.

24. The method of claim 18, wherein, The mask layer is any one or a combination of more than one of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer, and has a thickness of 1nm-100nm or 5nm-30nm; and / or, The mask layer on the first region is removed by an acid solution.

25. The preparation method according to claim 18, characterized in that, The second passivation structure on the second surface is prepared by: The silicon oxide layer and the aluminum oxide layer are deposited on the second surface by an ALD process, the deposition temperature of the silicon oxide layer is 180°C-300°C, and the thickness is 0.1nm-3nm, the deposition temperature of the aluminum oxide layer is 180°C-300°C, and the thickness is 3nm-10nm or 4nm-8nm, and then the silicon nitride layer is deposited on the surface of the aluminum oxide layer by a PECVD process, and the thickness is 60nm-100nm or 70nm-90nm; or, The silicon oxide layer and the silicon nitride layer are deposited on the second surface by a PECVD process, the thickness of the silicon oxide layer is 0.1nm-3nm, and the thickness of the silicon nitride layer is 60nm-100nm or 70nm-90nm.

26. The method of claim 18, wherein, The preparation method further comprises: The first doped layer on the first surface is prepared, and the doping type of the first doped layer is opposite to the doping type of the silicon substrate; and The first electrode in contact with the first doped layer is prepared on the first surface, and the second electrode in contact with the tunneling passivation contact structure is prepared on the first region.

27. The method of claim 26, wherein, The preparation method further comprises: The first passivation structure on the first surface of the silicon substrate is prepared, the aluminum oxide layer is deposited on the first surface by an ALD process, and the thickness is 3nm-10nm or 4nm-8nm, and then the silicon nitride layer is deposited on the surface of the aluminum oxide layer by a PECVD process, and the thickness is 60nm-100nm or 70nm-90nm.

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