Space converter and preparation method thereof
By using a silicon oxide layer as a passivation layer on a ceramic substrate, the problems of pinholes and thermal compatibility in the RDL process of ceramic substrates are solved, thereby improving production efficiency and yield.
Patent Information
- Application Number
- CN202511786560.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-01
- Publication Date
- 2026-03-10
AI Technical Summary
In traditional ceramic substrate RDL processes, organic materials are prone to pinhole formation, have poor high-temperature resistance, and their coefficients of thermal expansion differ significantly from those of ceramic materials, leading to thermal compatibility issues.
A silicon oxide layer is used as a passivation layer between redistribution layers of a ceramic substrate. A via array is formed through photolithography and etching processes to reduce pinhole problems. The thermal compatibility problem is solved by matching the thermal expansion coefficients of silicon oxide and ceramic materials.
It effectively reduces pinhole problems in the process, improves process yield, saves production time, increases production efficiency, and solves the problem of thermal compatibility between materials.
Smart Images
Figure CN121633575A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of probe card technology, specifically a space converter and its preparation method. Background Technology
[0002] The semiconductor industry is developing rapidly, and a large number of chips need to be tested before packaging. This process requires probe cards. The substrate (space converter) is the main component of the probe card. As the feature size on the chip shrinks, the size and cycle of the test pads also gradually shrink. This means that the size and cycle of the pads on the substrate also shrink, while the size of the substrate gradually increases. This poses a great challenge to traditional substrate manufacturing processes.
[0003] More and more advanced probe cards are opting to use ceramic substrates instead of organic substrates because ceramic substrates can be used to create probe cards with larger dimensions, better planarity, better PAD positioning, and a superior coefficient of thermal expansion. Currently, ceramic substrates are mostly fabricated using MLC (Multi-Layer Ceramic) + RDL (Redistribution Layer) technology. Traditional RDL processes often use organic materials such as PI or ABF films as passivation layers between metal traces. These organic materials are prone to pinhole formation during fabrication, have poor high-temperature resistance, and their coefficients of thermal expansion differ significantly from those of ceramic materials, leading to thermal compatibility issues during subsequent assembly and testing. Summary of the Invention
[0004] To overcome the shortcomings of the prior art, embodiments of the present invention provide a space converter and its preparation method, which are used to solve the above-mentioned problems.
[0005] This application discloses a method for preparing a space converter, comprising the following steps:
[0006] Step 1: Perform pretreatment on the ceramic substrate, and then form a first seed layer on the surface of the ceramic substrate;
[0007] Step 2: Coat the first seed layer with photoresist to form a first photoresist layer, and perform photolithography and development on the first photoresist layer to form a first circuit pattern;
[0008] Step 3: Electroplating is performed on the first circuit pattern to form the first redistribution layer;
[0009] Step 4: Remove the portions of the first photoresist layer and the first seed layer that do not correspond to the first redistribution layer;
[0010] Step 5: After coating liquid silicon oxide onto the surface of the ceramic substrate, dry it to form a first silicon oxide layer. Coat the surface of the first silicon oxide layer with photoresist to form a second photoresist layer. Perform photolithography and development on the second photoresist layer to form a first via pattern.
[0011] Step 6: Based on the first via pattern, etch the first silicon oxide layer to form a first via array that communicates with the first redistribution layer on the first silicon oxide layer.
[0012] Specifically, step 1 includes:
[0013] Step 11: Grind and polish the upper and lower surfaces of the ceramic substrate to make the TTV of the ceramic substrate less than or equal to 5μm and the roughness of the upper and lower surfaces of the ceramic substrate less than or equal to 30nm.
[0014] Step 12: Sputter a first seed layer onto the upper or lower surface of the ceramic substrate.
[0015] Specifically, step 2 includes:
[0016] Step 21: Spin-coating photoresist onto the first seed layer and then baking the photoresist to form a first photoresist layer with a thickness between 18 and 22 μm;
[0017] Step 22: Align and develop the first photoresist layer using the first mask to form the first circuit pattern.
[0018] Specifically, step 5 includes:
[0019] Step 51: Spin-coat liquid silicon oxide onto the surface of the ceramic substrate, and then place it on a hot plate and bake at a temperature of 110~120℃ for 10~12 minutes to form a thin layer of silicon oxide with a thickness of 4~5μm.
[0020] Step 52: Repeat step 51 multiple times to obtain multiple stacked silicon oxide thin layers, wherein the multiple silicon oxide thin layers constitute a first silicon oxide layer with a thickness between 25 and 26 μm;
[0021] Step 53: After grinding and polishing the first silicon oxide layer, spin-coat photoresist onto the surface of the first silicon oxide layer to form a second photoresist layer. Align and develop the second photoresist layer using photolithography to form the first via pattern.
[0022] Specifically, step 6 includes: etching the first silicon oxide layer using an ICP device according to the first via pattern, stopping the etching at the metal on the first redistribution layer.
[0023] Specifically, the preparation method further includes step 7: forming a second redistribution layer on the first silicon oxide layer that is connected to the first via array.
[0024] Specifically, the ceramic substrate comprises multilayer ceramic.
[0025] This application also discloses a space converter, which is prepared using the method described in this embodiment.
[0026] The present invention has at least the following beneficial effects: The space converter and its preparation method in this embodiment have the following advantages: the use of silicon oxide layer as a passivation layer between two redistribution layers effectively reduces pinhole problems in the process and improves the process yield; since it is not necessary to cure organic materials as in previous processes, it saves production time and improves production efficiency; the thermal expansion coefficient of silicon oxide is similar to that of ceramic materials, which solves the problem of thermal compatibility between materials.
[0027] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the structure of forming a first seed layer on the surface of a ceramic substrate in an embodiment of the present invention;
[0030] Figure 2 This is a schematic diagram of the structure for forming the first photoresist layer in an embodiment of the present invention;
[0031] Figure 3 This is a schematic diagram of the structure forming the first circuit pattern in an embodiment of the present invention;
[0032] Figure 4 This is a schematic diagram of the structure in an embodiment of the present invention, showing the formation of the first redistribution layer and the removal of the excess first photoresist layer and the first seed layer;
[0033] Figure 5 This is a schematic diagram of the structure forming the first silicon oxide layer in an embodiment of the present invention;
[0034] Figure 6 This is a schematic diagram of the structure for forming the second photoresist layer in an embodiment of the present invention;
[0035] Figure 7 This is a schematic diagram of the structure forming the first via pattern in an embodiment of the present invention;
[0036] Figure 8 This is a schematic diagram of the structure forming the first via array in an embodiment of the present invention.
[0037] The reference numerals in the above figures are as follows: 1. Ceramic substrate; 2. First seed layer; 3. First photoresist layer; 31. First circuit pattern; 4. First redistribution layer; 5. First silicon oxide layer; 51. First via pattern; 6. Second photoresist layer; 7. First via array. Detailed Implementation
[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "fixing," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.
[0040] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "below," and "over" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0041] In the description of this embodiment, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this application.
[0042] Furthermore, the terms "first" and "second" are used only to distinguish between different terms in description and do not have any special meaning.
[0043] Combination Figures 1 to 8 As shown, the method for preparing the space converter in this embodiment includes the following steps:
[0044] Step 1: Perform pretreatment on the ceramic substrate 1, and then fabricate the first seed layer 2 on the surface of the ceramic substrate 1 (e.g., ...). Figure 1 (As shown). The first seed layer 2 is a metal layer, which mainly serves to conduct electricity.
[0045] Step 2: Combining Figure 2 and Figure 3 As shown, photoresist is coated on the first seed layer 2 to form the first photoresist layer 3. Then, the first photoresist layer 3 is photolithographically etched and developed to form the first circuit pattern 31 on the first seed layer 2.
[0046] Step 3: According to the thickness design requirements of the metal wire, electroplating is performed on the first circuit pattern 31 to form the first redistribution layer 4 on the first seed layer 2 (e.g., Figure 4 (As shown).
[0047] Step 4: As Figure 4 As shown, the portions of the first photoresist layer 3 and the first seed layer 2 that do not correspond to the first redistribution layer 4 are removed. Specifically, after step 3, all remaining portions of the first photoresist layer 3 are removed; the first seed layer 2, except for the portion located below the first redistribution layer 4, is completely removed.
[0048] Step 5: Combining Figures 5 to 7As shown, liquid silicon oxide is coated onto the surface of the ceramic substrate 1 and then dried to form a first silicon oxide layer 5. Photoresist is then coated onto the surface of the first silicon oxide layer 5 to form a second photoresist layer 6. Next, photolithography and development are performed on the second photoresist layer 6 to form a first via pattern 51. Specifically, after step 4, the surface of the ceramic substrate 1 has a first redistribution layer 4 and areas below the first redistribution layer 4. Silicon oxide fills these areas and covers the first redistribution layer 4; after coating photoresist onto the first silicon oxide layer 5, alignment, photolithography, and development are performed to create the vias on the metal PADs of the first redistribution layer 4 using photoresist.
[0049] Step 6: Combining Figure 7 and Figure 8 As shown, according to the first via pattern 51, the first silicon oxide layer 5 is etched, and the vias made by photoresist are transferred to the first silicon oxide layer 5 by etching, so that a first via array 7 electrically connected to the first redistribution layer 4 is formed on the first silicon oxide layer 5. The first via array 7 includes a plurality of first vias, and then metal is filled in the first vias.
[0050] Specifically, step 1 includes the following steps:
[0051] Step 11: The ceramic substrate 1 used is preferably composed of multilayer ceramic, and the ceramic substrate 1 includes an upper surface and a lower surface disposed opposite to each other. The pretreatment of the ceramic substrate 1 includes: grinding and polishing the upper surface and the lower surface of the ceramic substrate 1 so that the TTV (Total Thickness Variation) of the ceramic substrate 1 is less than or equal to 5 μm, and the roughness of the upper surface and the lower surface of the ceramic substrate 1 is less than or equal to 30 nm.
[0052] Step 12: Sputter the first seed layer 2 onto the upper or lower surface of the ceramic substrate 1 after the treatment in step 11.
[0053] Specifically, step 2 includes the following steps:
[0054] Step 21: Spin-coat photoresist onto the first seed layer 2, and then bake the photoresist to form a first photoresist layer 3 on the surface of the first seed layer 2. The thickness of the first photoresist layer 3 is between 18 and 22 μm, preferably 20 μm.
[0055] Step 22: Align and develop the first photoresist layer 3 using the first mask to form the first circuit pattern 31.
[0056] Step 5 specifically includes the following:
[0057] Step 51: Spin-coat liquid silicon oxide onto the surface of ceramic substrate 1, and then place it on a hot plate and bake at a temperature of 110~120℃ for 10~12 minutes to form a thin layer of silicon oxide with a thickness of 4~5μm.
[0058] Step 52: Repeat step 51 multiple times to obtain multiple stacked silicon oxide thin layers. These stacked silicon oxide thin layers constitute the first silicon oxide layer 5, with a thickness between 25 and 26 μm. Specifically, the thickness of each silicon oxide thin layer can be controlled to approximately 5 μm. After five repetitions of step 51, a first silicon oxide layer 5 with a total thickness of approximately 25 μm can be obtained. Using this method, by fabricating silicon oxide thin layers multiple times to obtain a thicker first silicon oxide layer 5, pinhole problems during the process can be reduced, and the process yield can be improved.
[0059] Step 53: After grinding and polishing the first silicon oxide layer 5, spin-coating photoresist onto its surface forms the second photoresist layer 6. Alignment photolithography and development are then performed on the second photoresist layer 6 to obtain the first via pattern 51.
[0060] Step 6 specifically includes the following: According to the first via pattern 51, the first silicon oxide layer 5 is etched using an IPC device (ICP etching machine is a dry etching device based on inductively coupled plasma technology) until the etching stops when the metal on the first redistribution layer 4 is reached.
[0061] By repeating steps 1 to 6, a second redistribution layer electrically connected to the first redistribution layer 4 via the first via array 7 can be fabricated on the first silicon oxide layer 5. It should be noted that, when fabricating the second redistribution layer, "pre-treatment of the ceramic substrate 1" in step 1 refers to pre-treatment of the first silicon oxide layer 5 on the ceramic substrate 1 to ensure its flatness and roughness meet the requirements of subsequent processes. Alternatively, steps 1 to 6 can be repeated to fabricate a redistribution layer on the other side of the ceramic substrate 1.
[0062] In summary, the space converter and its fabrication method in this embodiment have the following advantages: using a silicon oxide layer as a passivation layer between two redistribution layers effectively reduces pinhole problems in the process and improves process yield; since it does not require curing of organic materials as in previous processes, it saves production time and improves production efficiency; the coefficient of thermal expansion of silicon oxide is similar to that of ceramic materials, which solves the problem of thermal compatibility between materials.
[0063] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.
Claims
1. A method for preparing a space converter, characterized in that, The method comprises the following steps: Step 1: pre-treating a ceramic substrate, and then making a first seed layer on the surface of the ceramic substrate; Step 2: coating a photoresist on the first seed layer to form a first photoresist layer, and then performing photoetching and developing on the first photoresist layer to form a first circuit pattern; Step 3: performing electroplating on the first circuit pattern to form a first redistribution layer; Step 4: removing the first photoresist layer and the part of the first seed layer corresponding to the non-first redistribution layer; Step 5: coating liquid silicon oxide on the surface of the ceramic substrate and then baking to form a first silicon oxide layer, coating a photoresist on the surface of the first silicon oxide layer to form a second photoresist layer, and then performing photoetching and developing on the second photoresist layer to form a first via pattern; Step 6: etching the first silicon oxide layer according to the first via pattern to form a first via array communicating with the first redistribution layer.
2. The method of claim 1, wherein the spacer is prepared by a method comprising: The step 1 specifically comprises: Step 11: grinding and polishing the upper and lower surfaces of the ceramic substrate to make the TTV of the ceramic substrate less than or equal to 5 μm, and to make the roughness of the upper and lower surfaces of the ceramic substrate less than or equal to 30 nm; Step 12: sputtering a first seed layer on the upper or lower surface of the ceramic substrate.
3. The method of claim 1, wherein the spacer is prepared by a process comprising: The step 2 specifically comprises: Step 21: spin-coating a photoresist on the first seed layer and then baking the photoresist to form a first photoresist layer with a thickness of 18-22 μm; Step 22: performing aligning photoetching and developing on the first photoresist layer with a first mask to form a first circuit pattern.
4. The method of claim 1, wherein the spacer is prepared by a process comprising: The step 5 specifically comprises: Step 51: spin-coating liquid silicon oxide on the surface of the ceramic substrate, and then baking on a hot plate at a temperature of 110-120 ℃ for 10-12 minutes to form a silicon oxide thin layer with a thickness of 4-5 μm; Step 52: repeatedly performing step 51 to obtain a plurality of silicon oxide thin layers stacked on each other, and the plurality of silicon oxide thin layers form a first silicon oxide layer with a thickness of 25-26 μm; Step 53: grinding and polishing the first silicon oxide layer, spin-coating a photoresist on the surface of the first silicon oxide layer to form a second photoresist layer, and then performing aligning photoetching and developing on the second photoresist layer to form a first via pattern.
5. The method of claim 1, wherein the spacer is prepared by a process comprising: The step 6 specifically comprises: etching the first silicon oxide layer according to the first via pattern by using an ICP device, and stopping etching on the metal of the first redistribution layer.
6. The method of claim 1, wherein the space transformer is prepared by a process comprising: The method further comprises a step 7: forming a second redistribution layer on the first silicon oxide layer and communicating with the first via array.
7. The method of claim 1, wherein the space transformer is prepared by a process comprising: The ceramic substrate comprises a multilayer ceramic.
8. A spatial transformer characterized by, The method is prepared by any one of claims 1-7.