Chip DFT (Discrete Fourier Transform) test system, method and equipment and storage medium

Abstract

The invention provides a chip DFT testing system, method and device and a storage medium, and relates to the technical field of chip testing. The chip DFT test system comprises an FPGA board card and a test upper computer, and the test upper computer is in communication connection with the FPGA board card and used for sending a test control instruction to a test circuit; the FPGA board card is loaded with a test circuit and is used for carrying out DFT test on the chip to be tested; the test circuit comprises a dynamic clock module, and the dynamic clock module is configured to generate a clock used for driving the test circuit and adjust time sequence parameters of the clock according to a test control instruction received by the test circuit. According to the invention, by adjusting the time sequence parameter of the clock used by the test circuit, the clock configuration can be matched with the characteristics of the chip to be tested, so that the accuracy and applicability of the chip DFT test are improved.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and more specifically, to a chip DFT testing system, a chip DFT testing method, a chip DFT testing device, and a computer-readable storage medium. Background Technology

[0002] In chip design and manufacturing, Design for Testability (DFT) technology is widely used to verify the functionality and timing characteristics of chips. Some related technologies utilize FPGA boards as test platforms, leveraging their flexible logic resources to load corresponding test circuits, thereby driving test vectors and acquiring chip response data.

[0003] With the increasing scale of chips and the growing demand for verification, ensuring the accuracy of testing under different testing environments or different chip characteristics has become an urgent problem to be solved in current DFT testing technology.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a chip DFT testing system, method, device, and storage medium. By adjusting the timing parameters of the clock used in the test circuit, the clock configuration can be matched to the characteristics of the chip under test, thereby improving the accuracy and applicability of chip DFT testing.

[0006] According to a first aspect of this disclosure, a chip DFT testing system is provided, comprising: an FPGA board and a test host computer, wherein:

[0007] The host computer for testing is communicatively connected to the FPGA board and is used to send test control commands to the test circuit.

[0008] The FPGA board is equipped with a test circuit for performing DFT testing on the chip under test. The test circuit includes a dynamic clock module, which is configured to generate a clock to drive the test circuit and adjust the timing parameters of the clock according to the test control commands received by the test circuit.

[0009] In one exemplary embodiment of this disclosure, the dynamic clock module is configured to generate at least one of a data transmission clock, a sampling clock, and a gated clock;

[0010] The data transmission clock is used to control the timing of the test circuit sending test vectors to the chip under test, the sampling clock is used to control the timing of the test circuit acquiring the test results output by the chip under test, and the gated clock is used to control the start and stop of the sampling clock during the DFT test.

[0011] In one exemplary embodiment of this disclosure, the timing parameters include frequency, phase, and duty cycle;

[0012] The dynamic clock module is further configured to adjust the frequency, phase, and duty cycle of at least one of the data transmission clock, the sampling clock, and the gated clock according to the test control command.

[0013] In one exemplary embodiment of this disclosure, the test circuit further includes:

[0014] The host computer communication module is connected to the test host computer and is used to receive the test control command sent by the test host computer, and configure the internal register of the test circuit according to the test control command, so that the dynamic clock module adjusts the timing parameters of the clock according to the configuration parameters in the internal register.

[0015] In one exemplary embodiment of this disclosure, the host computer communication module is further configured to receive test vectors issued by the test host computer, and to receive test results obtained by performing DFT tests on the chip under test based on the test vectors, and to return the test results to the test host computer.

[0016] In one exemplary embodiment of this disclosure, the test circuit further includes:

[0017] A test vector storage module is used to store the test vectors received by the host computer communication module;

[0018] The test vector import module is used to import the test vectors in the test vector storage module into the chip under test;

[0019] The test result export module is used to import the test results output by the chip under test into the test result storage module;

[0020] A test result storage module is used to store the test results.

[0021] In one exemplary embodiment of this disclosure, the test vector includes a reference test vector and an actual test vector;

[0022] The test circuit also includes:

[0023] The test result comparison module is used to compare the reference test result output by the chip under test with the corresponding target test result, and determine whether the timing parameters of the clock of the test circuit meet the timing adaptation conditions according to the first comparison result, so as to adjust the timing parameters when the timing parameters do not meet the timing adaptation conditions; and to compare the actual test result output by the chip under test with the corresponding target test result, and determine whether the chip under test passes the DFT test according to the second comparison result.

[0024] Wherein, the reference test result is the test result obtained by performing DFT test on the chip under test using the reference test vector; the actual test result is the test result obtained by performing DFT test on the chip under test using the actual test vector; the target test result corresponding to the reference test result is determined by the test host computer according to the reference test vector and sent to the test result comparison module; the target test result corresponding to the actual test result is determined by the test host computer according to the actual test vector and sent to the test result comparison module.

[0025] In one exemplary embodiment of this disclosure, the system further includes:

[0026] A general-purpose server is used to establish a communication connection between the FPGA board and the terminal device on which the test host computer is deployed.

[0027] The test host computer includes:

[0028] The remote communication module is used to send test control commands to the general server when the terminal device accesses the general server, and to receive test results returned by the FPGA board after executing the test control commands through the general server.

[0029] In one exemplary embodiment of this disclosure, the test host computer further includes:

[0030] The clock configuration module is used to generate the test control commands to configure the timing parameters of the clock generated by the dynamic clock module.

[0031] In one exemplary embodiment of this disclosure, the test vector includes a first test vector and a second test vector;

[0032] The host computer for testing also includes:

[0033] The test vector conversion module is used to convert the first test vector in the initial format into the second test vector in the target format.

[0034] The test vector loading module is used to send the second test vector generated by the test vector conversion module to the test circuit in the FPGA board through the remote communication module.

[0035] In one exemplary embodiment of this disclosure, the initial format is a test vector description format, and the target format is a digital vector data format.

[0036] In one exemplary embodiment of this disclosure, the test host computer further includes:

[0037] The test result download module is used to transmit the test results to the terminal device through the remote communication module, so as to generate a test report based on the test results.

[0038] In one exemplary embodiment of this disclosure, the test host computer further includes:

[0039] The batch testing module is used to sequentially send multiple second test vectors to the test circuit in the FPGA board through the remote communication module, and to transmit the received corresponding test results to the terminal device to generate a test report.

[0040] According to a second aspect of this disclosure, a chip DFT testing method is provided, applied to a chip DFT testing system, the method comprising:

[0041] Power on the FPGA board and load the configuration file for the characterization test circuit, so that the FPGA board runs the test circuit;

[0042] The host computer sends test control commands to the test circuit and configures the dynamic clock module in the test circuit according to the test control commands to adjust the timing parameters of the clock used by the test circuit.

[0043] After the timing parameters are configured, the test host computer sends test vectors to the test circuit to drive the test circuit to perform DFT testing on the chip under test using the test vectors.

[0044] In one exemplary embodiment of this disclosure, after the DFT test is completed, the method further includes:

[0045] Compare the current test result with the target test result corresponding to the test vector in the test control instruction;

[0046] When the current test result is inconsistent with the target test result, the timing parameters of the clock are adjusted, and the DFT test is performed again on the chip under test based on the adjusted timing parameters.

[0047] According to a third aspect of this disclosure, a chip DFT testing apparatus is provided, comprising:

[0048] The processing unit; and the storage unit for storing executable instructions of the processing unit; wherein the processing unit is configured to execute the above-described chip DFT test method by executing the executable instructions.

[0049] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program, when executed by a processing unit, implements the above-described chip DFT test method.

[0050] The exemplary embodiments disclosed herein may have some or all of the following beneficial effects:

[0051] The chip DFT testing system provided in this exemplary embodiment of the present disclosure, by loading a test circuit into an FPGA board and introducing a dynamic clock module capable of generating clock signals, eliminates the limitation to a single, fixed clock environment during testing. Because this dynamic clock module can adjust the timing parameters of the generated clock according to the test control commands received by the test circuit, the test circuit can operate under timing conditions that match different test environments and chip characteristics, thereby avoiding the sampling deviation problem caused by fixed clock parameters in related technologies. Simultaneously, the host computer maintains a communication connection with the FPGA board and issues test control commands, enabling testers to flexibly control the test circuit through the host computer. This makes the testing process more adaptable and able to meet the chip verification needs of different scenarios.

[0052] Furthermore, the dynamic clock module in the test circuit is responsible for generating and adjusting the drive clock. This configuration allows the chip's output data to be stably acquired, no longer limited by environmental errors under fixed configurations. This instruction-triggered clock adjustment method enables the test circuit to maintain a simple structure while providing flexible and controllable operating conditions, thereby improving overall test reliability.

[0053] Finally, because the host computer in the test system takes on the role of sending test control commands to the test circuit, it achieves centralized operation and management in the test process, making the test process remotely controllable. This avoids the limitation of the test environment being fixed in the laboratory, as is common in related technologies. Combined with the clock parameter adjustment function of the dynamic clock module, the host computer in the test system can quickly configure test conditions under different operating environments, ensuring that the test system can meet the complex and ever-changing chip verification requirements.

[0054] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0056] Figure 1 An architecture diagram of a chip DFT testing system according to an embodiment of this disclosure is shown.

[0057] Figure 2 An architecture diagram of another chip DFT testing system according to an embodiment of this disclosure is shown.

[0058] Figure 3 A schematic flowchart of a chip DFT testing method according to an embodiment of this disclosure is shown.

[0059] Figure 4 A logical architecture diagram of a chip DFT testing system according to an embodiment of this disclosure is shown.

[0060] Figure 5 A schematic diagram of the structure of a chip DFT testing device according to an embodiment of this disclosure is shown.

[0061] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0062] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0063] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0064] refer to Figure 1 The diagram shows an architecture diagram of a chip DFT testing system according to an embodiment of this disclosure. Figure 1 In the chip DFT testing system 100, there are FPGA (Field Programmable Gate Array) boards 101, terminal devices 102, and general-purpose servers 103, wherein:

[0065] The FPGA board 101 is equipped with a test circuit for performing DFT testing on the chip under test. Specifically, the test circuit includes a dynamic clock module. This module generates a clock signal to drive the test circuit and adjusts the timing parameters of the clock signal according to the test control command when the test circuit receives the command. This allows the test circuit to complete the test operation under different timing conditions. This enables the testing process to operate flexibly without relying on a fixed clock, improving the system's adaptability to different chip characteristics and testing environments.

[0066] For example, when the test circuit receives a test control command, it first configures the timing parameters of the clock signal according to the command to establish an initial runtime timing environment suitable for testing. Before the formal test begins, the clock parameters can be calibrated or corrected as necessary through a preset comparative test to ensure they meet the test requirements of the chip under test. Once the formal test phase begins, the clock parameters remain stable and are no longer frequently adjusted, thus ensuring the continuity of the test process and the reliability of the results.

[0067] In this example, the test control commands are control information generated by the host computer and sent to the test circuit. These commands configure and schedule the operating state of the test circuit during the DFT test. Specifically, the test control commands may include timing parameter configuration information for the dynamic clock module, indicating the set values ​​for the generated clock signal in terms of frequency, phase, and duty cycle, thereby adjusting the clock conditions. Furthermore, the test control commands may also include operation commands related to the test process, such as starting or stopping the test, loading or selecting test vectors, and triggering test result acquisition, enabling the test circuit to execute test tasks according to a predetermined process. By configuring and sending test control commands, the test circuit can operate in a suitable timing environment under different test requirements, thereby improving the overall flexibility and accuracy of the test.

[0068] Terminal device 102 includes, but is not limited to, desktop computers, laptops, smartphones, and tablets. A test host computer is deployed on terminal device 102, and a communication connection is established between the test host computer and a general-purpose server 103, which interacts with the FPGA board 101. In this embodiment, the test host computer is used to send test control commands to the test circuit to configure the timing parameters of the dynamic clock module, thereby changing the clock conditions of the test circuit during operation and completing the DFT test of the chip under test. Based on this, testers can remotely operate the test circuit on the terminal device, such as remotely controlling the test progress, reducing dependence on the on-site test environment and greatly improving the convenience of testing.

[0069] In practical applications, the general-purpose server 103 acts as a communication relay node, establishing a communication connection between the FPGA board 101 and the terminal device 102. This communication connection can include various types such as wired and wireless connections, ensuring that the host computer can remotely control and test the FPGA board 101. This architecture enables remote configuration and control of the test circuit, providing greater flexibility and scalability in the testing process and improving the efficiency of large-scale testing tasks.

[0070] It should be understood that Figure 1 The number of FPGA boards 101, terminal devices 102 and general-purpose servers 103 shown are merely illustrative. Any number and type of FPGA boards 101, terminal devices 102 and general-purpose servers 103 can be configured according to actual needs, thereby ensuring that the system can adapt to testing requirements of different scales.

[0071] It should be noted that the dynamic clock module is used to generate the clock that drives the entire test circuit. Its design purpose is to provide configurable timing conditions for different test stages. Specifically, the dynamic clock module can generate one or more clock signals according to different test requirements, which are used to drive processes such as data transmission, result acquisition, or clock control in the test circuit.

[0072] For example, the dynamic clock module is configured to generate at least one of a data transmission clock, a sampling clock, and a gated clock to meet the requirements of different clock signals during the DFT test.

[0073] The data transmission clock controls the timing of the test circuit sending test vectors to the chip under test (DUT), ensuring that the test vectors are transmitted to the DUT according to a set period, thus guaranteeing the consistency of the input stimulus and the test process. The sampling clock controls the timing of the test circuit acquiring the output test results from the DUT. By aligning the sampling edges with the chip's output signal, accurate acquisition of test results is ensured. The gated clock controls the start and stop of the sampling clock during DFT testing, allowing for flexible management of clock validity at different test stages, preventing irrelevant clocks from interfering with data transmission and sampling, and improving overall test accuracy.

[0074] Furthermore, the dynamic clock module in the exemplary embodiments of this disclosure not only generates multiple clock signals but also includes the function of dynamically adjusting timing parameters. Specifically, the timing parameters include frequency, phase, and duty cycle. Frequency refers to the number of clock signal cycles per unit time, used to characterize the speed of the clock signal; the frequency directly affects the data transmission and sampling rate in the test circuit. Phase refers to the relative offset of the same clock signal in time, used to adjust the alignment relationship between different signals to ensure the matching of the test vector and the sampled signal in the time dimension. Duty cycle is the ratio of the high-level duration to the entire cycle length within a clock cycle, used to determine the time distribution of the high and low levels of the clock signal, thereby affecting the triggering conditions and stability of the driven logic.

[0075] For example, when the test circuit receives a test control command from the host computer, the dynamic clock module can adjust the frequency, phase and duty cycle of at least one of the data transmission clock, sampling clock and gate clock according to the test control command, so that the test circuit can operate in a matching timing environment under different working conditions.

[0076] In this example implementation, the dynamic clock module ensures the normal driving of the test circuit while effectively ensuring the timing alignment of data transmission and sampling during the test process through fine adjustment of the clock frequency, phase and duty cycle. It also flexibly adapts to different test environments and different chip characteristics, thereby improving the accuracy and reliability of DFT testing.

[0077] In some example implementations, references Figure 2 The diagram illustrates the architecture of another chip DFT testing system according to an embodiment of this disclosure. The FPGA board 101 is equipped with a test circuit, which includes a host computer communication module. This module establishes a communication connection with a host computer via PCIe (Peripheral Component Interconnect Express) to receive test control commands from the host computer and configure the internal registers of the test circuit according to these commands. This allows the dynamic clock module to adjust the timing parameters of the clock based on the configuration parameters in the internal registers, thereby ensuring the timing adaptability of the test circuit under different test conditions.

[0078] The host computer communication module is also used to receive test vectors issued by the host computer and to receive test results obtained from DFT testing of the chip under test based on the test vectors. It then returns the test results to the host computer for subsequent analysis and processing. In some implementations, the host computer communication module not only supports interaction for a single test task but also, when multiple test tasks exist simultaneously, can parse and distribute multiple data streams based on address mapping and port allocation mechanisms, thereby improving parallel processing capabilities.

[0079] The test circuit also includes a test vector storage module, a test vector import module, a test result export module, and a test result storage module. The test vector storage module stores test vectors received by the host computer communication module to support subsequent import operations. The test vector import module, connected to the test vector storage module, imports test vectors from the storage module into the chip under test (DUT) to drive DFT testing. The test result export module imports test results output by the DUT into the test result storage module for storage, supporting result comparison, analysis, and archiving. For example, the test result storage module can employ a hierarchical caching and indexing mechanism to ensure high efficiency in storing and retrieving large-scale test data, thereby avoiding data bottlenecks in subsequent analysis stages.

[0080] Figure 2The test circuit also includes a test result comparison module for comparing and analyzing the output results of the chip under test. In some example implementations, the test vector may include a reference test vector and an actual test vector. For example, the reference test vector is used to verify and calibrate the operating environment of the test circuit before formal testing, so as to adjust the clock timing parameters by comparing the test results with the corresponding expected results, thereby establishing timing adaptation conditions that meet the test requirements. The actual test vector is used to perform formal DFT testing on the chip under test after the timing conditions have stabilized, and its output results will be compared with the corresponding expected results to verify the correctness of the chip under test in terms of functionality and timing characteristics.

[0081] Specifically, the test result comparison module can simultaneously perform two types of comparison tasks. First, it can compare the reference test result output by the chip under test (DUT) during the reference test phase with the corresponding target test result, and determine whether the timing parameters of the test circuit's clock meet the timing adaptation conditions based on the first comparison result. When the first comparison result shows an inconsistency, it can be inferred that the current timing parameter configuration does not yet meet the adaptation requirements. In this case, the frequency, phase, or duty cycle of the dynamic clock module needs to be appropriately adjusted to gradually approach a stable and compliant timing environment. In this way, the reference test phase can effectively complete the operational calibration of the test circuit.

[0082] Secondly, after completing the above calibration process and establishing a timing environment that meets the requirements, the test result comparison module can also compare the actual test results output by the chip under test with the corresponding target test results, and directly determine whether the chip under test meets the design function and timing characteristics under the action of the loaded actual test vector based on the second comparison result, thereby giving a conclusion on whether the chip under test passes the DFT test.

[0083] It should be noted that the reference test result is obtained by performing DFT testing on the chip under test using the reference test vector; the actual test result is obtained by performing DFT testing on the chip under test using the actual test vector; the target test result corresponding to the reference test result is determined by the test host computer based on the reference test vector and sent to the test result comparison module; the target test result corresponding to the actual test result is determined by the test host computer based on the actual test vector and sent to the test result comparison module.

[0084] For example, the desired response result can be obtained by combining functional simulation data from the design phase, the results output by ATPG (Automatic Test Pattern Generation), or by referring to existing verification libraries; that is, obtaining the target test result corresponding to the reference test result. This test result corresponds to the reference test vector and is stored as a golden value in the test host computer. When the test task is issued, the test host computer will transmit the reference test vector and the corresponding target test result to the test circuit. The reference test vector is stored in the test vector storage module, while the corresponding target test result is sent to the test result comparison module to ensure the synchronization of the comparison.

[0085] In this example implementation, the test result comparison module can provide dual support for both reference tests and actual tests, ensuring both clock environment adaptability and the reliability and traceability of test results.

[0086] In practice, the test result comparison module receives the reference test result under the driving of the sampling clock and reads the corresponding target test result according to a preset index or mapping relationship. The reference test result and the corresponding target test result are compared bit-by-bit or cycle-by-cycle after alignment processing. When the comparison results are consistent, it indicates that the test circuit meets the timing adaptation conditions under the current clock frequency, phase, and duty cycle configuration, ensuring that the test vector remains correctly synchronized during transmission and acquisition, thus obtaining reliable test results. When the comparison results are inconsistent, it indicates that there is a deviation in the existing clock configuration, and the configuration parameters of the dynamic clock module need to be adjusted. This adjustment can be achieved either by the test result comparison module feeding back the comparison information to the internal register and passing it to the dynamic clock module through configuration logic, or by the test host computer issuing new test control commands after receiving the comparison results, until the clock timing parameters meet the adaptation conditions.

[0087] In some example implementations, before formal batch testing, a reference test vector is selected as a preliminary calibration case. The test result comparison module compares the reference test result with the target test result provided by the host computer and obtains stable clock parameters through closed-loop adjustment. Once the clock parameters are stable, the batch execution phase of other test vectors, i.e., the actual test vectors, begins. At this time, the test result comparison module still performs comparison operations to determine whether the chip under test passes the test under all test vectors. Error information or statistical data during the comparison process can also be recorded in internal registers and provided to the test host computer for subsequent test report generation or further optimization of test conditions.

[0088] The test result comparison module can not only dynamically judge and adjust the clock adaptability during the test, but also work closely with the host computer, internal registers and dynamic clock module throughout the test process, thereby improving the accuracy, flexibility and automation of the test process.

[0089] Furthermore, the internal registers of the test circuit can store and manage the configuration parameters received by the host computer communication module. Moreover, such as... Figure 2 As shown, the internal registers are connected to multiple functional modules in the test circuit to achieve unified control of the test process.

[0090] Specifically, the internal registers establish a communication connection with the dynamic clock module to provide clock configuration parameters, enabling the dynamic clock module to adjust the frequency, phase, and duty cycle according to the configuration parameters stored in the internal registers. The internal registers are also connected to the test vector storage module to store state information during the test vector loading and parsing process, thereby ensuring that the test vectors can be correctly imported into the chip under test.

[0091] Furthermore, the internal registers are connected to the test result export module to provide necessary control information during test result transmission, ensuring that test results are exported to the test result storage module in the set order and format. The internal registers can also be synchronized with the host computer communication module. When the host computer issues new control commands, the contents of the internal registers can be updated in real time, thus enabling instant parameter modification and refreshing without affecting the normal operation of other modules.

[0092] The internal register, as the core control unit, coordinates the operating status of each functional module in the test circuit, ensuring that the test process maintains consistency and controllability under the condition of multiple modules running in parallel, and guaranteeing the stability and scalability of the overall system under different test scenarios.

[0093] Depend on Figure 2 It can be seen that the dynamic clock module is not only connected to the internal register to receive the timing parameters stored in the register, but also establishes a communication connection with the test vector import module and the test result export module.

[0094] For example, the dynamic clock module provides a data transmission clock to the test vector import module, controlling the import of test vectors to the chip under test (DUT) cycle by cycle. This ensures that the test vector loading process is consistent with the set timing conditions, thereby avoiding import errors caused by data and clock asynchrony. The dynamic clock module also provides a sampling clock to the test result export module, ensuring that the sampling process strictly follows the clock edge when the DUT outputs test results. This guarantees consistency between the acquired data and the actual output, improving the validity and accuracy of the test results.

[0095] In addition, the dynamic clock module can output a gated clock at specific stages to control the start and stop of the test vector import module and the test result export module, so that the relevant modules are in a disabled state during invalid cycles or non-test cycles, reducing the interference of redundant operations on the test process.

[0096] Through this connection, the dynamic clock module not only plays the role of generating clock signals in the test circuit, but also acts as a key time control unit, coordinating the entire process of test vector input and result output, ensuring the stability and accuracy of DFT testing under different conditions.

[0097] Through such Figure 2 The modules shown cooperate to enable the chip DFT testing system to receive, store, and import test vectors, and to collect, store, and transmit test results, thus ensuring the integrity and traceability of the testing process. This modular design not only enhances the system's scalability but also allows for flexible configuration of the testing process according to the needs of different test objects, thus balancing versatility and customization.

[0098] like Figure 2 As shown, the host computer for testing is deployed in terminal device 102 and is used to control and manage the chip DFT testing system in a remote environment. Specifically, the host computer includes a remote communication module, used to send test control commands to the general server when the terminal device accesses the general server, and to receive test results returned by the general server after the FPGA board executes the test control commands. For example, the remote communication module can use an SSH (Secure Shell) remote communication module to support remote access of a personal computer to the general server, submit commands to the general server, and receive return values ​​after command execution. In this process, the remote communication module can establish an encrypted secure channel to ensure the integrity and security of test data and control commands during cross-network transmission.

[0099] Furthermore, the host computer for testing also includes a clock configuration module. This module generates test control commands to configure the timing parameters of the clock generated by the dynamic clock module, thereby adjusting the operating clock conditions of the test circuit. For example, the clock configuration can be sent to the test circuit via the host computer communication module, ensuring that the dynamic clock module adjusts its output according to the configured parameters. In some examples, the clock configuration module can also preset multiple clock configuration schemes and quickly switch between them during testing to adapt to different test scenarios, significantly shortening the debugging cycle.

[0100] In the exemplary embodiments of this disclosure, the test vector may include a first test vector and a second test vector. The first test vector refers to a standardized test vector file commonly used in the design verification phase. It can adopt a test vector description format, such as WGL (Waveform Generation Language) or STIL (Standard Test Interface Language), which can clearly characterize the input, output, and timing requirements of the chip under test during the testing process. The second test vector refers to a target file adapted for loading into the test circuit after format conversion. It can adopt a digital vector data format, such as TXT (Text File), BIN (Binary File), or COE (Coefficient File), and is used to be directly parsed and executed in the test circuit. This disclosure does not limit the specific formats of the first and second test vectors.

[0101] Therefore, the first test vector primarily focuses on human-machine readability and design verification, emphasizing standardization and universality, while the second test vector is geared towards hardware execution, emphasizing data compactness and directness, enabling rapid loading and use by test circuits in the FPGA board. Through the differentiation and conversion of test vectors, both the standardization of the test data generation process and the efficiency and adaptability of the test execution process are ensured. Furthermore, this dual-format collaborative mechanism avoids the excessive resource consumption caused by directly parsing complex file formats in the FPGA board.

[0102] Accordingly, the host computer for testing also includes a test vector conversion module and a test vector loading module. The test vector conversion module converts a first test vector in an initial format into a second test vector in a target format. For example, it converts a WGL format test vector into TXT format binary data to meet the loading requirements of the test circuit. The test vector loading module sends the second test vector generated by the test vector conversion module to the test circuit on the FPGA board via a remote communication module. For example, it submits the binary data generated by the test vector conversion module to the test vector storage module in the test circuit via an SSH remote communication module for subsequent import and use. Optionally, the test vector loading module can also support batch file transfer and breakpoint resumption to ensure the stable execution of large-scale test tasks.

[0103] In addition, regarding test result processing, the host computer can also include a test result download module, used to transmit test results to terminal devices via a remote communication module, so as to generate test reports based on the test results. For example, data stored in the test result storage module of the test circuit can be downloaded to a personal computer via an SSH remote communication module, and a test report can be generated on the personal computer, improving the readability of the test results. At the same time, the test result download module can interface with data analysis software to automatically generate statistical charts and comparison reports, thereby enhancing the intuitiveness of the test conclusions.

[0104] In some example implementations, the host computer for testing also includes a batch testing module, which integrates the functions of a test vector loading module and a test result downloading module. This module is used to sequentially send multiple second test vectors to the test circuit in the FPGA board via a remote communication module, and to transmit the received corresponding test results to the terminal device to generate a test report.

[0105] The batch testing module supports continuous testing of multiple test cases. By configuring this module, efficiency and automation in large-scale testing scenarios can be improved. For example, in a scenario where a group of chip samples needs to be verified under different operating conditions, the batch testing module can automatically schedule test tasks and merge test results, reducing manual intervention and improving overall test throughput.

[0106] This disclosure also provides a chip DFT testing method, which can be applied to, for example... Figure 2 The chip DFT testing system shown is used to perform DFT testing on the chip under test. (Reference) Figure 3 As shown, the chip DFT testing method may include the following steps S310 to S330:

[0107] Step S310: Power on the FPGA board and load the configuration file for the characterization test circuit, so that the FPGA board runs the test circuit.

[0108] The process begins with powering on the FPGA board to ensure its power supply voltage, clock resources, and on-chip logic resources are in normal working order. After power-on, the internal logic units of the FPGA respond to the loading of the configuration file. Subsequently, a configuration file (e.g., a bitstream file) containing the test circuit logic is loaded onto the FPGA board, reconfiguring the FPGA board's lookup tables, flip-flops, routing resources, and other logic units into a hardware structure corresponding to the test circuit.

[0109] Through this process, the test circuit is initialized to a runnable state and can support subsequent clock adjustments and test data processing. For example, after configuration, the test circuit can enter standby mode, waiting for control commands and test data issued by the host computer.

[0110] Step S320: The host computer sends a test control command to the test circuit and configures the dynamic clock module in the test circuit according to the test control command to adjust the timing parameters of the clock used by the test circuit.

[0111] The host computer establishes data interaction with the FPGA board via a communication link (e.g., PCIe interface) and sends test control commands to the test circuit. Upon receiving the test control commands, the test circuit writes the included clock configuration parameters into its internal control register. The dynamic clock module then reads the parameters from the internal register and adjusts the generated clock signal.

[0112] Specifically, adjusting the timing parameters of the clock used in the test circuit can include modifying the clock frequency to control the rate of test vector transmission and response acquisition. It can also include adjusting the clock phase to align the sampling edge with the data settling time, thereby ensuring the reliability of data acquisition. Furthermore, it can include configuring the clock duty cycle to optimize the triggering conditions of logic units and reduce timing deviations caused by excessively narrow or wide pulse widths.

[0113] Step S330: After the timing parameters are configured, the test host computer sends a test vector to the test circuit to drive the test circuit to perform DFT test on the chip under test using the test vector.

[0114] In this step, the host computer first preprocesses the test vector in its initial format, for example, converting a standardized WGL format file into TXT format binary data to facilitate rapid parsing and loading by the test circuit. The converted test vector is then sent to the test circuit and loaded cycle-by-cycle onto the input port of the chip under test (DUT) under configured clock conditions. Upon receiving the test vector, the DUT operates according to its circuit logic and generates a response signal. Driven by the sampling clock, the test circuit acquires the response signal returned by the chip cycle-by-cycle, temporarily storing and transmitting the acquired data.

[0115] After the DFT test is completed, the host computer will compare and analyze the sampled results to verify the functionality and timing characteristics of the chip under test. For example, the current test result is compared item by item with the target test result corresponding to the test vector in the test control command. If the current test result matches the target test result, it can be confirmed that the current clock configuration meets the test requirements. However, if the current test result does not match the target test result, the clock timing parameters need to be adjusted, and the DFT test on the chip under test will be performed again based on the adjusted timing parameters.

[0116] Through this iterative process, ideal test conditions can be gradually approximated, ultimately ensuring that the sampled data remains consistent with the actual logic state of the chip under test, thereby achieving accurate verification of the chip's functionality and timing characteristics. It is understood that the process described in steps S310 to S330 corresponds to calibrating or making necessary corrections to the clock parameters before the formal test begins, ensuring that they meet the test requirements of the chip under test. After calibration, the formal test phase begins, at which point the clock parameters remain stable and are no longer frequently adjusted, thus ensuring the continuity of the test process and the reliability of the results.

[0117] In some example implementations, a test project is built upon a development and verification platform design environment, and combined with... Figure 4 The logical architecture diagram of the chip DFT testing system shown below illustrates the chip DFT testing method in this embodiment of the disclosure:

[0118] In this embodiment, the test circuit and the host computer communicate via a PCIe interface. The IP core used is a DMA (Direct Memory Access) and bridging module. The configuration parameters of this IP core include: a PCIe 3rd generation protocol, a general width of x16, an AXI (Advanced eXtensible Interface) address width of 64 bits, and an AXI data width of 512 bits. Through this interface, the host computer can transmit test vectors to the test circuit and write them into the internal DDR (Double Data Rate) memory of the test circuit via the IP core's AXI output.

[0119] In terms of AXI architecture configuration, the PCIe AXI master interface connects to the slave end of the on-chip interconnect network. The on-chip interconnect network has three AXI master output ports, two of which are connected to two independent DDR memories, namely DDR0 memory and DDR1 memory, for reading and writing test data. Specifically, the IP cores used for DDR0 and DDR1 memory are DDR4 SDRAM (Synchronous Dynamic Random Access Memory), with each DDR memory having a capacity of 2GB. DDR0 memory is used to store test vectors from the host computer, while DDR1 memory is used to store test response signals sampled from the chip under test. Furthermore, the system clock c0_ddr4_ui_clk (channel 0 DDR4 user interface clock) output by the DDR4 memory serves as the operating clock for the AXI bus, denoted as axi_clk, ensuring consistent timing across all data channels within the system. Another path is to convert the signal to an APB bus signal via an AXI-APB (Advanced Peripheral Bus) bridge, thereby managing the configuration processing units such as registers inside the test circuit to control the functional modules.

[0120] In terms of clock generation, the test system includes a dynamic clock module that outputs three independent, adjustable clock signals: data_clk (data transmission clock), shift_clk (gated clock), and sample_clk (sampling clock), all with a default frequency of 100MHz. Data_clk drives the input / output module to output test vectors to the chip under test (DUT) cycle by cycle. Shift_clk is generated based on a 100MHz reference clock using a BUFGCE (Global Clock Buffer with Clock Enable) structure. Its enable pin is driven by the control signal carried by the test vector, used to start and stop the clock at specific cycles, thus achieving gated output. Sample_clk drives the sampling input / output module to collect the test response signals returned by the DUT. The dynamic clock module supports independent adjustment of the frequency, phase, and duty cycle of the three clock signals to adapt to the timing requirements of different test sequences. This multi-channel independent clock adjustment mechanism allows the test system to maintain flexibility while ensuring high-precision timing matching, avoiding the insufficient adaptability problems caused by fixed clock configurations.

[0121] In terms of data transmission, the test system is equipped with a data transmission link and a data sampling link. The data transmission link consists of an AXI read processing unit and a read FIFO buffer. The AXI read processing unit reads test vectors from DDR0 memory and writes them to the read FIFO buffer. The write clock for the read FIFO buffer is axi_clk, and the read clock is data_clk; its bit width is 128 bits, and its depth is 16384. The test vectors are output from the read FIFO buffer and then sent to the driver input / output module, and loaded cycle-by-cycle to the input terminals of the chip under test. The data acquisition link consists of an AXI write processing unit and a write FIFO buffer. The output signal of the chip under test is first input to the sampling input / output module, and then written to the write FIFO buffer. The write clock for the write FIFO buffer is sample_clk, and the read clock is axi_clk. The acquired signal is sent to DDR1 memory via the AXI write processing unit module for subsequent analysis and processing. This dual-channel design ensures decoupling of the data transmission and acquisition processes in the clock domain, improving the stability of data processing and system throughput.

[0122] For data verification, the test system is also equipped with a data comparison module, which compares the actual response data collected by the input / output modules with the expected response data cycle by cycle. During the comparison process, if inconsistencies are found, the number of error cycles is accumulated in the register, facilitating error statistics and localization analysis by testers in subsequent stages. Furthermore, the data comparison results can be fed back to the host computer via register mapping to quickly locate abnormal timing or functional failure points, thereby improving debugging efficiency.

[0123] In terms of control interaction, the configuration processing unit, as the core configuration control logic, connects the AXI-APB bridge and other modules. It is used to configure parameters and manage the status of functional modules such as the dynamic clock module and data comparison module based on register write operations issued by the host computer. Through this configuration mechanism, the host computer can flexibly adjust the operating conditions of the test circuit. For example, the configuration processing unit can modify clock configuration parameters or reset some logic modules in real time without interfering with the main test process, thereby enhancing the system's maintainability and fault tolerance.

[0124] Specifically, the host computer communication module interacts with the FPGA board via the PCIe interface. On one hand, it loads test vectors into DDR0 memory; on the other hand, it configures the dynamic clock module and related registers through the AXI-APB interface, enabling dynamic adjustment of clock parameters (frequency, phase, duty cycle). Through this interaction mechanism, the host computer can remotely perform fine-grained control of the testing process.

[0125] During the actual testing process, the data output module, driven by `data_clk`, loads the test vectors to the chip under test (DUT) cycle by cycle, while simultaneously outputting `shift_clk` as a sampling gating signal. The data input module, driven by `sample_clk`, collects the output response of the DUT and stores it in DDR1 memory. The host computer then compares, analyzes, and generates a test report. In large-scale testing scenarios, this process can be combined with a batch testing mechanism to achieve continuous execution, thereby avoiding repetitive manual operations and improving testing efficiency.

[0126] In summary, Figure 4 The chip DFT testing system shown utilizes a PCIe interface, an AXI bus structure, and the collaborative operation of DDR0 and DDR1 memory. It combines a data transmission link consisting of an AXI read processing unit / read FIFO buffer / drive input / output module, a data acquisition link consisting of an AXI write processing unit / write FIFO buffer / sampling input / output module, and a control and comparison link consisting of a data comparison module, a configuration processing unit, and a dynamic clock module. This enables the loading of test vectors, the acquisition of the chip under test's response, the storage and verification of results, and supports dynamic configuration of multiple adjustable clock signals, thus ensuring the accuracy, flexibility, and scalability of the testing process.

[0127] In this example implementation, a configurable clock module, a complete data read / write channel, and a host computer remote communication interface enable accurate transmission of chip test vectors and synchronous sampling of response data, exhibiting high adjustability and flexibility. Furthermore, the test system can perform DFT testing on the chip while ensuring flexible clock configuration and data stream integrity, and possesses strong scalability and remote operability.

[0128] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when run on an electronic device, causes the electronic device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. This program product may be a portable compact disc read-only memory (CD-ROM) including program code and may run on an electronic device, such as a personal computer. However, the program product of this disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0129] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0130] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0131] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0132] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C#, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0133] Exemplary embodiments of this disclosure also provide a chip DFT testing apparatus capable of implementing the above-described method. Referring below... Figure 5 To describe an electronic device 500 according to such an exemplary embodiment of the present disclosure. Figure 5 The electronic device 500 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0134] like Figure 5 As shown, the electronic device 500 can be represented in the form of a general-purpose computing device. The components of the electronic device 500 may include, but are not limited to: at least one processing unit 510, at least one storage unit 520, a bus 530 connecting different system components (including storage unit 520 and processing unit 510), and a display unit 540.

[0135] Storage unit 520 stores program code that can be executed by processing unit 510, causing processing unit 510 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, processing unit 510 can perform... Figure 3 The methods and steps in the text.

[0136] Storage unit 520 may include readable media in the form of volatile storage units, such as random access memory (RAM) 521 and / or cache memory (Cache) 522, and may further include read-only memory (ROM) 523.

[0137] Storage unit 520 may also include a program / utility 524 having a set (at least one) program module 525, such program module 525 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0138] Bus 530 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0139] Electronic device 500 can also communicate with one or more external devices 600 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 500, and / or with any device that enables electronic device 500 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 550. Furthermore, electronic device 500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 560. As shown, network adapter 560 communicates with other modules of electronic device 500 via bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0140] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method according to the exemplary embodiments of this disclosure.

[0141] Furthermore, the above figures are merely illustrative representations of the processes included in the methods according to exemplary embodiments of this disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0142] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0143] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0144] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A chip DFT test system, characterized in that, The application relates to a test system for DFT (Design For Test) of a chip, which comprises an FPGA (Field Programmable Gate Array) board and a test host computer, wherein the test host computer is in communication connection with the FPGA board and is used for sending a test control instruction to a test circuit; the FPGA board is loaded with the test circuit and is used for performing DFT test on a chip to be tested; the test circuit comprises a dynamic clock module which is configured to generate a clock for driving the test circuit and to adjust a timing parameter of the clock according to the test control instruction received by the test circuit. The dynamic clock module is configured to generate at least one of a data transmission clock, a sampling clock and a gate clock; The timing parameter comprises frequency, phase and duty cycle; The dynamic clock module is further configured to adjust the frequency, phase and duty cycle of at least one of the data transmission clock, the sampling clock and the gate clock according to the test control instruction.

2. The chip DFT test system of claim 1, wherein, The test circuit further comprises a host computer communication module which is connected with the test host computer, is used for receiving the test control instruction sent by the test host computer, and configures an internal register of the test circuit according to the test control instruction so that the dynamic clock module adjusts the timing parameter of the clock according to the configuration parameter in the internal register. The host computer communication module is further used for receiving a test vector issued by the test host computer, receiving a test result obtained by performing DFT test on the chip to be tested based on the test vector, and returning the test result to the test host computer.

3. The chip DFT test system of claim 2, wherein, The test circuit further comprises a test vector storage module which is used for storing the test vector received by the host computer communication module; a test vector import module which is used for importing the test vector in the test vector storage module into the chip to be tested; a test result export module which is used for importing the test result output by the chip to be tested into a test result storage module; and the test result storage module which is used for storing the test result. The test vector comprises a reference test vector and an actual test vector.

4. The chip DFT testing system of claim 1, wherein, The test circuit further comprises a test result comparison module which is used for comparing a reference test result output by the chip to be tested with a corresponding target test result, determining whether the timing parameter of the clock of the test circuit meets a timing adaptation condition according to a first comparison result, adjusting the timing parameter when the timing parameter does not meet the timing adaptation condition, comparing an actual test result output by the chip to be tested with a corresponding target test result, and determining whether the chip to be tested passes the DFT test according to a second comparison result. ​ 5. The chip DFT test system of claim 4, wherein, ​ 6. The chip DFT test system of claim 5, wherein, ​ ​ ​ ​ ​ 7. The chip DFT test system of claim 6, wherein, ​ ​ ​ The reference test result is a test result obtained by performing DFT test on the chip to be tested by using the reference test vector; the actual test result is a test result obtained by performing DFT test on the chip to be tested by using the actual test vector; the target test result corresponding to the reference test result is determined by a test host computer according to the reference test vector and is delivered to the test result comparison module; and the target test result corresponding to the actual test result is determined by the test host computer according to the actual test vector and is delivered to the test result comparison module.

8. The chip DFT testing system of claim 1, wherein, The system further comprises: a general server configured to establish a communication connection between the FPGA board card and a terminal device in which the test host computer is deployed; the test host computer comprises: a remote communication module configured to send a test control command to the general server and receive a test result returned by the FPGA board card after the test control command is executed through the general server in a case that the terminal device accesses the general server.

9. The chip DFT testing system of claim 8, wherein, The test host computer further comprises: a clock configuration module configured to generate the test control command to configure a timing parameter of a clock generated by the dynamic clock module.

10. The chip DFT test system of claim 8, wherein, The test vector comprises a first test vector and a second test vector; The test host computer further comprises: a test vector conversion module configured to convert the first test vector in an initial format into the second test vector in a target format; a test vector loading module configured to send the second test vector generated by the test vector conversion module to the test circuit in the FPGA board card through the remote communication module.

11. The chip DFT test system of claim 10, wherein, The initial format is a test vector description format, and the target format is a digital vector data format.

12. The chip DFT testing system of claim 8, wherein, The test host computer further comprises: a test result downloading module configured to transmit the test result to the terminal device through the remote communication module to generate a test report according to the test result.

13. The chip DFT testing system of any of claims 8 to 12, wherein, The test host computer further comprises: a batch test module configured to send a plurality of second test vectors to the test circuit in the FPGA board card through the remote communication module in sequence and transmit the corresponding test result received to the terminal device to generate a test report.

14. A method of chip DFT testing, the method comprising: The method is applied to a chip DFT test system, and the method comprises: powering on an FPGA board card and loading a configuration file representing a test circuit to enable the FPGA board card to run the test circuit; sending a test control instruction to the test circuit through a test host computer and configuring a dynamic clock module in the test circuit according to the test control instruction to adjust a timing parameter of a clock used by the test circuit; after the timing parameter is configured, sending a test vector to the test circuit through the test host computer to drive the test circuit to perform DFT test on a chip to be tested by using the test vector.

15. The chip DFT testing method of claim 14, wherein, After the DFT test is completed, the method further comprises: comparing a current test result with a target test result corresponding to the test vector in the test control instruction; and When the current test result is inconsistent with the target test result, a timing parameter of the clock is adjusted, and DFT test is re-performed on the chip under test based on the adjusted timing parameter.

16. A chip DFT test apparatus, characterized by, The chip DFT test method comprises the steps of: a processing unit; and a storage unit for storing executable instructions of the processing unit; wherein the processing unit is configured to execute the chip DFT test method of any one of claims 14-15 by executing the executable instructions.

17. A computer readable storage medium having stored thereon a computer program, characterized in that The computer program, when executed by the processing unit, implements the chip DFT test method of any one of claims 14-15. The computer program, when executed by the processing unit, implements the chip DFT test method of any one of claims 14-15.

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