Sensor systems, methods, and instructions operating at multiple clock frequencies

Abstract

The invention relates to sensor systems, methods, and instructions operating at multiple clock frequencies. Methods, apparatus, systems, and articles of manufacture corresponding to sensor systems operating at multiple clock frequencies are described. An example system includes a radio frequency (RF) phase-locked loop (PLL) (114) that generates an output signal at a first frequency; a microcontroller (146) operating at a second frequency, the first frequency being a multiple of the second frequency; a transmitter (128) that outputs a chirp signal having a chirp period selected based on the second frequency; a receiver (130) that receives a reflected signal corresponding to the chirp signal; and a filter (138) that filters out Doppler bins corresponding to the reflected signal based on the chirp period.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims the benefit of and priority to Indian Provisional Patent Application No. 202441067207, filed September 5, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] This specification generally relates to computing devices, and more particularly to sensor systems, methods, and instructions operating at multiple clock frequencies. BACKGROUND

[0004] Manufacturers of integrated circuits (ICs) have developed technology to manufacture compact ICs that incorporate components of a computer or other electronic system. Such ICs are referred to as system on a chip or SoC. Such SoCs include transceivers, processor cores, memory, input / output ports, and auxiliary storage, all on the same substrate or in the same package. Depending on the application, a SoC can include digital, analog, mixed-signal, radio-frequency (RF), or other signal processing functionality.

[0005] Some SoCs include radar components. Radar components enable object detection in any number of environments. The automotive industry includes radar components in some vehicles to enable improved safety features, such as driver attention monitoring, object avoidance, emergency braking, and the like. SUMMARY

[0006] For a sensor system operating at multiple clock frequencies, one example apparatus includes a radio frequency (RF) phase-locked loop (PLL) that generates an output signal at a first frequency, a microcontroller that operates at a second frequency, the first frequency being a multiple of the second frequency, a transmitter that outputs a chirp signal having a chirp period selected based on the second frequency, a receiver that receives a reflected signal corresponding to the chirp signal, and a filter that filters out Doppler bins corresponding to the reflected signal based on the chirp period. Other examples are described.

[0007] For a sensor system operating at multiple clock frequencies, one example method includes generating an output signal at a first frequency, operating a core at a second frequency, the first frequency being a multiple of the second frequency, outputting a chirp signal having a chirp period selected based on the second frequency, receiving a reflected signal corresponding to the chirp signal, and filtering out Doppler bins corresponding to the reflected signal based on the chirp period. Other examples are described.

[0008] For a sensor system operating at multiple clock frequencies, an example instruction causes at least one programmable circuit to: select a first frequency of a first clock signal to be generated by a radio frequency (RF) phase-locked loop (PLL), the first clock signal used to generate a second clock signal at a second frequency, the first frequency selected based on a harmonic of the first clock signal and a harmonic of the second clock signal; select a chirp period of a chirp signal to be output by a transmitter of a radar, the chirp period of the chirp signal based on the second frequency of the second clock signal; cause a phase-locked loop to generate the first clock signal at the first frequency; and cause a transceiver to output the chirp signal based on the selected period. Other examples are described. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example system on a chip that implements radar in conjunction with the examples described herein is illustrated.

[0010] Figure 2 An alternative system on a chip that implements radar in conjunction with the examples described herein.

[0011] Figures 3 to 5 A flow diagram representing hardware operations, example machine-readable instructions, or example operations that can be performed, instantiated, or conducted by example programmable circuitry to implement a system on a chip of Figure 1 or 2 is illustrated.

[0012] Figure 6A An example range Doppler representation corresponding to a ghost target that is present based on a mismatch in frequencies corresponding to a clock signal generated by an oscillator and a clock signal used by a processor core of a system on a chip is illustrated.

[0013] Figure 6B An example range Doppler representation corresponding to a ghost target that has been moved to a maximum Doppler bin to enable filtering out of the ghost target using examples described herein is illustrated.

[0014] Figure 6C An alternative example range Doppler representation corresponding to a ghost target that has been moved zero Doppler bins to enable filtering out of the ghost target using examples described herein is illustrated.

[0015] Figure 7 An example chirp signal output by a system on a chip of Figure 1 or 2 is illustrated.

[0016] Figure 8 A block diagram of an example processing platform that includes programmable circuitry configured to execute, instantiate, or conduct example machine-readable instructions or conduct example operations of Figures 3 to 5 to implement a system on a chip of Figure 1or 2.

[0017] Figure 9 is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) to distribute software, instructions, or firmware (e.g., corresponding to Figures 3 to 5 example machine-readable instructions) to client devices associated with end users or consumers (e.g., for licensing, sale, or use), retailers (e.g., for sale, resale, licensing, or sub-licensing), or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, e.g., retailers or other end users (e.g., direct purchase customers)).

[0018] The same reference numbers or other reference indicators in the drawings indicate the same or similar (functionally or structurally) features. DETAILED DESCRIPTION

[0019] The drawings are not necessarily to scale. Generally, the same reference numbers in one or more drawings indicate the same or similar parts throughout the several drawings. Although the drawings depict zones with clear lines and boundaries, some or all of these lines or boundaries can be idealized. In practice, the boundaries or lines can be invisible, blended, or irregular.

[0020] Radar systems often utilize radar sensors to generate data for detecting obstacles and measuring physical distances, velocities, or directions corresponding to the obstacles. Radar systems can be used by any industry, including the automotive industry, which enables improved safety features (e.g., driver monitoring, object avoidance, emergency braking, etc.) and new autonomous driving features (e.g., navigation). Example radar systems can include, but are not limited to, a system-on-a-chip (SoC) device that communicates with or otherwise interacts with other processing devices to interpret radar data. In some examples, the SoC is electrically interfaced or otherwise in communication with a processing device to instantiate a warning or informational prompt regarding an obstacle parameter in view of a proximity limit, the processing device to facilitate user interaction / interface, etc.

[0021] A radar system operates by transmitting a chirp signal via an antenna. As used herein, a "chirp signal," "chirp," "radar chirp," or "radar signal" is an analog signal that is typically transmitted repeatedly over a set period of time (e.g., in a frame) representing radar information / data. If an object is in the path of the transmitted chirp signal, the chirp signal is reflected back to the antenna of the radar system. Generally, the reflected radar chirp is received or otherwise detected by the radar system and digitized to produce sample data. As used herein, "sample data" or "samples" is the digitized output from one or more analog-to-digital converters (ADCs), and this sample data can be stored in memory. Further, the radar system can include a processor core to process the sample data in conjunction with one or more signal processing techniques (e.g., a Fast Fourier Transform (FFT)) to produce processed radar data that is produced from the sample data that has been modified in conjunction with one or more digital signal processing (DSP) techniques or algorithms.

[0022] In some examples, sample data corresponding to a reflected chirp is subjected to a range FFT to convert the sample data to a frequency domain representation. Peaks correspond to the range (physical distance) of an object, and this range FFT processing can be performed on sample data corresponding to a previous chirp while other sample data corresponding to a current chirp is being collected (e.g., sometimes referred to as pipelining). The results of the range FFT can be stored in memory for further processing (e.g., processing to produce Doppler FFT or angle FFT data).

[0023] Some radar systems are designed to operate using one or more clock signals with specific frequencies to avoid ghosting targets. Ghosting targets are targets that appear in the Doppler FFT but do not actually exist. If a ghosting target appears in the Doppler FFT, the radar system informs the processing circuitry or user that an object exists at a specific physical distance or is moving at a specific speed, but the object does not actually exist. The presence of ghosting targets is based on a mismatch in the frequencies of the different clock signals used by components in the radar system. For example, ghosting targets may occur if M(MCU_CLK) ≠ N(XTAL_CLK), where M is an integer value, N is an integer value, MCU_CLK is the frequency of the clock applied to the microcontroller core of the radar system, and XTAL_CLK is the frequency of the clock generated by the oscillator that produces all the clock signals for the radar system. Ghosting targets occur if, for some value of M and N, the frequency M(MCU_CLK) – N(XTAL_CLK) is between 0 and the supported intermediate frequency (IF) bandwidth of the radar device (e.g., 10 MHz). In a given instance, for M = 5 and N = 1, then 0 ≤ M(MCU_CLK) - N(XTAL_CLK) ≤ 10 MHz. Some radar systems choose a clock signal for the microcontroller core such that M(MCU_CLK) = N(XTAL_CLK) to prevent ghosting of targets.

[0024] However, it may be necessary to adjust the frequency of the clock signal used by the MCU core to avoid bandwidth limitations or conserve power. For example, if the MCU uses a clock signal at a frequency of 200 MHz, then the MCU will generate a 200 MHz transmission and multiple harmonics at frequencies of 200 MHz (e.g., 400 MHz, 600 MHz, 800 MHz, etc.). If there is a standard that limits electromagnetic emissions to a specific narrow band (e.g., 1.6 GHz), then the radar could be limited to operating the MCU at 200 MHz because 1.6 GHz is a harmonic of 200 MHz (e.g., 200 MHz * 8 = 1.6 GHz). Therefore, the radar system will generate transmissions within a limited bandwidth. Adjusting the frequency of one or more clock signals to avoid bandwidth limitations can lead to ghosting targets in Doppler FFT.

[0025] To avoid emissions within a restricted frequency band, the examples described herein adjust the frequency of a radio frequency (RF) phase-locked loop (PLL) that generates clock signals at different frequencies for different components of the radar system. For example, the RF PLL converts a clock signal from a first frequency (e.g., 40 MHz) from an oscillator circuit system into a higher frequency clock signal (e.g., approximately 14.4 GHz). The output of the RF PLL is divided by one or more integers to generate clock signals at different frequencies for different components of the radar system. For example, a 14.4 GHz signal divided by 72 produces a 200 MHz signal applied to the MCU core. Therefore, if the harmonics emitted by the MCU core are within a restricted frequency band, the examples described herein adjust the frequency of the RF PLL output, adjusting the frequency of the clock signal used by the MCU, which in turn adjusts the harmonics. For example, if the restricted frequency band is 1.6 GHz, the RF PLL could output a clock signal at 14.32 GHz (e.g., instead of 14.4 GHz), causing the MCU core to operate at a frequency of 198.89 MHz. Because the harmonics of the 198.89MHz clock signal used for the MCU core are outside the 1.6GHz band (for example, 198.89MHz * 8 = 1.59GHz, which is outside the 1.6GHz band), the harmonics of the MCU core no longer cause emissions within the restricted 1.6GHz band.

[0026] Although adjusting the frequency of the clock signal output by the RF PLL results in harmonics outside the restricted band, adjusting the frequency of the clock signal used by the MCU ensures that M(MCU_CLK) ≠ N(XTAL_CLK). As mentioned above, if M(MCU_CLK) ≠ N(XTAL_CLK), then the ghosted target will appear at the range offset of M(MCU_CLK) - N(XTAL_CLK) on the rangefinder Doppler display (e.g., due to the coexistence of several components of the radar system operating at different frequencies). The examples described herein adjust the period of the chirp to move the ghosted target to a specific Doppler compartment (also known as a range-Doppler compartment) so that the ghosted target can be filtered out. The examples described herein can adjust the period of the chirp signal so that the ghosted target appears at the maximum positive or negative Doppler or the zero Doppler in the Doppler display. By moving the ghosted target to a predefined Doppler compartment, the examples described herein can filter out the Doppler compartment at a predefined frequency to remove the ghosted target. As used herein, the Doppler chamber is a direct representation of an object's velocity. A zero Doppler chamber means the object is static relative to the radar system, while a high Doppler chamber indicates the object is moving at a high velocity relative to the radar system. Therefore, the examples described herein adjust the clock signal frequency to avoid transmissions within a limited frequency band, while mitigating ghosting of targets caused by the adjusted clock signal frequency. Although the examples described herein adjust the clock frequency to avoid a limited frequency band, the examples described herein can also adjust the clock frequency to support lower clock frequency operation for increased power savings.

[0027] Figure 1 An example radar system 100 is illustrated, which can detect objects or object speeds by transmitting signals and analyzing reflected signals. The radar system 100 includes an example timing circuit system 102, an example transceiver 104, an example processor core 106, an example interconnect bus matrix 110, and example peripheral components 112. The timing circuit system includes an example radio frequency (RF) phase-locked loop (PLL) 114 and example frequency divider circuit systems 116 and 118. The transceiver 104 includes an example frequency modulated continuous wave (FMCW) PLL 120, an example frequency multiplier 122, an example phase shifter circuit system 124, example amplifiers 126 and 132, an example antenna 128 and 130, an example mixer circuit system 134, an example analog-to-digital converter (ADC) 136, and an example digital filter 138. The instance processor core 106 includes an instance random access memory 140, an instance application software processor core 142, an instance radar data fast Fourier transform (FFT) calculation processor core 144, and an instance RF microcontroller processor core 146. Figure 1 It further includes a processing unit 148 and an instance oscillator 150. The processor core 106 may include, in combination with the following: Figure 2 Additional or alternative cores described further.

[0028] Figure 1 The radar system 100 may be a system-on-a-chip (SoC) comprising multiple components to detect objects or the velocity of objects by transmitting signals and analyzing reflected signals. The timing circuitry 102 of the radar system 100 obtains a clock signal at a specific frequency (e.g., 40 MHz) from the oscillator 150 and converts the clock signal into multiple other clock signals of different frequencies to be applied to other components of the radar system 100. The RF PLL 114 is a control circuitry that increases the frequency by multiplying the frequency of the clock signal output from the oscillator 150 by an integer to generate a high-frequency clock (e.g., above 14 GHz). In some instances, the oscillator 150 may be implemented in the processing device 148 or within the radar system 100. As further described below, the RF PLL 114 generates a specific high-frequency clock signal, which, when divided by one or more frequency divider circuitry systems 116, 118, produces different clock signals that can be used by different components of the radar system 100. RF PLL 114 generates a specific high-frequency clock signal such that harmonics of different clock signals generated from the high-frequency clock signal do not fall within the restricted frequency band. For example, if the 1.6 GHz band is restricted, RF PLL 114 will generate a high-frequency clock signal that, when divided into low-frequency clock signals, will not generate harmonics within the 1.6 GHz band. However, RF PLL 114 cannot adjust the frequency of the generated clock signal too much because components of radar system 100 that depend on the generated clock signal may only operate within a specific frequency range. RF PLL 114 outputs the generated high-frequency clock signal to frequency divider circuit systems 116, 118 to generate low-frequency signals for other components of radar system 100. Frequency divider circuit systems 116, 118 output / provide the low-frequency clock signal to one or more of transceiver 104, processor core 106, or peripheral devices 112 for use during operation.

[0029] Figure 1 The FMCW PLL 120 obtains a clock signal from the frequency divider 116 and generates a chirp signal based on the obtained clock signal. The chirp signal is a signal that increases or decreases over time between a first frequency and a second frequency. The following section combines... Figure 7 The chirp signal is further described in the example. As mentioned above, the period of the chirp signal (e.g., wafer periodicity) causes the ghosted target (if present) to move to a predefined position within the Doppler representation. For example, the FMCW PLL 120 generates a chirp signal with a specific period to ensure that the ghosted target will appear at the maximum velocity range or zero velocity that the radar system 100 can recognize. Equation 1 below illustrates the position where the ghosted target will appear.

[0030] ghost_targetrange_offset = M(MCU_CLK)-N(XTAL_CLK) (Equation 1)

[0031] In Equation 1 above, ghost_target range_offset This is the distance frequency offset between the ghosted target and the actual object in the distance Doppler representation of the actual object. M is an integer value (e.g., 1), N is an integer value (e.g., 5), MCU_CLK is the frequency of the clock signal used by the RFMCU processor core 146, and XTAL_CLK is the frequency of the clock signal generated by the oscillator 150. To adjust the Doppler chamber of the ghosted target, the FMCW PLL 120 adjusts the chirp period to R(1 / (2*ghost_target)). range_offset Where R is an integer. If R is an odd integer, the Doppler of the ghosted target is shifted to the maximum Doppler frequency (e.g., the maximum positive or negative Doppler frequency) configured by the radar system 100 for detection (e.g., corresponding to a high-speed detected object). If R is an even integer, the Doppler of the ghosted target is shifted to the zero Doppler frequency (e.g., corresponding to a non-moving identified object). As further described below, the frequency shift corresponds to the distance difference between the ghosted object and the actual object. In this way, since the ghosted target appears at a predefined Doppler bin, the Doppler bin can be filtered out to remove the ghosted target.

[0032] Figure 1 The frequency multiplier circuit system 122 doubles the frequency of the FMCW PLL 120 to increase the frequency chirp signal generated by the FMCW PLL 120 to a frequency range, which can be determined before operation. The frequency multiplier circuit system 122 outputs the final chirp signal to the phase shift circuit system 124 and the mixer circuit system 134. The phase shift circuit system 124 adjusts the phase of the chirp signal output by the frequency multiplier circuit system 122. The phase shift circuit system 124 outputs the phase-shifted chirp signal to the amplifier 126. The amplifier 126 may be a power amplifier that amplifies the phase-shifted chirp signal from the phase shift circuit system 124 and outputs the amplified phase-shifted chirp signal to the antenna 128. The antenna 128 outputs the chirp signal. If the chirp signal reaches an object, the signal will be reflected from the object and travel back to the radar system 100 (e.g., obtained via the antenna 130). In the illustrated example, there are three phase shifters 124 that are coupled to three amplifiers 126, which are coupled to three antennas 128, thereby forming three transmission channels.

[0033] Figure 1Antenna 130 receives reflected chirped signals (e.g., chirped signals output from antenna 128 and reflected from an object / target). Amplifier 132 may be a linear amplifier that amplifies one or more of the acquired reflected signals and outputs the amplified reflected signals to mixer circuitry 134. Mixer circuitry 134 mixes the signals received from the corresponding amplifier 132 with the signals output from frequency multiplier circuitry 122. For example, mixer circuitry 134 may combine (e.g., add, subtract, etc.) the frequency of the chirped signal output from frequency multiplier 122 with the frequency of the reflected signal obtained from the corresponding antenna 130. Because the signal from frequency multiplier 122 is transmitted via antenna 128 and then acquired via antenna 130, there will be some delay in the acquired signal. Mixer circuitry 134 combines the acquired signal with the transmitted signal to generate an IF signal, which corresponds to the amount of delay in the acquired signal, the amount of delay corresponding to the physical distance from the detected object. ADC 136 converts the IF signal from mixer circuitry 134 from an analog signal to a digital signal. Digital filter circuitry 138 filters the digital signal from ADC 136 to remove potentially irrelevant frequencies from nearby objects or distant sources. The filtered signal is then passed to one or more processor cores 106 for analysis or storage of the results. In the illustrated example, there are four receive channels, each containing a corresponding one of the four antennas 130, a corresponding one of the four mixers 134, a corresponding one of the four ADCs 136, and a corresponding one of the four digital filters 138. Other examples may contain more... Figure 1 The number of more or fewer transmit and receive channels is shown.

[0034] The results (e.g., samples) of the obtained signal are passed from digital filter 138 to one or more processor cores 106. For example, the results may be stored in RAM 140 or processed by radar data FFT calculation processor core 144 or RF MCU processor core 146. Application software processor core 142 determines the frequency of the clock signal to be generated by RF PLL 114. As described above, the frequency of the clock signal to be generated by RF PLL 114 is selected to ensure that the frequency of the clock signal, the harmonics of the clock signal, one or more frequencies of any of the other clock signals generated by frequency divider circuit systems 116, 118, or the harmonics of the other clock signals generated by frequency divider circuit systems 116, 118 are not within the restricted frequency band. Therefore, application software processor core 142 can determine the frequency of the clock to be generated by RF PLL 114 such that the frequencies or harmonics of multiple clock signals are outside one or more restricted frequency bands. Alternatively, application software processor core 142 can reduce the frequency of the clock signal generated by RF PLL 114 for low-power mode. After the application software processor core 142 selects the frequency of the clock signal to be generated by the RF PLL 114, the application software processor core 142 provides instructions to the RF PLL 114 to generate the clock signal at the selected frequency. Furthermore, the application software processor core 142 determines the range offset of the ghosted target in the range Doppler representation based on Equation 1 above. The application software processor core 142 is based on R(1 / (2*ghost_target) range_offset The period of the chirped signal generated by the FMCW PLL 120 is selected, where R is an integer. As described above, if R is an odd integer, the Doppler of the ghosted target is shifted to the maximum Doppler frequency (e.g., the maximum positive or negative Doppler frequency) that the radar system 100 is configured to detect (e.g., corresponding to a high-speed detected object). If R is an even integer, the Doppler of the ghosted target is shifted to the zero Doppler frequency (e.g., corresponding to a non-moving identified object). After the application software processor core 142 selects the chirped period, it provides instructions to the FMCW PLL 120 to generate the chirped signal based on the selected period.

[0035] Figure 1 The radar data FFT calculation processor core 144 can be a hardware accelerator that processes samples obtained from RAM 140 or from digital filters 138 to generate one or more range Doppler representations of the samples. The one or more range Doppler representations may include range-Doppler heatmaps or Doppler-dimensional FFTs. A range-Doppler heatmap is a representation of how the processed signal changes with distance and relative velocity. In the range-Doppler heatmap, the identified object is represented by a peak in the heatmap, corresponding to the physical distance from the radar system 100 and the object's velocity. The following section combines...Figures 6A to 6C Further description of the instance visual representation of the distance-Doppler heatmap. The Doppler-dimensional FFT corresponds to the frequency domain of the distance-Doppler heatmap. The Doppler-dimensional FFT plots the detected objects and their corresponding Doppler signatures. The following section combines... Figures 6A to 6C Further describe the instance visual representation of the Doppler-dimensional FFT.

[0036] Figure 1 The RF MCU processor core 146 controls the operation of various components of the radar system 100. Furthermore, the RF MCU processor core 146 can analyze one or more range Doppler representations generated by the radar FFT calculation processor core 144. For example, the RF MCU processor core 146 can process one or more range Doppler representations to determine whether one or more objects have been detected or the velocity of the detected objects. In some instances, the RF MCU processor core 146 can filter out Doppler bins (e.g., range offsets within the range Doppler representation) based on the period of the chirp signal. As described above, the period of the chirp signal generated by the FMCW PLL 120 can be selected to move the ghosted target to a specific range offset (e.g., a maximum Doppler bin or a zero Doppler bin). Therefore, the RF MCU processor core 146 can filter out bins in one or more range Doppler representations corresponding to the maximum or zero Doppler bin (based on the period of the chirp signal). In this way, ghosted targets generated by adjusting the RF PLL 114 will be filtered out. The RF MCU processor core 146 can output processed analysis data to the processing device 148 via the interconnect bus matrix 110 and peripheral devices 112. The interconnect bus matrix 110 routes control or data signals from the peripheral devices 112 to one or more of the processor cores 106 and vice versa. The peripheral devices 112 are components that can interface with other components outside the radar system 100. (The following is in conjunction with...) Figure 2 Further descriptions of examples of different peripheral devices are provided.

[0037] Figure 1 The processing device 148 receives the results from the RF MCU processor core 146 to perform one or more actions (e.g., generating an alarm, activating autopilot, etc.) based on the results (e.g., the position or velocity of a detected object). In some instances, the processing device 148 may perform filtering on one or more Doppler bins of the distance Doppler representation. For example, instead of filtering on the Doppler bins corresponding to ghosted targets, the processing device 148 may perform filtering.

[0038] Figure 1The oscillator 150 is a device that generates a clock signal at a specific frequency. For example, the oscillator 150 may be a crystal oscillator that generates a clock signal at 40 MHz. The oscillator 150 outputs the clock signal to the RF PLL 114. As described above, the RF PLL 114 uses the clock signal to generate a high-frequency clock signal.

[0039] Figure 2 The drawing corresponds to Figure 1 The radar system 100 includes an instance of radar system 200 with an additional processor core and peripheral devices. Radar system 200 includes... Figure 1 The instance timing circuitry includes an instance timing system 102, an instance transceiver 104, an instance processor core 106, an instance interconnect bus matrix 110, and instance peripheral components 112. The timing circuitry includes... Figure 1 Examples include a radio frequency (RF) phase-locked loop (PLL) 114 and example frequency divider circuit systems 116 and 118. Transceiver 104 includes... Figure 1 The example includes a Frequency Modulated Continuous Wave (FMCW) PLL 120, a frequency multiplier 122, a phase shift circuit system 124, amplifiers 126 and 132, an antenna 128 and 130, a mixer circuit system 134, an analog-to-digital converter (ADC) 136, and a digital filter 138. The example processor core 106 includes... Figure 2 The example application software processor core 142, the example radar data fast Fourier transform (FFT) calculation processor core 144, and the example RF microcontroller processor core 146. Figure 1 Further include Figure 2 The processing device 148 and the example oscillator 150. Figure 2 The processor core 106 further includes instance Level 3 (L3) RAM 202, instance hardware accelerator processor core 204, instance digital signal processor software core 206, instance security hardware core 208, instance security cortex core 210 and Level 2 (L2) RAM 212. Figure 2 Peripheral devices 112 include an example Low Voltage Differential Signaling (LVDS) circuit system, CSI2 214, an example Ethernet 216, an example Controller Area Network Flexible Data Rate (CAN-FD) circuit system 218, an example Serial Peripheral Interface (SPI) 220, an example Joint Test Action Group (JTAG) / Universal Asynchronous Receiver / Transmitter (UART) circuit system 222, an example Real-Time Interrupt (RTI) timer 224, an example frame / ramp timer 226, and examples of hybrid peripheral components 228 and 230. Although radar system 200 includes... Figure 3The processor core 106 or peripheral device 112 may be a specific processor core 106 or peripheral device 112, but the processor core 106 or peripheral device may contain additional or alternative components. In addition, one or more of the processor core 106 or peripheral device 112 may be combined or removed.

[0040] Figure 1 This is a flowchart representing instance machine-readable instructions or instance operations 300, which can be executed, instantiated, or are in progress by at least one programmable circuit system to select the machine-readable instructions or instance operations to be executed by. Figure 3 The RF PLL114 generates a clock signal frequency to avoid transmission within a limited frequency band, or to switch resources and select a chirp period to adjust the ghosting target to a predefined Doppler bin. Figure 3 An instance of machine-readable instructions or instance of operation 300 begins at block 302, where the application software processor core 142 defines one or more restricted frequency bands. For example, one or more standards may define one or more restricted frequency bands based on the location and manner in which the radar system 100 is implemented.

[0041] At block 304, application software processor core 142 selects the RF PLL clock frequency. In some instances, application software processor core 142 may initially select an RF PLL clock frequency that results in M(MCU_CLK) = N(XTAL_CLK), where M and N are integers (e.g., 1 and 5, respectively), MCU_CLK is the frequency of the clock applied to RF MCU processor core 146, and XTAL_CLK is the frequency of the clock signal generated by oscillator 150. As described above, when M(MCU_CLK) = N(XTAL_CLK), there will be no ghosting targets. At block 306, application software processor core 142 determines the RF MCU clock frequency based on the selected RF PLL clock frequency. For example, if application software processor core 142 selects an RF PLL clock frequency of 14.4 GHz and the RF MCU clock frequency is configured as the RF PLL clock frequency divided by 72, then application software processor core 142 determines the RF MCU clock frequency to be 200 MHz (e.g., 14.4 GHz / 72). Although Figure 3 The description is based on the RF MCU clock frequency, but Figure 1 Can be combined with Figure 3 The timing circuitry 102 generates or is described by any clock signal used by any component of the radar system 100. For example, Figure 1 Can be combined with Figure 4 The clock signals used by one or more of the ADC 136, FMCW PLL 120, processor core 106, or peripheral devices 112 are described.

[0042] At box 308, the application software processor core 142 determines the harmonics of the clock signal used by the RF MCU or the clock signal generated by the RF PLL. For example, if the RF MCU clock has a frequency of 200MHz and the RF PLL has a frequency of 14.4GHz, then the application software processor core 142 determines that the harmonic of the RF MCU clock signal is X (200MHz), where X is a positive integer, and the harmonic of the RF PLL clock signal is Y (14.4GHz), where Y is a positive integer. At box 310, the application software processor core 142 determines whether the determined harmonics are within one or more restricted frequency bands. Restricted frequency bands can be narrow bands limited by policies, standards, laws, etc. An example restricted frequency band could be 1.6GHz. If the application software processor core 142 determines that the frequency or harmonics of the RF PLL clock or the RF MCU clock are not within the restricted frequency bands (box 310: No), then the instruction ends. For example, a preset chirp period is selected, and the application software processor core 142 instructs the RF PLL 114 or FMCW PLL to generate a signal based on the selected chirp period and the selected RF MCU clock frequency. If the application software processor core 142 determines that the frequency or harmonics of the RF PLL clock or RF MCU clock are within a restricted frequency band (box 310: Yes), then the application software processor core 142 selects an RF PLL clock frequency that causes the harmonics of the MCU clock and RF PLL clock to be outside one or more restricted frequency bands (box 312). The application software processor core 142 may select a frequency for the RF PLL that is close to the initially selected RF PLL, which also generates a clock signal with harmonics outside the restricted band. For example, the further away from the initial RF PLL clock frequency, the higher the probability that the frequency divider circuitry 116, 118 will generate a clock with a frequency outside the operating distance of the corresponding components. Therefore, the application software processor core 142 selects an RF PLL clock with a frequency that eliminates emissions outside the restricted band while still resulting in a clock signal within the operational limitations of the corresponding components of the radar system 100. For example, the application software processor core 142 may select an RF PLL frequency of 14.32 GHz, which would result in an RF MCU clock signal with a frequency of 198.89 MHz (e.g., 14.32 GHz / 72). The harmonics of the RF MCU clock signal now correspond to X (198.89 MHz), which is outside the instance restricted frequency of 1.6 GHz (e.g., 198.89 MHz * 8 = 1.591 GHz, which is outside the 1.6 GHz restricted band).

[0043] At box 314, application software processor core 142 determines whether radar will be implemented in a static environment. A static environment is one in which most of the environment will remain static and only moving objects will be tracked. For example, a static environment may include using radar for cabin monitoring. A non-static environment is one in which moving and non-moving objects will be tracked. For example, a non-static environment may include using radar to park a vehicle. If application software processor core 142 determines that radar system 100 will be implemented in a static environment (box 314: Yes), then application software processor core 142 selects the period of the chirp signal to adjust the ghosted target to a zero Doppler position / cabin (e.g., corresponding to a non-moving object) (box 318). For example, the range frequency offset of the ghosted target is a function of the difference between the frequency of the clock signal from oscillator 150 and the frequency of the clock signal used by MCU processor core 146, as shown in Equation 1 above. Therefore, based on the example data above, without adjusting the chirp period, the ghost target can appear at a frequency offset of 1.11MHz (e.g., (5)(40MHz)-(1)(198.89MHz)=1.11MHz) and a random Doppler frequency depending on the chirp period. To adjust the Doppler chamber (frequency) of the ghost target, the application software processor core 142 adjusts the chirp period to R(1 / (2*ghost_target)). range_offset ), where R is an even integer. As described above, the ghosted target is moved to the zero-Doppler chamber (e.g., zero frequency) using an even integer R. Because the radar system 100 is implemented in a static environment, objects detected in the zero-Doppler chamber will be filtered out.

[0044] If the application software processor core 142 determines that the radar system 100 will not be implemented in a static environment (box 314: No), then the application software processor core 142 selects the period of the chirp signal to adjust the ghost target to the positive / negative maximum Doppler position / bin (e.g., corresponding to the object with the maximum speed detectable by the radar system 100) (box 316). For example, the frequency offset of the ghost target is a function of the difference between the frequency of the clock signal from the oscillator 150 and the frequency of the clock signal used by the MCU processor core X, as shown in Equation 1 above. Therefore, based on the example data above, without adjusting the chirp period, the ghost target can appear at a frequency offset of 1.11MHz (e.g., (5)(40MHz)-(1)(198.89MHz)=1.11MHz) and a random Doppler bin (frequency) depending on the chirp period. To adjust the Doppler bin of the ghost target, the application software processor core 142 adjusts the chirp period to R(1 / (2*ghost_target)). range_offsetWhere R is an odd integer. As described above, the odd integer R is used to move the ghosted target to the maximum positive or negative Doppler bin. Because the radar system 100 is implemented in a non-static environment, the maximum positive and negative Doppler bins can be filtered out to remove the ghosted target. Following blocks 316 and 317, the application software processor core 142 instructs the RF PLL 114 and FMCW PLL 120 to generate signals based on the selected chirp period and the selected RF MCU clock frequency.

[0045] Figure 1 It means that at least one can be executed, instantiated, or performed by a programmable circuit system to operate in a static environment. Figure 4 A flowchart of an example machine-readable instruction or example operation 400 for a radar system 100. Figure 5 The instance machine-readable instruction or instance operation 400 begins at block 402, where the RF PLL 114 is activated at the selected RF PLL clock frequency. Therefore, the RF PLL 114 is activated to generate a clock signal with the selected RF PLL clock frequency. As described above, the selected RF PLL clock frequency is chosen to ensure that there are no harmonic emissions corresponding to the clock signal of the radar system 100 within one or more restricted frequency bands.

[0046] At block 404, FMCW PLL 120 generates a chirped signal with a selected chirped period. As described above, the period of the chirped signal is selected to move the ghosted target to the zero Doppler chamber. At block 406, antenna 128 outputs the generated chirped signal. If the object is within physical or velocity range, the chirped signal is reflected by the object and acquired via antenna 130. At block 408, antenna 130 acquires one or more delayed reflected signals. At block 410, amplifier 132, mixer circuitry 134, ADC 136, and filter 138 process the delayed reflected signals. For example, amplifier 132 amplifies the delayed reflected signal, mixer circuitry 134 mixes the delayed reflected signal with the chirped signal output from frequency multiplier 122, ADC 136 converts the analog signal into digital samples, and filter 138 filters the digital samples.

[0047] At box 412, RAM 140 stores samples of the processed, delayed reflected signal. At box 414, radar data FTT calculation processor core 144 performs a range-dimensional FFT on the stored samples to determine the physical distance to the object corresponding to the reflected signal. At box 416, radar data FTT calculation processor core 144 performs a Doppler-dimensional FFT on the range dimension to produce one or more range-Doppler representations. As further described above, the one or more range-Doppler representations may include a range-Doppler heatmap representation and a Doppler-dimensional FFT representation. At box 418, RF MCU core 146 filters out zero-Doppler bins from the range-Doppler representations. Because the period of the chirped signal causes ghosted targets to appear at the zero-Doppler bins, filtering out zero-Doppler bins removes ghosted targets from the one or more range-Doppler representations. At box 420, RF MCU processor core 146 detects objects or object velocities from the one or more range-Doppler representations. At box 422, the RF MCU processor core 146 performs an angular dimension FFT on the detected object. The angular dimension FFT identifies the object's angles. The angular dimension FFT can be performed based on comparisons of samples from different digital filters 138, each digital filter corresponding to an antenna 130 at a different location, thereby generating information that can be processed to determine the object's angles. After box 422, the RF MCU processor core 146 can output the analysis results (e.g., detected object, object velocity, angles, etc.) to the processing device 148 via peripheral device 112.

[0048] Figure 1 It means that at least one can be executed, instantiated, or performed by a programmable circuit system to operate in a non-static environment. Figure 5 A flowchart of an example machine-readable instruction or example operation 500 for a radar system 100. Figures 6A to 6C The instance machine-readable instruction or instance operation 500 begins at block 502, where the RF PLL 114 is activated at a selected RF PLL clock frequency. Thus, the RF PLL 114 is activated to generate a clock signal with the selected RF PLL clock frequency. As described above, the selected RF PLL clock frequency is chosen to ensure that there are no harmonic emissions corresponding to the clock signal of the radar system 100 within one or more restricted frequency bands.

[0049] At block 504, FMCW PLL 120 generates a chirped signal with a selected chirped period. As described above, the period of the chirped signal is selected to move the ghosted target to the maximum positive or negative Doppler chamber. At block 506, antenna 128 outputs the generated chirped signal. If the object is within physical or velocity range, the chirped signal is reflected by the object and obtained via antenna 130. At block 508, antenna 130 obtains one or more delayed reflected signals. At block 510, amplifier 132, mixer circuitry 134, ADC 136, and filter 138 process the delayed reflected signals. For example, amplifier 132 amplifies the delayed reflected signal, mixer circuitry 134 mixes the delayed reflected signal with the chirped signal output from frequency multiplier 122, ADC 136 converts the analog signal into digital samples, and filter 138 filters the digital samples.

[0050] At box 512, RAM 140 stores samples of the processed, delayed reflected signal. At box 514, radar data FTT calculation processor core 144 performs a range-dimensional FFT on the stored samples to determine the physical distance to the object corresponding to the reflected signal. At box 516, radar data FTT calculation processor core 144 performs a Doppler-dimensional FFT on the range dimension to produce one or more range-Doppler representations. As further described above, the one or more range-Doppler representations may include a range-Doppler heatmap representation and a Doppler-dimensional FFT representation. At box 518, RF MCU core 146 filters out the maximum positive Doppler binaries and the maximum negative Doppler binaries from the range-Doppler representations. Because the period of the chirped signal causes the ghosted target to appear at one of the maximum Doppler binaries, filtering out the maximum positive Doppler binaries and the maximum negative Doppler binaries removes the ghosted target from the one or more range-Doppler representations. At block 520, the RF MCU processor core 146 detects an object or object velocity from one or more distance Doppler representations. At block 522, the RF MCU processor core 146 performs an angular dimension FFT on the detected object. The angular dimension FFT identifies the angles of the object. The angular dimension FFT can be performed based on comparisons of samples from different digital filters 138, each digital filter corresponding to an antenna 130 at a different location, thereby generating information that can be processed to determine the angles of the object. After block 522, the RF MCU processor core 146 can output the analysis results (e.g., detected object, object velocity, angles, etc.) to the processing device 148 via peripheral device 112.

[0051] Figure 6A Plot an example of distance Doppler representation. Figure 6B It includes a first distance Doppler representation 600 and a second distance Doppler representation 602, where M(MCU_CLK)≠N(XTAL_CLK) and the period of the chirped signal has not been adjusted.Figure 6C It includes a first distance Doppler representation 604 and a second distance Doppler representation 606, where M(MCU_CLK)≠N(XTAL_CLK) and the period of the chirped signal has been adjusted to move the ghosted target to the maximum positive or negative Doppler bin. Figure 6A It includes a first distance Doppler representation 606 and a second distance Doppler representation 608, where M(MCU_CLK)≠N(XTAL_CLK) and the period of the chirped signal has been adjusted to move the ghosted target to the zero Doppler bin.

[0052] exist Figure 6B In this representation, the first distance Doppler representation 600 is a visual representation of the distance Doppler heatmap, and the second distance Doppler representation 602 is a visual representation of the Doppler-dimensional FFT. In the first distance Doppler representation 600, there is an indication 601a of an object at approximately 0 Hz, and an indication 601b of an object at approximately 1500 Hz. The 0 Hz indication 601a corresponds to a static, actual target object. The 1500 Hz indication 601b corresponds to a ghosted target moving at a specific frequency. The second distance Doppler representation 602 contains peaks at 0 Hz and 1500 Hz, as shown in example indications 603a and 603b. Although Doppler representations 600 and 602 reflect objects moving at specific speeds, these objects are not actually non-existent target objects.

[0053] exist Figure 5 In the diagram, the first distance Doppler representation 604 is a visual representation of the distance Doppler heatmap, and the second distance Doppler representation 606 is a visual representation of the Doppler-dimensional FFT. In the first distance Doppler representation 604, there is an indication 605a that the object is at approximately 0 Hz, and an indication 605b that the object is at approximately -3500 Hz (maximum negative Doppler chamber). The 0 Hz indication 605a corresponds to a static, actual target object. The -3500 Hz indication 605b corresponds to a ghosted target that has moved to the maximum negative Doppler chamber by adjusting the chirp period, as further described above. The second distance Doppler representation 606 contains peaks at 0 Hz and -3500 Hz, as shown in example indications 607a and 607b. Figure 6C The description further explains that ghosted targets are filtered out for use by radar system 100 in non-static environments.

[0054] exist Figure 4In the diagram, the first distance Doppler representation 608 is a visual representation of the distance Doppler heatmap, and the second distance Doppler representation 610 is a visual representation of the Doppler-dimensional FFT. In the first distance Doppler representation 608, there is an indication 609 that the object is located at approximately 0 Hz (zero frequency / Doppler chamber). The 0 Hz indication 609 corresponds to a ghosted target that has moved to the zero frequency / Doppler chamber by adjusting the chirp period, as further described above. (The above is combined with...) Figure 7 To be further described, ghosted targets are filtered out for use by radar system 100 in non-static environments.

[0055] Figure 1 The drawing corresponds to what can be drawn by Figure 8 The timing diagram 700 shows an instance chirp signal 701 generated by an FMCW PLL 120 of type 2. The chirp signal 701 increases from a first frequency (e.g., 76 GHz) to a second frequency (e.g., 80 GHz), then falls back and repeats. The period of the chirp signal 701 corresponds to the duration (e.g., the amount of time between adjacent peaks) taken to repeat the change in the chirp signal 701. As described above, the chirp periodicity is selected to move the ghosted target to one or more predefined Doppler chambers that are filtered out.

[0056] Figures 3 to 5 This is a block diagram of an instance programmable circuit system platform 800, which is configured to execute or instantiate... Figure 1 Instance machine-readable instructions or instance operations to implement Figure 1 The radar system 100 or 200 may be one or more components or combinations thereof. The programmable circuit system platform 800 may be, for example, a server, a personal computer, a computing system for a vehicle (e.g., an automobile), a workstation, or a mobile device (e.g., a mobile phone, smartphone, such as an iPad). TM Tablet computers, personal digital assistants (PDAs), internet-connected appliances, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices, or any other type of computing or electronic device.

[0057] The illustrated example of a programmable circuit system platform 800 includes a programmable circuit system 812. The programmable circuit system 812 in the illustrated example is hardware. For example, the programmable circuit system 812 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuit system 812 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 812 is implemented... Figures 3 to 5One or more components of a radar system 100 or 200.

[0058] The illustrated programmable circuit system 812 includes local memory 813 (e.g., cache, registers, etc.). The illustrated programmable circuit system 812 communicates with main memories 814 and 816 via bus 818, the main memories including volatile memory 814 and non-volatile memory 816. The volatile memory 814 may be one or more synchronous dynamic random access memories (SDRAM) or dynamic random access memories (DRAM). Dynamic Random Access Memory Or any other type of RAM device. Non-volatile memory 816 may be implemented by flash memory or one or a combination of any other desired type of memory device. Access to the main memory 814, 816 in the illustrated example is controlled by memory controller 817. In some instances, memory controller 817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired series or manufacturer, or any other type of circuit system to manage data flows to and from main memory 814, 816.

[0059] The programmable circuit system platform 800 illustrated in the example also includes an interface circuit system 820. The interface circuit system 820 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, etc. Interfaces include Near Field Communication (NFC) interfaces, Peripheral Component Interconnect (PCI) interfaces, and Peripheral Component Interconnect High Speed ​​(PCIe) interfaces.

[0060] In the illustrated example, one or more input devices 822 are connected to the interface circuitry system 820. The input devices 822 allow a user (e.g., a human user, a machine user, etc.) to input one or more data or commands into the programmable circuitry system 812. The input devices 822 may be implemented as one or more of, for example, an audio sensor, microphone, camera (still or video), keyboard, buttons, mouse, touchscreen, trackpad, trackball, dotted device, or voice recognition system.

[0061] One or more output devices 824 are also connected to the interface circuitry system 820 of the illustrated example. The one or more output devices 824 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuitry system 820 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuitry system such as a GPU.

[0062] The interface circuit system 820 of the illustrated example also includes communication devices, such as one or a combination of a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 826. Communication can be made via, for example, Ethernet connection, digital subscriber line (DSL) connection, telephone line connection, coaxial cable system, satellite system, beyond-line-of-sight wireless system, line-of-sight wireless system, cellular telephone system, optical connection, etc.

[0063] The programmable circuit system platform 800 illustrated in the example also includes one or more mass storage disks or devices 828 for storing one or more firmware, software, or data. Examples of such mass storage disks or devices 828 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0064] can be Figure 9 The machine-readable instructions 832 implemented by the machine-readable instructions may be stored in one or a combination of a mass storage device 828, a volatile memory 814, a non-volatile memory 816, or at least one removable, non-transitory computer-readable storage medium such as a CD or DVD.

[0065] Figure 8 The diagram is drawn in the middle, and its drawing is used to represent the software (e.g. Figure 8 An instance software distribution platform 905 distributes instance machine-readable instructions (832) to other hardware devices (e.g., one or more hardware devices owned or operated by a third party from the owner or operator of the software distribution platform). The instance software distribution platform 905 may be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transferring software to other computing devices. The third party may be a customer of an entity that owns or operates at least one of the software distribution platforms 905. For example, the entity that owns or operates at least one of the software distribution platforms 905 may be the software (e.g., Figures 3 to 5The third party may be at least one of the developers, sellers, or licensors of the machine-readable instruction 832. A third party may be a consumer, user, retailer, OEM, etc., who purchases or licenses one or more of the software for use, resale, or sublicense. In the illustrated example, the software distribution platform 905 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instruction 832, which may correspond to... Figures 3 to 5 The instance machine-readable instructions are as described above. One or more servers of the instance software distribution platform 905 communicate with the instance network 910, which may correspond to the Internet or any one or more of the instance networks described above. In some instances, one or more servers respond to a request to transfer software to a requesting party as part of a commercial transaction. Payment for at least one of the software delivery, sale, or licensing may be handled by one or more servers of at least one of the software distribution platforms or by a third-party payment entity. The servers enable one or more purchasers or licensors to download machine-readable instructions 832 from the software distribution platform 905. For example, this may correspond to... Figure 8 The instance machine-readable instructions of the software can be downloaded to the instance programmable circuit system platform 800, which will execute the machine-readable instructions 832 to implement the radar system 100. In some instances, one or more servers of the software distribution platform 905 periodically update the software (e.g., Figure 1 The instance machine-readable instruction 832) provides, transmits, or forces an update of at least one of the following to ensure that improvements, patches, updates, etc., are distributed and applied to the software at the end-user device. Although referred to as software above, distributed “software” may alternatively be firmware.

[0066] Although Figure 1 Or, as illustrated in Figure 2, the implementation is shown. Figure 1 Or, the radar system of type 2, such as 100 or 200, but... Figure 1 One or more of the elements, processes, or apparatuses illustrated in Figure 2 may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, Figure 1The components of radar systems 100 and 200 can be implemented by hardware alone, or by a combination of hardware, software, and firmware. Therefore, for example, any component of radar system 100, or more generally, an instance of radar system 100, can be implemented by a combination of a programmable circuit system with one or more machine-readable instructions (e.g., firmware or software), a processor circuit system, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more ASICs, one or more programmable logic devices (PLDs), or one or more field-programmable logic devices (FPLDs) (e.g., FPGAs). Furthermore, Figure 1 Example radar systems 100 and 200, or 2, may include [the following components] as [the following components]: Figures 3 to 5 It may be one or more elements, processes or devices that are supplementary or alternative to those shown in 2, or may include more than one of any and all of the elements, processes and devices shown.

[0067] Figure 1 The text illustrates instance machine-readable instructions (which can be executed by a programmable circuit system to implement or instantiate). Figure 1 (or at least one of radar systems 100, 200) or represents an instance operation (which can be implemented or instantiated by a programmable circuit system). Figure 8 One or more flowcharts of radar systems 100 and 200 (or 2). Machine-readable instructions may be for programmable circuit systems (e.g., in conjunction with the above). Figures 3 to 5 The programmable circuit system 812 shown in the example processor platform 800 described herein executes one or more executable programs or portions of one or more executable programs, and may be one or more functions or portions of functions performed by the example programmable circuit system (e.g., FPGA). In some instances, machine-readable instructions enable operations, tasks, etc., to be performed or carried out in a real-world manner in an automated manner. As used herein, “automation” means without human intervention.

[0068] The program may be embodied in instructions (e.g., at least one of software or firmware) stored on one or more non-transitory computer-readable or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage device or disk (e.g., floppy disk, hard disk drive (HDD) etc.), optical storage device or optical disk (e.g., Blu-ray disc, optical disc (CD), digital versatile disc (DVD) etc.), redundant array of independent disks (RAID), register, ROM, solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory etc.), volatile memory (e.g., any type of random access memory (RAM) etc.), or any other storage device or storage disk. The instructions of the non-transitory computer-readable or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated or embodied in dedicated hardware by one or more hardware devices other than the programmable circuit system. Machine-readable instructions may be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices may be implemented by endpoint client hardware devices (e.g., hardware devices associated with human or machine users) or by an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that facilitates communication between the server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media may contain one or more media. Furthermore, although references... Figures 3 to 5The flowcharts illustrated herein describe an example program, but many other methods of implementing the example radar system 100 may be used alternatively. For example, the execution order of the blocks of one or more flowcharts may be changed, or some of the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all blocks of the flowcharts may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete, integrated analog or digital circuitry, FPGA, ASIC, comparator, operational amplifier, logic circuitry, etc.) configured to perform the corresponding operation without executing software or firmware. The programmable circuitry may be distributed across different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, a programmable circuit system can be one or a combination of the following: a CPU or FPGA located in the same package (e.g., in the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers across server racks, multiple processors distributed across one or more server racks, or any one or a combination thereof.

[0069] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and packaged format. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., as one or more parts of an instruction, code, a representation of code, etc.), which can be used to create, manufacture, or generate machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations within a network or network set (e.g., in the cloud, at the edge, etc.). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., so that the machine-readable instructions are directly readable, interpretable, or executable by a computing device or another machine. For example, machine-readable instructions may be stored individually in multiple portions on separate computing devices, wherein the portions are decrypted, decompressed, or combined in response to a set of one or more computer-executable or machine-executable instructions that implement one or more functions or operations that may together form a program (such as the program described herein).

[0070] In another instance, machine-readable instructions may be stored in a state readable by a programmable circuit system, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the machine-readable instructions on a particular computing device or another device. In yet another instance, the machine-readable instructions (e.g., stored settings, data inputs, recorded network addresses, etc.) may need to be configured before they can be executed wholly or partially. Therefore, as used herein, machine-readable, computer-readable, or machine-readable media may contain one or more instructions and programs, regardless of the specific format or state of the machine-readable instructions or programs.

[0071] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0072] As mentioned above, Figure 1The instance operation can be implemented using executable instructions (e.g., computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are explicitly defined as comprising any type of computer-readable storage device or disk that does not contain propagating signals and does not contain an emission medium. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk in which information is stored for any duration (e.g., extended time period, permanent, transient, temporary buffer, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware for retaining information for a period of time, but excluding the propagation of signals and the transmission of media. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, hard disk, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of the following: mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured by, or manufactured to execute, computer-readable instructions, machine-readable instructions, etc.

[0073] Figure 1 Or, as shown in Figure 2, the implementation is as follows. Figure 1 Or one or more instances of radar systems 100, 200. However, Figures 1 to 2 One or more of the elements, processes or apparatuses shown in 2 may be combined, divided, rearranged, omitted, eliminated or implemented in any other way.

[0074] Furthermore, one or more of the processor core 106 or other components of the radar systems 100 and 200 may be implemented by one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more programmable logic devices (PLDs) or one or more field-programmable logic devices (FPLDs).

[0075] When reading any of the device or system technical solutions in this patent to cover only software or firmware implementations, at least one of the processor core 106 or any component of the radar system 100 is hereby expressly defined as including a non-transitory computer-readable storage device or storage disk, such as a memory, digital multifunction disc (DVD), optical disc (CD), Blu-ray disc, etc., which includes software or firmware. Furthermore, one or more of the processor core 106 or components of the radar system 100 may include, in addition to Figures 1 to 2 The term "communication" may refer to one or more elements, processes, or devices other than or replacing those elements, processes, or devices illustrated herein, or may include more than one of any or all of the illustrated elements, processes, and devices. As used herein, the phrase "communication" includes variations thereof, encompassing direct communication or indirect communication through one or more intermediate components, and not requiring direct physical (e.g., wired) communication or continuous communication, but also including selective communication performed at one or more of periodic intervals, predetermined intervals, non-periodic intervals, or one-off events.

[0076] While certain example methods, apparatuses, and articles of manufacture have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles of manufacture that fall within the scope of the claims of this patent.

[0077] The descriptive terms “first,” “second,” “third,” etc., are used herein to identify multiple elements or components that may be referenced separately. Unless otherwise specified or understood from the context of their use, these descriptive terms do not imply any priority, physical order, or arrangement or chronological order in a list, but are merely labels to refer to multiple elements or components separately to facilitate understanding of the described instance. In some instances, the descriptive term “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to in the claims by different descriptive terms such as “second” or “third.” In such cases, these descriptive terms are used solely for ease of reference to multiple elements or components.

[0078] As used herein, the terms “coupled,” “couples,” and variations thereof may cover a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B, then: if in a first instance device A is coupled to device B; or if in a second instance device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via a control signal generated by device A. Furthermore, the terms “coupled,” “couples,” or variations thereof encompass indirect or direct electrical or mechanical connections.

[0079] Despite ​ Not all components are separately labeled, but the components or elements of the systems and circuits depicted therein have one or more conductors or ends that allow signals to enter or exit the components or elements. Conductors or ends (or portions thereof) may be pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0080] The term “or” when used in the form of, for example, A, B or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C.

[0081] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) configured to perform one or more specific operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); or (ii) one or more general-purpose semiconductor-based circuits programmable by instructions to perform one or more specific functions or operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) capable of executing a first instruction to perform one or more operations or functions; a field-programmable gate array (FPGA) programmable with a second instruction to configure or structure at least one of the FPGAs, thereby instantiating one or more operations or functions corresponding to the first instruction; a graphics processing unit (GPU) capable of executing the first instruction to perform one or more operations or functions; a digital signal processor (DSP) capable of executing the first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers capable of executing the first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes various types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any one or more combinations thereof) and configuration technologies (e.g., one or more application programming interfaces (one or more APIs)) that can assign one or more computing tasks to any one or more types of programmable circuit systems that are suitable for and can be used to perform one or more computing tasks.

[0082] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0083] This document describes example methods, apparatuses, systems, and articles of art corresponding to sensor systems operating at multiple clock frequencies. Other examples and combinations thereof include the following: Example 1 includes a system comprising: a radio frequency (RF) phase-locked loop (PLL) that generates an output signal at a first frequency; a microcontroller that operates at a second frequency, the first frequency being a multiple of the second frequency; a transmitter that outputs a chirped signal having a chirped period selected based on the second frequency; a receiver that receives a reflected signal corresponding to the chirped signal; and a filter that filters out Doppler cells corresponding to the reflected signal based on the chirped period.

[0084] Example 2 includes the system according to Example 1, wherein the harmonics of the first frequency and the harmonics of the second frequency are outside a restricted frequency band.

[0085] Example 3 includes the system according to Example 1, wherein the RF PLL generates the output signal at the first frequency based on a clock signal at a third frequency lower than the first frequency.

[0086] Example 4 includes the system according to Example 3, wherein the chirp period is also selected based on the third frequency.

[0087] Example 5 includes the system according to Example 1, further comprising a processor core that generates a range Doppler representation based on the reflected signal, the range Doppler representation including Doppler chambers corresponding to different velocities.

[0088] Example 6 includes the system according to Example 5, wherein a mismatch between the second frequency and a third frequency for generating a clock signal of the first frequency results in a ghosted target at a specific distance-Doppler bin in the range-Doppler representation.

[0089] Example 7 includes the system according to Example 1, further including a frequency divider that generates a clock signal at the second frequency based on the output signal, the microcontroller using the clock signal for operation.

[0090] Example 8 includes the system according to Example 1, wherein the Doppler chamber corresponds to the maximum positive or negative velocity that can be detected by the system.

[0091] Example 9 includes the system according to Example 1, wherein the Doppler chamber corresponds to zero velocity.

[0092] Example 10 includes the system according to Example 1, wherein the system is a system-on-a-chip.

[0093] Example 11 includes the system according to Example 1, further including a processor core that selects the chirp period to move the ghosted target to a specific Doppler bin in the distance-Doppler representation, the Doppler bin being determined prior to operation.

[0094] Example 12 includes a method comprising: generating an output signal at a first frequency; operating a core at a second frequency, the first frequency being a multiple of the second frequency; outputting a chirped signal having a chirped period selected based on the second frequency; receiving a reflected signal corresponding to the chirped signal; and filtering out a Doppler chamber corresponding to the reflected signal based on the chirped period.

[0095] Example 13 includes the method according to Example 12, wherein the harmonics of the first frequency and the harmonics of the second frequency are outside a restricted frequency band.

[0096] Example 14 includes the method according to Example 12, further comprising generating the output signal at the first frequency based on a clock signal at a third frequency lower than the first frequency.

[0097] Example 15 includes the method according to Example 14, wherein the chirping period is also selected based on the third frequency.

[0098] Example 16 includes the method according to Example 12, further comprising generating a range Doppler representation based on the reflected signal, the range Doppler representation including Doppler chambers corresponding to different velocities.

[0099] Example 17 includes the method according to Example 16, wherein a mismatch between the second frequency and a third frequency for generating a clock signal of the first frequency results in a ghosted target at a specific distance-Doppler bin in the distance-Doppler representation.

[0100] Example 18 includes the method according to Example 12, further comprising generating a clock signal at the second frequency based on the output signal, the core operating using the clock signal.

[0101] Example 19 includes the method according to Example 12, wherein the Doppler chamber corresponds to the maximum positive or negative velocity that can be detected by the radar system.

[0102] Example 20 includes the method according to Example 12, wherein the Doppler chamber corresponds to zero velocity.

[0103] Example 21 includes the method according to Example 12, further comprising selecting the chirp period to move the ghosted target to a specific Doppler bin in the distance Doppler representation, the Doppler bin being determined prior to operation.

[0104] Example 22 includes a non-transitory computer-readable storage medium comprising instructions that cause at least one programmable circuitry to perform at least the following operations: selecting a first frequency of a first clock signal to be generated by a radio frequency (RF) phase-locked loop (PLL), the first clock signal being used to generate a second clock signal at a second frequency, the first frequency being selected based on harmonics of the first clock signal and harmonics of the second clock signal; selecting a chirp period of a chirp signal to be output by a transmitter of a radar, the chirp period of the chirp signal being based on the second frequency of the second clock signal; causing the PLL to generate the first clock signal at the first frequency; and causing a transceiver to output the chirp signal based on the selected period.

[0105] Example 23 includes a non-transitory computer-readable storage medium according to Example 22, wherein one or more of the at least one programmable circuitry selects the first frequency to ensure that the harmonics of the first clock signal and the second clock signal are outside a restricted frequency band.

[0106] Example 24 includes a non-transitory computer-readable storage medium according to Example 22, wherein the second frequency is the first frequency divided by an integer.

[0107] Example 25 includes a non-transitory computer-readable storage medium according to Example 22, wherein the chirp period is selected based on a third frequency of a third clock signal of an oscillator.

[0108] Example 26 includes a non-transitory computer-readable storage medium according to Example 22, wherein one or more of the at least one programmable circuits select the chirp period to move the ghosted target to a specific Doppler compartment in the distance-Doppler representation, the Doppler compartment being determined prior to operation.

[0109] Within the scope of the claims, modifications may be made to the described instances, and other instances are possible.

Claims

1. A system comprising: a radio frequency (RF) phase-locked loop (PLL) that generates an output signal at a first frequency; a microcontroller that operates at a second frequency, the first frequency being a multiple of the second frequency; a transmitter that outputs a chirp signal having a chirp period selected based on the second frequency; a receiver that receives a reflected signal corresponding to the chirp signal; and a filter that filters out Doppler bins corresponding to the reflected signal based on the chirp period.

2. The system of claim 1, wherein harmonics of the first frequency and harmonics of the second frequency are outside a limited frequency band.

3. The system of claim 1, wherein the RF PLL is to generate the output signal at the first frequency based on a clock signal at a third frequency lower than the first frequency.

4. The system of claim 3, wherein the chirp period is selected based on the third frequency as well.

5. The system of claim 1, further including a processor core that generates a range-Doppler representation based on the reflected signal, the range-Doppler representation including Doppler bins corresponding to different velocities.

6. The system of claim 5, wherein a mismatch corresponding to the second frequency and a third frequency of a clock signal used to generate the first frequency results in a ghost target at a particular range-Doppler bin in the range-Doppler representation.

7. The system of claim 1, further including a frequency divider that generates a clock signal at the second frequency based on the output signal, the microcontroller operating using the clock signal.

8. The system of claim 1, wherein the Doppler bins correspond to a maximum positive or negative velocity that can be detected by the system.

9. The system of claim 1, wherein the Doppler bins correspond to zero velocity.

10. The system of claim 1, wherein the system is a system-on-a-chip.

11. The system of claim 1, further including a processor core that selects the chirp period to move a ghost target to a Doppler bin in a range-Doppler representation.

12. A method comprising: generating an output signal at a first frequency; operating a core at a second frequency, the first frequency being a multiple of the second frequency; outputting a chirp signal having a chirp period selected based on the second frequency; receiving a reflected signal corresponding to the chirp signal; and filtering out Doppler bins corresponding to the reflected signal based on the chirp period.

13. The method of claim 12, wherein harmonics of the first frequency and harmonics of the second frequency are outside a limited frequency band.

14. The method of claim 12, further including generating the output signal at the first frequency based on a clock signal at a third frequency lower than the first frequency.

15. The method of claim 14, wherein the chirp period is selected based on the third frequency as well.

16. The method of claim 12, further comprising generating a range Doppler representation based on the reflected signal, the range Doppler representation including Doppler bins corresponding to different velocities.

17. The method of claim 16, wherein a mismatch corresponding to the second frequency and a third frequency of a clock signal used to generate the first frequency results in a ghost target in the range Doppler representation at a particular range-Doppler bin.

18. The method of claim 12, further comprising generating a clock signal at the second frequency based on the output signal, the core operating using the clock signal.

19. The method of claim 12, wherein the Doppler bins correspond to a maximum positive or negative velocity that can be detected by a radar system.

20. The method of claim 12, wherein the Doppler bins correspond to zero velocity.

21. The method of claim 12, further comprising selecting the chirp period to move a ghost target to a Doppler bin in a range Doppler representation.

22. A non-transitory computer-readable storage medium comprising instructions that cause at least one programmable circuit to at least: select a first frequency of a first clock signal to be generated by a radio frequency (RF) phase-locked loop (PLL), the first clock signal used to generate a second clock signal at a second frequency, the first frequency selected based on a harmonic of the first clock signal and a harmonic of the second clock signal; select a chirp period of a chirp signal to be output by a transmitter of a radar, the chirp period of the chirp signal based on the second frequency of the second clock signal; cause a phase-locked loop to generate the first clock signal at the first frequency; and cause a transceiver to output the chirp signal based on the selected period.

23. The non-transitory computer-readable storage medium of claim 22, wherein one or more of the at least one programmable circuit is to select the first frequency to ensure that the harmonics of the first clock signal and the second clock signal are outside of a restricted frequency band.

24. The non-transitory computer-readable storage medium of claim 22, wherein the second frequency is the first frequency divided by an integer.

25. The non-transitory computer-readable storage medium of claim 22, wherein the chirp period is selected based on a third frequency of a third clock signal of an oscillator.

26. The non-transitory computer-readable storage medium of claim 22, wherein one or more of the at least one programmable circuit is to select the chirp period to move a ghost target to a Doppler bin in a range Doppler representation. ​

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