Amplification circuit and method for stabilizing bias current of amplification circuit

Abstract

An amplifier circuit and a method for stabilizing bias current of the amplifier circuit are provided. The amplifier circuit includes an input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a voltage tracking circuit. The input end receives an input signal. And the output end outputs the amplified input signal. The control ends of the first transistor and the second transistor are coupled to each other. The voltage tracking circuit is coupled to the first end and the control end of the first transistor, the first end of the second transistor and the first end of the third transistor. When the voltage tracking circuit is in an initial state, the potential of the first end of the first transistor is substantially equal to the potential of the first end of the third transistor. And the potential of the first end of the first transistor and the potential of the first end of the second transistor are maintained to be substantially equal in a stable state.

Description

Technical Field

[0001] This invention relates to an amplifier circuit and a bias current method, particularly an amplifier circuit that can provide bias voltage in a stable state and a bias current method for stabilizing the amplifier circuit. Background Technology

[0002] A current mirror is a fundamental component in analog circuits, widely used in bias circuits and amplifier stage loads in various circuits. Therefore, the accurate mirroring characteristics of a current mirror are crucial; the stability and accuracy of its output current determine its overall performance. Current mirror devices are typically constructed using metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar junction transistors (BJTs). For example, when the drain bias of a transistor rises to the saturation region, the channel length shortens. This means that the relationship between the operating current and voltage in the saturation region is not ideally dependent solely on the gate-source voltage (VGS), but also on the drain-source voltage (VDS) due to the channel length modulation effect. Therefore, current mirror devices are susceptible to variations in the manufacturing process and bias voltage of MOSFETs, making it difficult to accurately and stably map the output current. When current mirrors are used in amplifiers (e.g., power amplifiers, low-noise amplifiers, etc.), they can provide current to the amplifier, but often cause unexpected oscillations due to circuit instability. Therefore, there is a lack of suitable solutions in the art to address these problems. Summary of the Invention

[0003] An embodiment provides an amplifier circuit including an input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a voltage tracking circuit. The input terminal is used to receive an input signal. The output terminal is used to output the amplified input signal. The first transistor includes a first terminal for receiving a first reference current, a second terminal coupled to a first bias terminal, and a control terminal. The second transistor includes a first terminal for receiving a second reference current, a second terminal coupled to the first bias terminal, and a control terminal coupled to the input terminal and the control terminal of the first transistor. The third transistor includes a first terminal for receiving a third reference current, a second terminal coupled to the first bias terminal, and a control terminal. The voltage tracking circuit includes a first input terminal coupled to the first terminal of the first transistor, a second input terminal coupled to the first terminal of the second transistor, a third input terminal coupled to the first terminal of the third transistor, a first output terminal coupled to the control terminal of the first transistor. The voltage tracking circuit is configured to maintain the potential of the first terminal of the first transistor and the first terminal of the third transistor substantially equal in an initial state, and to maintain the potential of the first terminal of the first transistor and the first terminal of the second transistor substantially equal after a predetermined time.

[0004] Another embodiment provides a method for stabilizing the bias current of an amplifier circuit, wherein the amplifier circuit includes an input terminal for receiving an input signal and an output terminal for outputting the amplified input signal. The steps include providing a first transistor for receiving a first reference current; providing a second transistor for receiving a second reference current, with a control terminal of the second transistor coupled to the input terminal and the control terminal of the first transistor, wherein the first transistor and the second transistor are coupled to a first bias terminal; providing a third transistor for receiving a third reference current; providing a voltage tracking circuit coupled to a first terminal of the first transistor for maintaining substantially equal potentials at a first terminal of the first transistor and a first terminal of the third transistor in an initial state, and for maintaining substantially equal potentials at a first terminal of the first transistor and a first terminal of the second transistor after a predetermined time; and providing a first output terminal of the voltage tracking circuit coupled to the control terminal of the first transistor. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of the amplifier circuit in the embodiment.

[0006] Figure 2 for Figure 1 ,and Figures 3 to 9A schematic diagram of the operation of the amplifier circuit in one embodiment.

[0007] Figure 3 This is a schematic diagram of the amplifier circuit in another embodiment.

[0008] Figure 4 This is a schematic diagram of the amplifier circuit in another embodiment.

[0009] Figure 5 This is a schematic diagram of the amplifier circuit in another embodiment.

[0010] Figure 6 for Figure 1 and Figures 3 to 5 The diagram below shows a voltage tracking circuit.

[0011] Figure 7 This is a schematic diagram of the amplifier circuit in another embodiment.

[0012] Figure 8 In one embodiment, Figure 7 Schematic diagram of the amplifier circuit

[0013] Figure 9 for Figures 1 to 7 In one embodiment, a flowchart of a method for stabilizing the bias current of an amplifier circuit is provided.

[0014] Figure 10 This is a schematic diagram of the amplifier circuit in another embodiment.

[0015] Symbol explanation:

[0016] 100, 300, 400, 500, 700, 900: Amplifier circuits

[0017] A1, A3, A4, A5, A7, A9: Amplifiers

[0018] 710: Low-pass filter

[0019] 755: Detection Circuit

[0020] 800: Bias Current Method

[0021] 810 to 850: Steps

[0022] C1: Voltage tracking circuit

[0023] C12: Common gate circuit

[0024] C81: Capacitor

[0025] IREF1, IREF2, IREF3, IREF4, IREF5: Reference currents

[0026] IS: Current source

[0027] N11, N12, N13, N14, NIN: Input terminals

[0028] NO, NOUT: Output terminals

[0029] OP, OP2, OP91, OP92: Operational amplifiers

[0030] TP: Reservation Time

[0031] R81: Resistor

[0032] SIN: Input signal

[0033] SOUT: Signal

[0034] SW: Switching circuit

[0035] SW1, SW2, SW3, SW91, SW92: Switches

[0036] T1, T2, T3, T4, T5, T6, T7, T8, T9: Transistors

[0037] Time0, Time1: Time

[0038] VD1, VD2, VD4: Potential

[0039] VDD: Reference voltage source

[0040] VR1: Bias end

[0041] VREF, VREF2: Reference voltage terminals

[0042] α,β,γ: Nodes Detailed Implementation

[0043] In this document, when referring to the size of a transistor, the transistor size is defined by the equivalent size of the transistor, which can be commonly defined by the gate width, width / length ratio (W / L ratio, W to L), and / or the number of fingers. In this document, when referring to two transistors corresponding to the same width / length ratio, one transistor may consist of at least one first transistor unit, and the other transistor may consist of at least one second transistor unit, and the first and second transistor units may have the same width / length ratio. In this document, according to embodiments, when the two components are coupled to each other, they may be directly coupled or indirectly coupled through other components. The circuits of the embodiments are described below with reference to the accompanying drawings. Reasonable modifications to the circuits described below still fall within the scope of the embodiments.

[0044] Figure 1This is a schematic diagram of the amplifier circuit 100 in the embodiment. The amplifier circuit 100 may include an input terminal NIN, an output terminal NOUT, transistors T1, T2, and T3, a voltage tracking circuit C1, and a common gate circuit C12. The input terminal NIN can be used to receive the input signal SIN. The output terminal NOUT can be used to output the amplified input signal SIN, i.e., the signal SOUT. Figure 1 In this context, the input signal SIN can be an RF signal, and the signal SOUT can be an amplified RF signal. The transistors mentioned in this article can be, but are not limited to, field-effect transistors, and their control terminal is the gate, while the first and second terminals can be the drain and source, respectively.

[0045] Transistor T1 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive a reference current IREF1, and the second terminal is coupled to a bias terminal VR1.

[0046] Transistor T2 and common-gate circuit C12 can form amplifier A1 to amplify the input signal SIN and generate signal SOUT.

[0047] Transistor T2 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive the reference current IREF2, the second terminal is coupled to the bias terminal VR1, and the control terminal is coupled to the input terminal NIN and the control terminal of transistor T1.

[0048] Transistor T3 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive a reference current IREF3, and the second terminal is coupled to the bias terminal VR1.

[0049] The voltage tracking circuit C1 may include input terminals N11, N12, N13, and output terminal NO. Input terminal N11 is coupled to the first terminal of transistor T1, input terminal N12 is coupled to the first terminal of transistor T2, input terminal N13 is coupled to the first terminal of transistor T3, and output terminal NO is coupled to the control terminal of transistor T1. In one embodiment, input terminal N11 may be directly coupled to the first terminal of transistor T1, input terminal N12 may be directly coupled to the first terminal of transistor T2, input terminal N13 may be directly coupled to the first terminal of transistor T3, and output terminal NO may be directly coupled to the control terminal of transistor T1.

[0050] The voltage tracking circuit C1 can be used to maintain the potential VD1 of the first terminal of transistor T1 substantially equal to the potential VD4 of the first terminal of transistor T3 in the initial state, and to maintain the potential VD1 of the first terminal of transistor T1 substantially equal to the potential VD2 of the first terminal of transistor T2 after a predetermined time. In one embodiment, the voltage difference between the potential VD1 of the first terminal of transistor T1 and the potential VD4 of the first terminal of transistor T3 or the potential VD of the first terminal of transistor T2 is less than 3%.

[0051] For example, if the bias terminal VR1 is ground and has a ground potential, then potential VD1 can be the drain-source voltage of transistor T1 (commonly referred to as VDS), potential VD2 can be the drain-source voltage of transistor T2, and potential VD4 can be the drain-source voltage of transistor T3. However, the embodiment is not limited to this, and the potential of the bias terminal VR1 can be set as needed.

[0052] Figure 2 for Figure 1 ,and Figures 3 to 10 A schematic diagram of the operation of the amplifier circuit in one embodiment. Figure 2 The horizontal axis can be considered the time axis. Figure 1 For example, amplifier circuit 100 can start operating at time Time0. The period between time Time0 and time Time1 can be the initial state, and the duration of the initial state can be a predetermined time TP. In the initial state, voltage tracking circuit C1 can make potential VD1 and potential VD4 substantially equal.

[0053] After time 1, the initial state ends and the system can enter a stable state. In the stable state, the voltage tracking circuit C1 makes potential VD1 and potential VD2 substantially equal.

[0054] Figure 2 In this context, the scheduled time TP can be between 0 and 2 microseconds (usec). Figure 1 and Figure 2 For example, transistor T2 can be part of an amplifier (e.g., but not limited to, a power amplifier or a low-noise amplifier). In the initial state, voltage tracking circuit C1 makes potential VD1 substantially equal to potential VD4, thus avoiding the unexpected oscillation problem caused by potential VD1 tracking potential VD2.

[0055] In a steady state, the voltage tracking circuit C1 makes potentials VD1 and VD2 substantially equal, which stabilizes the current provided by the current mirror architecture composed of transistors T1 and T2. For example, it can ensure that the reference current IREF2 is an integer multiple of the reference current IREF1, so that the amplifier can operate normally.

[0056] Figure 3 This is a schematic diagram of another embodiment of the amplifier circuit 300. The similarities between amplifier circuit 300 and amplifier circuit 100 will not be repeated. Figure 3 As shown, Figure 1The common-gate circuit C12 may include transistor T4, and transistor T4 and transistor T2 may form amplifier A3. Transistor T4 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal may be coupled to the output terminal NOUT, the second terminal may be coupled to the first terminal of transistor T2, and the control terminal may be coupled to the reference voltage terminal VREF to receive a predetermined bias voltage.

[0057] The amplifier circuit 300 may further include a transistor T5, which includes a first terminal, a second terminal, and a control terminal, wherein the second terminal is coupled to the first terminal of transistor T3, and the control terminal is coupled to the reference voltage terminal VREF and the control terminal of transistor T4.

[0058] Figure 3 In this configuration, transistors T4 and T5 can correspond to the same width-to-length ratio (W / L ratio). The size of transistor T4 can be an integer multiple of the size of transistor T5. Transistors T4 and T5 can form a current mirror structure. Figure 2 In the initial state, when the voltage tracking circuit C1 makes potential VD1 and potential VD4 substantially equal, potential VD2 can be approximated to potential VD4 by mirroring, and potential VD2 can be approximated to potential VD1. This is indirect voltage tracking.

[0059] Figure 4 This is a schematic diagram of an amplifier circuit 400 in another embodiment. The similarities between amplifier circuit 400 and amplifier circuit 100 will not be repeated. Amplifier circuit 400 may include transistors T2, T4, and T9. Transistor T4 may include a first terminal, a second terminal, and a control terminal, wherein the second terminal may be coupled to the first terminal of transistor T2, and the control terminal may be coupled to a reference voltage terminal VREF to receive a predetermined bias voltage. Transistor T9 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the output terminal NOUT, the second terminal is coupled to the first terminal of transistor T4, and the control terminal is coupled to the reference voltage terminal VREF2 to receive a predetermined bias voltage. Figure 4 In this amplifier, transistors T9, T4, and T2 can form amplifier A4, such as a power amplifier or a low-noise amplifier.

[0060] Figure 5This is a schematic diagram of an amplifier circuit 500 in another embodiment. The similarities between amplifier circuit 500 and amplifier circuits 100 and 300 will not be repeated. In amplifier circuit 500, transistor T2 and common-gate circuit C12 can form amplifier A5. Amplifier circuit 500 may further include transistors T7 and T8. Transistor T7 may include a first terminal, a second terminal, and a control terminal, wherein the second terminal can be used to output a reference current IREF4. For example, the second terminal of transistor T7 may be coupled to a current source IS to provide the reference current IREF4. Transistor T8 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal may be coupled to the first terminal of transistor T7, the second terminal may be coupled to the first terminal of transistor T1, and the control terminal may be coupled to the control terminal of transistor T7. The first terminal of transistor T8 and the first terminal of transistor T7 are respectively coupled to a reference voltage source VDD. Transistors T7 and T8 can form a current mirror, which can generate a reference current IREF1 based on the reference current IREF4.

[0061] like Figure 5 As shown, the voltage tracking circuit C1 may additionally include an input terminal N14. The amplifier circuit 500 may additionally include an operational amplifier OP2, which may include a first terminal, a second terminal, and an output terminal. The first terminal of operational amplifier OP2 may be coupled to the second terminal of transistor T7; the second terminal of operational amplifier OP2 may be coupled to the input terminal N14 of the voltage tracking circuit C1; and the output terminal may be coupled to the control terminals of transistors T7 and T8. The voltage tracking circuit C1 can be controlled to selectively connect the input terminal N14 to either the input terminal N12 or the input terminal N13.

[0062] The first terminal of operational amplifier OP2 can be, but is not limited to, the negative input terminal, and the second terminal of operational amplifier OP2 can be, but is not limited to, the positive input terminal. Figure 5 In the architecture consisting of transistor T7, transistor T8, and operational amplifier OP2, a reference current IREF1 can be provided.

[0063] Figure 5 In this configuration, transistors T7 and T8 can correspond to the same width-to-length ratio (W / L ratio). The size of transistor T8 can be an integer multiple of the size of transistor T7, where the size can be defined using the gate width, width-to-length ratio, and / or the number of fingers of the transistor.

[0064] Figure 6 for Figure 1 and Figures 3 to 5The diagram shows a voltage tracking circuit C1. The voltage tracking circuit C1 may include an operational amplifier OP1 and a switching circuit SW. The operational amplifier OP1 may include a first terminal, a second terminal, and an output terminal. The first terminal is coupled to the input terminal N11 of the voltage tracking circuit C1, the second terminal is coupled to the input terminal N14 of the voltage tracking circuit C1, and the output terminal is coupled to the output terminal NO of the voltage tracking circuit C1. The switching circuit SW is used to couple the second terminal of the operational amplifier OP1 to the input terminal N12 or N13 of the voltage tracking circuit C1, thereby controlling the coupling of the second terminal of the operational amplifier OP1 to the first terminal of transistor T2 or the first terminal of transistor T3. In this embodiment, the operational amplifier OP1 can make the voltages at the first and second terminals equal; therefore, the voltage at input terminal N11 can be equal to the voltage at input terminal N13 or input terminal N12.

[0065] In one embodiment, the first terminal of operational amplifier OP1 can be, but is not limited to, a negative input terminal, and the second terminal of operational amplifier OP1 can be, but is not limited to, a positive input terminal. In one embodiment, the first terminal of operational amplifier OP1 is directly coupled to the input terminal of switching circuit SW, and the two output terminals of switching circuit SW are directly coupled to input terminals N12 and N13.

[0066] Figure 7 This is a schematic diagram of the amplifier circuit 700 in another embodiment. Figure 7 As shown, the switching circuit SW of the voltage tracking circuit C1 may include a first switch SW1 and a second switch SW2. The first switch SW1 may be coupled between the input terminal N14 of the voltage tracking circuit C1 and the second terminal of the operational amplifier OP1. The second switch SW2 may be coupled between the input terminal N12 of the voltage tracking circuit C1 and the second terminal of the operational amplifier OP1. The node between the first switch SW2 and the second switch SW may be coupled to... Figure 5 The voltage tracking circuit C1 has an input terminal N14. Therefore, the first switch SW1 can be coupled to the input terminal N14 of the voltage tracking circuit C1, the second terminal of the operational amplifier OP1, and the first terminal of the transistor T3; and the second switch SW2 can be coupled to the input terminal N14 of the voltage tracking circuit C1, the second terminal of the operational amplifier OP1, and the first terminal of the transistor T2.

[0067] When one of the first switch SW1 and the second switch SW2 is turned on, the other can be turned off, as described below.

[0068] like Figure 2 , Figure 7 As shown, in the initial state (e.g.) Figure 2During the period from Time0 to Time1, the first switch SW1 can be turned on and the second switch SW2 can be turned off, so that potentials VD1 and VD4 are substantially equal. At this time, through the mirroring of transistors T4 and T5, potential VD2 is made approximately equal to potential VD1, so that current IREF2 is a predetermined multiple of current IREF1. Since the second switch SW2 is turned off during this stage, unexpected oscillations caused by circuit loops can be avoided.

[0069] like Figure 2 , Figure 7 As shown, in a steady state (e.g.) Figure 2 After Time1, the first switch SW1 can be closed, and the second switch SW2 can be turned on, so that potentials VD1 and VD2 are substantially equal, and current IREF2 is a predetermined multiple of current IREF1. Since the circuit operation is stable at this time, unexpected oscillations caused by circuit loops can be avoided.

[0070] like Figure 7 As shown, the amplifier circuit 700 may selectively include a low-pass filter 710. The low-pass filter 710 may include a first terminal and a second terminal, wherein the first terminal may be coupled to the input terminal N12 of the voltage tracking circuit C1, and the second terminal may be coupled to the first terminal of the transistor T2. The low-pass filter 710 can reduce the interference of the signal SOUT (e.g., radio frequency signal) on the circuit.

[0071] Figure 8 In the example, Figure 7 A schematic diagram of the 700 amplifier circuit. (See attached diagram.) Figure 8 As shown, the low-pass filter 710 includes, for example but not limited to, a capacitor C81 and a resistor R81, wherein the capacitor C81 is coupled between the input terminal N12 of the voltage tracking circuit C1 and the bias terminal VR1, and the resistor R81 is coupled between the input terminal N12 of the voltage tracking circuit C1 and the first terminal of the transistor T2.

[0072] like Figure 7 and Figure 8 As shown, the amplifier circuit 700 may further include a transistor T6. Transistor T6 may include a first terminal, a second terminal, and a control terminal. The first terminal may receive a reference current IREF5, the second terminal may be coupled to a bias terminal VR1, and the control terminal may be coupled to the control terminal of transistor T3 and the first terminal of transistor T6. Transistor T6 and transistor T3 may form a current mirror to provide a reference current IREF3 based on the reference current IREF5. In one embodiment, transistor T6, the fourth transistor T4, and the first transistor T1 may correspond to the same aspect ratio.

[0073] Figure 7 and Figure 8In this example, amplifier A7 may include transistors T4 and T2, but this is only an example. If... Figure 4 As shown, the amplifier includes transistors T9, T4, and T2, which is also within the scope of this embodiment. When the amplifier includes transistors T9, T4, and T2, the control terminal of transistor T4 can be coupled to the control terminal of transistor T5 to perform mirroring operation and indirect voltage tracking, so that in an unstable state, the potential VD2 approximates the potential VD4.

[0074] like Figure 7 and Figure 8 As shown, the voltage of node α can be made to track the voltage of node β by operational amplifier OP2, and the voltage of node γ can be made to track the voltage of node β by operational amplifier OP1. Therefore, the ratio of reference current IREF1 to reference current IREF4 can be accurate.

[0075] exist Figure 1 and Figures 3 to 8 In one embodiment, transistors T1 and T2 may correspond to the same aspect ratio. The size of transistor T2 may be substantially equal to M times the size of transistor T1, where M is a positive integer or the number of fingers. For example, in semiconductor layout and semiconductor manufacturing processes, if transistor T1 is a unit, M transistors T1 can be used to form transistor T2. In one embodiment, transistors T1 and T3 may correspond to the same aspect ratio.

[0076] like Figure 7 and Figure 8 As shown, the amplifier circuit 700 may further include a switch SW3, which may be coupled to the transistor T3 to control the switching on and off of the transistor T3.

[0077] Figure 7 and Figure 8 In this embodiment, switch SW3 is coupled to the control terminal of transistor T3. However, this is only an example and the embodiment is not limited to this. Switch SW3 may be selectively coupled to at least one of the first terminal, the second terminal and the control terminal of transistor T3 to turn transistor T3 on and off.

[0078] The control of transistor T3 is described below. When the amplifier circuit 700 is configured such that the potential VD1 at the first terminal of transistor T1 and the potential VD4 at the first terminal of transistor T3 are maintained substantially equal (e.g., in...), Figure 2 In the initial state, switch SW3 can turn on transistor T3.

[0079] At Figure 2 After the scheduled time TP (that is, Figure 2After Time1, in a stable state, when the potential VD1 at the first terminal of transistor T1 and the potential VD2 at the first terminal of transistor T2 are substantially equal, switch SW3 can turn off transistor T3.

[0080] exist Figures 1 to 5 , Figure 7 and Figure 8 In this circuit, the input terminal N13 of the voltage tracking circuit C1 can maintain the potential VD1 of the first terminal of transistor T1 and the potential VD4 of the first terminal of transistor T3 substantially equal in an unstable state. The aforementioned unstable state can be, for example, as follows: Figure 2 The initial state is when the amplifier circuit has just started operating and has not yet stabilized. Or, for example, it may enter an unstable state due to factors such as main power supply switching, reference voltage switching, excessive changes in the input signal SIN, and / or sudden temperature changes.

[0081] like Figure 7 As shown, the amplifier circuit 700 may optionally include a detection circuit 755, which can be used to detect the potential VD1 of the first terminal of transistor T1 and the potential VD2 of the first terminal of transistor T2, in order to determine Figure 2 The length of the predetermined time TP, that is, the detection circuit 755 can determine. Figure 2 The initial state duration. In one embodiment, the detection circuit 755 is coupled to the voltage tracking circuit C1 or notifies the voltage tracking circuit C1 of the end of a predetermined time TP via a control circuit.

[0082] When the potential VD1 at the first terminal of transistor T1 and the potential VD2 at the first terminal of transistor T2 change from being unequal to being substantially equal, the detection circuit 755 can end the predetermined time TP, and the voltage tracking circuit C1 can maintain the potentials VD1 and VD2 substantially equal to maintain the predetermined ratio between the reference current IREF2 and the reference current IREF1.

[0083] Transistors T3 and T6 can form a current mirror architecture to generate a voltage for transistor T5, allowing the electrical state of transistor T5 to be mirrored to transistor T4, thus generating the same current. Because the reference voltage terminal VREF only provides voltage to the control terminal of transistor T4 (e.g., the gate terminal of transistor T4), a potential VD2, which is the potential of the second terminal of transistor T4 (e.g., the source potential), must still be defined to determine the voltage difference between the control terminal and the second terminal of transistor T4 (e.g., the gate-source voltage of transistor T4) to drive transistor T4.

[0084] According to an embodiment, the channel length of transistor T3 can be greater than that of transistor T2. When transistor T2 is part of an amplifier, for example, when transistor T2 is part of a low-noise amplifier (LNA), in order to improve the gain of the amplifier, the amplifier transistors often use a smaller channel length than the bias transistors. A smaller channel length will lead to undesirable effects, resulting in a poorer mirroring effect of the current mirror formed by transistors T1 and T2. Therefore, a voltage tracking circuit C1 can be used to assist in voltage tracking. For example, a voltage tracking circuit C1 can be used... Figure 6 and Figure 7 The operational amplifier OP1 shown is used to aid voltage tracking. To reduce the use of additional components, transistors T3 and T6 can use a larger channel length than transistor T2, thereby reducing the adverse effects caused by an insufficient channel length and improving the mirroring effect.

[0085] Once the overall circuit operation is stable, voltage tracking circuit C1 can be used for direct tracking to ensure that the potential VD1 at the first terminal of transistor T1 is substantially equal to the potential VD2 at the first terminal of transistor T2. At this point, indirect voltage tracking via transistor T3 is no longer necessary. Therefore, with potential VD1 stable and accurate, transistors T3 and T6 can be turned off.

[0086] Figure 8 for Figures 1 to 7 In one embodiment, a flowchart of a bias current method 800 for stabilizing an amplifier circuit is provided. The bias current method 800 may include the following steps: Step 810: Providing transistor T1 to receive a reference current IREF1; Step 820: Providing transistor T2 to receive a reference current IREF2, wherein the control terminal of transistor T2 is coupled to the input terminal NIN and the control terminal of transistor T1, and the second terminals of transistor T1 and T2 are coupled to the bias terminal VR1; Step 830: Providing transistor T3 to receive a reference current IREF3; Step 840: Providing the output terminal NO of voltage tracking circuit C1 coupled to the control terminal of transistor T1; Step 85 0a: Provide a voltage tracking circuit C1 coupled to the first terminal of transistor T1, the voltage tracking circuit C1 being used to maintain the potential VD1 of the first terminal of transistor T1 and the potential VD4 of the first terminal of transistor T3 substantially equal in the initial state; step 850b: after entering a stable state, maintain the potential VD1 of the first terminal of transistor T1 and the potential VD2 of the first terminal of transistor T2 substantially equal; and step 850c: when entering an unstable state, maintain the potential VD1 of the first terminal of transistor T1 and the potential VD4 of the first terminal of transistor T3 substantially equal.

[0087] Figure 9In this example, the order of steps 810 to 850 is merely an example. If the order of the steps is reasonably adjusted, it still falls within the scope of the embodiment.

[0088] like Figures 1 to 9 As shown, before the amplifier circuit is stable (e.g., Figure 2 In the initial state, voltage tracking circuit C1 can be used to make potential VD1 and potential VD4 approximate each other, and then through mirroring techniques (e.g., by...) Figure 7 Transistors T5 and T4 are used to approximate potentials VD4 and VD2. This indirect voltage tracking operation allows the amplifier's current (e.g., the reference current IREF2) to approximate the expected current value, avoiding unexpected oscillations. After the amplifier circuit stabilizes (e.g., ...), Figure 2 In a stable state, voltage tracking circuit C1 can be used to make potential VD1 and potential VD2 approximate each other. Through this direct voltage tracking operation, it can be ensured that the current of the amplifier (e.g., amplifiers A1, A3, A4, A5, and A7) has the expected current value.

[0089] Figure 10 This is a schematic diagram of amplifier circuit 900 in another embodiment. The similarities between amplifier circuit 900 and amplifier circuit 700 will not be repeated. Amplifier circuit 900 may include transistors T1, T2, T4, T3, T5, and T6, and voltage tracking circuit C91, wherein voltage tracking circuit C91 includes a first operational amplifier OP91, a second operational amplifier OP92, a first switch SW91, and a second switch SW92. The function of voltage tracking circuit C91 may be similar to that of voltage tracking circuit C1 described above.

[0090] When the operation of amplifier circuit 900 is not yet stable (for example, Figure 2 In the initial state, the first switch SW91 can be turned on and the second switch SW92 can be turned off, so that the potential VD1 and the potential VD4 are substantially equal. Furthermore, through the mirror relationship between transistor T5 and transistor T4, the potential VD2 is approximated to the potential VD1 through indirect voltage tracking.

[0091] When the operation of amplifier circuit 900 has stabilized (for example, Figure 2 In a stable state, the first switch SW91 can be closed and the second switch SW92 can be turned on, so that potentials VD1 and VD2 are substantially equal through direct voltage tracking.

[0092] Through the above operations, it can be ensured that the reference current IREF2 is a predetermined multiple of the reference current IREF1. For example, transistors T2 and T4 can be transistors of amplifier A9 (e.g., a power amplifier or a low-noise amplifier). When the reference current IREF2 has a stable current value, the performance of amplifier A9 can be ensured.

[0093] In summary, by using the aforementioned amplifier circuits 100, 300, 400, 500, 700, and 900, along with the bias current method 800, indirect voltage tracking can be performed in the unstable state of the amplifier circuit to avoid unexpected oscillations. In the stable state of the amplifier circuit, direct voltage tracking can be performed to further ensure the amplifier's current value and performance. Therefore, the amplifier circuits and bias current method provided in this embodiment are beneficial for improving amplifier control.

[0094] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

1. An amplification circuit, characterized by, The amplifier circuit comprises: an input terminal for receiving an input signal; an output terminal for outputting the amplified input signal; a first transistor comprising: a first terminal for receiving a first reference current; a second terminal coupled to a first bias terminal; and a control terminal; a second transistor comprising: a first terminal for receiving a second reference current; a second terminal coupled to the first bias terminal; and a control terminal coupled to the input terminal and the control terminal of the first transistor; and a third transistor comprising: a first terminal for receiving a third reference current; a second terminal coupled to the first bias terminal; and a control terminal; a voltage tracking circuit comprising: a first input terminal coupled to the first terminal of the first transistor; a second input terminal coupled to the first terminal of the second transistor; a third input terminal coupled to the first terminal of the third transistor; and a first output terminal coupled to the control terminal of the first transistor; wherein the voltage tracking circuit is configured to maintain the potentials of the first terminal of the first transistor and the first terminal of the third transistor substantially equal at an initial state, and to maintain the potentials of the first terminal of the first transistor and the first terminal of the second transistor substantially equal after a predetermined time.

2. The amplification circuit of claim 1, wherein The amplifier circuit further comprises: a fourth transistor comprising: a first terminal coupled to the output terminal; a second terminal coupled to the first terminal of the second transistor; and a control terminal coupled to a reference voltage terminal.

3. The amplification circuit of claim 2, wherein The amplifier circuit further comprises: a fifth transistor comprising: a first terminal; a second terminal coupled to the first terminal of the third transistor; and a control terminal coupled to the reference voltage terminal.

4. The amplification circuit of claim 3, wherein The fourth transistor and the fifth transistor correspond to the same width-to-length ratio.

5. The amplification circuit of claim 1, wherein, The amplifier circuit further comprises: a fourth transistor comprising: a first terminal; a second terminal coupled to the first terminal of the second transistor; and a control terminal coupled to a first reference voltage terminal; a ninth transistor comprising: a first terminal coupled to the output terminal; a second terminal coupled to the first terminal of the fourth transistor; and a control terminal coupled to a second reference voltage terminal.

6. The amplification circuit of claim 1, wherein The amplifier circuit further comprises: a seventh transistor comprising: a first terminal; a second terminal for outputting a fourth reference current; and a control terminal; and an eighth transistor comprising: a first terminal coupled to the first terminal of the seventh transistor; a second terminal coupled to the first terminal of the first transistor; and a control terminal coupled to the control terminal of the seventh transistor.

7. The amplifier circuit of claim 6, wherein: the amplifier circuit further comprises a second operational amplifier, the second operational amplifier comprising: a first terminal coupled to the second terminal of the seventh transistor; a second terminal coupled to a fourth input terminal of the voltage tracking circuit; and an output terminal coupled to the control terminal of the seventh transistor; and the voltage tracking circuit further comprises: the fourth input terminal; and a first switch coupled between the fourth input terminal and the first terminal of the third transistor.

8. The amplification circuit of claim 6, wherein, The seventh transistor and the eighth transistor correspond to the same width-to-length ratio.

9. The amplification circuit of claim 1, wherein, The voltage tracking circuit further comprises: a first operational amplifier comprising: a first terminal coupled to the first input terminal of the voltage tracking circuit; a second terminal; and an output terminal coupled to the output terminal of the voltage tracking circuit; and a switch circuit for coupling the second terminal of the first operational amplifier to the second input terminal of the voltage tracking circuit or the third input terminal of the voltage tracking circuit, comprising: a first terminal coupled to the second terminal of the first operational amplifier; a second terminal coupled to the second input terminal of the voltage tracking circuit; and a third terminal coupled to the third input terminal of the voltage tracking circuit.

10. The amplification circuit of claim 9, wherein, The switch circuit comprises: a first switch coupled between the second terminal of the first operational amplifier and the first terminal of the third transistor; and a second switch coupled between the second terminal of the first operational amplifier and the first terminal of the second transistor.

11. The amplification circuit of claim 9, wherein, The amplification circuit further comprises: a low-pass filter comprising: a first terminal coupled to the second input terminal of the voltage tracking circuit; and a second terminal coupled to the first terminal of the second transistor.

12. The amplification circuit of claim 1, wherein: the first transistor and the second transistor correspond to the same width-to-length ratio; and a size of the second transistor is substantially equal to M times a size of the first transistor, and M is a positive integer.

13. The amplification circuit of claim 12, wherein: the first transistor and the third transistor correspond to the same width-to-length ratio.

14. The amplification circuit of claim 1, wherein, the predetermined time is between 0 and 2 microseconds (μβsec). The amplification circuit further comprises:

15. The amplification circuit of claim 14, wherein, a third switch for turning on or off the third transistor. The third switch turns off the third transistor after the predetermined time.

16. The amplification circuit of claim 15, wherein, The third transistor is turned on when potentials at the first terminal of the first transistor and the first terminal of the third transistor are maintained substantially equal.

17. The amplification circuit of claim 15, wherein, The third input terminal of the voltage tracking circuit is for maintaining the potentials at the first terminal of the first transistor and the first terminal of the third transistor substantially equal during an unstable state.

18. The amplification circuit of claim 1, wherein, A detection circuit is further included for detecting the potentials at the first terminal of the first transistor and the first terminal of the second transistor to determine a length of the predetermined time, wherein the detection circuit ends the predetermined time when the potentials at the first terminal of the first transistor and the first terminal of the second transistor change from unequal to substantially equal, and the voltage tracking circuit is for maintaining the potentials at the first terminal of the first transistor and the first terminal of the second transistor substantially equal.

19. The amplification circuit of claim 1, wherein, ​ 20. A method for stabilizing the bias current of an amplifier circuit, comprising: The amplification circuit includes an input terminal for receiving an input signal and an output terminal for outputting the amplified input signal, comprising the steps of: providing a first transistor for receiving a first reference current; providing a second transistor for receiving a second reference current, and a control terminal of the second transistor is coupled to the input terminal and the control terminal of the first transistor, wherein the first transistor and the second transistor are coupled to the first bias terminal; providing a third transistor for receiving a third reference current; providing a voltage tracking circuit coupled to the first terminal of the first transistor for maintaining a potential of a first terminal of the first transistor substantially equal to a potential of a first terminal of the third transistor at an initial state, and for maintaining the potential of the first terminal of the first transistor substantially equal to a potential of a first terminal of the second transistor after a predetermined time; and providing a first output terminal of the voltage tracking circuit coupled to the control terminal of the first transistor.

21. The method of claim 20, wherein the bias current is provided by a current source. The voltage tracking circuit is used to maintain the potential of the first terminal of the first transistor substantially equal to the potential of the first terminal of the third transistor at an unstable state.

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