Source follower circuit and flip source follower circuit

Abstract

The invention provides a source follower circuit. The source follower circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a feedback loop circuit. For the first MOS transistor, a grid electrode is used for receiving an input signal of the source follower circuit, and a source electrode is used for outputting an output signal of the source follower circuit. For the second MOS transistor, a gate is coupled to a bias voltage, a source is coupled to a first reference voltage, and a drain is coupled to a source of the first MOS transistor. The third MOS transistor is a metal oxide semiconductor transistor having a self-biased diode connection with its own gate coupled to its own drain. The drain of the third MOS transistor is coupled to the drain of the first MOS transistor, and the source of the third MOS transistor is coupled to a second reference voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to voltage buffer design, and in particular, to a source follower circuit with at least one feedback loop and at least one metal-oxide-semiconductor (MOS) load that is self-biased diode-connected. BACKGROUND

[0002] Conventional source followers have high input impedance and low output impedance, and can be used as voltage buffers to drive capacitive loads. If a local negative feedback loop is employed, the output impedance can be further reduced, a topology often referred to as a "flipped source follower". In addition, the feedback path can also slightly improve the slew rate of the output signal. In the first implementation, the local negative feedback loop was formed by a direct current (DC) coupling path, but this is not suitable for high linearity applications using modern advanced complementary metal-oxide-semiconductor (CMOS) manufacturing processes. To overcome this limitation and improve bias flexibility, a local feedback path formed by a floating capacitor became popular. However, for designs using this topology, the DC bias of the internal nodes becomes very unstable. Therefore, there is a need for an innovative circuit design that can provide a simple and power-efficient way to solve this problem. SUMMARY

[0003] One of the objectives of the present invention is to propose a source follower circuit with at least one feedback loop and at least one metal-oxide-semiconductor load that is self-biased diode-connected.

[0004] In one embodiment of the present invention, a source follower circuit is disclosed. The source follower circuit includes a first metal oxide semiconductor transistor, a second metal oxide semiconductor transistor, a third metal oxide semiconductor transistor, and a feedback loop circuit. A gate of the first metal oxide semiconductor transistor is configured to receive an input signal of the source follower circuit, and a source of the first metal oxide semiconductor transistor is configured to output an output signal of the source follower circuit. A gate of the second metal oxide semiconductor transistor is coupled to a bias voltage, a source of the second metal oxide semiconductor transistor is coupled to a first reference voltage, and a drain of the second metal oxide semiconductor transistor is coupled to the source of the first metal oxide semiconductor transistor. The third metal oxide semiconductor transistor is a self-bias diode-connected metal oxide semiconductor transistor, a gate of the third metal oxide semiconductor transistor is coupled to a drain of the third metal oxide semiconductor transistor, the drain of the third metal oxide semiconductor transistor is coupled to a drain of the first metal oxide semiconductor transistor, and a source of the third metal oxide semiconductor transistor is coupled to a second reference voltage. The feedback loop circuit is coupled between the drain of the first metal oxide semiconductor transistor and the gate of the second metal oxide semiconductor transistor.

[0005] In one embodiment of the present invention, a flipped source follower circuit is disclosed. The flipped source follower circuit includes a first metal oxide semiconductor transistor, a second metal oxide semiconductor transistor, and a low pass filter. A gate of the first metal oxide semiconductor transistor is configured to receive an input signal of the flipped source follower circuit, and a source of the first metal oxide semiconductor transistor is configured to output an output signal of the flipped source follower circuit. A drain of the second metal oxide semiconductor transistor is coupled to a drain of the first metal oxide semiconductor transistor, and a source of the second metal oxide semiconductor transistor is coupled to a reference voltage. An input node of the low pass filter is coupled to the drain of the second metal oxide semiconductor transistor, and an output node of the low pass filter is coupled to a gate of the second metal oxide semiconductor transistor.

[0006] In one embodiment of the present invention, a flip-around source follower circuit is disclosed. The flip-around source follower circuit includes a first metal oxide semiconductor transistor, a second metal oxide semiconductor transistor, a third metal oxide semiconductor transistor, a fourth metal oxide semiconductor transistor, a resistor, and another resistor. A gate of the first metal oxide semiconductor transistor is configured to receive an input signal of the flip-around source follower circuit, and a source of the first metal oxide semiconductor transistor is configured to output an output signal of the flip-around source follower circuit. A drain of the second metal oxide semiconductor transistor is coupled to a drain of the first metal oxide semiconductor transistor, and a source of the second metal oxide semiconductor transistor is coupled to a reference voltage. A gate of the third metal oxide semiconductor transistor is configured to receive another input signal of the flip-around source follower circuit, a source of the third metal oxide semiconductor transistor is configured to output another output signal of the flip-around source follower circuit, the input signal and the another input signal are differential inputs, and the output signal and the another output signal are differential outputs. A gate of the fourth metal oxide semiconductor transistor is coupled to a gate of the second metal oxide semiconductor transistor, a drain of the fourth metal oxide semiconductor transistor is coupled to a drain of the third metal oxide semiconductor transistor, and a source of the fourth metal oxide semiconductor transistor is coupled to the reference voltage. The resistor is coupled between the drain and the gate of the second metal oxide semiconductor transistor. The another resistor is coupled between the drain and the gate of the fourth metal oxide semiconductor transistor.

[0007] The disclosed techniques can achieve high-speed, low-voltage, low-power, and high-linearity source follower circuits. For example, the disclosed techniques include using a self-biased diode-connected MOS transistor to determine the DC bias of the drain of another MOS transistor, using AC ground to ensure the regulated DC level of the drain voltage at low frequencies, using high impedance to ensure high local feedback loop gain at high frequencies, and using injected (or sunk) current to increase the output voltage swing range. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 FIG. 1 is a circuit diagram of a source follower circuit with a first single-ended topology according to one embodiment of the present invention.

[0009] Figure 2 FIG. 2 is a circuit diagram of a source follower circuit with a first fully differential topology according to one embodiment of the present invention.

[0010] Figure 3 FIG. 3 is a circuit diagram of a source follower circuit with a second single-ended topology according to one embodiment of the present invention.

[0011] Figure 4 is a circuit diagram of a source follower circuit having a second fully differential topology according to an embodiment of the present invention.

[0012]

Symbol Explanation

[0013] 100, 200, 300, 400: Source follower circuit

[0014] 102: Low pass filter

[0015] 104, 204_P, 204_N: Feedback loop circuit

[0016] 106, 206, 306, 406: Reference current generator circuit

[0017] 108, 208_P, 208_N: High pass filter

[0018] M1, M2, M3, M1P, M2P, M3P, M1N, M2N, M3N: MOS transistor

[0019] V IN , V INP , V INN : Input signal

[0020] V OUT , V OUTP , V OUTN : Output signal

[0021] R B , R LP , R BP , R LPP , R BN , R LPN : Resistance

[0022] C B , C LP , C BP , C BN : Capacitance

[0023] V B : Bias voltage

[0024] V DD : Supply voltage

[0025] GND: Ground voltage

[0026] V D , V DP , V DN : Drain voltage

[0027] V X , V G , V GP , VGN Gate voltage

[0028] I BLEED Reference current Detailed Implementation

[0029] Certain terms are used in this specification and the claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the claims do not distinguish components based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout this specification and the claims are open-ended and should be interpreted as "including but not limited to". Furthermore, the term "coupled" or "coupled" here includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0030] Figure 1 This is a circuit diagram of a source follower circuit with a first single-ended topology according to an embodiment of the present invention. The source follower circuit 100 can be used as a voltage buffer to drive a capacitive load (e.g., the capacitor of a sampler). Figure 1 As shown, the source follower circuit 100 includes multiple metal-oxide-semiconductor (MOS) transistors M1, M2, and M3, a low-pass filter 102, a feedback loop circuit 104, and a reference current generator circuit 106. In this embodiment, each of the MOS transistors M1 and M2 is a P-channel MOS transistor, and the MOS transistor M3 is an N-channel MOS transistor. Regarding the MOS transistor M1, its gate is used to receive the input signal V from the source follower circuit 100. IN (It is a single-ended voltage input), and the source terminal is used to output the output signal V of the source follower circuit 100. OUT (It is a single-ended voltage output). Regarding the MOS transistor M2, the gate is connected to a resistor R. B And coupled to the bias voltage V B The source terminal is coupled to a first reference voltage (e.g., the supply voltage V). DDThe drain terminal of MOS transistor M3 is coupled to the source terminal of MOS transistor M1. In this embodiment, MOS transistor M3 is a MOS transistor connected to a self-biased diode (i.e., a MOS load connected to a self-biased diode), wherein the gate terminal of MOS transistor M3 is coupled to the drain terminal of MOS transistor M3. Furthermore, the drain terminal of MOS transistor M3 is coupled to the drain terminal of MOS transistor M1, and the source terminal of MOS transistor M3 is coupled to a second reference voltage (e.g., ground voltage GND, where GND < V). DD ).

[0031] In this embodiment, the source follower circuit 100 is designed based on a flip-flop source follower structure with low output impedance, low noise, and high linearity. Therefore, a feedback loop circuit 104 is used to provide an alternating current (AC) coupled feedback path, such as... Figure 1 As shown, the feedback loop circuit 104 uses capacitor C B This is achieved by resistor R, and the high-pass filter 108 is made of resistor R. B and capacitor C B This constitutes the gate voltage V of the MOS transistor M2. G The DC level is determined by the bias voltage V. B To set it.

[0032] The main difference between the source follower circuit 100 proposed in this invention and the traditional flip-over source follower circuit is that the source follower circuit 100 proposed in this invention uses a MOS load (implemented by MOS transistor M3) connected to a self-biased diode to set the drain voltage V of MOS transistor M1 (which is the input transistor). D The DC level (i.e., the DC bias voltage at the drain terminal). Specifically, MOS transistor M3 operates in the saturation region, and the gate voltage V of MOS transistor M3... X It has a fixed DC value equal to the gate-to-source voltage of MOS transistor M3. Therefore, due to the gate voltage V of MOS transistor M3... X Having a fixed DC value, the drain voltage V of MOS transistor M1 D The DC level will also remain constant.

[0033] In this embodiment, the low-pass filter 102 may include a large resistor R. LP and large capacitor C LP Where the resistance R LP Coupled between the drain and gate terminals of MOS transistor M3, and capacitor C LPIt is coupled between the gate terminal of MOS transistor M3 and a second reference voltage (e.g., ground voltage GND). Specifically, the input node of low-pass filter 102 is coupled to the drain terminal of MOS transistor M3, and the output node of low-pass filter 102 is coupled to the gate terminal of MOS transistor M3. Due to capacitor C LP The provided AC coupling results in the gate voltage V of the MOS transistor M3. X It is AC-grounded, meaning that the gate terminal of MOS transistor M3 acts as the AC ground for the AC signal component. Therefore, the drain voltage V... D It has a stable DC level at low frequencies.

[0034] The source follower circuit 100 can be used in high-speed receivers, with resistor R... LP It can provide high impedance at high frequencies, so that the high-frequency signal component at the drain terminal of MOS transistor M1 can flow through the feedback loop circuit 104, thereby avoiding a decrease in local feedback loop gain. Since the feedback loop circuit 104 has high feedback loop gain, it can effectively reduce the output impedance of the source follower circuit 100.

[0035] As mentioned above, the drain voltage V D The DC level is determined by the gate voltage V of the MOS transistor M3. X The DC level is used to set the drain voltage V. D The DC level will be equal to the gate voltage V. X The DC level. In some embodiments, the gate-source voltage of MOS transistor M3 can be 0.4V-0.45V. When the source follower circuit 100 is used by a low-power receiver with a low supply voltage, the DC bias voltage at the drain terminal of MOS transistor M1 may be too high, resulting in a small output voltage swing range for MOS transistor M1 due to the small gate-source voltage. To enhance linearity and drive capability, this invention proposes adding a reference current generator circuit 106 to the source follower circuit 100. In one example, the reference current generator circuit 106 can be implemented using a current source. In another example, the reference current generator circuit 106 can be implemented using a voltage source and a resistor.

[0036] like Figure 1 As shown, the reference current generator circuit 106 is coupled to the gate of the MOS transistor M3 and is used to generate current flowing through the resistor R. LP Reference current I BLEEDIn this embodiment, the reference current I BLEED is the source current injected to the resistor R LP , which makes the drain voltage of the MOS transistor M3 (which is also the drain voltage V D of the MOS transistor Ml) lower than the gate voltage V X of the MOS transistor M3, in particular, As the DC level of the drain voltage V D of the MOS transistor Ml is lowered, the drain-to-source voltage range of the MOS transistor Ml is increased, so the output voltage swing range of the source follower circuit 100 is increased.

[0037] In this embodiment, the source follower circuit 100 is a flipped source follower circuit with local feedback loop, and the source follower circuit 100 is implemented with one or more of the techniques disclosed in this application to achieve a high-speed, low-voltage, low-power, high-linearity source follower circuit, for example, the source follower circuit 100 is implemented with one or more of the techniques disclosed in this application including using the MOS transistor M3 with self-biased diode connection to determine the DC bias of the drain terminal of the MOS transistor Ml, using the AC ground (which is provided through the capacitor C LP to ensure the regulated DC level of the drain voltage V D at low frequency, using the high impedance (which is provided through the resistor R LP to ensure the high local feedback loop gain at high frequency, and using the source current (which is provided through the reference current generator circuit 106) injected to the resistor R LP to increase the output voltage swing range. However, this is only an example and not a limitation of this application, in fact, any source follower circuit (especially, any flipped source follower circuit with local feedback loop) implemented with one or more of the techniques disclosed in this application falls within the scope of this application.

[0038] In short, the topology proposed in this invention uses simple circuit components without complex operational amplifiers to define the DC bias of a source follower circuit with high local feedback loop gain, while occupying only a low voltage headroom. With the help of additional injection current, the source follower circuit with low output impedance can have an increased output voltage swing range, thereby achieving high linearity performance. Due to this simple, compact, and low-power design, this topology is suitable for multi-channel analog-to-digital converter applications, where an array of analog-to-digital converters is driven in parallel by multiple source follower circuits to achieve time-interleaving analog-to-digital conversion.

[0039] Figure 1 The source follower circuit 100 shown has a single-ended topology; however, the techniques proposed in this invention can also be applied to source follower circuits with a fully-differential topology. Figure 2 This is a circuit diagram of a source follower circuit with a first fully differential topology according to an embodiment of the present invention. The source follower circuit 200 can be used as a voltage buffer to drive a capacitive load (e.g., the capacitor of a sampler). Figure 2 As shown, the source follower circuit 200 includes multiple MOS transistors M1P, M1N, M2P, M2N, M3P, M3N, and multiple resistors R. LPP R LPN The system includes multiple feedback loop circuits 204_P and 204_N, and a reference current generator circuit 206. In this embodiment, each of the MOS transistors M1P, M2P, M1N, and M2N is a PMOS transistor, and each of the MOS transistors M3P and M3N is an NMOS transistor.

[0040] Regarding the MOS transistor M1P, the gate terminal is used to receive an input signal V from the source follower circuit 200. INP The source terminal is used to output an output signal V of the source follower circuit 200. OUTP Regarding the MOS transistor M1N, the gate terminal is used to receive another input signal V from the source follower circuit 200. INN The source terminal is another output signal V used to output the source follower circuit 200. OUTN Input signal V INP V INN It is the differential voltage input of the source follower circuit 200, and the output signal V. OUTP VOUTN It is the differential voltage output of the source follower circuit 200.

[0041] Regarding the MOS transistor M2P, the gate is connected to a resistor R. BP Coupled to bias voltage V B The source terminal is coupled to a first reference voltage (e.g., the supply voltage V). DD The drain terminal is coupled to the source terminal of the MOS transistor M1P. Regarding the MOS transistor M2N, the gate terminal is connected to the resistor R. BN Coupled to bias voltage V B The source terminal is coupled to a first reference voltage (e.g., the supply voltage V). DD The drain terminal is coupled to the source terminal of the MOS transistor M1N.

[0042] In this embodiment, both MOS transistors M3P and M3N are self-biased diode-connected MOS transistors. The gate terminal of MOS transistor M3P is coupled to its drain terminal, and the gate terminal of MOS transistor M3N is connected to its drain terminal. According to the fully differential topology, the gate terminals of MOS transistors M3P and M3N are connected to each other to form a virtual ground. Specifically, due to the inherent characteristics of the fully differential topology, a gate voltage V is generated at the node that serves as the AC ground for the AC signal component. X Therefore, in a fully differential topology, the capacitor C used in a single-ended topology can be omitted. LP .

[0043] Additionally, the drain terminal of MOS transistor M3P is coupled to the drain terminal of MOS transistor M1P, and the source terminal of MOS transistor M3P is coupled to a second reference voltage (e.g., ground voltage GND, where GND < V). DD The drain terminal of MOS transistor M3N is coupled to the drain terminal of MOS transistor M1N, and the source terminal of MOS transistor M3N is coupled to a second reference voltage (e.g., ground voltage GND).

[0044] as Figure 1 The source follower circuits 100 and 200 shown are also designed based on a flip-flop source follower structure, which provides low output impedance and isolates noise performance and in-band linearity. Figure 2 As shown, the source follower circuit 200 uses feedback loop circuits 204_P and 204_N to provide AC-coupled feedback paths, respectively. Feedback loop circuit 204_P uses capacitor C. BP To achieve this, the high-pass filter 208_P is made of resistor R. BPand capacitor C BP Formed. The feedback loop circuit 204_N uses capacitor C. BN To achieve this, the high-pass filter 208_N is made of resistor R. BN and capacitor C BN Formation. Gate voltage V of MOS transistor M2P. GP The DC level is determined by the bias voltage V. B The gate voltage V of the MOS transistor M2N is set. GN The DC level is also determined by the bias voltage V. B The settings.

[0045] The source follower circuit 200 proposed in this invention uses a MOS load (implemented by MOS transistor M3P) connected to a self-biased diode to set the drain voltage V of MOS transistor M1P (which is an input transistor). DP The DC level (i.e., the DC bias voltage at the drain terminal) is used, and the drain voltage V of the MOS transistor M1N (which is another input transistor) is set using another self-biased diode connected to the MOS load (implemented by the MOS transistor M3N). DN The DC level (i.e., the DC bias voltage at the drain terminal). Specifically, both MOS transistors M3P and M3N operate in the saturation region, and the gate voltage V of both MOS transistors M3P and M3N is... X Having a fixed DC value equal to the gate-source voltage of MOS transistors M3P and M3N, therefore, the drain voltage V of MOS transistor M1P is... DP The DC level will be affected by the gate voltage V X The DC level has a fixed value, and the drain voltage V of the MOS transistor M1N is... DN The DC level will be affected by the gate voltage V X It has a fixed value due to the DC level.

[0046] Due to the inherent characteristics of the fully differential topology, the gate voltage V of both MOS transistors M3P and M3N is... X It is generated at the node where the AC signal is grounded, thus the drain voltage V DP and V DN It exhibits a stable DC level even at low frequencies. The source follower circuit 200 can be used in high-speed receivers, with resistor R... LPP and R LPNEach of these circuits can provide high impedance at high frequencies. In this way, the high-frequency signal components at the drain of MOS transistor M1P flow through feedback loop circuit 204_P, and the high-frequency signal components at the drain of MOS transistor M1N flow through feedback loop circuit 204_N, thus avoiding a decrease in local feedback loop gain. Since both feedback loop circuits 204_P and 204_N have high feedback loop gain, the output impedance of the source follower circuit 200 can be effectively reduced.

[0047] As mentioned above, the drain voltage V DP and V DN The DC level of each of them is based on the gate voltage V. X The DC level (which is set by the gate-source voltage of MOS transistors M3P and M3N) is used to set the voltage. In some embodiments, the gate-source voltage of MOS transistors M3P and M3N can be approximately 0.4V-0.45V. When the source follower circuit 200 is applied to a low-power receiver with a low supply voltage, the DC bias at the drain terminals of MOS transistors M1P and M1N may be too high, resulting in a small output voltage swing range for MOS transistors M1P and M1N due to the small gate-source voltage. To enhance linearity and drive capability, this invention proposes adding a reference current generator circuit 206 to the source follower circuit 200. In one example, the reference current generator circuit 206 can be implemented using a current source. In another example, the reference current generator circuit 206 can be implemented using a voltage source and a resistor.

[0048] like Figure 2 As shown, the reference current generator circuit 206 is coupled to the gates of MOS transistors M3P and M3N, and is used to generate the reference current I. BLEED The first reference current It will flow through resistor R LPP and the second reference current It will flow through resistor R LPN In this embodiment, the reference current I BLEED The injected current will cause the drain voltage of MOS transistor M3P (which is also the drain voltage V of MOS transistor M1P) to increase. DP The gate voltage V of the MOS transistor M3P is lower than that of the MOS transistor M3P. X The injected current, and causes the drain voltage of MOS transistor M3N (which is also the drain voltage V of MOS transistor M1N) to increase. DN The gate voltage V of the MOS transistor M3N is lower than that of the MOS transistor M3N. X To be clear, as well as Due to the drain voltage V of the MOS transistor M1P DPAs the DC level decreases, the drain-source voltage range of the MOS transistor M1P increases; similarly, due to the decrease in the drain voltage V of the MOS transistor M1N... DN As the DC level decreases, the drain-source voltage range of the MOS transistor M1N increases, which in turn increases the output voltage swing range of the source follower circuit 200.

[0049] In this embodiment, the source follower circuit 200 is a flip-flop source follower circuit with a local feedback loop, and employs several techniques proposed in this invention to achieve a high-speed, low-voltage, low-power, and high-linearity source follower circuit. For example, the techniques proposed in this invention employed in the source follower circuit 200 include using self-biased diode-connected MOS transistors M3P and M3N to determine the DC bias voltage of MOS transistors M1P and M1N, and using AC ground (provided through a virtual ground at the gate terminals of MOS transistors M1P and M1N) to ensure the drain voltage V at low frequencies. DP and V DN To adjust the DC level, use a high impedance (which is through resistor R). LPP R LPN To provide) to ensure high local feedback loop gain at high frequencies, and using injection into resistor R LPP and R LPN The injected current (provided by the reference current generator circuit 206) increases the output voltage swing range. However, this is merely illustrative and not intended to limit the invention. In fact, any source follower circuit employing one or more of the techniques proposed in this invention (especially any flip-flop source follower circuit with a local feedback loop) falls within the scope of this invention.

[0050] exist Figure 1 In the illustrated embodiment, both MOS transistors M1 and M2 are PMOS transistors, and MOS transistor M3 is an NMOS transistor. In some embodiments of the present invention, the technology proposed in this invention can also be used in alternative source follower designs having MOS transistors M1 and M2 implemented using NMOS transistors and MOS transistor M3 implemented using PMOS transistors.

[0051] Figure 3 This is a circuit diagram of a source follower circuit with a second single-ended topology according to an embodiment of the present invention. Regarding the source follower circuit 300, both MOS transistors M1 and M2 are NMOS transistors, and MOS transistor M3 is a PMOS transistor. The source terminal of MOS transistor M3 is coupled to a first reference voltage (e.g., the supply voltage V). DDThe source terminal of MOS transistor M2 is coupled to a second reference voltage (e.g., ground voltage GND, where GND < V). DD ).like Figure 3 As shown, the reference current generator circuit 306 is coupled to the gate of the MOS transistor M3 and is used to generate current flowing through the resistor R. LP Reference current I BLEED Since the MOS load connected to the self-biased diode is implemented by a PMOS transistor, the reference current I... BLEED It draws current to maintain the drain voltage of MOS transistor M3 (which is also the drain voltage V of MOS transistor M1). D The gate voltage V of MOS transistor M3 is higher than that of MOS transistor M3. X To be clear, Due to the drain voltage V of MOS transistor M1 D As the DC level increases, the drain-source voltage range of the MOS transistor M1 will increase, as will the output voltage swing range of the source follower circuit 300.

[0052] In this embodiment, the source follower circuit 300 is a flip-flop source follower circuit with a local feedback loop, and employs multiple technologies proposed in this invention to achieve a high-speed, low-voltage, low-power, and high-linearity source follower circuit. For example, the technologies proposed in this invention employed in the source follower circuit 300 include using a MOS transistor M3 connected to a self-biased diode to determine the DC bias of the MOS transistor M1, and using AC ground (which is connected through capacitor C). LP To provide) to ensure the drain voltage V at low frequencies D To adjust the DC level, use a high impedance (which is through resistor R). LP To provide) to ensure high local feedback loop gain at high frequencies, and using draw from resistor R LP The current drawn (provided by the reference current generator circuit 306) is used to increase the output voltage swing range. However, this is merely illustrative and not intended to limit the invention. In fact, any source follower circuit employing one or more of the techniques proposed in this invention (especially any flip-flop source follower circuit with a local feedback loop) falls within the scope of this invention.

[0053] exist Figure 2In the illustrated embodiments, MOS transistors M1P, M1N, M2P, and M2N are all PMOS transistors, and MOS transistors M3P and M3N are both NMOS transistors. In some embodiments of the present invention, the technology proposed in this invention can also be used in alternative source follower designs having MOS transistors M1P, M1N, M2P, and M2N implemented using NMOS transistors and MOS transistors M3P and M3N implemented using PMOS transistors.

[0054] Figure 4 This is a circuit diagram of a source follower circuit with a second fully differential topology according to an embodiment of the present invention. Regarding the source follower circuit 400, MOS transistors M1P, M1N, M2P, and M2N are all NMOS transistors, and MOS transistors M3P and M3N are both PMOS transistors. The source terminals of both MOS transistors M3P and M3N are coupled to a first reference voltage (e.g., the supply voltage V). DD The source terminals of both MOS transistors M2P and M2N are coupled to a second reference voltage (e.g., ground voltage GND, where GND < V). DD ).like Figure 4 As shown, the reference current generator circuit 406 is coupled to the gates of MOS transistors M3P and M3N and is used to generate the reference current I. BLEED The first reference current It will flow through resistor R LPP and the second reference current It will flow through resistor R LPN Since the MOS load connected to the self-biased diode is implemented by a PMOS transistor, the reference current I... BLEED It draws current, which will cause the drain voltage of MOS transistor M3P (which is also the drain voltage V of MOS transistor M1P) to decrease. DP The gate voltage V of the MOS transistor M3P is higher than that of the MOS transistor M3P. X This will also affect the drain voltage of MOS transistor M3N (which is also the drain voltage V of MOS transistor M1N). DN The gate voltage V of the MOS transistor M3N is higher than that of the MOS transistor M3N. X To be clear, as well as Due to the drain voltage V of the MOS transistor M1P DP As the DC level increases, the drain-source voltage range of the MOS transistor M1P will increase; similarly, due to the increase in the drain voltage V of the MOS transistor M1N... DN As the DC level increases, the drain-source voltage range of the MOS transistor M1N will increase, which in turn will increase the output voltage swing range of the source follower circuit 400.

[0055] In this embodiment, the source follower circuit 400 is a flip-flop source follower circuit with a local feedback loop, and employs several techniques proposed in this invention to achieve a high-speed, low-voltage, low-power, and high-linearity source follower circuit. For example, the techniques proposed in this invention employed in the source follower circuit 400 include using self-biased diode-connected MOS transistors M3P and M3N to determine the DC bias voltage of MOS transistors M1P and M1N, and using AC ground (provided through a virtual ground at the gate terminals of MOS transistors M3P and M3N) to ensure the drain voltage V at low frequencies. DP V DN To adjust the DC level, use a high impedance (which is through resistor R). LPP R LPN To provide) to ensure high local feedback loop gain at high frequencies, and to use the draw-from resistor R LPP R LPN The current drawn (provided by the reference current generator circuit 406) is used to increase the output voltage swing range. However, this is only illustrative and not intended to limit the invention. In fact, any source follower circuit that employs one or more of the techniques proposed in this invention (in particular, any flip-flop source follower circuit with a local feedback loop) falls within the scope of this invention.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A source follower circuit, comprising: a first metal oxide semiconductor transistor, wherein a gate of the first metal oxide semiconductor transistor is configured to receive an input signal of the source follower circuit, and a source of the first metal oxide semiconductor transistor is configured to output an output signal of the source follower circuit; a second metal oxide semiconductor transistor, wherein a gate of the second metal oxide semiconductor transistor is coupled to a bias voltage, a source of the second metal oxide semiconductor transistor is coupled to a first reference voltage, and a drain of the second metal oxide semiconductor transistor is coupled to the source of the first metal oxide semiconductor transistor; a third metal oxide semiconductor transistor, wherein the third metal oxide semiconductor transistor is a self-bias diode-connected metal oxide semiconductor transistor, a gate of the third metal oxide semiconductor transistor is coupled to a drain of the third metal oxide semiconductor transistor, the drain of the third metal oxide semiconductor transistor is coupled to a drain of the first metal oxide semiconductor transistor, and a source of the third metal oxide semiconductor transistor is coupled to a second reference voltage; and a feedback loop circuit coupled between the drain of the first metal oxide semiconductor transistor and the gate of the second metal oxide semiconductor transistor.

2. The source follower circuit of claim 1, further comprising: a resistor coupled between the drain and the gate of the third metal oxide semiconductor transistor.

3. The source follower circuit of claim 2, further comprising: a reference current generator circuit coupled to the gate of the third metal oxide semiconductor transistor and configured to generate a reference current flowing through the resistor.

4. The source follower circuit of claim 3, wherein each of the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor is a P-channel metal oxide semiconductor transistor, the third metal oxide semiconductor transistor is an N-channel metal oxide semiconductor transistor, and the reference current is a sinking current configured to lower a drain voltage of the third metal oxide semiconductor transistor below a gate voltage of the third metal oxide semiconductor transistor.

5. The source follower circuit of claim 3, wherein the first reference voltage is higher than the second reference voltage, and the reference current is a sinking current configured to lower a drain voltage of the third metal oxide semiconductor transistor below a gate voltage of the third metal oxide semiconductor transistor. ​ 6. The source follower circuit of claim 3, wherein each of the first and second MOS transistors is an N-channel MOS transistor; the third MOS transistor is a P-channel MOS transistor; and the reference current is a sink current to cause a drain voltage of the third MOS transistor to be higher than a gate voltage of the third MOS transistor.

7. The source follower circuit of claim 3, wherein the first reference voltage is lower than the second reference voltage; and the reference current is a sink current to cause a drain voltage of the third MOS transistor to be higher than a gate voltage of the third MOS transistor.

8. The source follower circuit of claim 1, further comprising: a capacitor coupled between the gate of the third MOS transistor and the second reference voltage.

9. The source follower circuit of claim 1, further comprising: a fourth MOS transistor, wherein a gate of the fourth MOS transistor is to receive another input signal of the source follower circuit, a source of the fourth MOS transistor is to output another output signal of the source follower circuit, the input signal and the another input signal are a differential input, and the output signal and the another output signal are a differential output; a fifth MOS transistor, wherein a gate of the fifth MOS transistor is coupled to the bias voltage, a source of the fifth MOS transistor is coupled to the first reference voltage, and a drain of the fifth MOS transistor is coupled to the source of the fourth MOS transistor; a sixth MOS transistor, wherein the sixth MOS transistor is a self-bias diode-connected MOS transistor, a gate of the sixth MOS transistor is coupled to the gate of the third MOS transistor and a drain of the sixth MOS transistor, the drain of the sixth MOS transistor is coupled to a drain of the fourth MOS transistor, and a source of the sixth MOS transistor is coupled to the second reference voltage; and another feedback loop circuit coupled between the drain of the fourth MOS transistor and the gate of the fifth MOS transistor.

10. The source follower circuit of claim 9, further comprising: a resistor coupled between the drain and the gate of the third MOS transistor; and another resistor coupled between the drain and the gate of the sixth MOS transistor.

11. The source follower circuit of claim 10, further comprising: ​ ​ ​ ​ ​ ​ ​ ​ a reference current generator circuit coupled to the gate of the third metal oxide semiconductor transistor and the gate of the sixth metal oxide semiconductor transistor and configured to generate a reference current flowing through the resistor and another reference current flowing through the other resistor.

12. The source follower circuit of claim 11, wherein each of the first metal oxide semiconductor transistor, the second metal oxide semiconductor transistor, the fourth metal oxide semiconductor transistor, and the fifth metal oxide semiconductor transistor is a P-channel metal oxide semiconductor transistor; each of the third metal oxide semiconductor transistor and the sixth metal oxide semiconductor transistor is an N-channel metal oxide semiconductor transistor; the reference current is a sinking current to cause a drain voltage of the third metal oxide semiconductor transistor to be lower than a gate voltage of the third metal oxide semiconductor transistor; and the other reference current is a sinking current to cause a drain voltage of the sixth metal oxide semiconductor transistor to be lower than a gate voltage of the sixth metal oxide semiconductor transistor.

13. The source follower circuit of claim 11, wherein the first reference voltage is higher than the second reference voltage; the reference current is a sinking current to cause a drain voltage of the third metal oxide semiconductor transistor to be lower than a gate voltage of the third metal oxide semiconductor transistor; and the other reference current is a sinking current to cause a drain voltage of the sixth metal oxide semiconductor transistor to be lower than a gate voltage of the sixth metal oxide semiconductor transistor.

14. The source follower circuit of claim 11, wherein each of the first metal oxide semiconductor transistor, the second metal oxide semiconductor transistor, the fourth metal oxide semiconductor transistor, and the fifth metal oxide semiconductor transistor is an N-channel metal oxide semiconductor transistor; each of the third metal oxide semiconductor transistor and the sixth metal oxide semiconductor transistor is a P-channel metal oxide semiconductor transistor; the reference current is a sinking current to cause a drain voltage of the third metal oxide semiconductor transistor to be lower than a gate voltage of the third metal oxide semiconductor transistor; and the other reference current is a sinking current to cause a drain voltage of the sixth metal oxide semiconductor transistor to be lower than a gate voltage of the sixth metal oxide semiconductor transistor.

15. The source follower circuit of claim 11, wherein the first reference voltage is lower than the second reference voltage; the reference current is a sinking current to cause a drain voltage of the third metal oxide semiconductor transistor to be lower than a gate voltage of the third metal oxide semiconductor transistor; and the other reference current is a sinking current to cause a drain voltage of the sixth metal oxide semiconductor transistor to be lower than a gate voltage of the sixth metal oxide semiconductor transistor.

16. An inverting source follower circuit, comprising: a first metal oxide semiconductor transistor, wherein a gate of the first metal oxide semiconductor transistor is to receive an input signal of the inverting source follower circuit, and a source of the first metal oxide semiconductor transistor is to output an output signal of the inverting source follower circuit; a second metal oxide semiconductor transistor, wherein a drain of the second metal oxide semiconductor transistor is coupled to a drain of the first metal oxide semiconductor transistor, and a source of the second metal oxide semiconductor transistor is coupled to a reference voltage; a low pass filter, wherein an input node of the low pass filter is coupled to the drain of the second metal oxide semiconductor transistor, and an output node of the low pass filter is coupled to a gate of the second metal oxide semiconductor transistor.

17. The inverting source follower circuit of claim 16, wherein the low pass filter comprises: a resistor coupled between the drain and the gate of the second metal oxide semiconductor transistor; and a capacitor coupled between the gate and the reference voltage of the second metal oxide semiconductor transistor; and the inverting source follower circuit further comprises: a reference current generator circuit coupled to the gate of the second metal oxide semiconductor transistor and to generate a reference current flowing through the resistor.

18. An inverting source follower circuit, comprising: a first metal oxide semiconductor transistor, wherein a gate of the first metal oxide semiconductor transistor is to receive an input signal of the inverting source follower circuit, and a source of the first metal oxide semiconductor transistor is to output an output signal of the inverting source follower circuit; a second metal oxide semiconductor transistor, wherein a drain of the second metal oxide semiconductor transistor is coupled to a drain of the first metal oxide semiconductor transistor, and a source of the second metal oxide semiconductor transistor is coupled to a reference voltage; a third metal oxide semiconductor transistor, wherein a gate of the third metal oxide semiconductor transistor is to receive another input signal of the inverting source follower circuit, a source of the third metal oxide semiconductor transistor is to output another output signal of the inverting source follower circuit, the input signal and the another input signal are a differential input, and the output signal and the another output signal are a differential output; a fourth metal oxide semiconductor transistor, wherein a gate of the fourth metal oxide semiconductor transistor is coupled to a gate of the second metal oxide semiconductor transistor, a drain of the fourth metal oxide semiconductor transistor is coupled to a drain of the third metal oxide semiconductor transistor, and a source of the fourth metal oxide semiconductor transistor is coupled to the reference voltage; a resistor coupled between the drain and the gate of the second metal oxide semiconductor transistor; and a capacitor coupled between the gate and the reference voltage of the second metal oxide semiconductor transistor; and the inverting source follower circuit further comprises: a reference current generator circuit coupled to the gate of the second metal oxide semiconductor transistor and to generate a reference current flowing through the resistor. Another resistor coupled between the drain and the gate of the fourth metal oxide semiconductor transistor.

19. The inverting source follower circuit of claim 18, further comprising: a reference current generator circuit coupled to the gate of the second metal oxide semiconductor transistor and the gate of the fourth metal oxide semiconductor transistor and configured to generate a reference current through the resistor and another reference current through the another resistor.

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