Atomic operation processing method and related product

Abstract

The invention provides an atomic operation processing method and device, electronic equipment, a computer readable storage medium and a computer program product, and relates to the technical field of chips. The method is applied to an SIMD architecture, and comprises the following steps: determining a plurality of target threads which access the same memory address and execute the same type of atomic operation in a plurality of threads corresponding to the SIMD architecture; wherein the atomic operation accords with a combination law and an exchange law; the operands of the multiple target threads are reduced and merged according to atomic operation, and target operands corresponding to the multiple target threads are obtained; and according to the target operand, executing one atomic operation on the memory addresses corresponding to the plurality of target threads to obtain a final atomic operation result of all threads corresponding to the SIMD architecture. The method can improve the memory access efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and specifically to a method, apparatus, electronic device, computer-readable storage medium, and computer program product for processing atomic operations. Background Technology

[0002] When performing atomic operations in SIMD (Single Instruction Multiple Data), if atomic operations at the same address occur in multiple parallel threads, these atomic operations need to be sent one by one to the memory subsystem for processing, resulting in reduced memory access efficiency. Summary of the Invention

[0003] This disclosure provides a method, apparatus, electronic device, and computer-readable storage medium for processing atomic operations.

[0004] In a first aspect, embodiments of this disclosure propose a method for processing atomic operations, applied to a SIMD architecture. The method includes: identifying multiple target threads among multiple threads corresponding to the SIMD architecture that access the same memory address and perform the same type of atomic operation; wherein the atomic operation conforms to the associative and commutative laws; reducing and merging the operands of the multiple target threads according to the atomic operation to obtain target operands corresponding to the multiple target threads; and performing an atomic operation once on the memory address corresponding to the multiple target threads according to the target operands to obtain the final atomic operation result of all threads corresponding to the SIMD architecture.

[0005] In some embodiments, determining multiple target threads that access the same memory address and perform the same type of atomic operation among multiple threads corresponding to the SIMD architecture includes: determining an address mask for each memory address based on the memory address accessed by the multiple threads performing atomic operations according to the SIMD architecture; wherein, one address mask corresponds to one memory address, and the mask bit width of each address mask is the same as the architecture bit width of the SIMD architecture, used to identify whether each thread accesses the memory address corresponding to the address mask; and determining multiple target threads that access the same memory address and perform the same type of atomic operation based on multiple address masks.

[0006] In some embodiments, the method further includes: recording the operands and operation type corresponding to each target thread in response to the need for a return value for the atomic operation; and obtaining the return value of the atomic operation corresponding to each target thread based on the operands and operation type corresponding to each target thread.

[0007] In some embodiments, an atomic operation is performed on the memory addresses corresponding to multiple target threads based on the target operands to obtain the final atomic operation result for all threads corresponding to the SIMD architecture. This includes: merging multiple target threads into a single merged thread based on the target operands corresponding to the multiple target threads; identifying other threads besides the multiple target threads among the multiple threads corresponding to the SIMD architecture; performing memory access merging on the merged thread and other threads to obtain a memory access merging result; and performing an atomic operation on each memory address in the SIMD architecture based on the memory access merging result to obtain the final atomic operation result for all threads corresponding to the SIMD architecture.

[0008] In some embodiments, atomic operations include at least one of atomic addition, atomic maximum, atomic minimum, atomic bitwise AND, atomic bitwise OR, and atomic bitwise XOR.

[0009] Secondly, embodiments of this disclosure also provide an atomic operation processing apparatus applied to a SIMD architecture. The apparatus includes: an address determination unit, used to determine multiple target threads among multiple threads corresponding to the SIMD architecture that access the same memory address and perform the same type of atomic operation; wherein the atomic operation conforms to the associative and commutative laws; a logic operation unit, used to reduce and merge the operands of the multiple target threads according to the atomic operation to obtain target operands corresponding to the multiple target threads; and a memory access merging unit, used to perform an atomic operation on the memory address corresponding to the multiple target threads according to the target operands to obtain the final atomic operation result of all threads corresponding to the SIMD architecture.

[0010] In some embodiments, the address determination unit includes: a first determination subunit, configured to determine the address mask of each memory address based on the memory addresses accessed by multiple threads performing atomic operations corresponding to the SIMD architecture; wherein, one address mask corresponds to one memory address, and the mask bit width of each address mask is the same as the architecture bit width of the SIMD architecture, used to identify whether each thread accesses the memory address corresponding to the address mask; and a second determination subunit, configured to determine multiple target threads that access the same memory address and perform the same type of atomic operation based on multiple address masks.

[0011] In some embodiments, the processing apparatus further includes: a recording unit, configured to record the operands and operation type corresponding to each target thread in response to the need for a return value in an atomic operation; and a logic operation unit, configured to obtain the return value of the atomic operation corresponding to each target thread based on the operands and operation type corresponding to the target thread.

[0012] In some embodiments, the memory access merging unit includes: a thread merging subunit, configured to merge multiple target threads into a merged thread based on the target operands corresponding to multiple target threads; a third determining subunit, configured to determine other threads besides the multiple target threads among the multiple threads corresponding to the SIMD architecture; a memory access merging subunit, configured to perform memory access merging on the merged thread and other threads to obtain a memory access merging result; and an execution subunit, configured to perform an atomic operation on each memory address in the SIMD architecture based on the memory access merging result to obtain the final atomic operation result for all threads corresponding to the SIMD architecture.

[0013] Thirdly, embodiments of this disclosure provide an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement a processing method of atomic operations as described in any implementation of the first aspect.

[0014] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that enable a computer to perform a processing method of atomic operations as described in any implementation of the first aspect.

[0015] Fifthly, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the steps of a processing method for atomic operations as described in any implementation of the first aspect.

[0016] The atomic operation processing method provided in this disclosure reduces and merges the operands of multiple threads that access the same address and perform the same atomic operation to obtain a target operand. Therefore, the atomic operation results of all threads in the thread group can be obtained by performing only one atomic operation based on the target operand, which reduces the number of memory accesses and improves memory access efficiency. Attached Figure Description

[0017] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating a method for processing atomic operations provided in this embodiment of the disclosure; Figure 2 This is a flowchart illustrating a method for processing atomic operations based on an application scenario, as provided in this disclosure embodiment. Figure 3 A schematic diagram illustrating an atomic operation that does not require a return value, provided as an embodiment of this disclosure; Figure 4 A schematic diagram illustrating an atomic operation requiring a return value, provided as an embodiment of this disclosure; Figure 5 A structural block diagram of a processing apparatus for atomic operations provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0018] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0019] SIMD (Single Instruction, Multiple Data) architecture is a parallel computing architecture whose core idea is that a single instruction can process multiple data elements simultaneously.

[0020] In terms of hardware, the SIMD architecture enables a single instruction to process multiple data elements simultaneously by using ultra-wide registers (such as a 128-bit Single Instruction Multiple Data Register and a 512-bit Advanced Vector Extension Register) and corresponding parallel execution units. These ultra-wide registers can be divided into multiple smaller "channels," each corresponding to a memory address that can store one data element. An instruction (such as an addition) can be executed concurrently on all channels.

[0021] In many scenarios, each thread may want to have exclusive access to this data and perform a series of operations before other threads access the same data, which can be achieved through atomic operations.

[0022] In parallel programming, atomic operations are a class of synchronization primitives that modify only shared memory locations. These operations focus on ensuring the atomicity of the modification (i.e., the operation either executes completely or not at all, without being interrupted by other threads), and are suitable for scenarios that only need to update the state without knowing the previous value.

[0023] If a group of threads happens to access elements at different memory addresses in the SIMD architecture, that is, the destination addresses of atomic operations from different threads are different, then the atomic operations of different threads can be executed in parallel.

[0024] For example, suppose a group of threads includes four threads, t0, t1, t2, and t3, which access memory addresses a0, a1, a2, and a3 of four elements in a SIMD architecture and perform atomic addition operations respectively. Since the four threads perform atomic addition operations on elements at different memory addresses, the atomic addition operations of the four threads can be executed in parallel. Specifically, the data in thread t0 is added to the data at address a0, and then written back to address 0; the data in thread t1 is added to the data at address a1, and then written back to address 1; the data in thread t2 is added to the data at address a2, and then written back to address 2; the data in thread t3 is added to the data at address a3, and then written back to address 3.

[0025] However, if a group of threads perform atomic operations on the same memory address in a SIMD architecture, then in order to execute the atomic operations of each thread correctly, the atomic operations of each thread must be performed sequentially. That is, the atomic operation of the second thread must be completed before the atomic operation of the first thread can begin, and the atomic operation of the third thread must be completed before the atomic operation of the second thread can begin, and so on.

[0026] Taking a group of four threads (t0, t1, t2, and t3) as an example, all four threads access the same memory address a0 in the SIMD architecture to perform atomic addition operations. Since the four threads perform atomic addition operations on elements at the same memory address, these operations must be executed sequentially. Specifically, in the first processing stage, the data in thread t0 is added to the data at address a0, and then written back to address 0; in the second processing stage, the data in thread t1 is added to the data at address a0, and then written back to address 0; in the third processing stage, the data in thread t2 is added to the data at address a0, and then written back to address 0; in the fourth processing stage, the data in thread t3 is added to the data at address a0, and then written back to address 0.

[0027] Therefore, when multiple threads perform atomic operations on the same memory address in the SIMD architecture, the atomic operations of each thread need to be performed sequentially in order to ensure that each thread's atomic operations are executed correctly. This results in low system throughput and slow program execution speed.

[0028] To address the aforementioned problems, this disclosure provides a method for processing atomic operations, which can improve memory access efficiency.

[0029] Figure 1 This is a flowchart of a method for processing atomic operations provided in this disclosure, which is applied to a SIMD architecture.

[0030] like Figure 1 As shown, the method specifically includes the following steps: Step 101: Identify multiple target threads that access the same memory address and perform the same type of atomic operations among the multiple threads corresponding to the SIMD architecture; wherein the atomic operations conform to the associative and commutative laws.

[0031] Specifically, the SIMD architecture includes a register that can be divided into multiple smaller memory addresses, each capable of storing one data element. Therefore, for the SIMD architecture, multiple atomic operations can be issued simultaneously to execute multiple corresponding threads concurrently across all memory addresses. The number of threads is the same as the number of memory addresses corresponding to SIMD.

[0032] Atomic operations in multiple threads can be operations on different memory addresses or operations on the same memory address. Because the operands of the same atomic operation on different memory addresses are different, the corresponding threads can be executed in parallel. However, for the same atomic operation on the same memory address, the corresponding atomic operations need to be issued sequentially and the corresponding threads executed serially to ensure the accuracy of the atomic operation.

[0033] In this context, atomic operations of the same type refer to atomic operations that have the same operation type. Atomic operations conforming to the associative and commutative laws ensure that the final atomic operation result remains unchanged after arbitrary rearrangement, merging, or segmentation reduction of multiple atomic operations corresponding to multiple threads, thus guaranteeing the accuracy of atomic operations. Before performing atomic operations, multiple target threads corresponding to SIMD that have the same memory address and the same atomic operation type are first identified.

[0034] In some embodiments, before performing atomic operations, the multiple threads corresponding to SIMD can first be divided into multiple thread groups according to memory addresses and atomic operation types. That is, all threads that access the same memory address and perform the same atomic operation form a thread group. Specifically, the multiple threads corresponding to the SIMD architecture can be divided into one or more thread groups based on the memory addresses accessed by each thread and the atomic operations performed.

[0035] Step 102: Reduce and merge the operands of multiple target threads according to atomic operations to obtain the target operands corresponding to the multiple target threads.

[0036] Specifically, each of the multiple target threads accesses the same memory address and performs the same atomic operation. Since this atomic operation is associative and commutative, the operands of the multiple target threads can be reduced and merged to obtain a single target operand. In other words, reduction and merging can combine multiple operands corresponding to multiple target threads into a single target operand.

[0037] For example, consider a group of four threads, t0, t1, t2, and t3, all of which access the same memory address a0 in the SIMD architecture to perform an atomic addition operation. The operands for the four threads t0, t1, t2, and t3 are 2, 2, and 3, respectively. Therefore, by reducing and merging according to the operation type of this atomic operation, the target operands for the four target threads are: 2 + 2 + 3 = 7.

[0038] Step 103: Based on the target operands, perform an atomic operation on the memory addresses corresponding to multiple target threads to obtain the final atomic operation results for all threads corresponding to the SIMD architecture.

[0039] Specifically, for multiple target threads, the target operand is used as the total operand for the multiple target threads, and the address element is obtained by accessing the memory address corresponding to the target thread. Then, an atomic operation is performed on the target operand and the address element to obtain the atomic operation result of the thread group.

[0040] Taking the four threads in step 102 above as an example, the target operand for each of the four target threads is 7. The target operand 7 and the atomic addition operation are directly sent to the corresponding memory address a0 to execute the atomic operation. By performing the atomic addition operation once, the four target threads can obtain the atomic operation result: 7 + a0. Compared to the previous method requiring four processing stages and four atomic operations, this reduces the number of memory accesses and improves memory access efficiency.

[0041] The atomic operation processing method provided in this disclosure reduces and merges the operands of multiple threads that access the same address and perform the same atomic operation to obtain a target operand. Therefore, the atomic operation results of all threads in the thread group can be obtained by performing only one atomic operation based on the target operand, which reduces the number of memory accesses and improves memory access efficiency.

[0042] In response to the above Figure 1 Step 101 in the process can determine multiple target threads based on the mask. A specific implementation method is given below.

[0043] In some embodiments, determining multiple target threads that access the same memory address and perform the same type of atomic operation among multiple threads corresponding to the SIMD architecture includes: determining an address mask for each memory address based on the memory address accessed by the multiple threads performing atomic operations according to the SIMD architecture; wherein, one address mask corresponds to one memory address, and the mask bit width of each address mask is the same as the architecture bit width of the SIMD architecture, used to identify whether each thread accesses the memory address corresponding to the address mask; and determining multiple target threads that access the same memory address and perform the same type of atomic operation based on multiple address masks.

[0044] Specifically, the SIMD architecture corresponds to M memory addresses, so a group of threads includes M threads. Each memory address corresponds to an address mask, generating a total of M address masks. Each address mask also includes M bits, with each bit identifying one of the M threads, where M is a positive integer greater than 1.

[0045] For example, if M is 4, it corresponds to 4 threads t0, t1, t2, and t3, and 4 memory addresses a0, a1, a2, and a3. Based on the memory addresses accessed by the M threads performing atomic operations, the 4 memory addresses can be represented by address masks A0, A1, A2, and A3, respectively. Each address mask is initialized with mask = 0bxxxx, where 0b is the mask format, and each bit of xxxx represents thread t0, t1, t2, and t3, respectively. 0 indicates that the corresponding thread does not access that memory address, and 1 indicates that the corresponding thread accesses that memory address. If the addresses accessed by the four threads are a0, a0, a2, and a2 respectively, then A0 = 0b1100, indicating that threads t0 and t1 access memory address a0; A1 = 0b0000, indicating that no thread accesses memory address a1; A2 = 0b0011, indicating that threads t2 and t3 access memory address a2; and A3 = 0b0000, indicating that no thread accesses memory address a3. Therefore, based on the address masks, the four threads can be divided into two thread groups: the first thread group consists of t0 threads (t1) accessing memory address a0; the second thread group consists of t2 threads (t3) accessing memory address a2.

[0046] Of course, in addition to determining the target thread based on the mask as described above, other methods can be used, such as sequentially judging the memory addresses accessed by each thread, etc. This disclosure does not limit this method.

[0047] This embodiment generates an address mask for each memory address by performing atomic operations on the memory addresses accessed by multiple threads. Based on the address mask, all target threads that access the same memory address and perform the same atomic operation can be determined from multiple threads, which can improve the accuracy and efficiency of target thread group determination and further improve the memory access efficiency of atomic operations.

[0048] Depending on the specific application scenario, some atomic operations do not require a return value, while others do. For atomic operations that do not require a return value, the final atomic operation result can be obtained directly based on the reduction and merging described above. However, for atomic operations that require a return value, it is necessary to deduce the return value of each atomic operation by working backward from the results of the atomic operations performed once by each thread group.

[0049] In some embodiments, the method for processing atomic operations includes not only steps 101-103 described above, but also: in response to the need for a return value for the atomic operation, recording the operands and operation type corresponding to each target thread; and obtaining the return value of the atomic operation corresponding to each target thread based on the operands and operation type corresponding to the target thread.

[0050] Specifically, if the atomic operation requires a return value, the operands and operation type of the atomic operation corresponding to the same memory address need to be recorded so that appropriate processing can be performed upon return.

[0051] For example, a thread group consists of four threads accessing the same memory address, with operands of 1, 2, 2, and 3 respectively; the atomic operation type is atomic addition. After the thread group executes one atomic operation, the final atomic result is 10. When calculating the return value, firstly, the original value of the memory address, 2, is used as the first return value; furthermore, based on the operands of each thread, the other three return values ​​are obtained sequentially: 2+1=3, 3+2=5, and 5+2=7.

[0052] Therefore, the return values ​​of the atomic operations of the four threads are 2, 3, 5, and 7, respectively.

[0053] This embodiment of the disclosure records the operands and operation types of each target thread, thereby not only obtaining the atomic operation results of multiple target threads based on a single atomic operation, improving memory access efficiency, but also obtaining the return value of each target thread based on the operands and operation types of each target thread.

[0054] In SIMD (Single Instruction Multiple Data) architecture, memory access merging can be performed between threads accessing different memory addresses to fully utilize memory bandwidth optimization techniques and improve memory access efficiency.

[0055] In some embodiments, an atomic operation is performed on the memory addresses corresponding to multiple target threads based on the target operands to obtain the final atomic operation result for all threads corresponding to the SIMD architecture. This includes: merging multiple target threads into a single merged thread based on the target operands corresponding to the multiple target threads; identifying other threads besides the multiple target threads among the multiple threads corresponding to the SIMD architecture; performing memory access merging on the merged thread and other threads to obtain a memory access merging result; and performing an atomic operation on each memory address in the SIMD architecture based on the memory access merging result to obtain the final atomic operation result for all threads corresponding to the SIMD architecture.

[0056] Memory access coalescing is an optimization technique that combines scattered memory accesses from multiple parallel threads (or vector elements) into fewer memory transactions to fully utilize memory bandwidth. This is a key strategy for improving the performance of SIMD programs and directly impacts the efficiency of the memory subsystem. In other words, memory access coalescing automatically merges discrete memory access requests from multiple threads to different (adjacent) memory addresses into a single, wider cache / memory transaction, thereby saving bandwidth and increasing throughput.

[0057] In SIMD, if multiple parallel threads perform atomic operations on the same memory address, they cannot be directly merged. However, by reducing and merging multiple target threads accessing the same memory address, these multiple target threads can be converted into a single merged thread. This merged thread, along with the other threads in the SIMD architecture (excluding the multi-target thread), represents discrete memory access requests to different memory addresses. Therefore, the merged thread can save bandwidth and improve throughput through memory access merging with other threads. Furthermore, based on the memory access merging result, an atomic operation can be performed on each memory address in the SIMD architecture, yielding the final atomic operation result for all threads in the SIMD architecture.

[0058] In some embodiments, atomic operations include at least one of atomic addition, atomic maximum, atomic minimum, atomic bitwise AND, atomic bitwise OR, and atomic bitwise XOR.

[0059] Specifically, atomic add, atomic max, atomic min, atomic bitwise AND, atomic bitwise OR, and atomic bitwise XOR all satisfy the commutative and associative laws. When multiple threads perform the corresponding atomic operations, the final atomic operation result remains unchanged after reducing and merging the multiple threads, and will not affect the final atomic operation result.

[0060] Specifically, when the atomic operation for multiple target threads is `atomic add`, the target operand for each target thread is obtained by adding the operands of the multiple target threads together. When the atomic operation for multiple target threads is `atomic max`, the target operand for each target thread is obtained by comparing the maximum value of the operands of each target thread. When the atomic operation for multiple target threads is `atomic min`, the target operand for each target thread is obtained by comparing the minimum value of the operands of the multiple target thread groups. When the atomic operation for multiple target threads is `atomic bitwise AND`, the target operand for each target thread is obtained by sequentially performing a bitwise AND operation on the operands of the multiple target threads. When the atomic operation for each thread within multiple target threads is `atomic bitwise OR`, the target operand for each target thread is obtained by sequentially performing a bitwise OR operation on the operands of the multiple target threads. When the atomic operation for multiple target threads is `atomic bitwise XOR`, the target operand for each target thread is obtained by sequentially performing a bitwise XOR operation on the operands of the multiple target threads.

[0061] Figure 2 This is a flowchart illustrating an atomic operation processing method provided by an embodiment of the present disclosure based on an application scenario.

[0062] like Figure 2 As shown, the method specifically includes the following steps: Step 201: Receive SIMD memory access request.

[0063] Specifically, it receives operation requests from multiple threads based on the architecture bit width of the SIMD architecture.

[0064] Step 202: Determine whether the operation request is an atomic operation request.

[0065] If the request is not an atomic request, proceed to step 208: process it according to the original memory access merging method.

[0066] If the request is an atomic request, proceed to step 203.

[0067] Step 203: Determine whether the type of the atomic operation corresponding to the atomic request is a reducible type.

[0068] If the type of the atomic operation corresponding to the atomic request is not a reducible type, then continue to step 208: process according to the original memory access merging method.

[0069] If the type of the atomic operation corresponding to the atomic request is a reducible type, then proceed to step 204.

[0070] Step 204: Determine whether the atomic operation corresponding to the atomic request needs to return a value.

[0071] If the atomic operation corresponding to the atomic request requires a return value, then proceed to steps 205-207.

[0072] Step 205: Record the operands of the thread at the same address so that appropriate processing can be performed upon return.

[0073] Step 206: Reduce and merge addresses with the same address.

[0074] Step 207: The merged requests and all remaining requests are processed according to the original memory access merging method.

[0075] Returning to step 204, if the atomic operation corresponding to the atomic request does not require a return value, steps 206-207 can be executed directly without recording the number of operations of threads at the same address.

[0076] The specific details of each step in this embodiment are the same as in any of the above embodiments, and will not be repeated here.

[0077] Figure 3 This is a schematic diagram of an atomic operation that does not require a return value, provided as an embodiment of this disclosure.

[0078] like Figure 3 As shown, the SIMD architecture corresponds to N threads, namely Thread0, Thread1...ThreadN.

[0079] First, we perform a common memory address determination logic on the N threads. Specifically, based on the memory addresses accessed by each thread, we determine which of the N threads accessed the same memory address, thus generating a common memory address mask. Each mask corresponds to a memory address, and each mask has a bit width of N, used to identify whether each thread accesses that memory address.

[0080] Then, based on the generated address mask, multiple threads accessing the same memory address are processed by reduction logic, ultimately merging N threads into M threads. The M merged threads all access different memory addresses.

[0081] Finally, since the resulting M threads all access different memory addresses, we can further process the memory access merging logic on the M threads to ultimately obtain the atomic operation results of N threads.

[0082] It should be noted that the specific processing details of the same address judgment logic, same address mask generation and memory access merging logic involved in the embodiments of this disclosure can be found in the description of any of the above embodiments, and will not be repeated here.

[0083] The embodiments of this disclosure reduce the number of memory accesses and improve memory access efficiency by performing reduction logic processing on threads accessing the same memory address, thereby improving the efficiency of atomic operations.

[0084] Figure 4 This is a schematic diagram of an atomic operation that requires a return value, provided as an embodiment of this disclosure.

[0085] like Figure 4 As shown, the SIMD architecture corresponds to N threads, namely Thread0, Thread1...ThreadN.

[0086] in, Figure 4 The corresponding embodiment performs atomic operations logical AND Figure 3 The corresponding implementation is similar, first performing address-based matching logic on N threads. Then, based on the generated address-based mask, multiple threads accessing the same memory address are processed using reduction logic, ultimately merging the N threads into M threads. Finally, since the resulting M threads all access different memory addresses, further memory access merging logic can be applied to the M threads to obtain the memory access requests.

[0087] Figure 4 Corresponding embodiments and Figure 3 The only difference between the corresponding embodiments is that, Figure 4 The atomic operations in the corresponding embodiments require a return value. Therefore, in Figure 4 When performing reduction logic processing on multiple threads at the same address, it is necessary to record the atomic operation type and operands of each thread in each mask at the same address as a return data lookup table. Based on the operands and atomic operation types in the return data lookup table, the return value of each thread can be obtained.

[0088] like Figure 4 As shown, taking three groups of threads accessing the same memory address among the N threads as an example, when performing reduction logic processing on multiple threads at the same address, it is necessary to assign corresponding request IDs to the three groups of threads, and at the same time record the mask corresponding to the same address for each of the three groups of threads, as well as the atomic operation type of each group of threads and the number of operations of each thread in each group of threads, namely operand 0, operand 1... operand M, to obtain the return data lookup table.

[0089] Furthermore, for each thread in each thread group, the operands of each thread are: operand 0, operand 1, ..., operand M. Based on the corresponding operation type, the return values ​​of each thread in the thread group are obtained through the logical operation unit: return value 0, return value 1, ..., return value M.

[0090] This embodiment of the disclosure reduces the number of memory accesses and improves memory access efficiency by performing reduction logic processing on threads accessing the same memory address, thereby improving the efficiency of atomic operations. Simultaneously, by recording the operands and atomic operation types of each thread accessing the same memory address, the return values ​​of each thread can be accurately obtained while reducing the number of memory accesses and improving memory access efficiency.

[0091] The atomic operation processing method disclosed herein improves memory access efficiency by adding a reduction operation of atomic operations at the same address in the SIMD architecture. In addition, for atomic operations that require a return value, by recording the operands of each thread and performing the opposite logical operation upon return, the return value of the atomic operation of each thread can be accurately obtained while improving memory access efficiency.

[0092] Based on the same inventive concept as the above-described atomic operation processing method, this disclosure also provides an atomic operation processing apparatus.

[0093] Figure 5 This is a structural block diagram of a processing apparatus for atomic operations provided in an embodiment of the present disclosure.

[0094] Further reference Figure 5 As an implementation of the methods shown in the above figures, this device embodiment is similar to... Figure 1 Corresponding to the method embodiment shown, the device can be specifically applied to a SIMD architecture.

[0095] like Figure 5 As shown, the atomic operation processing unit 500 in this embodiment may include: an address judgment unit 501, a logic operation unit 502, and a memory access merging unit 503.

[0096] The address-based judgment unit 501 is used to identify multiple target threads that access the same memory address and perform the same type of atomic operation among multiple threads corresponding to the SIMD architecture; wherein the atomic operation conforms to the associative and commutative laws; the logic operation unit 502 is used to reduce and merge the operands of multiple target threads according to the atomic operation to obtain the target operands corresponding to multiple target threads; the memory access merging unit 503 is used to perform an atomic operation on the memory address corresponding to multiple target threads according to the target operands to obtain the final atomic operation result of all threads corresponding to the SIMD architecture.

[0097] In this embodiment, the specific processing of the address determination unit 501, the logic operation unit 502, and the memory access merging unit 503 in the atomic operation processing device 500, and the resulting technical effects, can be found in the following references: Figure 1 The relevant descriptions of steps 101-103 in the corresponding embodiments will not be repeated here.

[0098] The specific implementation details and technical effects of the atomic operation processing apparatus provided in this disclosure are the same as the implementation details and technical effects of the atomic operation processing method embodiments described above, and will not be repeated here.

[0099] In some embodiments, the address determination unit 501 includes a first determining subunit and a second determining unit. The first determining unit is used to determine the address mask of each memory address based on the memory addresses accessed by multiple threads performing atomic operations corresponding to the SIMD architecture; wherein one address mask corresponds to one memory address, and the mask width of each address mask is the same as the architecture width of the SIMD architecture, used to identify whether each thread accesses the memory address corresponding to the address mask; the second determining subunit is used to determine multiple target threads that access the same memory address and perform the same type of atomic operation based on multiple address masks.

[0100] In some embodiments, the processing apparatus 500 includes not only a same address judgment 501, a logic operation unit 502, and a memory access merging unit 503, but also a recording unit. The recording unit is used to record the operands and operation types corresponding to each target thread in response to the need for a return value in atomic operations; the logic operation unit 502 is also used to obtain the return values ​​of the atomic operations corresponding to each target thread based on the operands and operation types corresponding to the target threads.

[0101] In some embodiments, the memory merging unit 503 includes a thread merging subunit, a third determining subunit, a memory merging subunit, and an execution subunit. The thread merging subunit is used to merge the multiple target threads into a single merged thread based on the target operands corresponding to the multiple target threads. The third determining subunit is used to determine the other threads besides the multiple target threads among the multiple threads corresponding to the SIMD architecture. The memory merging subunit is used to perform memory merging on the merged thread and other threads to obtain a memory merging result. The execution subunit is used to perform an atomic operation on each memory address in the SIMD architecture based on the memory merging result, obtaining the final atomic operation result for all threads corresponding to the SIMD architecture.

[0102] In some embodiments, atomic operations include at least one of atomic addition, atomic maximum, atomic minimum, atomic bitwise AND, atomic bitwise OR, and atomic bitwise XOR.

[0103] This embodiment exists as a device embodiment corresponding to the method embodiment described above. In the atomic operation processing device 500 provided in this embodiment, the logic operation unit 502 reduces and merges the operands of multiple threads accessing the same address and performing the same atomic operation to obtain a target operand. Therefore, the memory access merging unit 503 can perform the atomic operation only once based on this target operand to obtain the atomic operation results of multiple target threads, reducing the number of memory accesses and improving memory access efficiency. Furthermore, the logic operation unit 502 can also obtain the return value of the atomic operation corresponding to each target thread based on the operand and operation type. This allows the processing device 500 provided in this disclosure to improve memory access efficiency while accurately obtaining the return value of each atomic operation. Moreover, the logic operation unit 502, which calculates the reduction and merging logic and the return value calculation logic, can be shared, further reducing hardware overhead.

[0104] According to embodiments of this disclosure, this disclosure also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the processing method of atomic operations described in any of the above embodiments when executed.

[0105] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 6 As shown, the electronic device 600 of this embodiment includes a processor 601 and a memory 602; wherein, the memory 602 is used to store computer execution instructions; the processor 601 is used to execute the computer execution instructions stored in the memory to implement the various steps performed by the electronic device in the above embodiment. For details, please refer to the relevant descriptions in the foregoing method embodiments. For example, the electronic device 600 can be a general-purpose processor, a graphics processing device, a neural network computing device, or a graph neural network computing device.

[0106] In some embodiments, the memory 602 can be either standalone or integrated with the processor 601.

[0107] When the memory 602 is set up independently, the electronic device also includes a bus 603 for connecting the memory 602 and the processor 601.

[0108] It should be understood that the processor 601 described above can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.

[0109] The memory 602 may include high-speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk storage device, and may also be a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0110] Bus 603 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0111] This disclosure also provides a computer storage medium storing computer execution instructions, which, when executed by a processor, implement the steps of the processing method for atomic operations in any of the above method embodiments.

[0112] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of a processing method based on atomic operations according to any of the above embodiments.

[0113] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0114] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0115] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit composed of the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0116] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute partial steps of the methods in the various embodiments of this application.

[0117] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0118] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0119] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0120] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0121] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0122] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A processing method of an atomic operation, characterized by, The method is applied to a SIMD architecture, and the method comprises the following steps: determining a plurality of target threads that access a same memory address and perform the same type of atomic operation in a plurality of threads corresponding to the SIMD architecture; wherein the atomic operation conforms to the associative law and the commutative law; reducing and merging operation numbers of the plurality of target threads according to the atomic operation to obtain target operation numbers corresponding to the plurality of target threads; performing an atomic operation on the memory address corresponding to the plurality of target threads once according to the target operation numbers to obtain a final atomic operation result of all threads corresponding to the SIMD architecture.

2. The method of claim 1, wherein, The method further comprises the following steps: in response to the atomic operation requiring a return value, recording the operation number and the operation type corresponding to each target thread; obtaining the return value of the atomic operation corresponding to each target thread according to the operation number and the operation type corresponding to the target thread.

3. The method of claim 1, wherein, The method further comprises the following steps: combining the plurality of target threads into one thread after combination according to the target operation numbers corresponding to the plurality of target threads; determining other threads in the plurality of threads corresponding to the SIMD architecture except the plurality of target threads; 4. The method of claim 1, wherein, performing memory access combination on the thread after combination and the other threads to obtain a memory access combination result; performing an atomic operation on each memory address in the SIMD architecture once according to the memory access combination result to obtain the final atomic operation result of all threads corresponding to the SIMD architecture. The atomic operation comprises at least one of an atomic addition operation, an atomic maximum value operation, an atomic minimum value operation, an atomic bitwise AND operation, an atomic bitwise OR operation, and an atomic bitwise XOR operation. The apparatus is applied to a SIMD architecture, and the apparatus comprises: an address determination unit configured to determine a plurality of target threads that access a same memory address and perform the same type of atomic operation in a plurality of threads corresponding to the SIMD architecture; wherein the atomic operation conforms to the associative law and the commutative law; 5. The method of claim 1, wherein, a logical operation unit configured to reduce and merge operation numbers of the plurality of target threads according to the atomic operation to obtain target operation numbers corresponding to the plurality of target threads; and 6. A processing device for atomic operations, characterized by a memory access unit configured to perform an atomic operation on the memory address corresponding to the plurality of target threads once according to the target operation numbers to obtain a final atomic operation result of all threads corresponding to the SIMD architecture. ​ ​ The memory access merging unit is configured to perform an atomic operation on the memory addresses corresponding to the plurality of target threads according to the target operands to obtain a final atomic operation result of all threads corresponding to the SIMD architecture.

7. The processing device of claim 6, wherein, The address judging unit comprises: The first determining sub-unit is configured to determine an address mask of each memory address according to the memory addresses accessed by the atomic operation of the plurality of threads corresponding to the SIMD architecture; wherein one address mask corresponds to one memory address, and the mask bit width of each address mask is the same as the architecture bit width of the SIMD architecture, and is used to identify whether each thread accesses the memory address corresponding to the address mask; The second determining sub-unit is configured to determine the plurality of target threads that access the same memory address and perform the same type of atomic operation according to the plurality of address masks.

8. The processing device of claim 6, wherein, The processing device further comprises: The recording unit is configured to record the operand and the operation type corresponding to each target thread in response to the atomic operation requiring a return value; The logic operation unit is further configured to obtain the return value of the atomic operation corresponding to each target thread according to the operand and the operation type corresponding to the target thread.

9. The processing device of claim 6, wherein, The memory access merging unit comprises: The thread merging sub-unit is configured to merge the plurality of target threads into one merged thread according to the target operands corresponding to the plurality of target threads; The third determining sub-unit is configured to determine other threads in the plurality of threads corresponding to the SIMD architecture except the plurality of target threads; The memory access merging sub-unit is configured to perform memory access merging on the merged thread and the other threads to obtain a memory access merging result; The execution sub-unit is configured to perform an atomic operation on each memory address in the SIMD architecture according to the memory access merging result to obtain a final atomic operation result of all threads corresponding to the SIMD architecture.

10. An electronic device, comprising: comprise: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the atomic operation processing method in any one of claims 1-5.

11. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to enable the computer to perform the atomic operation processing method in any one of claims 1-5.

12. A computer program product, characterised in that, The computer program is executed by the processor to implement the steps of the atomic operation processing method in any one of claims 1-5.

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