Memory controller and microcontroller chip

Abstract

The present invention provides a memory controller and a microcontroller chip, on the basis of the present memory controller architecture, a second memory controller is newly added and coupled to a second non-volatile memory, and the content of a first non-volatile memory of the memory controller is backed up in the second non-volatile memory. In addition, the first storage controller is further provided with a self-checking module, corresponding content in the first nonvolatile memory can be automatically checked at a proper stage, ECC correction is carried out according to error conditions, and use of a user is facilitated. Furthermore, the first nonvolatile memory can be repaired by reading the backup content in the second nonvolatile memory by utilizing the second memory controller on the basis of fully utilizing the high reading speed of the first nonvolatile memory through the added memory access, so that the first nonvolatile memory can be repaired. Therefore, the content read by the CPU and the like is still correct, and the execution of a system program is not interrupted.

Description

Technical Field

[0001] This invention relates to the field of storage control technology, and in particular to a memory controller and a microcontroller chip. Background Technology

[0002] With the technological evolution of microcontroller unit (MCU) chips, the process platforms used in MCU design and manufacturing are becoming increasingly advanced. The evolution of embedded non-volatile memory (eflash), a commonly used core component of MCUs, towards advanced process nodes is gradually lagging behind the evolution of MCU process platforms. Furthermore, the operating mechanism and read / write speed of eflash are increasingly constraining the performance of high-specification MCUs. Therefore, new process platforms typically offer various new types of non-volatile memory (NVM) to replace and upgrade eflash in various aspects. Common new NVMs include ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM). They retain data non-volatilely through different mechanisms and generally offer better performance than eflash. However, some of these new memories are still immature, and some are susceptible to external environmental influences due to their data storage mechanisms. Therefore, the reliability of many new NVMs is lower than that of the more mature eflash or NOR flash. In other words, the data stored in the new NVM is more susceptible to external interference, and its content is more likely to change. However, the write capability of the new NVM remains normal, and the correct content can be rewritten to correct the issue.

[0003] The following example uses RRAM as a new type of NVM to illustrate the typical application structure of RRAM in MCUs, as shown below. Figure 1As shown, the RRAM resides within the NVM controller (NVMC) and is used to store user code and other data. The RRAM controller (RRAM ctrl) is responsible for reading and writing to the RRAM. The bus interface module (bus_if) receives bus data and converts it into data for reading from the RRAM. The bus here can be AXI, AHB, or other bus protocols. More advanced MCU chips typically use an AXI interface. Considering the relatively low reliability of RRAM, existing technologies usually use ECC (Error Checking and Correcting) functions (which can perform "correction 1, checking 2" or "correction 2, checking 3," etc.) to enhance reliability. If a 1-bit data error occurs at a certain address in the RRAM, the correct value can be obtained after ECC processing. However, when the error in the RRAM data exceeds the error correction capability of the ECC function, the existing NVMC architecture cannot obtain the correct data.

[0004] Therefore, a new NVMC architecture and microcontroller chip are needed that can not only detect errors in NVM in a timely manner and implement ECC function according to the error situation, but also repair the NVM data as needed when the errors in the NVM data exceed the error correction capability of the ECC function. Summary of the Invention

[0005] The purpose of this invention is to provide a memory controller and a microcontroller chip that can improve performance.

[0006] To achieve the above objectives, the present invention provides a memory controller coupled to a second non-volatile memory and comprising:

[0007] The first non-volatile memory has a higher read / write speed than the second non-volatile memory and is used as main memory to store the contents required for system operation;

[0008] The first storage controller is responsible for controlling the read and write operations of the first non-volatile memory.

[0009] The first bus interface is coupled to the first storage controller and the system bus, and is used to realize content transfer between the system bus and the first storage controller;

[0010] The second storage controller is coupled to the first storage controller and is used to cooperate with the first storage controller to back up the contents of the first non-volatile memory to the second non-volatile memory.

[0011] The first storage controller includes a self-test module. This self-test module, based on configuration information, reads and compares the corresponding content in the first non-volatile memory with the corresponding backup content in the second non-volatile memory during the power-on reset phase, system reset phase, or system operation phase. This performs a self-test on the content in the first non-volatile memory. If there is no difference between the two, the content being self-tested in the first non-volatile memory is correct; if there is a difference, the content being self-tested in the first non-volatile memory is incorrect.

[0012] The memory controller of this invention, based on the existing memory controller architecture, adds a second memory controller coupled to a second non-volatile memory, and backs up the contents of the first non-volatile memory of the memory controller within the second non-volatile memory. Furthermore, the first memory controller also has a self-test module, thereby automatically checking the corresponding contents in the first non-volatile memory at appropriate stages, promptly detecting errors in the first non-volatile memory, and implementing ECC correction based on the error situation, thus facilitating user operation. Furthermore, by adding an additional memory path, while fully utilizing the high read speed of the first non-volatile memory, when the errors in the first non-volatile memory detected by the self-test exceed the ECC error correction capability, the second memory controller can read the backup contents from the second non-volatile memory to repair the first non-volatile memory, thereby ensuring that the content read by the CPU and other components is still correct and does not interrupt the execution of the system program.

[0013] Optionally, the memory controller further includes a control register coupled to the first memory controller, and the first memory controller is further configured to read option bytes and load them into the control register after a system reset, so that the option bytes are effective;

[0014] The option byte is a specific storage area in the first non-volatile memory or the second non-volatile memory, and is used to store the configuration information.

[0015] Therefore, the memory controller of the present invention can configure appropriate processing mechanisms for different error conditions in the first non-volatile memory through the configuration information in the option byte, so as to meet the error handling needs of different users or application scenarios.

[0016] Optionally, the option bytes loaded in the control register include self-test option bytes. The configuration information stored in the self-test option bytes includes a self-test address range and at least one corresponding register value. The self-test address range is used to determine which areas of the first non-volatile memory the self-test module performs a self-test on. The size of the register value is used to determine whether the self-test module should perform a self-test on the contents of the first non-volatile memory and to determine the stage at which the self-test module performs a self-test on the first non-volatile memory.

[0017] The self-test module is used to, when the register value is configured for self-test, sequentially read the contents of the first non-volatile memory and the corresponding backup contents in the second non-volatile memory for each address within the self-test address range during the self-test phase determined by the register value, and compare them. If there is no difference between the contents of the two, it indicates that the contents stored at the address currently being self-tested in the first non-volatile memory are correct, and the self-test of the next address within the self-test address range continues until the self-test of all addresses within the self-test address range is completed.

[0018] Therefore, the memory controller of the present invention can configure the self-test option byte to configure the content range and implementation stage of the self-test for the first non-volatile memory, further facilitating the user's use.

[0019] Optionally, the memory controller further includes a second bus interface, coupled to the second memory controller and the system bus, and used to transmit the backup content read by the second memory controller from the second non-volatile memory to the system bus. This allows the second memory controller to automatically read the backup content from the second non-volatile memory when the system bus detects erroneous content or addresses in the first non-volatile memory, and then return it to the system bus via the second bus interface, without needing to transmit it through the first memory controller and the first bus interface to the system bus, thus shortening the transmission path and improving read speed.

[0020] Optionally, the first storage controller includes a first soft error correction module, configured to perform ECC verification on the corresponding content read from the first non-volatile memory when the system bus reads the first non-volatile memory, or when the self-test module performs a self-test on the content in the first non-volatile memory, and...

[0021] The first soft error correction module is also used to perform ECC correction on errors detected by ECC within its error correction capability range and provide them to the system bus when the configuration information is preset not to repair the first non-volatile memory.

[0022] Alternatively, regardless of whether the configuration information pre-sets the repair of the first non-volatile memory, the first soft error correction module is further used to first perform ECC correction on the errors detected by ECC within its error correction capability range and provide them to the system bus. Then, when the memory controller is idle, the second memory controller is used to read the corresponding backup content of the default backup area and write the backup content into the first non-volatile memory for content repair.

[0023] Therefore, the memory controller of the present invention can rely on the first soft error correction module (which can correct 1 bit and check 2 bits or correct 2 bits and check 3 bits, the former being called "correction 1 and check 2", and the latter being called "correction 2 and check 3") to perform ECC verification on the contents of the first non-volatile memory, and can configure option bytes to select whether to use the backup contents in the second non-volatile memory to repair the errors in the first non-volatile memory. Thus, the first soft error correction module can be used to perform ECC correction on errors with fewer bits (e.g., 1 bit errors), realizing the real-time ECC detection and correction function of the correctness of the contents of the first non-volatile memory, saving time costs, and since the contents after ECC correction are still correct, the system program can be executed normally without interruption.

[0024] Optionally, the first soft error correction module is further configured to generate a corresponding ECC code when writing content to the first non-volatile memory and / or when backing up the content of the first non-volatile memory to the second non-volatile memory, and the ECC code generated by the first soft error correction module and the content of the first non-volatile memory are stored together in the second non-volatile memory.

[0025] Alternatively, the second storage controller may further include a second soft error correction module, which is used to generate a corresponding ECC code when backing up the contents of the first non-volatile memory to the second non-volatile memory, and the ECC code generated by the second soft error correction module and the contents of the first non-volatile memory are stored together in the second non-volatile memory.

[0026] Specifically, when the system bus reads the corresponding content in the first non-volatile memory, the first soft error correction module uses the ECC code to perform ECC verification on the read content in real time.

[0027] Therefore, the first soft error correction module can implement ECC protection for the content written to the first non-volatile memory, and the first soft error correction module and / or the second soft error correction module can implement ECC protection for the backup content written to the second non-volatile memory, thereby improving the storage reliability of the first and second non-volatile memories.

[0028] Optionally, the second storage controller is further configured to, in the event that the system bus reads the first non-volatile memory and / or the self-test module performs a self-test on the first non-volatile memory, read the backup content in the second non-volatile memory according to the configuration information, and write it into the first non-volatile memory through the first storage controller for content repair.

[0029] Therefore, the memory controller of the present invention can configure the configuration information in the option byte to select to repair errors in the first non-volatile memory when reading the first non-volatile memory from the system bus and / or during self-test, and then read the backup content from the second non-volatile memory and write it into the first non-volatile memory for content repair, so as to continue executing the program after successful repair, thereby improving the reliability and continuity of system operation.

[0030] Optionally, the second storage controller, based on the configuration information, reads the backup content in the second non-volatile memory in units of a single address, a single row address, or a single block of the first non-volatile memory, and writes it into the first non-volatile memory to repair the first non-volatile memory.

[0031] Therefore, the memory controller of the present invention can be configured with corresponding repair units as needed.

[0032] Optionally, the configuration information also sets a threshold for the number of repeated repairs. The second storage controller is further configured to repeatedly repair errors in the first non-volatile memory using the backup content of the second non-volatile memory, and the number of repeated repairs does not exceed the threshold. This repeated repair strategy can promptly identify physically damaged addresses or blocks in the first non-volatile memory (i.e., addresses or blocks that fail to repair even after repeated repairs up to the threshold). The threshold prevents repeated repairs from entering an infinite loop. Furthermore, when the first non-volatile memory has physical damage, it can automatically skip the physically damaged addresses or blocks in the first non-volatile memory and read the backup content in the second non-volatile memory to continue operation, thus improving system security.

[0033] Optionally, the memory controller further includes a status register, the status register including:

[0034] A first register is configured to, when reading the first non-volatile memory from the system bus, record first status information of the first non-volatile memory after ECC correction, where the configuration information specifies that the first non-volatile memory should not be repaired; and, when the configuration information specifies that the first non-volatile memory should be repaired, record second status information of the repair result of the first non-volatile memory, where the second status information includes at least one of the following: the status, address, number, and number of repair failures.

[0035] And / or, the second register is used to record the third state information of the first non-volatile memory after the self-test is performed when the self-test module performs a self-test on the first non-volatile memory. The third state information includes at least one of the following: the state of the error detected by the self-test, the address, the number of repair failures, etc.

[0036] Therefore, the first register in the status register stores relevant information after ECC correction and real-time repair when the system bus reads the first non-volatile memory. The second register in the status register stores relevant information after ECC correction and real-time repair when the first non-volatile memory is self-tested in real time.

[0037] Optionally, the erroneous address recorded in the first register and / or the second register may be stored as a corrupted address in the configuration information of the option byte, as determined by a software policy. This ensures the reliability of the operation when the erroneous address recorded in the status register is read next time.

[0038] Optionally, the second storage controller is further configured to automatically skip the first non-volatile memory and read the corresponding backup content in the second non-volatile memory when the system bus reads a corrupted address set by the configuration information and / or reads an erroneous address recorded in the status register, and return it to the system bus.

[0039] Therefore, when reading the first non-volatile memory, the memory controller of the present invention can skip the corrupted address configured in the option byte of the first non-volatile memory and / or the previously recorded erroneous address in the status register, and directly access the backup content of the second non-volatile memory. This improves the speed at which the system bus obtains correct data and ensures as much as possible that the content read by the CPU (Central Processing Unit) or other bus master unit on the system bus is still correct, without interrupting the execution of the system program.

[0040] Optionally, the status register is also used to generate an interrupt based on the corresponding records inside the first register and / or the second register. This allows the CPU (Central Processing Unit) or other bus master unit on the system bus to subsequently perform corresponding processing based on the interrupt.

[0041] Optionally, the first storage controller further includes a counting module for counting at least one of the following: the number of errors in the first non-volatile memory verified by the first soft error correction module (ECC), the number of errors in the first non-volatile memory detected by the self-test module, the number of times the second storage controller repeatedly repairs the first non-volatile memory, and the number of errors in the first non-volatile memory that the second storage controller fails to repair.

[0042] Therefore, the memory controller of the present invention can use the count value of the counting module to determine whether to generate an interrupt or perform error repair, etc.

[0043] Optionally, the first non-volatile memory is an embedded memory that does not need to be erased before being written to, and the second non-volatile memory is an off-chip memory.

[0044] Optionally, the first non-volatile memory includes at least one of ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM); and / or, the second non-volatile memory includes flash memory. Thus, these types of memory are embedded in the MCU chip using advanced process platforms as the first non-volatile memory. Furthermore, leveraging the large capacity, high reliability, and ease of integration with the MCU on a PCB or within a single MCU die package using stacking technology, a corresponding MCU architecture can be implemented.

[0045] Based on the same inventive concept, the present invention also provides a microcontroller chip, which includes a central processing unit and a memory controller as described in the present invention. The central processing unit is coupled to the memory controller via a system bus and reads and writes to the first non-volatile memory in the memory controller. The microcontroller chip also has a second non-volatile memory built in or externally connected to it. The second non-volatile memory is coupled to a second memory controller in the memory controller.

[0046] The microcontroller chip of the present invention, by employing the memory controller of the present invention, greatly reduces the probability of being interrupted during system program startup or operation due to errors in the contents of the first non-volatile memory, thereby improving system reliability and operating performance. Attached Figure Description

[0047] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0048] Figure 1 This is a schematic diagram of an existing memory controller architecture based on RRAM.

[0049] Figure 2 This is a simplified architecture diagram of a memory controller according to an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of the mapping relationship between memories in the memory controller architecture of an embodiment of the present invention.

[0051] Figures 4A to 4C yes Figure 2 The diagram shows three specific example architectures of the memory controller.

[0052] Figures 5A to 5C This is a schematic diagram illustrating three example workflows of a read operation under the architecture of a memory controller according to an embodiment of the present invention.

[0053] Figure 6A and Figure 6B These are schematic diagrams illustrating two specific example architectures of a memory controller with a self-test module according to an embodiment of the present invention.

[0054] Figure 7 This is a schematic diagram illustrating the workflow of a self-test operation under the architecture of a memory controller with a self-test module according to an embodiment of the present invention.

[0055] Figure 8A and Figure 8B These are schematic diagrams illustrating two specific example architectures of a microcontroller chip according to an embodiment of the present invention. Detailed Implementation

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0058] Please refer to Figure 2 An embodiment of the present invention provides a memory controller (NVMC) 10, which is coupled to a second non-volatile memory (e.g., flash) 20 and includes a first non-volatile memory (e.g., RRAM) 11, a first memory controller (RRAM ctrl) 12, a first bus interface (bus if 1) 13, a second bus interface (bus if 2, optionally) 14, and a second memory controller (flash ctrl) 15.

[0059] The second non-volatile memory 20 can be either off-chip or on-chip memory, and can be any suitable non-volatile memory such as flash memory. Its capacity can be equal to or greater than that of the first non-volatile memory 11, its read / write speed can be lower than that of the first non-volatile memory 11, and its reliability can be higher than that of the first non-volatile memory 11. The second non-volatile memory 20 can be a memory chip externally mounted on the chip containing the memory controller 10 (e.g., an MCU chip), and implemented together with the chip containing the memory controller 10 on the PCB; or it can be a memory die, packaged together with the MCU die containing the memory controller 10 into a single MCU die using System in a Package (SiP) technology (e.g., implementing a SiP Flash architecture). In application, the second non-volatile memory 20 is used to store backups of the contents (including code, data, etc.) of the first non-volatile memory 11.

[0060] The first non-volatile memory 11 is an embedded non-volatile memory that does not require erasure before writing. It can be formed using any suitable single or multiple embedded memory arrays, such as ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM), and can non-volatilely store corresponding content (e.g., code, data). For example, the first non-volatile memory 11 can be integrated with the central processing unit (CPU) core of an MCU chip (e.g., ...). Figure 4A and Figure 4B The first non-volatile memory 11 (as shown in Figure 30) is manufactured together on a more advanced process platform node, thereby avoiding limitations on the evolution speed and performance of the MCU chip on the process platform. In this case, the read / write speed of the first non-volatile memory 11 is higher than that of the second non-volatile memory 20, and it is used as the main memory for MCU chip program execution to store the contents required for MCU chip system operation (such as code, data, etc.), thereby improving system performance. In addition, the first non-volatile memory 11 may logically belong to the memory controller 10, but physically it is independent of the memory controller 10. That is, the first non-volatile memory 11 is physically located outside the memory controller 10. Therefore, the first non-volatile memory 11 in each figure is shown with a "dashed box" inside the memory controller 10, while the modules such as the first memory controller (RRAM ctrl) 12, the first bus interface (bus if 1) 13, and the second bus interface (bus if 2, optionally) 14, which are also physically located inside the memory controller 10, are shown with "solid boxes" inside the memory controller 10.

[0061] Among them, FeRAM, MRAM, RRAM, and PCM respectively store data non-volatilely through different mechanisms. Specifically, FeRAM utilizes the ferroelectric effect of ferroelectric crystals to achieve data storage. The ferroelectric effect refers to the phenomenon that when a certain electric field is applied to a ferroelectric crystal, the central atoms of the crystal move under the influence of the electric field and reach a stable state; when the electric field is removed from the crystal, the central atoms will remain in their original positions. Therefore, ferroelectric random access memory can write "1" or "0" simply by applying an electric field in the desired direction to change the state of the ferroelectric crystal. Ferroelectric random access memory has fast read and write speeds, low power consumption, and does not require voltage to retain data, nor does it require periodic refreshing like DRAM. MRAM uses the magnetoresistance effect to store data. Specifically, it uses a magnetic tunnel junction (MTJ) as the storage cell and stores "1" or "0" by changing the magnetization direction. RRAM has a very simple structure, with metal oxide sandwiched between two electrodes. By applying a pulse voltage to the metal oxide thin film, a large resistance difference is generated to store "0" and "1". PCM uses the difference in conductivity exhibited by phase change materials when they transform between crystalline and amorphous states to store "1" or "0".

[0062] Unlike flash memory, rewriting FeRAM, MRAM, RRAM, and PCM does not require erasure. Therefore, when any one of FeRAM, MRAM, RRAM, and PCM is used as the first non-volatile memory 11, if an error is detected in the contents of the first non-volatile memory 11, the backup contents of the second non-volatile memory 20 can be read and the corresponding erroneous contents in the first non-volatile memory 11 can be accurately overwritten and repaired.

[0063] As an example, please refer to Figure 3 The second non-volatile memory 20 is a Nor flash, and the first non-volatile memory 11 is an RRAM. The Nor flash (i.e., the second non-volatile memory 20) has a larger capacity than the RRAM (i.e., the first non-volatile memory 11) and includes an RRAM backup area and other storage areas. The logical address range of the RRAM backup area has a corresponding mapping relationship with the logical address range of the RRAM (i.e., the first non-volatile memory 11). The RRAM backup area is used to back up the contents of the RRAM (i.e., the first non-volatile memory 11), and the other storage areas of the Nor flash (i.e., the second non-volatile memory 20) are used to store contents outside the logical address range of the RRAM.

[0064] The first memory controller 12 is responsible for controlling the read and write operations of the first non-volatile memory 11. The first bus interface 13 is coupled to the first memory controller 12 and the system bus (which can be AXI, AHB, or other bus protocols) and is used to implement content transfer between the system bus and the first memory controller 12. In other words, the memory controller 10 in this embodiment can be connected to the system bus via the first bus interface 13.

[0065] The second storage controller 15 is responsible for reading and writing control of the second non-volatile memory 20. Specifically, the second storage controller 15 is coupled to the first storage controller 12 and works with the first storage controller 12 to back up the contents of the first non-volatile memory 11 to the second non-volatile memory 20.

[0066] In this embodiment, the backup content of the second non-volatile memory 20 can be used in the following two situations: (1) when reading the first non-volatile memory 11 on the system bus, it is used to repair the read error content in real time; (2) when performing a self-test on the first non-volatile memory 11, it is used to repair the self-tested error content in real time.

[0067] Let's combine the following... Figures 2 to 5B The first case of the backup contents of the second non-volatile memory 20 is described in detail.

[0068] In this case, the second storage controller 15 can read the corresponding backup content in the second non-volatile memory 20 according to the configuration information, and write it into the first non-volatile memory 11 through the first storage controller 12 for content repair, or transmit it to the system bus through the first storage controller 12 and the first bus interface 13, or transmit it to the system bus through the second bus interface 14, and then provide it to the CPU core or other master devices on the system bus to obtain the correct content (such as code, data, etc.).

[0069] Therefore, the memory controller in this embodiment, Figure 1Based on the memory controller architecture shown, a memory path is added by adding a second memory controller 15 and coupling it to a second non-volatile memory 20. When the system bus reads the first non-volatile memory 11, the contents of the first non-volatile memory are backed up using the second non-volatile memory. If the system bus reads an error in the contents of the first non-volatile memory or if there is an address problem, the second memory controller 15 can automatically and accurately read the backup contents in the second non-volatile memory 20 and return them to the system bus, or accurately repair the error in the first non-volatile memory 11. This ensures that the contents read by the CPU (Central Processing Unit) or other bus master units on the system bus are still correct and does not interrupt the execution of the system program.

[0070] It should be understood that when it is necessary to read the corresponding backup content from the second non-volatile memory 20 and return it to the system bus (for example, when the system bus reads erroneous content or corrupted addresses from the first non-volatile memory 11), the second storage controller 15 will automatically read the backup content from the second non-volatile memory 20 according to the configuration information, and further return it to the system bus through an appropriate return path. For example, if there is a second bus interface 14, the return path of the read backup content is second non-volatile memory 20 → second storage controller 15 → second bus interface 14 → system bus; if there is no second bus interface 14, the return path of the read backup content is second non-volatile memory 20 → second storage controller 15 → first storage controller 12 → first bus interface 13 → system bus. Obviously, the backup content can be returned to the system bus regardless of whether there is a second bus interface 14, but with a second bus interface 14, the return path is shorter and the reading speed is relatively faster. Therefore, the second bus interface 14 can be set or omitted according to actual needs.

[0071] Please refer to Figures 4A to 4C The memory controller also includes a register group 16, which includes a control register 161. The control register 161 is primarily used to control the real-time repair function. It is coupled to the first memory controller 12. After a system reset, the first memory controller 12 reads the configuration information of the option byte (Opt) and loads it into the control register 161 to make the option byte effective. The option byte (Opt) can be a specific storage area in the first non-volatile memory 11 and is used to store configuration information required by the system, such as... Figure 4A As shown in Opt 111, or, this option byte (Opt) is a specific storage area in the second non-volatile memory 20, used to store relevant system configuration information, such as... Figure 4BAs shown in Opt 201, the configuration information in this option byte may include pre-set configuration information from the system, as well as configuration information updated by the system's software policy based on relevant records after ECC correction or real-time repair of the first non-volatile memory 11. Furthermore, this configuration information can determine whether the memory controller chooses to repair the first non-volatile memory 11.

[0072] Therefore, in this embodiment, by storing the configuration information in the option bytes, appropriate processing mechanisms can be configured and selected for different error conditions in the first non-volatile memory 11. After each system reset, the memory controller 10 first reads the configuration information of the option bytes in the first non-volatile memory 11 or the second non-volatile memory 20, and reloads the read configuration information of the corresponding option bytes into the control register 161 inside the memory controller 10. Then the corresponding option bytes take effect, thereby meeting the error handling needs of different users or application scenarios.

[0073] In this embodiment, the second storage controller 15 is also used to automatically read the corresponding backup content in the second non-volatile memory 20 when the system bus reads the damaged address set by the configuration information (or by the option byte or control register 161) of the first non-volatile memory 11, and return it to the system bus through the first storage controller 12 or through the second bus interface 14.

[0074] It should be understood that the control register 161 is not limited to a CPU read-only or read-write register, nor is it limited to a single register. It can also be a register group consisting of multiple registers (e.g., including a damaged address setting register, a number of times threshold setting register, a selection register for whether to repair, etc.). This invention does not make any specific limitations in this regard.

[0075] In one example, please refer to Figure 4CThe first storage controller 12 includes a first soft error correction module (ECC_r1) 121, which has at least one of the following functions (1) to (4): (1) when writing content to the first non-volatile memory 11 from the system bus, generating a corresponding ECC (Error Checking and Error Correction) function. Correcting (Error Correction) code 112, the ECC code 112 and the corresponding content are stored together in the first non-volatile memory 11; (2) when reading the corresponding content in the first non-volatile memory 11 on the system bus, the ECC code 112 is read at the same time, thereby using the ECC code 112 to perform ECC verification on the read corresponding content in real time, and when the configuration information (or option byte or control register 161) is preset not to repair the first non-volatile memory 11, the errors detected by ECC and within its error correction capability range are ECC corrected and provided to the system bus, or, regardless of whether the configuration information is preset to repair the first non-volatile memory, the errors detected by ECC and within its error correction capability range are first ECC corrected and provided to the system bus, and then in the memory controller (NVMC) When idle, the second storage controller reads the corresponding backup content of the default backup area and writes the backup content into the first non-volatile memory 11 for content repair; (3) When the second storage controller 15 backs up the content of the first non-volatile memory 11 to the second non-volatile memory 20, the corresponding ECC code 202 is generated, and the second storage controller 15 stores the ECC code 202 and the content of the first non-volatile memory 11 together into the second non-volatile memory 20; (4) Before the first storage controller 12 returns the backup content read by the second storage controller 15 to the system bus or writes it into the first non-volatile memory 11 for content repair, the ECC code 202 is read and the backup content read by the second storage controller 15 in the second non-volatile memory 20 is checked and corrected according to the ECC code 202.

[0076] For example, the ECC function (i.e., ECC verification and ECC correction) of the first soft error correction module 121 can be implemented using methods such as "correct 1 check 2 (i.e., correct 1 bit and check 2 bits)" or "correct 2 check 3 (i.e., correct 2 bits and check 3 bits)". Specifically, the "correct 1 check 2" method involves the first soft error correction module 121 correcting a 1-bit error at a certain address of the first non-volatile memory 11 to the correct content, and then checking the 2-bit content at the same address. The "correct 2 check 3" method involves the first soft error correction module 121 correcting a 2-bit error at a certain address of the first non-volatile memory 11 to the correct content, and then checking the 3-bit content at the same address.

[0077] The memory controller in this example can rely on the first soft error correction module 121 to realize the real-time detection function of the data correctness of the first non-volatile memory 11, that is, to realize ECC verification of the contents of the first non-volatile memory 11, and can rely on the first soft error correction module 121 to perform ECC correction on errors with a small number of bits (e.g., 1-bit errors), thus realizing the real-time ECC detection and correction function of the contents correctness of the first non-volatile memory 11, saving time costs, and since the contents after ECC correction are still correct, the system program can be executed normally without being interrupted.

[0078] Alternatively, please refer to Figure 4CThe first storage controller 12 includes a first soft error correction module (ECC_r1) 121, and the second storage controller 15 includes a second soft error correction module (ECC_r2) 151. The first soft error correction module (ECC_r1) 121 has the following functions: (1) when writing content to the first non-volatile memory 11 from the system bus, it generates a corresponding ECC code 112, which is stored in the first non-volatile memory 11 along with the corresponding content; (2) when reading the corresponding content from the first non-volatile memory 11 from the system bus, it reads the ECC code 112 at the same time, thereby using the ECC code 112 to perform ECC verification on the read corresponding content in real time, and pre-setting it in the configuration information (or option byte or control register 161). If the first non-volatile memory 11 is not repaired, the errors detected by its ECC and within its error correction capability range are corrected by ECC and provided to the system bus. Alternatively, regardless of whether the configuration information pre-sets the repair of the first non-volatile memory 11, the errors detected by its ECC and within its error correction capability range are first corrected by ECC and provided to the system bus. Then, when the memory controller is idle, the second memory controller 15 reads the corresponding backup content of the default backup area and writes the read backup content into the first non-volatile memory 11 to perform content repair. The second soft error correction module 151 has the following functions: (1) When the second storage controller 15 backs up the contents of the first non-volatile memory 11 to the second non-volatile memory 20, it generates a corresponding ECC code 202 and causes the second storage controller 15 to store the ECC code 202 and the contents of the first non-volatile memory 11 together in the second non-volatile memory 20; (2) Before the first storage controller 12 returns the backup contents read by the second storage controller 15 to the system bus or writes them into the first non-volatile memory 11 for content repair, it reads the ECC code 202 and performs ECC verification and error correction on the backup contents read by the second storage controller 15 in the second non-volatile memory 20 based on the ECC code 202.

[0079] Therefore, the ECC protection function can be implemented on the contents written to the first non-volatile memory 11 by the first soft error correction module 121, and the ECC protection function can be implemented on the backup contents written to the second non-volatile memory 20 by the second soft error correction module 151, thereby improving the storage reliability of the first non-volatile memory 11 and the second non-volatile memory 20.

[0080] Optionally, the second storage controller 15 is further configured to read the backup content in the second non-volatile memory 20 and write it into the first non-volatile memory 11 for content repair when the error detected by the first soft error correction module 121 is still present or exceeds the error correction capability range of the first soft error correction module 121, and when the configuration information (or option byte or control register 161) is pre-set to repair the first non-volatile memory 11, and to enable the system bus to read back the corresponding content from the first non-volatile memory 11 to determine whether the first non-volatile memory 11 has been successfully repaired.

[0081] Please refer to Figures 4A to 4C The memory controller in this embodiment also includes a status register 162. The status register 162 is used to record the first status information of the first non-volatile memory 11 after being corrected by the first soft error correction module 121ECC when the configuration information (or option byte or control register 161) is preset not to repair the first non-volatile memory 11. The first status information includes the error status and address. The second status information is used to record the repair result of the first non-volatile memory 11 when the configuration information is preset to repair the first non-volatile memory 11. The second status information includes at least one of the error status, address, number and repair failure count of the repair failure.

[0082] The first storage controller 12 or the second storage controller 15 is further configured to record the addresses of errors that failed to be repaired in the first non-volatile memory 11 (which may be the addresses of each error, or the start and end addresses of the blocks in which each error is located) in the status register 162, so that the software policy may determine whether to store them as corrupted addresses in the configuration information of the option byte Opt.

[0083] The second storage controller 15 is also configured to automatically skip the first non-volatile memory 11 and read the corresponding backup content in the second non-volatile memory 20 when the system bus reads a corrupted address set by the configuration information and / or reads an erroneous address recorded in the status register 162, and return it to the system bus. For example, when the software policy determines that the erroneous address recorded in the status register 162 is a corrupted address and stores it in (or "updates" to) the configuration information of the option byte Opt, the first storage controller 12 will skip the corrupted address when the system bus reads the erroneous address recorded in the status register 162 (i.e., the corrupted address updated in the configuration information) the next time, and the second storage controller 15 automatically reads the backup content in the second non-volatile memory 20 to return to the system bus. Thus, the storage controller 10 of this embodiment can improve the speed of reading the correct content (i.e., backup content) corresponding to the corresponding erroneous or problematic address (hereinafter collectively referred to as "corrupted address") in the first non-volatile memory 11 next time, based on the previous record in the status register 162.

[0084] Optionally, status register 162 is also used to generate an interrupt based on the corresponding record within it. This allows the CPU (Central Processing Unit) or other bus master unit on the system bus to subsequently perform appropriate processing based on the interrupt.

[0085] It should be understood that the status register 162 can be a CPU-read-only register that can be cleared by the CPU. It can be a single register or a register group consisting of multiple registers (e.g., including address register, count register, number of times register, result register of whether the repair was successful, etc.). This invention does not make any specific limitations on this.

[0086] Optionally, the configuration information of the option byte Opt also sets a threshold for the number of repeated repairs. The second storage controller 15 is also used to repeatedly repair the errors in the first non-volatile memory 11 using the backup content of the second non-volatile memory 20 until the number of repeated repairs does not exceed the threshold. When the number of repeated repairs reaches the threshold and the repair is still unsuccessful, the repair of the first non-volatile memory 11 is considered to have failed.

[0087] Optionally, the first memory controller 12 further includes a counter module 122, used to count at least one of the following: the number of errors in the first non-volatile memory 11 verified by the first soft error correction module 121, the number of times the first non-volatile memory 11 has been repeatedly repaired, and the number of errors in the first non-volatile memory 11 that failed to be repaired. Thus, the memory controller of the present invention can use the count value of the counter module to determine whether to generate an interrupt or perform error repair, etc.

[0088] In one example, please refer to Figure 5A and combined Figures 2 to 4C When the CPU (or other system bus master unit, such as DMA) reads the first non-volatile memory 11 through the system bus, the working mechanism of the memory controller 10 in this embodiment is as follows:

[0089] S101, the first storage controller 12 determines whether it reads the configuration information loaded by the control register 161 (or, the corrupt address set by the option byte Opt or the control register 161). If not, the first soft error correction module (which is an ECC hardware circuit) 121 further performs ECC verification on the content of the first non-volatile memory 11 in real time to detect whether there is an ECC error in the content of the first non-volatile memory 11 in real time.

[0090] If the address read by the first storage controller 12 does not contain the corrupt address set by the configuration information and the content read does not have an ECC error (defined as the first read case), then jump to step S110 and return the correct content to the system bus (that is, the first storage controller 12 directly returns the content of the first non-volatile memory 11 read to the CPU through the first bus interface 13). The CPU and other devices read the correct content and the system program executes normally.

[0091] If the first storage controller 12 reads a corrupt address (defined as the second read case) set by the configuration information (or by the non-volatile option byte Opt or control register 161), it jumps to step S102. The second storage controller 15 automatically reads the corresponding backup content in the second non-volatile memory 20 according to the set corrupt address, and further executes step S110 to return the correct content to the system bus, that is, to return it to the CPU through the first storage controller 12 and the first bus interface 13 or to the CPU through the second bus interface 14. This second read case operation consumes more time than the first read case operation, but the CPU can still read the correct data, so the system program can continue to execute.

[0092] If the first soft error correction module 121 determines that the content read by the first storage controller 12 has an ECC error (defined as the third read case), then further execute step S103 to determine whether the ECC error in the content read by the first storage controller 12 is still within the error correction capability range of the first soft error correction module 121. If so, that is, the ECC error in the content read by the first storage controller 12 has few bits and is still within the error correction capability range of the ECC function of the first soft error correction module 121 (e.g., 1-bit error), then execute step S104 to select whether to repair the first non-volatile memory 11 according to the pre-set configuration information (or control register 161 or option byte Opt) (the "repair" and "repair" below both refer to reading the backup content from the second non-volatile memory 20).

[0093] If no repair is selected, step S105 is executed, where the first soft error correction module 121 performs ECC correction on the erroneous content, and further executes step S106 to record the error status (brk_status, e.g., whether it is a 1-bit error or a 2-bit error), address (brk_addr), and count (brk_times, e.g., the number of 1-bit errors and the number of 2-bit errors) in the status register 162. Then, step S110 is executed to return the correct content to the system bus, i.e., the correct content corrected by the first soft error correction module 121 after ECC is returned to the CPU through the first memory controller 12 and the first bus interface 13, or returned to the CPU through the first bus interface 13. Since the content corrected by ECC is still correct at this time, the system program can execute normally. It should be understood that the status register 162 may include multiple registers for recording the aforementioned first status information. Optionally, the status register 162 can also generate an interrupt based on the recorded error status and address information, which will be processed by the CPU later.

[0094] If repair is selected, step S108 is executed. The second storage controller 15 reads the backup content from the second non-volatile memory 20 and writes it to the first non-volatile memory 11 through the first storage controller 12 for content repair (i.e., following the path "second non-volatile memory 20 → second storage controller 15 → first storage controller 12 → first non-volatile memory 11"). Then, step S109 is executed. The first storage controller 12 reads back to determine whether the repair was successful (i.e., whether the path "first non-volatile memory 11 → first storage controller 12 → first bus interface 13" was successful). If the repair is successful, step S109 is executed. S110 returns the correct content to the CPU and continues program execution. If the repair fails, step S108 is executed again to repeatedly repair, and the number of repeated repairs does not exceed the threshold (i.e., there are two possible outcomes: either the repair is successful before the number of repeated repairs reaches the threshold, or the repair still fails when the number of repeated repairs reaches the threshold). Alternatively, step S106 is executed to record the address, status, and number of errors that failed to repair in the status register 162. Optionally, the status register 162 can also generate an interrupt based on the recorded error status and address and other second status information, which is then handed over to the CPU for further processing.

[0095] If, in step S103, it is determined that the ECC error occurring in the content read by the first storage controller 12 exceeds the error correction capability range of the first soft error correction module 121 (e.g., a 2-bit error), then step S107 is executed to directly repair the first non-volatile memory 11.

[0096] In another example, the working mechanism of the memory controller 10 of this embodiment for performing ECC correction and real-time repair on the first non-volatile memory 11 is as follows: Figure 5B As shown, this working mechanism is similar to Figure 5A The difference in the example shown is that, after determining in step S103 that the ECC error occurring in the read content is still within the error correction capability range of the first soft error correction module 121, if in step S104 it is determined that the configured information (or control register 161 or option byte Opt) selects to repair the first non-volatile memory 11, then the following steps need to be executed sequentially:

[0097] S111, the first soft error correction module 121 performs ECC correction on the erroneous content. This step S111 is the same as step S105 above, and will not be described in detail here.

[0098] S112, record the first status information such as the error status, address, and number in the status register 162. This step S112 is the same as step S106 above, and will not be described in detail here.

[0099] S113, return the corrected content after correction by the first soft error correction module 121ECC to the system bus. This step S113 is the same as the above step S110, and will not be described in detail here.

[0100] S114, waiting for the memory controller (NVMC) to become idle;

[0101] S115, when the memory controller (NVMC) is idle, the second memory controller 15 reads the backup content in the default backup area of ​​the second non-volatile memory 20 and writes it into the first non-volatile memory 11 through the first memory controller 12 for content repair. This step S115 is the same as the above step S108, and will not be described in detail here.

[0102] Therefore, the working mechanism of this example is to pre-set the error repair in the first non-volatile memory 11 in the configuration information, and when the number of errors detected by ECC is small, ECC correction is performed first and the corrected content is returned to the system bus, so as not to interrupt the operation of the system program, and the error in the first non-volatile memory 11 is repaired by utilizing the idle time of the memory controller (NVMC), thus making reasonable use of system resources.

[0103] In other words, Figure 5B In the example shown, when reading the first non-volatile memory 11 from the system bus, if the error detected by the first soft error correction module 121 through the ECC function is within its ECC error correction capability, regardless of whether the configuration information (or control register 161 or option byte Opt) is preset to repair the first non-volatile memory 11, the first soft error correction module 121 will perform ECC correction on the error detected by ECC and provide the correct content after ECC correction to the system bus in a timely manner, so as not to interrupt the operation of the system program.

[0104] because Figure 5B The illustrated working mechanism contains identical steps; therefore, in other examples of the working mechanism of this invention, the process can be simplified and operational efficiency improved by adjusting the order of the steps. For example, please refer to... Figure 5C As shown, the working mechanism of the memory controller 10 in this example for ECC correction and real-time repair of the first non-volatile memory 11 is similar to... Figure 5BThe difference in the example shown is that after executing step S103, steps S105 (i.e., the first soft error correction module 121 performs ECC correction on the erroneous content), S106 (i.e., the first status information such as the error status, address, and number is recorded in the status register 162), and step S110 (i.e., the correct content after ECC correction by the first soft error correction module 121 is returned to the system bus) are executed first, and then step S104 (it is determined whether the configuration information pre-sets the repair of the first non-volatile memory 11). If it is determined that the configuration information pre-sets the repair of the first non-volatile memory 11, then the following steps are further executed: step S114, waiting for the memory controller (NVMC) to be idle; and step S115, when the memory controller (NVMC) is idle, the second memory controller 15 reads the backup content from the default backup area of ​​the second non-volatile memory 20 and writes it into the first non-volatile memory 11 through the first memory controller 12 for content repair. Thus, steps S111 to S113 can be omitted.

[0105] In the working mechanisms of the above examples, when repairing the first non-volatile memory 11, repair can be performed on a per-address basis or on a per-block basis (e.g., a row of memory cells). Addresses that err when not repaired can also be automatically recorded in the status register 162 (i.e., the error address is reported) for later repair attempts if needed.

[0106] For addresses where repair fails, the first memory controller 12 or the second memory controller 15 will automatically record them in the status register 162 (i.e., report the error address), so that the CPU's software policy can determine whether to store them as the corrupted address in the option byte Opt. If the CPU's software policy decides to store them as the corrupted address in the option byte Opt, then when the CPU reads that address the next time, the memory controller 10 will automatically read the backup content in the second non-volatile memory 20 according to the configuration information of the option byte Opt and return it to the system bus.

[0107] For addresses that fail to be repaired repeatedly, the second storage controller 15 can define the address as a corrupted address (or simply a "bad address"), or define the row of storage cells containing the address as a bad row, or define the block containing the address as a bad block. For example, if several bits in a row of storage cells are physically faulty or damaged due to abnormal reasons such as short circuits, and the repair still fails after repeated repairs by the software up to the number of times set in the configuration information, these bits can be considered as physically damaged addresses, or the row or block containing these bits can be considered as physically damaged bad rows or bad blocks. The address of the corrupted address, bad row address, or bad block address is recorded in the status register 162 by the first memory controller 12 or the second memory controller 15 (i.e., the error address is reported). This indicates that the previous path from the second non-volatile memory 20 → second memory controller 15 → first memory controller 12 → first non-volatile memory 11, and then from the first non-volatile memory 11 back to the first bus interface 13 failed. The CPU's software policy will determine whether to store it as a corrupted address in the option byte Opt (or update it in the configuration information). If the CPU's software policy decides to store it as a corrupted address in the option byte Opt, then the next time the CPU reads the recorded address, it will skip the first non-volatile memory 11 and read the backup content in the second non-volatile memory 20. That is, it will take the path of second non-volatile memory 20 → second memory controller 15 → first memory controller 12 → first bus interface 13, or take the path of second non-volatile memory 20 → second memory controller 15 → second bus interface 14.

[0108] Therefore, the memory controller in this embodiment can read the backup content corresponding to the problematic address in real time without interrupting the execution of the program. Furthermore, when there is a physically damaged address, bad row, or bad block in the first non-volatile memory 11, it can automatically skip the physically damaged address, bad row, or bad block in the first non-volatile memory 11, and the system can continue to work, thus improving the security of the MCU chip.

[0109] The following is combined with Figures 6A-6B as well as Figure 7 This section will detail the second application of the backup content of the second non-volatile memory 20, namely: real-time repair of errors detected during the self-test of the first non-volatile memory 11. This is also the focus of the present invention.

[0110] Because the first non-volatile memory differs from embedded flash memory, its data storage mechanism is susceptible to interference from the external environment, leading to a greater likelihood of changes in the stored data. Therefore, the memory controller in this embodiment adds a self-test function, which can automatically check the corresponding content in the first non-volatile memory at appropriate stages and perform ECC correction or real-time repair on errors detected by the self-test to ensure the reliability of the content stored in the first non-volatile memory. Consequently, when the CPU reads the first non-volatile memory, the accuracy of the read content can be improved, reducing the number of times the first non-volatile memory needs ECC correction or the use of backup content from the second non-volatile memory to repair the first non-volatile memory. This improves system operating speed and consistency, and facilitates user operation.

[0111] Please refer to Figure 6A and Figure 6B In the memory controller (NVMC) 10 provided in this embodiment, the first memory controller 12 further includes a self-test module 123. The self-test module 123 is used to read and compare the corresponding contents in the first non-volatile memory 11 and the corresponding backup contents in the second non-volatile memory 20 during the power-on reset (POR) phase, system reset phase, or system run phase, to perform a self-test on the contents of the first non-volatile memory 11. If there is no difference between the two, it indicates that the self-tested contents in the first non-volatile memory 11 are correct; if there is a difference, it indicates that the self-tested contents in the first non-volatile memory 11 have errors. Therefore, the self-test module 123 can automatically check the corresponding contents in the first non-volatile memory 11 at appropriate stages (e.g., after reset or during MCU operation) and perform ECC correction or real-time repair on errors detected during self-testing, facilitating user operation.

[0112] In this embodiment, a self-test option byte is added to the option byte Opt to control the self-test function. The configuration information stored in the self-test option byte includes the self-test address range and at least one corresponding register value. That is, the configuration information in the option byte loaded by the control register 161 includes not only configuration information for ECC verification and real-time repair of the first non-volatile memory 11, but also configuration information for implementing self-tests at appropriate stages of the system (such as power-on, reset, or operation).

[0113] The self-test address range is used to determine which areas of the first non-volatile memory 11 the self-test module 123 will perform a self-test on. The values ​​of these registers determine whether the self-test module 123 should perform a self-test on the contents of the first non-volatile memory 11 and the stage at which the self-test module 123 performs the self-test on the first non-volatile memory 11. The configuration of the self-test option byte can be implemented by software reading and writing after the CPU starts running. After the system is reset, the first memory controller 12 reads the self-test option byte from the option byte (Opt) and loads it into the control register 161 to make the self-test option byte effective.

[0114] Accordingly, the status register 162 is used to perform at least one of the following functions: (1) record the corresponding status information (including the first status information of ECC correction and the second status information of real-time repair) when reading the first non-volatile memory 11 during system operation; (2) record the third status information generated during the self-test process, the third status information including at least one of the status, address, number of repair failures, etc. of the errors detected by the self-test.

[0115] For example, the status register 162 includes at least one of a first register 162a and a second register 162b. The first register 162a is used to record, when reading the first non-volatile memory 11 from the system bus, if the configuration information specifies that the first non-volatile memory 11 should not be repaired, a first status information of the first non-volatile memory 11 after being corrected by the first soft error correction module 121, the first status information including the error status and address; and, if the configuration information specifies that the first non-volatile memory 11 should be repaired, a second status information of the repair result of the first non-volatile memory 11, the second status information including at least one of the error status, address, number, and number of repair failures; and to record related status information.

[0116] The second register 162b is used to record the third status information of the first non-volatile memory 11 after self-testing (including ECC correction and repair processing) when the self-test module 123 performs self-testing on the first non-volatile memory 11. The third status information includes at least one of the following: the status of the error detected by the self-test, the address, the number of repair failures, etc.

[0117] The option byte (Opt) can be a specific storage area in the first non-volatile memory 11 and is used to store system configuration information, such as... Figure 6A As shown in Opt 111, or, this option byte (Opt) is a specific storage area in the second non-volatile memory 20, used to store system configuration information, etc., such as... Figure 6BAs shown in Opt 201. The size of the self-test address range can be configured as needed, for example, it can be a portion of the address range of the first non-volatile memory 11, or it can be the entire range of the first non-volatile memory 11.

[0118] Further, please refer to Figure 6A and Figure 6B The self-test module 123 is used to, when the register value in the self-test option byte is configured for self-test (or, the corresponding register value in the configuration information is configured to a specific value to indicate that a self-test is performed at the corresponding stage), in the stage of implementing self-test determined by the register value in the self-test option byte, sequentially read out the contents of the first non-volatile memory 11 and the corresponding backup contents of the second non-volatile memory 20 for each address in the self-test address range in the self-test option byte and compare them. If there is no difference between the contents of the two, it means that the contents stored at the address currently being self-tested in the first non-volatile memory 11 are correct, and the self-test of the next address in the self-test address range continues until the self-test of all addresses in the self-test address range is completed. If there is a difference between the contents of the two, it indicates that the content stored at the address currently being self-tested in the first non-volatile memory 11 is incorrect. At this time, the second storage controller 15 is also used to read the backup content in the second non-volatile memory 20 and write it into the first non-volatile memory 11 to repair the content when the self-test module 123 detects an error in the first non-volatile memory 11 and the option byte or control register 161 is preset to repair the first non-volatile memory 11, and to make the self-test module 123 read back and compare again.

[0119] Further optionally, the first soft error correction module 121 is also used to perform ECC correction on the error in the first non-volatile memory 11 detected by the self-test module 123 when the error detected by the self-test module 123 is still within the error correction capability of the first soft error correction module 121, and the configuration information (or, option byte or control register 161) is preset to not repair the first non-volatile memory 11.

[0120] Optionally, the first memory controller 12 further includes a counting module 122, used to count at least one of the following: the number of errors in the first non-volatile memory 11 verified by the first soft error correction module 121; the number of errors in the first non-volatile memory 11 detected by the self-test module 123; the number of times the second memory controller 15 repeatedly repairs the first non-volatile memory 11; and the number of errors in the first non-volatile memory 11 that the second memory controller 15 fails to repair. Thus, the memory controller of the present invention can use the count value of the counting module to determine whether to generate an interrupt or perform error repair, etc.

[0121] Please refer to Figure 7 This embodiment uses a self-test after a reset (including a system reset or a power-on reset, POR) as an example to illustrate the workflow of the memory controller 10 implementing the self-test, which includes the following steps:

[0122] S201, after a reset, the memory controller 10 (e.g., through the first memory controller 12 therein) reads the option byte Opt stored in the first non-volatile memory 11 or the second non-volatile memory 20. This option byte Opt is reloaded into the control register 161, and the corresponding option bytes, including the self-test option byte, take effect. The memory controller 10 (e.g., through the self-test module 123 in the first memory controller 12) determines whether to perform a self-test on the contents of the first non-volatile memory 11 based on the corresponding register values ​​in the configuration information loaded in the control register 161.

[0123] If configured not to perform a self-test, the system will skip the other steps of the self-test process and proceed to step S208, whereby the system will proceed to the next startup step.

[0124] If configured to perform a self-test, step S202 is executed. The self-test module 123 sequentially reads the contents of the first non-volatile memory 11 at each address in the self-test address range set in the configuration information loaded in the control register 161. At the same time, for each address, the backup contents corresponding to the second non-volatile memory 20 are read through the second storage controller 15. Then, the contents of the first non-volatile memory 11 and the backup contents of the second non-volatile memory 20 corresponding to the currently read address are compared.

[0125] If there is no difference in the comparison in step S202, it means that the content of the first non-volatile memory 11 at the current address is correct, and you can jump to step S207. The self-test module 123 determines whether it is the last address in the self-test address range. If not, it jumps back to step S202 to perform the self-test of the next address. If yes, it means that the self-test is completed, and you can jump to step S208.

[0126] If there is a difference in the comparison in step S202, then step S204 is further executed, and the self-test module 123 determines whether the content error of the first non-volatile memory 11 is within the ECC error correction capability range of the first soft error correction module 121 and whether it can be corrected by ECC.

[0127] If the error is within the ECC correction capability range (for example, the first soft error correction module 121 adopts the "correct 1, check 2" method, and the self-detected error in the first non-volatile memory 11 is a 1-bit error) and there are two cases according to the configuration information loaded by the control register 161: First, choose not to repair, that is, the self-detected error at the current address can be corrected by the ECC function, then execute step S205, the self-test module 123 can enable the first soft error correction module 121 to work, so as to perform ECC correction on the error in the first non-volatile memory 11 through the first soft error correction module 121 to obtain the correct content, and then jump to step S207; Second, choose to repair, then execute step S206, the self-test module 123 can enable the second storage controller 15 to work, the second storage controller 15 reads the backup content in the second non-volatile memory 20, and then writes it to the current address of the first non-volatile memory 11 through the first storage controller 12 for refresh repair.

[0128] If the error exceeds the ECC correction capability (i.e., the error detected at the current address cannot be corrected by the ECC function, for example, the first soft error correction module 121 uses the "correct 1, check 2" method, and the error detected in the first non-volatile memory 11 is an error of no less than 2 bits), and according to the configuration information loaded by the control register 161, there are two possibilities: First, choose not to repair, because the error detected at the current address cannot be corrected by the ECC function. Even if the self-test module 123 enables the first soft error correction module 121 to work, the first soft error correction module 121 cannot perform ECC correction on the error in the first non-volatile memory 11. Therefore, the current address can be skipped directly and the process can jump to step S207; Second, choose to repair, then step S206 is executed. The self-test module 123 enables the second storage controller 15 to work, reads the backup content in the second non-volatile memory 20 through the second storage controller 15, and then writes it to the current address of the first non-volatile memory 11 through the first storage controller 12 for refresh repair (e.g., a 2-bit error).

[0129] Furthermore, in step S206, the content written to the current address of the first non-volatile memory 11 can be read back for confirmation. If the readback confirmation is successful, the process jumps to step S208 to perform a self-test on the next address. If the readback confirmation fails, step S206 is executed again to repeatedly perform the repair. The number of repeated repairs does not exceed the threshold number set in the configuration information. That is, there are two possible results after the self-test of the current address: either the repair is successful before reaching the threshold number, or the repair fails even after the number of repeated repairs reaches the threshold number. When either of these two results is achieved, the self-test of the current address is considered to be over, and then the process jumps to step S207 to perform a self-test on the next address. When it is finally confirmed that the current address repair failed during the self-test, the address, status and number of errors that failed to be repaired during the self-test are recorded in the status register 162. For example, the address that failed to be repaired is marked as a bad block so that the system avoids using the address, or when the address is used, the system automatically skips the first non-volatile memory 11 and reads the backup content in the second non-volatile memory 20.

[0130] During the self-test process described above, when every address in the self-test address range has been checked (i.e., all addresses in the self-test address range have been scanned), the self-test of the contents of the first non-volatile memory 11 is completed, and then step S208 can be executed to proceed to the next startup step.

[0131] Furthermore, during the self-test, if an error is reported due to an abnormality in the second non-volatile memory 20 itself (such as physical damage), an interrupt is generated to notify the CPU, thereby allowing the CPU to consider subsequent response strategies through software.

[0132] Optionally, during the self-test process, if the number of failed repairs exceeds a set threshold, an interrupt notification can be generated to the CPU, thereby allowing the CPU's software to consider subsequent response strategies.

[0133] It should be understood that during system startup or operation, the CPU and other system bus master devices can read the contents of the first non-volatile memory 11 via the system bus as needed. In this case, the working mechanism of the memory controller 10 in this embodiment is basically the same as that of the memory controller 10 in the first scenario described above, and can be referred to... Figures 5A to 5C As mentioned in the first scenario above, the details will not be repeated here.

[0134] Obviously, the memory controller in this embodiment, by adding a self-test module, can configure option bytes to enable the self-test module to perform self-tests on the first non-volatile memory at appropriate stages (e.g., power-on reset, system reset, or system operation), ensuring the reliability of the contents stored in the first non-volatile memory, reducing errors caused by external interference, and thus improving the accuracy of the read content when the CPU reads the first non-volatile memory. This reduces the number of times the first non-volatile memory needs ECC correction or to be repaired using backup contents of the second non-volatile memory, thereby improving system operating speed and consistency.

[0135] It should also be understood that when the system performs a self-test during operation, this self-test is performed before the system bus (i.e., the CPU or other system bus master device) reads the first non-volatile memory. This ensures the reliability of the contents stored in the first non-volatile memory, reduces errors caused by external interference, and thus improves the accuracy of the read content when the CPU reads the first non-volatile memory. This self-test can also be performed synchronously with the system bus (i.e., the CPU or other system bus master device) reading the first non-volatile memory, or it can be performed after the system bus (i.e., the CPU or other system bus master device) reading the first non-volatile memory. This ensures the reliability of the contents stored in the first non-volatile memory, reduces errors caused by external interference, and thus improves the accuracy of the read content when the CPU reads the first non-volatile memory again.

[0136] In addition, based on the same inventive concept, please refer to Figure 8A and Figure 8B An embodiment of the present invention also provides a microcontroller chip, which includes a central processing unit (CPU) 30 and a memory controller (NVMC) 10 as described in any embodiment of the present invention. The CPU 30 is coupled to the memory controller 10 via a system bus and reads and writes to a first non-volatile memory 11 in the memory controller 10. The microcontroller chip also has a built-in second non-volatile memory 20 (e.g., ...). Figure 8A (as shown) or coupled to a second non-volatile memory 20 (such as Figure 8B As shown, the second non-volatile memory 20 is coupled to the second memory controller 15 in the memory controller 10.

[0137] The microcontroller chip of the present invention, by employing the memory controller 10 of the present invention, greatly reduces the probability of being interrupted during system program startup or operation due to errors in the contents of the first non-volatile memory 11, thereby improving system reliability and operating performance.

[0138] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A memory controller, comprising: The memory controller is coupled to a second non-volatile memory and comprises: a first non-volatile memory with higher read-write speed than the second non-volatile memory and used as a main memory for storing contents required for system operation; a first storage controller for controlling read-write of the first non-volatile memory; a first bus interface coupled to the first storage controller and the system bus and used for transferring contents between the system bus and the first storage controller; a second storage controller coupled to the first storage controller and used for cooperating with the first storage controller to backup contents of the first non-volatile memory into the second non-volatile memory; wherein the first storage controller comprises a self-checking module for reading and comparing corresponding contents in the first non-volatile memory and corresponding backup contents in the second non-volatile memory according to configuration information in a power-on reset stage, a system reset stage or a system operation stage to implement self-checking of the contents in the first non-volatile memory, and if there is no difference between the two, it means that the contents in the first non-volatile memory being self-checked are correct; if there is a difference between the two, it means that the contents in the first non-volatile memory being self-checked are incorrect.

2. The memory controller of claim 1, wherein, Further comprising a control register coupled to the first storage controller, and the first storage controller is further used for reading an option byte after system reset and loading it into the control register to make the option byte effective; wherein the option byte is a specific storage area in the first non-volatile memory or the second non-volatile memory and used for storing the configuration information.

3. The memory controller of claim 2, wherein, The option byte loaded into the control register comprises a self-checking option byte, and the configuration information stored in the self-checking option byte comprises a self-checking address range and a corresponding at least one register value, the self-checking address range is used for determining which regions of the contents in the first non-volatile memory are self-checked by the self-checking module, and the size of the register value is used for determining whether the self-checking module implements self-checking of the contents in the first non-volatile memory and determining the stage of implementing self-checking of the first non-volatile memory by the self-checking module; the self-checking module is used for reading the contents in the first non-volatile memory and corresponding backup contents in the second non-volatile memory of each address in the self-checking address range in sequence and comparing them in the stage of implementing self-checking determined by the register value when the register value is configured to self-check, and if there is no difference between the two, it means that the contents stored in the current self-checked address in the first non-volatile memory are correct, and the self-checking of the next address in the self-checking address range is continued until the self-checking of all addresses in the self-checking address range is completed.

4. The memory controller of claim 1, wherein, Further comprising a second bus interface coupled to the second storage controller and the system bus and used for transferring backup contents read from the second non-volatile memory by the second storage controller to the system bus when the system bus reads the first non-volatile memory.

5. The memory controller of claim 1, wherein, The first storage controller comprises a first soft failure correction module, which is configured to perform ECC check on the corresponding content read from the first non-volatile memory when the system bus reads the first non-volatile memory or when the self-check module performs self-check on the content in the first non-volatile memory, and The first soft failure correction module is further configured to perform ECC correction on the error within the ECC correction capability and provide the error to the system bus when the configuration information is preset to not repair the first non-volatile memory. Alternatively, the first soft failure correction module is further configured to perform ECC correction on the error within the ECC correction capability and provide the error to the system bus, and then read the corresponding backup content of the default backup area by the second storage controller when the memory controller is idle, and write the backup content into the first non-volatile memory for content repair, regardless of whether the configuration information is preset to repair the first non-volatile memory.

6. The memory controller of claim 5, wherein, The first soft failure correction module is further configured to generate the corresponding ECC code when writing the content into the first non-volatile memory and / or when backing up the content of the first non-volatile memory into the second non-volatile memory, and the ECC code generated by the first soft failure correction module is stored into the second non-volatile memory together with the content of the first non-volatile memory. Alternatively, the second storage controller further comprises a second soft failure correction module, which is configured to generate the corresponding ECC code when backing up the content of the first non-volatile memory into the second non-volatile memory, and the ECC code generated by the second soft failure correction module is stored into the second non-volatile memory together with the content of the first non-volatile memory. When the system bus reads the corresponding content in the first non-volatile memory, the first soft failure correction module performs real-time ECC check on the read corresponding content by using the ECC code.

7. The memory controller of claim 1, wherein, The second storage controller is further configured to read the backup content in the second non-volatile memory according to the configuration information and write the backup content into the first non-volatile memory through the first storage controller for content repair when the system bus reads the first non-volatile memory and / or when the self-check module performs self-check on the first non-volatile memory.

8. The memory controller of claim 7, wherein, The second storage controller reads the backup content in the second non-volatile memory according to the configuration information in units of a single address or a single row address or a single block of the first non-volatile memory, and writes the backup content into the first non-volatile memory through the first storage controller to repair the first non-volatile memory.

9. The memory controller of claim 7, wherein, The configuration information further sets a threshold of the number of repeated repairs, and the second storage controller is further configured to repeatedly repair errors in the first nonvolatile memory using backup content of the second nonvolatile memory, and the number of repeated repairs does not exceed the threshold.

10. The memory controller of claim 7, wherein, The state register further comprises: a first register configured to record first state information of the first nonvolatile memory after ECC correction when the system bus reads the first nonvolatile memory and the configuration information sets that the first nonvolatile memory is not repaired, the first state information comprising at least one of the state and address of errors; and record second state information of repair results of the first nonvolatile memory when the system bus reads the first nonvolatile memory and the configuration information sets that the first nonvolatile memory is repaired, the second state information comprising at least one of the state, address, number and number of repair failures of errors that fail to be repaired; and / or a second register configured to record third state information of the first nonvolatile memory after self-checking when the self-checking module performs self-checking on the first nonvolatile memory, the third state information comprising at least one of the state, address, number of repair failures of errors detected by the self-checking.

11. The memory controller of claim 10, wherein, The address of errors recorded in the first register and / or the second register is determined by a software strategy whether to be stored as a damaged address in the configuration information of the option byte.

12. The memory controller of claim 11, wherein, The second storage controller is further configured to automatically skip the first nonvolatile memory and read corresponding backup content in the second nonvolatile memory and return to the system bus when the system bus reads the damaged address set by the configuration information and / or reads the address of errors recorded in the state register.

13. The memory controller of claim 12, wherein, The state register is further configured to generate an interrupt according to corresponding records in the first register and / or the second register.

14. The memory controller of claim 9, wherein, The first storage controller further comprises a counting module configured to count at least one of the number of errors in the first nonvolatile memory checked by the first soft failure correction module ECC, the number of errors in the first nonvolatile memory detected by the self-checking module, the number of repeated repairs of the first nonvolatile memory by the second storage controller, and the number of errors in the first nonvolatile memory that fail to be repaired by the second storage controller.

15. The memory controller of any one of claims 1-14, wherein, The first nonvolatile memory is an embedded memory and does not need to be erased before writing, and the second nonvolatile memory is an off-chip memory.

16. The memory controller of claim 15, wherein, The first nonvolatile memory comprises at least one of ferroelectric random access memory, magnetic random access memory, resistive random access memory and phase change memory; and / or the second nonvolatile memory comprises a flash memory.

17. A microcontroller chip, characterized by The microcontroller chip comprises a central processing unit and a memory controller as claimed in any one of claims 1-16, the central processing unit is coupled with the memory controller through a system bus and reads and writes the first non-volatile memory in the memory controller, and the microcontroller chip is further internally built or externally hung with a second non-volatile memory, the second non-volatile memory is coupled with a second storage controller in the memory controller.

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