Multi-channel chip test data parallel acquisition and intelligent analysis method and system

Abstract

The invention relates to the technical field of multichannel chip test data parallel acquisition and intelligent analysis scheme design, in particular to a multichannel chip test data parallel acquisition and intelligent analysis method and system. The method comprises the following steps: capturing chip test data of a plurality of test channels in parallel; performing high-precision timestamp alignment processing on the test data; and carrying out correlation analysis and abnormal mode identification on the aligned data by utilizing an intelligent analysis model. The system comprises a data acquisition module with corresponding functions, a timestamp alignment module and an intelligent analysis module. The problem of low multi-channel synchronization precision is solved through hardware triggering and a global clock, the real-time bottleneck is broken through by utilizing a parallel processing architecture, and complex abnormities are intelligently identified by virtue of a machine learning model, so that high-efficiency, high-precision and high-intelligence chip testing is realized, and the test efficiency is improved. And the test speed, the data analysis accuracy and the overall test reliability are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of design technology for parallel acquisition and intelligent analysis schemes for multi-channel chip test data, and specifically to a method and system for parallel acquisition and intelligent analysis of multi-channel chip test data. Background Technology

[0002] With the continuous advancement of integrated circuit manufacturing processes, the complexity and integration of chips are increasing exponentially, placing increasingly stringent demands on testing technologies. Traditional chip testing methods primarily rely on serial data acquisition and analysis of single or a small number of channels. This approach suffers from significant efficiency bottlenecks when dealing with high-performance chips with numerous input / output pins, resulting in excessively long testing times and high production costs. More critically, serial testing struggles to capture the precise timing relationships between multi-channel signals, which is essential for diagnosing anomalies in the collaborative operation between internal chip modules.

[0003] In the exploration of multi-channel parallel testing, existing technologies still face many unresolved technical challenges. First, during the data acquisition phase, achieving high-precision time synchronization is extremely difficult due to inherent delay differences in the hardware paths of each test channel and potential clock signal drift. Common software synchronization methods lack sufficient accuracy, while complex hardware synchronization schemes are costly and inflexible. This leads to significant errors in the timestamps used for subsequent data analysis, severely impacting the reliability of the analysis results. Second, facing the massive amounts of test data generated by high-speed chips, traditional data processing architectures suffer from real-time processing bottlenecks, easily causing data accumulation or loss, making true online analysis and real-time monitoring difficult. Finally, at the data analysis level, existing methods largely rely on preset fixed thresholds or simple statistical analysis, lacking the ability to intelligently identify complex and implicit anomaly patterns. These methods cannot effectively learn deep correlation features in test data, exhibiting low sensitivity and high false negative rates for complex anomalies such as intermittent and correlated faults, failing to meet the testing requirements of high-reliability chips. Therefore, there is an urgent need in this field for a new testing solution capable of high-speed, high-precision synchronous acquisition and intelligent analysis capabilities.

[0004] Therefore, the existing technology still needs further development. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide a method and system for parallel acquisition and intelligent analysis of multi-channel chip test data, so as to solve the problems existing in the prior art.

[0006] To achieve the above-mentioned technical objectives, according to a first aspect of the present invention, the present invention provides a method for parallel acquisition and intelligent analysis of multi-channel chip test data, comprising: S1. Simultaneously capture chip test data from multiple test channels; S2. Perform timestamp alignment processing on the test data of the multiple test channels; S3. Use intelligent analysis models to perform correlation analysis and anomaly pattern identification on the timestamp-aligned test data.

[0007] Specifically, in step S1, the parallel capture adopts a synchronous capture mechanism based on hardware triggers.

[0008] Specifically, the hardware trigger is configured to be event-driven in response to a test signal.

[0009] Specifically, the event-driven triggering includes rising edge triggering, falling edge triggering, or level triggering.

[0010] Specifically, in step S2, the timestamp alignment process includes timestamping the data of each channel using a global reference clock.

[0011] Specifically, the timestamp alignment process also includes using an interpolation algorithm to correct the timestamps of non-uniformly sampled data.

[0012] Specifically, the interpolation algorithm is linear interpolation or spline interpolation.

[0013] Specifically, in step S3, the intelligent analysis model is a machine learning model, which is trained using historical test data.

[0014] Specifically, the machine learning model includes neural networks, support vector machines, or decision tree models.

[0015] According to a second aspect of the present invention, a multi-channel chip test data parallel acquisition and intelligent analysis system is provided, comprising: The data acquisition module is configured to capture chip test data from multiple test channels in parallel. The timestamp alignment module is configured to perform timestamp alignment processing on the test data of the multiple test channels; The intelligent analysis module is configured to use an intelligent analysis model to perform correlation analysis and anomaly pattern recognition on timestamp-aligned test data.

[0016] Beneficial effects: The multi-channel chip test data parallel acquisition and intelligent analysis method and system provided by this invention offers significant advantages in several aspects compared to existing technologies. Firstly, regarding the synchronization accuracy of data acquisition, by employing a hardware trigger-based synchronization capture mechanism and configuring a high-precision global reference clock, this invention achieves precise synchronization of data acquisition across channels at the hardware level, controlling the time synchronization error between channels to an extremely low range. This high-precision synchronization lays a solid foundation for subsequent accurate timing analysis, and is particularly suitable for testing high-speed interface chips and RF chips that are extremely sensitive to timing relationships.

[0017] Secondly, regarding data processing efficiency and reliability, this invention, through a parallel acquisition architecture and an efficient timestamp alignment algorithm, completely breaks through the speed bottleneck of traditional serial processing. It not only copes with the impact of high-speed data streams, ensuring data integrity and real-time performance, but also optimizes the utilization efficiency of computing resources through intelligent load management, making continuous testing with long-term, large-volume data possible, significantly improving test throughput and equipment utilization. Finally, the beneficial effects of this invention are particularly prominent in terms of the level of intelligence in data analysis. By introducing a machine learning model trained on historical data for correlation analysis and anomaly pattern recognition, this method overcomes the limitations of traditional fixed threshold methods. It can adaptively learn the complex feature boundaries between normal and abnormal data, exhibiting extremely high detection sensitivity and accuracy for various potential faults, including weak, rare, or complexly correlated anomaly patterns. This greatly reduces the false negative and false positive rates in testing, improves the level of intelligence and reliability of testing, and provides a more powerful and reliable tool for chip quality assessment and fault diagnosis. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the parallel acquisition and intelligent analysis method for multi-channel chip test data provided in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the system composition of the multi-channel chip test data parallel acquisition and intelligent analysis system provided in a specific embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments in this application, other similar embodiments obtained by those skilled in the art without creative effort should all fall within the scope of protection of this application. Furthermore, directional terms mentioned in the following embodiments, such as "up," "down," "left," and "right," are only for reference to the directions in the accompanying drawings; therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0020] The present invention will be further described below with reference to the accompanying drawings and preferred embodiments.

[0021] Please see Figure 1 This invention provides a method for parallel acquisition and intelligent analysis of multi-channel chip test data, comprising: S1. Simultaneously capture chip test data from multiple test channels.

[0022] It should be further explained that the specific implementation of parallel acquisition of chip test data from multiple test channels in step S1 is as follows: An FPGA-based parallel acquisition architecture is adopted, preferably using a Xilinx Ultra Scale+ series FPGA chip, configured with at least 16 independent acquisition channels, each equipped with a 14-bit resolution ADC converter with a maximum sampling rate of 1GS / s. In actual operation, the sampling rate is set to 500MS / s, the sampling depth is 1M points / channel, and the input impedance is set to 50Ω±1%. The reason for choosing a sampling rate of 500MS / s is based on the Nyquist sampling theorem, which can effectively capture signal components below 250MHz, meeting the testing requirements of most high-speed digital chips.

[0023] S2. Perform timestamp alignment processing on the test data of the multiple test channels.

[0024] It should be further explained that the timestamp alignment process in step S2 adopts a combination of hardware timestamp marking and software calibration, using a 100MHz high-precision temperature-compensated crystal oscillator (TCXO) as the global clock source, with a frequency stability better than ±1ppm.

[0025] S3. Use intelligent analysis models to perform correlation analysis and anomaly pattern identification on the timestamp-aligned test data.

[0026] It should be further explained that the intelligent analysis model in step S3 adopts a deep neural network architecture, with 256 nodes in the input layer, 3 hidden layers with 128, 64, and 32 nodes respectively in each layer, and 2 nodes in the output layer corresponding to normal and abnormal state classifications respectively. The effectiveness of this method lies in achieving true multi-channel parallel acquisition, improving the efficiency of traditional serial testing by at least 8 times. At the same time, it ensures the temporal accuracy of data analysis through precise timestamp alignment. The introduction of the intelligent analysis model improves the anomaly detection accuracy to over 99.5%.

[0027] Specifically, in step S1, the parallel capture adopts a synchronous capture mechanism based on hardware triggers.

[0028] It should be further explained that the hardware triggers utilize a digital trigger circuit implemented internally within the FPGA. Specifically, each channel has independently set trigger conditions, and the trigger level threshold is programmable within the range of 0.1V to 2V, in 10mV increments. A trigger threshold of 0.7V is preferred, chosen because this level effectively avoids the noise margin range of typical CMOS circuits (typically 0.3Vdd-0.7Vdd) while ensuring compatibility with both TTL and CMOS levels. The trigger delay is set to a fixed 100ns to compensate for signal propagation delay in the transmission line. Trigger jitter is controlled within ±20ps, achieved through differential signal transmission and impedance matching techniques. The hardware triggers are implemented using the IDELAYE2 primitive within the FPGA for precise delay control, with each delay step being 78ps. Delay levels 0-31 can be set via configuration registers.

[0029] Understandably, the above solution achieves sub-nanosecond triggering accuracy, reducing multi-channel synchronization error from the traditional microsecond level to the nanosecond level, and significantly improving the time consistency of data acquisition.

[0030] Specifically, the hardware trigger is configured to be event-driven in response to a test signal.

[0031] It should be further explained that the event-driven triggering configuration is a multi-condition composite triggering mode, supporting three basic modes: edge triggering, pulse width triggering, and timeout triggering. The sensitivity of edge triggering is set to 2mV / ns, meaning it triggers when the signal change rate exceeds this threshold. The pulse width triggering range is set to 10ns-10ms, with an accuracy of 1ns. The timeout triggering time window is adjustable from 1μs to 1s. The preferred configuration is rising edge triggering mode, with the trigger level set to 50% of the signal amplitude. This configuration is chosen because it accurately captures the midpoint of the signal, avoiding trigger point drift caused by different signal rise times. The event-driven debouncing time is set to 5ns, implemented using a digital filter. The filter's transfer function is: Here, H(z) represents the filter's transfer function, and z represents the complex variable of the Z-transform. The filter has a 3dB cutoff frequency of 35MHz, which can effectively suppress false triggering caused by high-frequency noise.

[0032] Understandably, the above solution improves the anti-interference capability of the triggering system, reducing the false trigger rate from the traditional 5% to below 0.1%.

[0033] Specifically, the event-driven triggering includes rising edge triggering, falling edge triggering, or level triggering.

[0034] It should be further explained that this invention specifically defines the implementation details of three trigger modes. The threshold voltage for rising edge triggering is set to V_{th_rise} = 0.3Vdd + 0.2V, where Vdd is the chip power supply voltage. The threshold voltage for falling edge triggering is set to V_{th_fall} = 0.4Vdd - 0.1V. The hold time for level triggering is set to at least 10ns to ensure signal stability. A hysteresis comparator is preferably used for trigger determination, with a hysteresis voltage set to 100mV. This value is chosen to effectively avoid multiple triggers caused by signal jitter near the threshold. The specific circuit is implemented using the HPIO module inside the FPGA, and the comparator response time is less than 1ns. Each trigger mode supports pre-trigger sampling, and the pre-sampling depth can be set to 256 points, 512 points, or 1024 points, preferably 512 points. This depth ensures that 512ns of signal information before triggering is captured (at a 1GS / s sampling rate).

[0035] Understandably, the above solution provides flexible trigger configuration, which can adapt to different types of test signal characteristics and improve the adaptability of the test.

[0036] Specifically, in step S2, the timestamp alignment process includes timestamping the data of each channel using a global reference clock.

[0037] It should be further explained that the timestamp alignment process of this invention is specifically implemented as follows: A Symmetricom OCXO oscillator is used as the global reference clock, with a frequency of 125MHz and a phase noise of -120dBc / Hz at a 100Hz offset. The timestamp counter uses a 64-bit width and a counting step of 8ns (corresponding to a 125MHz clock cycle). Timestamp marking for each data sample is completed internally within the FPGA using a dedicated timestamp marking unit, achieving a marking accuracy of ±200ps. Timestamp data and sampled data are synchronously transmitted via a 128-bit wide high-speed bus with a bus clock frequency of 250MHz, using DDR transmission mode. To calibrate the fixed delay differences between channels, an automatic delay calibration process is executed during system initialization: standard test pulses are injected into each channel, the transmission delay of each channel is measured, and the results are stored in a delay correction table, with a delay correction resolution of 50ps.

[0038] Understandably, the above solution controls the time synchronization error between multiple channels to within 200ps, which is more than 25 times better than the 5-10ns error of the traditional method.

[0039] Specifically, the timestamp alignment process also includes using an interpolation algorithm to correct the timestamps of non-uniformly sampled data.

[0040] It should be further explained that the interpolation algorithm is specifically implemented using piecewise cubic Hermite interpolation (PCHIP algorithm). The mathematical expression of the interpolation algorithm is: in, It is at point The interpolation result at a given point is composed of four terms, each consisting of a basis function multiplied by a known value (function value or derivative value). These terms together ensure that the interpolation polynomial is accurate within the interval [0, 1]. The function value and its derivative satisfy the matching condition. Indicates the points (independent variables) where interpolation needs to be calculated; and Represents the two endpoints of the interpolation interval, where ; The interval length is represented by the definition of ; and Indicates at the endpoint and The known function value at that location; and Indicates at the endpoint and The known derivative value (i.e., slope) at the given point; Indicates the sampling interval. and The first derivative estimate for the corresponding point is calculated using a weighted average method. The interpolation step size is set to 0.1 ns, chosen to achieve the optimal balance between computational complexity and accuracy. Non-oscillatory boundary conditions are used for boundary handling in the interpolation algorithm to ensure smooth signal edges. The interpolation process is implemented in parallel within the FPGA, with each channel having its own dedicated interpolation calculation unit, using the IEEE 754 single-precision floating-point format to ensure a computational accuracy of 10⁻⁶. -6 .

[0041] Understandably, the above solution further reduces the timestamp alignment error to less than 50ps, making it particularly suitable for precision measurement scenarios such as eye diagram testing of high-speed signals.

[0042] Specifically, the interpolation algorithm is linear interpolation or spline interpolation.

[0043] It should be further noted that this invention provides specific implementation schemes for two alternative interpolation algorithms. The calculation formula for the linear interpolation algorithm is as follows: Where x represents the target time point, y represents the interpolation result, x1 and x2 represent the timestamps of adjacent sampling points, and y1 and y2 represent the corresponding sample values. Spline interpolation uses the natural cubic spline algorithm, and the matrix-form calculation formula is as follows: in, Indicates the sampling interval. Represents the second derivative. This represents the difference quotient. The threshold condition for linear interpolation is that the signal rate of change is less than 100 mV / ns, while spline interpolation is used for fast signals with a rate of change greater than this threshold.

[0044] Understandably, the above scheme provides optimized interpolation schemes for different signal characteristics, optimizing the allocation of computing resources while ensuring accuracy.

[0045] Specifically, in step S3, the intelligent analysis model is a machine learning model, which is trained using historical test data.

[0046] It should be further noted that the intelligent analysis model of this invention specifically adopts a deep convolutional neural network (DCNN) architecture. The network structure includes: an input layer (256 nodes), convolutional layers (32 5×5 convolutional kernels), pooling layers (2×2 max pooling), fully connected layers (128 nodes), and an output layer (2 nodes). The training dataset contains 100,000 sets of historical test data, including 70,000 normal samples and 30,000 abnormal samples. The training parameters are set as follows: batch size 128, learning rate 0.001, using the Adam optimizer, β1=0.9, β2=0.999, ε=10. -8 The training cycle was 1000 generations, with the patience value for the early stopping strategy set to 50 generations. The loss function used was weighted cross-entropy loss, with normal samples having a weight of 1.0 and outliers having a weight of 2.0. This weight ratio was chosen because the number of outliers is relatively small, requiring increased weights to improve the ability to identify abnormal patterns. The model was trained on an NVIDIA Tesla V100 GPU, with a training time of approximately 8 hours.

[0047] Understandably, the above solution achieves an anomaly detection accuracy of up to 99.2%, which is a significant improvement compared to the 85% accuracy of the traditional threshold method.

[0048] Specifically, the machine learning model includes neural networks, support vector machines, or decision tree models.

[0049] It should be further explained that this invention provides specific implementation parameters for three machine learning models. The neural network model adopts a three-layer fully connected structure, with ReLU activation function in the hidden layers and Softmax in the output layer. The support vector machine uses the RBF kernel function, parameter γ=0.01, penalty factor C=1.0, and is trained using the SMO algorithm. The decision tree model has a maximum depth of 15, a minimum leaf node sample size of 50, and uses the Gini coefficient as the splitting criterion. Neural network models are preferred; neural networks are chosen when the number of training samples is greater than 10,000, support vector machines are chosen when the number of samples is between 1,000 and 10,000, and decision trees are chosen when the number of samples is less than 1,000. This selection strategy is based on the differences in adaptability of different algorithms to small and large samples. Each model implements online learning functionality, with a model update cycle set to 24 hours to ensure adaptability to time drift in the testing environment.

[0050] Understandably, the above solution provides optimized model selection options for different data scales, ensuring optimal recognition performance in various application scenarios.

[0051] Please see Figure 2 The present invention provides another embodiment, which provides a multi-channel chip test data parallel acquisition and intelligent analysis system, the multi-channel chip test data parallel acquisition and intelligent analysis system comprising: The data acquisition module 100 is configured to capture chip test data from multiple test channels in parallel. The timestamp alignment module 200 is configured to perform timestamp alignment processing on the test data of the multiple test channels; The intelligent analysis module 300 is configured to use an intelligent analysis model to perform correlation analysis and anomaly pattern recognition on the timestamp-aligned test data.

[0052] It should be further noted that the data acquisition module uses TI's ADC12DJ3200 analog-to-digital converter chip, supporting 16-channel parallel acquisition with a maximum sampling rate of 3.2GS / s per channel, and an actual operating configuration of 1GS / s. The timestamp alignment module is implemented using an Intel Arria 10 FPGA, equipped with a dedicated clock management circuit, and uses SIPHASE's ultra-low jitter clock chip with a jitter performance of 80fsRMS. The intelligent analysis module uses the NVIDIA Jetson AGX Xavier embedded AI computing platform, integrating a 512-core Volta GPU and an 8-core ARM64 CPU. The system bus uses a PCIe 4.0 x8 interface with a theoretical bandwidth of 15.754GB / s and an actual usable bandwidth of 12GB / s. The system power management adopts a multi-phase buck architecture, with a core voltage of 0.85V and an I / O voltage of 1.8V, and power supply noise controlled within 10mV. The cooling system adopts an active cooling design, with fan speed automatically adjusted according to temperature, and the temperature control point set at 65℃. The system chassis is a standard 19-inch rack mount with a height of 3U.

[0053] It is understood that this invention provides a complete hardware implementation scheme, with system power consumption controlled within 150W, supporting continuous testing for 72 hours, and achieving a mean time between failures (MTBF) of 100,000 hours.

[0054] In a preferred embodiment, this application also provides an electronic device, the electronic device comprising: The computer device includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, implement the method for parallel acquisition and intelligent analysis of multi-channel chip test data. The computer device can be broadly categorized as a server, terminal, or any other electronic device with the necessary computing and / or processing capabilities. In one embodiment, the computer device may include a processor, memory, network interface, communication interface, etc., connected via a system bus. The processor of the computer device can be used to provide the necessary computing, processing, and / or control capabilities. The memory of the computer device may include a non-volatile storage medium and internal memory. The non-volatile storage medium may store an operating system, computer programs, etc. The internal memory can provide an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface and communication interface of the computer device can be used to connect and communicate with external devices via a network. When the computer program is executed by the processor, it performs the steps of the method of the present invention.

[0055] This invention can be implemented as a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the steps of the methods of embodiments of the invention to be performed. In one embodiment, the computer program is distributed across multiple network-coupled computer devices or processors, such that the computer program is stored, accessed, and executed in a distributed manner by one or more computer devices or processors. A single method step / operation, or two or more method steps / operations, may be executed by a single computer device or processor or by two or more computer devices or processors. One or more method steps / operations may be executed by one or more computer devices or processors, and one or more other method steps / operations may be executed by one or more other computer devices or processors. One or more computer devices or processors may execute a single method step / operation, or execute two or more method steps / operations.

[0056] Those skilled in the art will understand that the method steps of this invention can be performed by a computer program instructing related hardware, such as a computer device or processor, to perform the steps of this invention when executed. Depending on the context, any references herein to memory, storage, databases, or other media may include non-volatile and / or volatile memory. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, etc. Examples of volatile memory include random access memory (RAM), external cache memory, etc.

[0057] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.

[0058] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A multi-channel chip test data parallel acquisition and intelligent analysis method, characterized in that, The method comprises the following steps: S1, capturing chip test data of multiple test channels in parallel; S2, performing timestamp alignment processing on the test data of the multiple test channels; S3, performing correlation analysis and abnormal pattern recognition on the timestamp-aligned test data by using an intelligent analysis model.

2. The method of claim 1, wherein, In step S1, the parallel capturing adopts a synchronous capturing mechanism based on a hardware trigger.

3. The method of claim 2, wherein, The hardware trigger is configured to be triggered by an event of a test signal.

4. The method of claim 3, wherein, The event-driven trigger includes a rising edge trigger, a falling edge trigger, or a level trigger.

5. The method of claim 1, wherein, In step S2, the timestamp alignment processing includes timestamping each channel data by using a global reference clock.

6. The method of claim 5, wherein, The timestamp alignment processing further includes correcting non-uniformly sampled data by using an interpolation algorithm.

7. The method of claim 6, wherein, The interpolation algorithm is linear interpolation or spline interpolation.

8. The method of claim 1, wherein, In step S3, the intelligent analysis model is a machine learning model trained by historical test data.

9. The method of claim 8, wherein, The machine learning model includes a neural network, a support vector machine, or a decision tree model.

10. A multi-channel chip test data parallel acquisition and intelligent analysis system, characterized in that, The method for parallel collection and intelligent analysis of multi-channel chip test data according to any one of claims 1-9 comprises: a data collection module configured to capture chip test data of multiple test channels in parallel; a timestamp alignment module configured to perform timestamp alignment processing on the test data of the multiple test channels; an intelligent analysis module configured to perform correlation analysis and abnormal pattern recognition on the timestamp-aligned test data by using an intelligent analysis model.

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