An optical module splitting mode configuration method and an electronic device

Abstract

The application discloses a light module split mode configuration method and electronic equipment, and relates to the technical field of network communication. The method introduces an acceleration module between a processor and a light module, and constructs a cooperative architecture with separated high-speed and low-speed buses. In the configuration process, the acceleration module is responsible for tasks such as reading of light module information related to the low-speed bus, mode verification, parallel configuration and state monitoring, and the processor only issues instructions and receives results through the high-speed bus without participating in time-consuming polling. The scheme completely decouples the processor from low-speed serial operation, significantly releases computing resources, and greatly improves the efficiency of light module split configuration and the overall response speed of the system through parallel processing of the acceleration module.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and in particular to a method for configuring optical module splitting modes and an electronic device. Background Technology

[0002] White-box switches are flexible and open network devices that support software and hardware decoupling, allowing users to deploy different applications and services on the same hardware according to their needs, thereby reducing costs and improving deployment flexibility. Optical modules are core components that realize photoelectric and electro-optical conversion, responsible for transmitting data between the switch and optical fiber, and are an important part of data center networks. To adapt to different network topologies and bandwidth requirements, the physical ports of a switch (such as 400G) need to be split into multiple logical channels (such as 4×100G, 2×200G). In this case, the optical modules also need to be configured accordingly to match the changes in port signal channels. A common method for configuring optical module split modes is to obtain the required port split mode from the switching chip through the network operating system running on the central processing unit, then obtain the split modes supported by the optical modules through the low-speed bus, confirm that the optical modules support the required split modes, and finally configure the required split modes for all optical modules sequentially through the low-speed bus. The configuration process for optical module splitting mode conforms to the standard definition in the CMIS (Common Management Interface Specification, a communication protocol for managing and monitoring optical modules) document. It requires multiple acquisitions of the optical module's operating status via a low-speed bus to ensure successful splitting configuration. This configuration process is complex, and the central processing unit (CPU) frequently waits during configuration, resulting in low efficiency. Optical modules that fail to configure splitting mode are retried. However, if the configuration still fails after retrying, an error message is displayed in the system. The lack of an effective error handling mechanism makes it difficult to detect and handle configuration failures in real time, impacting system reliability and port availability. Summary of the Invention

[0003] This application provides a method for configuring optical module splitting mode and an electronic device to at least solve the problems of low configuration efficiency and lack of effective real-time anomaly handling mechanism in related technologies.

[0004] This application provides a method for configuring optical module splitting modes, applied to an acceleration module of a switch. The acceleration module is connected to the switch's processor via a high-speed communication bus and to multiple optical modules of the switch via a low-speed communication bus. The optical module splitting mode configuration method includes: in response to a configuration trigger event, determining a target optical module and a target mode code; reading a first register in the target optical module to obtain multiple mode codes supported by the target optical module, and writing the multiple mode codes into a first buffer of the acceleration module; in response to receiving a code reading request, obtaining a first decision instruction generated by the processor based on the target mode code and the multiple mode codes; in response to the first decision instruction instructing splitting, reading a second register in the target optical module to obtain the current mode code, and comparing the target mode code with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing configuration, writing the target mode code into a second buffer of the acceleration module, and performing a configuration operation on the target optical module according to the target mode code to obtain a mode configuration result; updating the mode configuration result to a third buffer of the acceleration module, and feeding back a corresponding configuration status signal to the processor according to the mode configuration result.

[0005] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement at least the following steps of an optical module splitting mode configuration method: in response to a configuration trigger event, determining a target optical module and a target mode code; reading a first register in the target optical module to obtain multiple mode codes supported by the target optical module, and writing the multiple mode codes into a first buffer of an acceleration module; in response to receiving a code reading request, obtaining a first decision instruction generated by the processor based on the target mode code and the multiple mode codes; in response to the first decision instruction instructing splitting to be performed, reading a second register in the target optical module to obtain a current mode code, and comparing the target mode code with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing configuration to be performed, writing the target mode code into a second buffer of the acceleration module, and performing a configuration operation on the target optical module according to the target mode code to obtain a mode configuration result; updating the mode configuration result to a third buffer of the acceleration module, and feeding back a corresponding configuration status signal to the processor according to the mode configuration result.

[0006] This application introduces an acceleration module located between the processor and the optical module, constructing a collaborative architecture that separates high-speed and low-speed buses. During configuration, the acceleration module is responsible for all tasks related to the low-speed bus, including reading optical module information, mode verification, parallel configuration, and status monitoring. The processor only issues instructions and receives results via the high-speed bus, without participating in time-consuming polling. This solution completely decouples the processor from low-speed serial operations, significantly freeing up computing resources. Simultaneously, the parallel processing of the acceleration module greatly improves the efficiency of optical module splitting and configuration, as well as the overall system response speed. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a flowchart illustrating the optical module splitting mode configuration method in the first embodiment;

[0009] Figure 2 This is a schematic diagram showing the connection of the acceleration module, processor, and multiple optical modules in the switch in the first embodiment;

[0010] Figure 3 This is a diagram of the internal structure of the electronic device in the second embodiment. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0012] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] In the first embodiment, such as Figure 1 , Figure 2 As shown, a method for configuring optical module splitting modes is provided, applied to an acceleration module of a switch. The acceleration module is connected to the switch's processor via a high-speed communication bus and to multiple optical modules of the switch via a low-speed communication bus. The optical module splitting mode configuration method includes: in response to a configuration trigger event, determining a target optical module and a target mode code; reading a first register in the target optical module to obtain multiple mode codes supported by the target optical module, and writing the multiple mode codes into a first buffer of the acceleration module; in response to receiving a code reading request, obtaining a first decision instruction generated by the processor based on the target mode code and the multiple mode codes; in response to the first decision instruction instructing splitting, reading a second register in the target optical module to obtain the current mode code, and comparing the target mode code with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing configuration, writing the target mode code into a second buffer of the acceleration module, and performing a configuration operation on the target optical module according to the target mode code to obtain a mode configuration result; updating the mode configuration result to a third buffer of the acceleration module, and feeding back a corresponding configuration status signal to the processor according to the mode configuration result.

[0015] Specifically, by separating high-speed / low-speed buses and unloading acceleration modules, the processor is freed from low-speed serial configuration, significantly improving the overall system configuration efficiency and processor resource utilization.

[0016] In a specific embodiment, the acceleration module can be an FPGA (Field Programmable Gate Array). The white-box switch network operating system on the processor can operate the FPGA through the memory space mapped by the high-speed bus. Simultaneously, the FPGA can also report interrupts to the processor via the PCIe (Peripheral Component Interconnect Express) bus. Since the optical modules communicate with the FPGA through their respective low-speed buses, the FPGA can configure all optical modules in parallel. If configuration fails, the FPGA first attempts to retry. If configuration still fails after retrying, it reports an interrupt to the processor, prompting the optical module splitting management program to handle it immediately, and reports the reason for the failure to the processor through the FPGA's third buffer. The optical module splitting management program needs to obtain the target splitting mode through a switching chip or other means after startup, and after confirming that the target splitting mode belongs to multiple splitting modes supported by the target optical module, it issues the first decision instruction to the FPGA.

[0017] In a specific embodiment, during FPGA operation, three configuration registers are opened to each optical module of the processor via the PCIe bus: Register 1 is used to indicate the splitting modes supported by this optical module, displaying splitting modes in formats such as 4X100G, 1X400G, and 2X200G; Register 2 is used to display the current splitting mode, with the same display format as Register 1; Register 3 is used to indicate whether the optical module has completed splitting, with the following format: 0 indicates that splitting is complete and successful; 1 indicates that splitting is in progress; negative numbers indicate splitting failure, -1 indicates that the error is that the optical module does not support the target splitting mode; -2 indicates that the error is that the register read / write instruction sequence of the optical module failed to execute; -3 indicates that the error is that a communication error occurred during the execution of the register read / write instruction sequence, etc.

[0018] Furthermore, the configuration trigger events are optical module access events and mode configuration instruction events. In response to the configuration trigger events, the target optical module and target mode code are determined, including: in response to detecting an optical module access signal, determining the target physical port identifier of the access action based on the optical module access signal; determining the optical module corresponding to the target physical port identifier as the target optical module based on the pre-stored mapping relationship between multiple physical port identifiers and multiple optical modules, wherein multiple physical port identifiers correspond one-to-one with multiple optical modules; and in response to the mode configuration instruction from the processor for the target physical port identifier, determining the target mode code based on the mode configuration instruction.

[0019] Specifically, it enables automatic identification and target determination in scenarios involving hot-swapping of optical modules, simplifies manual intervention, and improves the degree of deployment automation and port readiness speed.

[0020] Further configuring the trigger events as port configuration instruction events and mode configuration instruction events, in response to the configuration trigger events, determining the target optical module and the target mode code, also includes: in response to the port configuration instruction from the processor, determining the target physical port identifier according to the port configuration instruction; detecting whether there is an optical module in place on the physical port corresponding to the target physical port identifier; in response to detecting that there is an optical module in place, determining the optical module corresponding to the target physical port identifier as the target optical module according to the pre-stored mapping relationship between multiple physical port identifiers and multiple optical modules, wherein multiple physical port identifiers correspond one-to-one with multiple optical modules; in response to the mode configuration instruction from the processor for the target physical port identifier, determining the target mode code according to the mode configuration instruction.

[0021] Specifically, in scenarios where configuration is triggered by software, presence detection is added to avoid issuing invalid commands to empty ports, thereby improving operational accuracy and system robustness.

[0022] Further, obtaining the first decision instruction generated by the processor based on the target mode code and multiple mode codes includes: obtaining the first decision instruction returned by the processor, wherein the indication content of the first decision instruction depends on whether the target mode code belongs to multiple mode codes; in response to the target mode code belonging to multiple mode codes, obtaining the first decision instruction indicating to perform splitting; in response to the target mode code not belonging to multiple mode codes, obtaining the first decision instruction indicating to interrupt splitting; after obtaining the first decision instruction indicating to interrupt splitting, the optical module splitting mode configuration method further includes: in response to the first decision instruction indicating to interrupt splitting, writing a preset first abnormal state value into the third buffer and feeding back a configuration failure signal to the processor.

[0023] Specifically, pattern support validation is performed early in the configuration process to quickly identify and terminate mismatched configuration requests, avoid invalid operations, and improve system response efficiency.

[0024] In a specific embodiment, the optical module splitting management program checks whether the optical module supports the target splitting mode. If it does not, it prompts the user that this port cannot be matched for splitting and the optical module needs to be replaced. Since the processor reads and writes high-speed bus registers very quickly, the FPGA's optical module configuration process does not require the processor's participation after the target splitting mode is issued. Therefore, the optical module splitting management program on the processor can run as a single process. After the optical module splitting management program completes the splitting of all optical modules, it enters the monitoring mode.

[0025] Further, the target pattern code is compared with the current pattern code to generate a second decision instruction, including: comparing the target pattern code with the current pattern code; in response to the target pattern code being consistent with the current pattern code, generating a second decision instruction indicating that no configuration is required; in response to the target pattern code being inconsistent with the current pattern code, generating a second decision instruction indicating that the configuration is executed.

[0026] Specifically, by comparing the current mode with the target mode, redundant configuration of optical modules that are already in the target state is avoided, saving processing resources and time.

[0027] Further, configuration operations are performed on the target optical module according to the target mode code to obtain the mode configuration result, including: determining the corresponding target split mode according to the target mode code; generating and executing a register read / write instruction sequence according to the preset optical module general management interface specification and the target split mode, wherein the register read / write instruction sequence includes at least an operation instruction to write the target mode code into the second register; monitoring the execution process of the register read / write instruction sequence; in response to the failure of the register read / write instruction sequence execution, or a communication error occurring during execution, determining that the configuration operation has failed, and setting the mode configuration result to a preset abnormal state value, wherein the preset abnormal state value is... The status value is used to indicate configuration failure, and the preset abnormal status value includes at least the first abnormal status value; in response to the successful execution of the register read / write instruction sequence and the absence of communication errors, it is determined whether the target optical module has been stably operating in the target split mode; in response to the target optical module being stably operating in the target split mode, the configuration operation is determined to have been successfully executed, and the mode configuration result is set to the preset success status value, wherein the preset success status value is used to indicate configuration success; in response to the target optical module not being stably operating in the target split mode, the configuration operation is determined to be in progress, and the mode configuration result is set to the preset progress status value, wherein the preset progress status value is used to indicate configuration in progress.

[0028] Specifically, complex configuration operations are standardized and serialized, and the three states of success, in progress, and failure are clearly defined, making the configuration process controllable, monitorable, and the results clear.

[0029] Further, based on the target mode encoding, the corresponding target splitting mode is determined, including: in response to the target mode encoding being a first type of mode encoding, the target splitting mode is determined to be a full-port bandwidth multiplexing mode, wherein the full-port bandwidth multiplexing mode indicates that the aggregated bandwidth of the target optical module is used as a single logical channel; in response to the target mode encoding being a second type of mode encoding, the target splitting mode is determined to be a uniform channel splitting mode, wherein the uniform channel splitting mode indicates that the aggregated bandwidth of the target optical module is equally divided into multiple logical channels with the same rate and independent of each other, and the multiple logical channels with the same rate and independent of each other correspond one-to-one with multiple physical ports on the switch; in response to the target mode encoding being a third type of mode encoding, the target splitting mode is determined to be a non-uniform channel splitting mode, wherein the non-uniform channel splitting mode indicates that the aggregated bandwidth of the target optical module is divided into multiple logical channels with different rates and independent of each other, and the sum of the rates of the multiple logical channels with different rates and independent of each other is equal to the nominal aggregated bandwidth of the target optical module.

[0030] Specifically, specific rate combinations are abstracted into three functional modes, making the solution independent of specific rate values ​​and improving the foresight of the technology and the universality of the protection scope.

[0031] Furthermore, based on the mode configuration result, the corresponding configuration status signal is fed back to the processor, including: in response to the mode configuration result being a preset success status value, generating a configuration success signal based on the preset success status value and sending the configuration success signal to the processor; in response to the mode configuration result being a preset progress status value, generating a configuration progress signal based on the preset progress status value and sending the configuration progress signal to the processor; in response to the mode configuration result being a preset abnormal status value, generating a configuration failure signal based on the preset abnormal status value and sending the configuration failure signal to the processor.

[0032] Specifically, a direct mapping is established from configuration results to status signals, providing a unified and clear status feedback interface for upper-level processors and simplifying system management logic.

[0033] Furthermore, the preset abnormal state value also includes at least a second abnormal state value and a third abnormal state value. Generating a configuration failure signal based on the preset abnormal state value and sending the configuration failure signal to the processor includes: in response to the preset abnormal state value being the first abnormal state value, generating a first-type configuration failure signal indicating that the target optical module does not support the target splitting mode, and sending the first-type configuration failure signal to the processor; in response to the preset abnormal state value being the second abnormal state value, generating a second-type configuration failure signal indicating that the register read / write instruction sequence failed to execute, and sending the second-type configuration failure signal to the processor; and in response to the preset abnormal state value being the third abnormal state value, generating a third-type configuration failure signal indicating that a communication error occurred during execution, and sending the third-type configuration failure signal to the processor.

[0034] Specifically, configuration failures are finely categorized and reported differently, enabling the processor to accurately pinpoint the root cause of the fault (mode, execution, communication), laying the foundation for intelligent processing.

[0035] Furthermore, in the processor applied to the switch, after the configuration failure signal is sent to the processor, the optical module split mode configuration method further includes: in response to receiving the first type of configuration failure signal, executing a first post-processing strategy, wherein the first post-processing strategy includes: marking the logical port corresponding to the target physical port identifier as unavailable; generating a user alarm log indicating that the target optical module does not match the target split mode; issuing a data clearing command to the acceleration module to clear the cached data in the first buffer, the second buffer, and the third buffer; in response to receiving the second type of configuration failure signal, executing a second post-processing strategy, wherein the second post-processing strategy includes: within a preset time interval, re-issuing the configuration trigger event for the target optical module and the target mode encoding to the acceleration module to trigger the retry configuration process; and recording the number of retries. If a configuration success signal is received before the preset maximum number of retries is reached, the process ends. If a second type of configuration failure signal is received after the preset maximum number of retries is reached, a system-level critical alarm indicating a potential hardware link or module failure is generated, and maintenance personnel are notified to conduct on-site hardware testing. In response to receiving a third type of configuration failure signal, a third post-processing strategy is executed, which includes: notifying the acceleration module to suspend subsequent configuration operations on the target optical module; establishing a direct link through the bus control logic, bypassing the acceleration module, and performing in-depth diagnosis on the target optical module; and, based on the diagnosis results, deciding to perform one of the following operations: generating a configuration instruction containing correction parameters and triggering a new round of configuration process, marking the target optical module as an abnormal device requiring firmware upgrade, and permanently disabling the target physical port.

[0036] Specifically, differentiated post-processing strategies (such as disabling, retrying, and diagnosis) are automatically executed for different failure types to achieve fault self-healing and degradation processing, greatly improving system reliability and maintainability.

[0037] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0038] In a second embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it performs the following steps: in response to a configuration trigger event, it determines a target optical module and a target mode code; reads a first register in the target optical module to obtain multiple mode codes supported by the target optical module, and writes the multiple mode codes into a first buffer of an acceleration module; in response to receiving a code reading request, it obtains a first decision instruction generated by the processor based on the target mode code and the multiple mode codes; in response to the first decision instruction instructing a split to be performed, it reads a second register in the target optical module to obtain the current mode code, and compares the target mode code with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing a configuration to be performed, it writes the target mode code into a second buffer of the acceleration module, performs a configuration operation on the target optical module according to the target mode code, and obtains a mode configuration result; updates the mode configuration result to a third buffer of the acceleration module, and feeds back a corresponding configuration status signal to the processor according to the mode configuration result.

[0039] When the program instructions are read and executed by one or more processors, they can also perform operations corresponding to the steps in the above method embodiments, as described above, and will not be repeated here. Reference Figure 3 This example illustrates the architecture of an electronic device, which may include a processor 310, a video display adapter 311, a disk drive 312, an input / output interface 313, a network interface 314, and a memory 320. The processor 310, video display adapter 311, disk drive 312, input / output interface 313, network interface 314, and memory 320 can communicate with each other via a communication bus 330.

[0040] The processor 310 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to achieve the technical solution provided in this application.

[0041] The memory 320 can be implemented as a read-only memory (ROM), random access memory (RAM), static storage device, dynamic storage device, etc. The memory 320 can store an operating system 321 for controlling the operation of the electronic device 300, and a basic input / output system (BIOS) 322 for controlling the low-level operations of the electronic device 300. Additionally, it can store a web browser 323, data storage management 324, and an icon / font processing system 325. The icon / font processing system 325 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when implementing the technical solution provided in this application through software or firmware, the relevant program code is stored in the memory 320 and executed by the processor 310.

[0042] Input / output interface 313 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0043] Network interface 314 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0044] Bus 330 includes a pathway for transmitting information between various components of the device, such as processor 310, video display adapter 311, disk drive 312, input / output interface 313, network interface 314, and memory 320.

[0045] In addition, the electronic device 300 can also obtain information on specific acquisition conditions from the virtual resource object acquisition condition information database (not shown in the figure) for condition judgment.

[0046] It should be noted that although the above-described electronic device 300 only shows a processor 310, a video display adapter 311, a disk drive 312, an input / output interface 313, a network interface 314, a memory 320, and a bus 330, in specific implementations, the electronic device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0047] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause an electronic device (which may be a personal computer, cloud server, or network device, etc.) to execute the methods of various embodiments or some parts of the embodiments of this application.

[0048] In a third embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: in response to a configuration trigger event, a target optical module and a target mode code are determined; a first register in the target optical module is read to obtain multiple mode codes supported by the target optical module, and the multiple mode codes are written into a first buffer of an acceleration module; in response to receiving a code reading request, a first decision instruction generated by the processor based on the target mode code and the multiple mode codes is obtained; in response to the first decision instruction instructing splitting, a second register in the target optical module is read to obtain the current mode code, and the target mode code is compared with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing configuration, the target mode code is written into a second buffer of the acceleration module, and a configuration operation is performed on the target optical module according to the target mode code to obtain a mode configuration result; the mode configuration result is updated to a third buffer of the acceleration module, and a corresponding configuration status signal is fed back to the processor according to the mode configuration result.

[0049] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are quite specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

[0052] In a fourth embodiment, a computer program product is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: in response to a configuration trigger event, a target optical module and a target mode code are determined; a first register in the target optical module is read to obtain multiple mode codes supported by the target optical module, and the multiple mode codes are written into a first buffer of an acceleration module; in response to receiving a code reading request, a first decision instruction generated by the processor based on the target mode code and the multiple mode codes is obtained; in response to the first decision instruction instructing splitting to be performed, a second register in the target optical module is read to obtain the current mode code, and the target mode code is compared with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing configuration to be performed, the target mode code is written into a second buffer of the acceleration module, and a configuration operation is performed on the target optical module according to the target mode code to obtain a mode configuration result; the mode configuration result is updated to a third buffer of the acceleration module, and a corresponding configuration status signal is fed back to the processor according to the mode configuration result.

[0053] In a fourth embodiment, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it performs the following steps: in response to a configuration trigger event, determining a target optical module and a target mode code; reading a first register in the target optical module to obtain multiple mode codes supported by the target optical module, and writing the multiple mode codes into a first buffer of an acceleration module; in response to receiving a code reading request, obtaining a first decision instruction generated by the processor based on the target mode code and the multiple mode codes; in response to the first decision instruction instructing splitting, reading a second register in the target optical module to obtain the current mode code, and comparing the target mode code with the current mode code to generate a second decision instruction; in response to the second decision instruction instructing configuration, writing the target mode code into a second buffer of the acceleration module, and performing a configuration operation on the target optical module according to the target mode code to obtain a mode configuration result; updating the mode configuration result to a third buffer of the acceleration module, and feeding back a corresponding configuration status signal to the processor according to the mode configuration result.

[0054] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer program product, and when the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0055] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are quite specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A method for configuring optical module splitting modes, applied to the acceleration module of a switch, characterized in that, The acceleration module is connected to the processor of the switch via a high-speed communication bus and to multiple optical modules of the switch via a low-speed communication bus. The method includes: In response to a configuration trigger event, the target optical module and target mode code are determined; The first register in the target optical module is read to obtain multiple mode codes supported by the target optical module, and the multiple mode codes are written into the first buffer of the acceleration module; In response to receiving an encoding read request, the processor obtains a first decision instruction generated based on the target mode encoding and the plurality of mode encodings; In response to the first decision instruction instructing the splitting to be performed, the second register in the target optical module is read to obtain the current mode code, and the target mode code is compared with the current mode code to generate a second decision instruction; In response to the second decision instruction to perform configuration, the target mode code is written into the second buffer of the acceleration module, and a configuration operation is performed on the target optical module according to the target mode code to obtain the mode configuration result; The mode configuration result is updated to the third cache of the acceleration module, and the corresponding configuration status signal is fed back to the processor according to the mode configuration result.

2. The method according to claim 1, characterized in that, The configuration triggering event is an optical module access event and a mode configuration command event. The step of determining the target optical module and target mode code in response to the configuration triggering event includes: In response to the detection of an optical module access signal, the target physical port identifier of the access action is determined based on the optical module access signal; Based on the pre-stored mapping relationship between multiple physical port identifiers and multiple optical modules, the optical module corresponding to the target physical port identifier is determined as the target optical module, wherein the multiple physical port identifiers correspond one-to-one with the multiple optical modules; In response to a mode configuration instruction from the processor for the target physical port identifier, the target mode code is determined according to the mode configuration instruction.

3. The method according to claim 1, characterized in that, The configuration trigger event is a port configuration command event and a mode configuration command event. The step of determining the target optical module and target mode encoding in response to the configuration trigger event further includes: In response to a port configuration instruction from the processor, the target physical port identifier is determined according to the port configuration instruction; Detect whether an optical module is present on the physical port corresponding to the target physical port identifier; In response to the detection of an optical module in place, the optical module corresponding to the target physical port identifier is determined as the target optical module according to the pre-stored mapping relationship between multiple physical port identifiers and multiple optical modules, wherein the multiple physical port identifiers correspond one-to-one with the multiple optical modules; In response to a mode configuration instruction from the processor for the target physical port identifier, the target mode code is determined according to the mode configuration instruction.

4. The method according to claim 1, characterized in that, The step of obtaining the first decision instruction generated by the processor based on the target pattern encoding and the plurality of pattern encodings includes: Obtain the first decision instruction returned by the processor, wherein the content of the first decision instruction depends on whether the target pattern code belongs to the plurality of pattern codes; In response to the target pattern encoding belonging to the plurality of pattern codes, a first decision instruction indicating the execution of splitting is obtained; In response to the fact that the target pattern code does not belong to the plurality of pattern codes, the first decision instruction indicating interruption of splitting is obtained; After obtaining the first decision instruction indicating the interruption split, the method further includes: In response to the first decision instruction indicating an interrupt split, a preset first abnormal state value is written to the third cache, and a configuration failure signal is fed back to the processor.

5. The method according to claim 1, characterized in that, The step of comparing the target pattern code with the current pattern code to generate a second decision instruction includes: The target pattern code is compared with the current pattern code; In response to the target pattern code being consistent with the current pattern code, a second decision instruction indicating that no configuration is required is generated; In response to the discrepancy between the target mode encoding and the current mode encoding, a second decision instruction is generated to instruct the execution of the configuration.

6. The method according to claim 4, characterized in that, The step of performing a configuration operation on the target optical module according to the target mode encoding to obtain a mode configuration result includes: Based on the target pattern encoding, the corresponding target splitting pattern is determined; According to the preset optical module general management interface specification and the target splitting mode, a register read and write instruction sequence is generated and executed, wherein the register read and write instruction sequence includes at least an operation instruction to write the target mode encoding into the second register; Monitor the execution process of the register read / write instruction sequence; In response to the failure of the register read / write instruction sequence or the occurrence of a communication error during execution, it is determined that the configuration operation has failed, and the mode configuration result is set to a preset abnormal state value, wherein the preset abnormal state value is used to indicate configuration failure, and the preset abnormal state value includes at least the first abnormal state value. In response to the successful execution of the register read / write instruction sequence without communication errors, it is determined whether the target optical module has been stably operating in the target split mode; In response to the fact that the target optical module has been stably running in the target split mode, it is determined that the configuration operation has been successfully executed, and the mode configuration result is set to a preset success status value, wherein the preset success status value is used to indicate that the configuration is successful; In response to the target optical module not operating stably in the target split mode, it is determined that the configuration operation is in progress, and the mode configuration result is set to a preset progress state value, wherein the preset progress state value is used to indicate that the configuration is in progress.

7. The method according to claim 6, characterized in that, The step of determining the corresponding target splitting pattern based on the target pattern encoding includes: In response to the target mode encoding being a first type of mode encoding, the target splitting mode is determined to be a full-port bandwidth multiplexing mode, wherein the full-port bandwidth multiplexing mode indicates that the aggregated bandwidth of the target optical module is used as a single logical channel; In response to the target mode encoding being a second type of mode encoding, the target splitting mode is determined to be a uniform channel splitting mode, wherein the uniform channel splitting mode means that the aggregate bandwidth of the target optical module is equally divided into multiple logical channels with the same rate and independent of each other, and the multiple logical channels with the same rate and independent of each other correspond one-to-one with multiple physical ports on the switch. In response to the target mode encoding being a third type of mode encoding, the target splitting mode is determined to be a non-uniform channel splitting mode, wherein the non-uniform channel splitting mode means that the aggregate bandwidth of the target optical module is divided into multiple logical channels with different rates and independent of each other, and the sum of the rates of the multiple logical channels with different rates and independent of each other is equal to the nominal aggregate bandwidth of the target optical module.

8. The method according to claim 6, characterized in that, The step of feeding back a corresponding configuration status signal to the processor based on the mode configuration result includes: In response to the mode configuration result being the preset success status value, a configuration success signal is generated based on the preset success status value, and the configuration success signal is sent to the processor; In response to the mode configuration result being the preset progress status value, a configuration progress signal is generated based on the preset progress status value, and the configuration progress signal is sent to the processor; In response to the mode configuration result being the preset abnormal state value, a configuration failure signal is generated based on the preset abnormal state value, and the configuration failure signal is sent to the processor.

9. The method according to claim 8, characterized in that, The preset abnormal state value further includes at least a second abnormal state value and a third abnormal state value. The step of generating a configuration failure signal based on the preset abnormal state value and sending the configuration failure signal to the processor includes: In response to the preset abnormal state value being the first abnormal state value, a first type of configuration failure signal indicating that the target optical module does not support the target splitting mode is generated, and the first type of configuration failure signal is sent to the processor; In response to the preset abnormal state value being the second abnormal state value, a second type of configuration failure signal indicating that the register read / write instruction sequence has failed is generated and sent to the processor; In response to the preset abnormal state value being the third abnormal state value, a third type of configuration failure signal indicating a communication error has occurred during execution is generated, and the third type of configuration failure signal is sent to the processor.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the optical module split mode configuration method as described in any one of claims 1 to 9 when executing the computer program.

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