Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a glass layer having a through hole; the insulating material is arranged in the through hole and is provided with a through hole; and a metal via hole disposed in the via hole. The metal via includes a first metal layer disposed substantially conformally on a wall surface of the via hole, a second metal layer disposed substantially conformally on the first metal layer, and a third metal layer disposed on the second metal layer and filling at least a portion of the via hole.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0117346, filed August 30, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a printed circuit board. BACKGROUND

[0003] Recently, high performance of a package substrate requires its large area, multi-layering, and miniaturization. In addition, a copper clad laminate (CCL) is generally used as a core substrate included in a package substrate, but in the case of a CCL, warpage is likely to occur due to low modulus and high coefficient of thermal expansion, and there is also a limitation in realizing a microcircuit. Therefore, there is a need for a core substrate including a new material such as glass, which has high modulus and low coefficient of thermal expansion to suppress warpage, and also has a smooth surface to facilitate realization of a microcircuit. However, in the case of a glass core, it can be difficult to secure adhesion in a process of forming a seed metal layer in a via hole. In addition, during a fill plating process, non-plating can occur in a central portion of the via hole, which can cause a via open defect. SUMMARY

[0004] An aspect of the disclosure is to provide a printed circuit board that can secure adhesion of a seed metal layer and can prevent non-plating from occurring during fill plating in a case where a via hole is formed in a glass layer such as a glass core and the via hole is filled with plating.

[0005] One of the various aspects proposed by the disclosure is to form a through hole in a glass layer such as a glass core, fill the through hole with an insulating material, form a via hole in the insulating material, and form a metal via including a plurality of seed layers in the via hole.

[0006] For example, a printed circuit board according to an example embodiment can include a glass layer having a through hole, a first insulating material disposed within the through hole and having a first via hole, and a first metal via disposed within the first via hole. The first metal via can include a first metal layer having at least a portion thereof disposed substantially conformally on a wall surface of the first via hole, a second metal layer having at least a portion thereof disposed substantially conformally on the first metal layer, and a third metal layer disposed on the second metal layer and filling at least a portion of the first via hole.

[0007] For example, a printed circuit board according to an example embodiment can include a core including a glass core having a via hole, an insulating material disposed within the via hole and having a through-hole, and a metal via disposed within the through-hole, and a build-up including an insulating body disposed on the core, one or more interconnection layers disposed on or within the insulating body, respectively, and one or more via layers disposed within the insulating body, respectively. The metal via can include a first metal layer at least a portion of which is conformally disposed on a wall surface of the through-hole, a second metal layer at least a portion of which is conformally disposed on the first metal layer, and a third metal layer disposed on the second metal layer and filling at least a portion of the through-hole.

[0008] For example, a printed circuit board according to an example embodiment can include a glass layer having a via hole, a first insulating material disposed within the via hole and having a first through-hole, and a first metal via disposed within the first through-hole. The first metal via can include a first metal layer at least a portion of which is substantially conformally disposed on a wall surface of the first through-hole, a second metal layer at least a portion of which is substantially conformally disposed on the first metal layer, and a third metal layer disposed on the second metal layer and filling at least a portion of the first through-hole, wherein a nano-gap is formed at a boundary between the second metal layer and the first metal layer.

[0009] One of various effects of the disclosure is to provide a printed circuit board that can secure adhesion of a seed metal layer and can prevent un-plating from occurring during filling plating in a case where a through-hole is formed in a glass layer such as a glass core and the through-hole is filled with plating. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a cross-sectional view schematically illustrating an example of a printed circuit board; Figures 3A to 3M is a cross-sectional view schematically illustrating various shapes of a via hole, a through-hole, and a metal via of a printed circuit board applicable to Figure 2 ; Figure 4 is a process diagram schematically illustrating an example of manufacturing a printed circuit board of Figure 2 ; Figure 5 is a process diagram schematically illustrating an example of manufacturing a printed circuit board of Figure 2is a cross-sectional view schematically illustrating a modification example of the printed circuit board of Figure 6 is a cross-sectional view schematically illustrating another example of the printed circuit board. Figure 7 is a process diagram schematically illustrating an example of manufacturing Figure 6 the printed circuit board. Figure 8 is a cross-sectional view schematically illustrating a modification example of the printed circuit board of Figure 6 Figure 9 is a cross-sectional view schematically illustrating another example of the printed circuit board. Figure 10 is a process diagram schematically illustrating an example of manufacturing Figure 9 the printed circuit board. Figure 11 is a cross-sectional view schematically illustrating a modification example of the printed circuit board of Figure 9 Figure 12 is a cross-sectional view schematically illustrating another example of the printed circuit board. Figure 13 is a process diagram schematically illustrating an example of manufacturing Figure 12 the printed circuit board. Figure 14 is a cross-sectional view schematically illustrating a modification example of the printed circuit board of Figure 12 DETAILED DESCRIPTION

[0011] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shape and size of elements can be exaggerated or reduced for more clear description.

[0012] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0013] Referring to Figure 1 , a main board 1010 is housed in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040, etc. are physically and / or electrically connected to the main board 1010. These components are also coupled to other electronic components to be described below through various signal lines 1090.

[0014] ​​​The chip-related components 1020 can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory), etc., application processor chips such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc., and logic chips such as analog-to-digital converters (ADCs), application specific ICs (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and can further include other types of chip-related components. Also, the chip-related components 1020 can be combined with each other. The chip-related components 1020 can have a form of a package including the above-described chips.

[0015] The network-related components 1030 can include components compatible with or operating according to protocols such as Wireless-Fidelity (Wi-Fi) (such as IEEE 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed Packet Access (+HSPA+), High Speed Downlink Packet Access (HSDPA+), High Speed Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) protocol, Fourth Generation Mobile Communication Technology (4G) protocol, and Fifth Generation Mobile Communication Technology (5G) protocol, and any other wireless standards or protocols and wired standards or protocols designated thereafter. However, the network-related components 1030 are not limited thereto, and can further include components compatible with or operating according to any of a plurality of other wireless or protocols and wired standards or protocols. Also, the network-related components 1030 can be combined to the chip-related components 1020.

[0016] The other components 1040 can include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, the other components are not limited thereto, and can further include passive components in the form of chip components for various other purposes. In addition, the other components 1040 can be combined with each other, with the chip-related components 1020, and / or with the network-related components 1030.

[0017] According to the type of the electronic device 1000, the electronic device 1000 can include other electronic components that are physically and / or electrically connected to the main board 1010 or are not physically and / or electrically connected to the main board 1010. These other electronic components can include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but can also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a large-capacity storage device (e.g., a hard disk drive), a compact disc (CD), a digital versatile disc (DVD), etc. In addition thereto, according to the type of the electronic device 1000, the electronic device 1000 can also include other electronic components for various purposes.

[0018] The electronic device 1000 can be a smart phone, a personal digital assistant, a digital camcorder, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smart watch, a car component, etc. However, the electronic device 1000 is not limited thereto, and can be any other electronic device capable of processing data.

[0019] Figure 2 is a cross-sectional view schematically showing an example of a printed circuit board.

[0020] Referring to Figure 2 The printed circuit board 100A can include a glass layer 110 having a via hole h, an insulating material 120 disposed within the via hole h and having a through-hole v, and a metal via 130 disposed within the through-hole v. The metal via 130 can include a first metal layer m1 having at least a portion thereof disposed substantially conformally on a wall surface of the through-hole v, a second metal layer m2 having at least a portion thereof disposed substantially conformally on the first metal layer m1, and a third metal layer m3 disposed on the second metal layer m2 and filling at least a portion of the through-hole v. The first metal layer m1 and the second metal layer m2 can be seed metal layers, and the third metal layer m3 can be a fill plating metal layer.

[0021] In this way, in the printed circuit board 100A, the via hole h that penetrates the region between the upper surface and the lower surface of the glass layer 110 can be formed in the glass layer 110, and after the via hole h is filled with the insulating material 120, the via hole v that penetrates the region between the upper surface and the lower surface of the insulating material 120 can be formed in the via hole h, and the metal via 130 including a plurality of seed metal layers (for example, the first metal layer m1 and the second metal layer m2) and a fill plating metal layer (for example, the third metal layer m3) can be formed in the via hole v. That is, the plurality of seed metal layers can be formed in the via hole v formed in the insulating material 120 instead of being formed in the glass layer 110, so that sufficient coverage can be ensured, and the adhesion problem of the seed metal layer can be effectively improved. In addition, since the fill plating metal layer can be formed after sufficient coverage is ensured, the via open problem due to the occurrence of non-plating can be effectively improved.

[0022] In addition, the insulating material 120 can include an organic insulating material. For example, the insulating material 120 can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including the above-described resin and an inorganic filler and / or an organic filler. For example, the insulating material 120 can be an ABF or the like, in which case the insulating material 120 can be more easily formed in the via hole h, and the via hole v can also be more easily processed in the insulating material 120, but the present disclosure is not limited thereto.

[0023] In addition, the seed metal layer can be formed by sputtering and electroless plating. For example, the first metal layer m1 can be formed by sputtering and can include, for example, a fill metal. In addition, the second metal layer m2 can be formed by electroless plating and can include, for example, electroless copper. In this case, adhesion can be ensured by the first metal layer m1, and coverage can be ensured by the second metal layer m2. For example, when the thickness of the glass layer 110 increases, there can be a region in which the first metal layer m1 is not formed on the wall surface in the central region of the via hole v, but even in this case, the second metal layer m2 can cover the region in which the first metal layer m1 is not formed on the wall surface of the via hole v, so that coverage can be ensured. The second metal layer m2 formed by electroless plating can be thicker than the first metal layer m1 formed by sputtering. The thickness of the first metal layer m1 and the second metal layer m2 can be confirmed in a cut cross section or a cut plane of the metal via 130, and when the thickness is not constant, the thickness can be confirmed as an average value at five arbitrary points.

[0024] In addition, the first metal layer m1 can include a plurality of sputter layers, and can include, for example, a first sputter layer connected to a wall surface of the via hole v and a second sputter layer connected to the second metal layer m2 (e.g., electroless copper plating). In order to improve the bonding strength with the insulating material 120, the first sputter layer can include titanium (Ti), and in order to improve the bonding strength with the second metal layer m2, the second sputter layer can include copper (Cu), but the present disclosure is not limited thereto. When the second sputter layer includes copper (Cu) and the second metal layer m2 includes electroless copper plating, a nano void can be formed at the boundary between the sputtered copper and the electroless copper plating, which can be confirmed by a high-resolution scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), a focused ion beam (FIB), etc. In addition, the shape and size of the grains can be confirmed and compared using the SEM, TEM, STEM, FIB, etc. to distinguish the grains. In addition, when analyzed using an energy dispersive X-ray spectrometer (EDX) or the like, nickel (Ni) can be concentrated in the electroless copper plating at a relatively high concentration, which can also be used to distinguish the grains. In addition, the third metal layer m3 (e.g., a filled plating metal layer) can be formed by electrolytic plating. For example, the third metal layer m3 can include electrolytic copper plating. Since the seed metal layer described above is formed on the wall surface of the via hole v, at least a portion of the via hole v can be easily filled with the third metal layer m3 without any special plating defects. For example, it is possible to prevent the occurrence of a via open defect such as un-plated in the central portion of the via hole v. In addition, the electroless copper plating and the electrolytic copper plating can be distinguished by confirming and comparing the shape and size of the grains using the SEM, TEM, STEM, FIB, etc. In addition, when analyzed using the EDX, nickel (Ni) is concentrated in the electroless copper plating at a relatively high concentration compared to the electrolytic copper plating, which can also be used to distinguish the grains.

[0025] It should be noted that, herein, as a non-limiting example, trace amounts of nickel (Ni) can be present in the sputtered copper, electroless copper plating, and electrolytic copper plating due to impurities or contamination during the process. For example, in the case of electroless copper plating, nickel (Ni) can be partially contained in the deposit due to the use of a Pd / Ni catalyst during surface activation. Therefore, the grains can be distinguished, and thus the different metal layers can be distinguished, by means of the concentration of nickel (Ni).

[0026] The printed circuit board 100A can further include a first metal pattern 132 connected to the upper side of the metal via 130 and a second metal pattern 134 connected to the lower side of the metal via 130. The first metal pattern 132 and the second metal pattern 134 can be a pad and / or a land of the metal via 130. If necessary, different metal patterns 136 and 138 can be further provided on the upper and lower surfaces of the glass layer 110, and the different metal patterns 136 and 138 can include a line pattern and a land pattern. The first metal pattern 132 and the second metal pattern 134 and the different metal patterns 136 and 138 can each include the first metal layer m1, the second metal layer m2, and the third metal layer m3 described above. For example, the first metal pattern 132 can include an extension portion of the first metal layer m1 extending substantially conformally to the upper surface of the insulating material 120 and the upper surface of the glass layer 110, an extension portion of the second metal layer m2 extending substantially conformally to the upper surface of the insulating material 120 and the upper surface of the glass layer 110 onto the first metal layer m1, and an extension portion of the third metal layer m3 extending onto the second metal layer m2 from the upper surface of the insulating material 120 and the upper surface of the glass layer 110 and protruding to the upper side of the via hole v. Further, the second metal pattern 134 can include an extension portion of the first metal layer m1 extending substantially conformally to the lower surface of the insulating material 120 and the lower surface of the glass layer 110, an extension portion of the second metal layer m2 extending substantially conformally to the lower surface of the insulating material 120 and the lower surface of the glass layer 110 onto the first metal layer m1, and an extension portion of the third metal layer m3 extending onto the second metal layer m2 from the lower surface of the insulating material 120 and the lower surface of the glass layer 110 and protruding to the lower side of the via hole v.

[0027] Further, the extension portions of the first metal layer m1 can be in direct contact with the upper surface of the insulating material 120 and the upper surface of the glass layer 110 and the lower surface of the insulating material 120 and the lower surface of the glass layer 110, respectively. For example, the upper and lower surfaces of the glass layer 110 can not be covered by the insulating material 120. For example, a stack structure in which the glass layer 110, the insulating material 120, the first metal layer m1, the second metal layer m2, and the third metal layer m3 are sequentially provided can be formed inside the via hole v, and a stack structure in which the glass layer 110, the first metal layer m1, the second metal layer m2, and the third metal layer m3 are sequentially provided can be formed on the upper and / or lower surface of the glass layer 110. Thus, an unnecessary increase in thickness can be prevented. In addition, since the patterns can be directly formed on the surfaces of the glass layer 110, this can more easily allow pitch refinement. In addition, the upper surface of the glass layer 110 can be substantially coplanar with the upper surface of the insulating material 120, and the lower surface of the glass layer 110 can be substantially coplanar with the lower surface of the insulating material 120. Thus, a substantially flat surface can be more easily provided on the upper and / or lower surface of the glass layer 110.

[0028] Hereinafter, components of the printed circuit board 100A will be explained in more detail with reference to the accompanying drawings.

[0029] The glass layer 110 can include glass (an amorphous solid). The glass can include, for example, pure silica (about 100% of SiO2), soda-lime glass, borosilicate glass, and alumino-silicate glass. However, the present disclosure is not limited thereto, and alternative glass materials (e.g., fluoro glass, phosphate glass, chalcogenide glass, etc.) can also be used as the material of the glass layer 110. In addition, other additives can be included to form glass having specific physical properties. These additives can include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates (e.g., calcium carbonate (e.g., limestone) and sodium carbonate (e.g., soda)) and / or oxides of these elements and other elements. The glass layer 110 can be a layer different from a layer of an organic insulating material (specifically, a copper-clad laminate (CCL), a prepreg (PPG)) including, for example, glass fibers (e.g., a glass fabric exemplified by a glass cloth). For example, the glass layer 110 can be a glass plate.

[0030] The via h can penetrate a region between the upper surface and the lower surface of the glass layer 110. For example, the via h can be a glass through-hole. The via h can have an hourglass shape in which a central portion has the narrowest width on a cross-section passing through the via h, but the present disclosure is not limited thereto. The glass layer 110 can have a plurality of such vias h. The plurality of vias h can be spaced apart from each other and can be formed in the glass layer 110. The number of the plurality of vias h can not be particularly limited.

[0031] The insulating material 120 can include an organic insulating material. For example, the insulating material 120 can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including the above-described resin and an inorganic filler and / or an organic filler. For example, the insulating material 120 can be an ABF (Anisotropic Conductive Film) or the like, in which case the insulating material 120 can be more easily formed in the via h and a via hole v can also be more easily processed in the insulating material 120, but the present disclosure is not limited thereto. The insulating material 120 can be disposed between the glass layer 110 within the via h and the metal via 130 and can continuously surround the side surface of the metal via 130.

[0032] The via hole v can penetrate a region between the upper surface and the lower surface of the insulating material 120 located within the via h. For example, the via hole v can be a through-hole. The via hole v can have an hourglass shape in which a central portion has the narrowest width on a cross-section passing through the via hole v, but the present disclosure is not limited thereto. When a plurality of vias h are formed in the glass layer 110, the insulating material 120 can be respectively disposed in the plurality of vias h, and a plurality of via holes v can be respectively formed in the insulating material 120.

[0033] The metal via 130 can include a metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the metal via 130 can include a first metal layer m1, a second metal layer m2, and a third metal layer m3. The first metal layer m1 and the second metal layer m2 can be seed metal layers formed using sputtering and electroless plating, and the third metal layer m3 can be a metal layer filled with plating using electroplating. The first metal layer m1 can include a plurality of sputtered layers. For example, the first metal layer m1 can include a composite layer of a sputtered titanium layer and a sputtered copper layer, the second metal layer m2 can include electroless copper plating, and the third metal layer m3 can include electrolytic copper plating. The metal via 130 can perform various functions according to design. For example, the metal via 130 can include a signal via, a power via, and a ground via. When a plurality of via holes v are formed, a plurality of metal vias 130 can be respectively disposed in corresponding via holes v of the plurality of via holes v.

[0034] Each of the first metal pattern 132 and the second metal pattern 134 can include a metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first metal pattern 132 and the second metal pattern 134 can include the first metal layer m1, the second metal layer m2, and the third metal layer m3 described above. Each of the first metal pattern 132 and the second metal pattern 134 can perform various functions according to design. For example, the first metal pattern 132 and the second metal pattern 134 can include a signal pattern, a power pattern, and a ground pattern, and each of these patterns can have a pad and / or a land shape. When a plurality of metal vias 130 are formed, a plurality of first metal patterns 132 and a plurality of second metal patterns 134 can be respectively disposed on the upper side and the lower side of the plurality of metal vias 130.

[0035] Each of the other metal patterns 136 and 138 can include a metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the other metal patterns 136 and 138 can include the first metal layer m1, the second metal layer m2, and the third metal layer m3 described above. The other metal patterns 136 and 138 can each perform various functions according to design, and can include, for example, a signal pattern, a power pattern, and a ground pattern. These patterns can have various shapes, such as a line, a plane, a pad, and a land.

[0036] Figures 3A to 3M are cross-sectional views schematically showing various shapes of through-holes, via holes, and metal vias that can be applied to a printed circuit board of Figure 2 .

[0037] Referring to Figures 3A to 3M , in a cross section passing through the through-hole h and the via-hole v, the shape of the through-hole h and the via-hole v can substantially correspond to each other, or can be independent of each other. For example, referring to Figure 3A , each of the through-hole h and the via-hole v can have an hourglass shape having a narrowest width in a central portion thereof. Alternatively, referring to Figure 3B , each of the through-hole h and the via-hole v can have a rectangular shape having a substantially vertical wall surface. Alternatively, referring to Figure 3C , the through-hole h can have a substantially vertical rectangular shape, and the via-hole v can have a tapered shape having a width of an upper end thereof wider than a width of a lower end thereof. Alternatively, referring to Figure 3D , the through-hole h can have a substantially vertical rectangular shape, and the via-hole v can have an hourglass shape having a central portion thereof having a narrowest width. Alternatively, referring to Figure 3E , each of the through-hole h and the via-hole v can have a tapered shape having a width of an upper end thereof wider than a width of a lower end thereof. Alternatively, referring to Figure 3F , the through-hole h can have a tapered shape having a width of an upper end thereof wider than a width of a lower end thereof, and the via-hole v can have an hourglass shape having a central portion thereof having a narrowest width. Alternatively, referring to Figure 3G , the through-hole h can have an hourglass shape having a central portion thereof having a narrowest width, and the via-hole v can have a tapered shape having a width of an upper end thereof wider than a width of a lower end thereof. Alternatively, referring to Figure 3H , the through-hole h can have an hourglass shape having a central portion thereof having a narrowest width, and the via-hole v can have a rectangular shape having a substantially vertical wall surface. Further, referring to Figures 3I to 3M , in each of the structures shown in the above Figure 3A , Figure 3B , Figure 3D , Figure 3F and Figure 3H , there can be a region on a wall surface of the via-hole v at a central region thereof on which the first metal layer m1 is not formed due to insufficient step coverage of sputtering, but even in this case, the second metal layer m2 can cover the region on the wall surface of the via-hole v on which the first metal layer m1 is not formed, and thus, sufficient coverage can be ensured. For example, a stacked structure in which the glass layer 110, the insulating material 120, the second metal layer m2, and the third metal layer m3 are sequentially disposed can be formed in a central portion of the via-hole v. For example, the second metal layer m2 can be in direct contact with the insulating material 120 in the central portion of the via-hole v. Further, other descriptions can be substantially the same as those described with respect to the printed circuit board 100A.

[0038] Figure 4 is a process diagram schematically showing an example of manufacturing Figure 2 a printed circuit board.

[0039] Referring to Figure 4 , first, a via h can be formed in a glass layer 110. The glass layer 110 can be a glass plate or the like. The via h can be formed by a chemical method such as etching, sandblasting, laser, or plasma and / or a mechanical method. Next, an insulating material 120 can be coated to the glass layer 110 to fill the via h. For example, ABF lamination or the like can be used. The insulating material 120 can be formed with a plurality of layers as needed, and the boundary between the plurality of layers can be apparent or not apparent. Next, portions of the insulating material 120 disposed on the upper and lower surfaces of the glass layer 110 can be removed. The removal of the insulating material 120 can be performed using a chemical mechanical planarization (CMP) polishing process or etching. Next, a via hole v can be formed in the insulating material 120. Laser processing using carbon dioxide gas can be used to process the via hole v. If needed, a desmear process can also be performed after the via hole v is processed. Next, sputtering and electroless plating can be sequentially performed to form a first metal layer m1 and a second metal layer m2 on the glass layer 110 and inside the via hole v. Next, a third metal layer m3 can be formed on the glass layer 110 and inside the via hole v using a circuit process including electrolytic plating. Then, the first metal layer m1, the second metal layer m2, and the third metal layer m3 on the glass layer 110 are patterned, whereby a metal via 130, a first metal pattern 132, and a second metal pattern 134, and other metal patterns 136 and 138 can be formed. The printed circuit board 100A can be manufactured by a series of processes. Other descriptions can be substantially the same as described for the printed circuit board 100A.

[0040] Figure 5 is a cross-sectional view schematically showing Figure 2 a modified example of the printed circuit board.

[0041] Referring to Figure 5 , the printed circuit board 500A can be a multilayer printed circuit board including a core 100-1, a first build-up portion 210 disposed on the upper side of the core 100-1, and a second build-up portion 220 disposed on the lower side of the core 100-1. For example, the printed circuit board 500A can be used as a flip chip board (FCB), a ball grid array (BGA) substrate, an interposer substrate, a package substrate, or the like. However, the present disclosure is not limited thereto, and can also be used as various other types of substrates. In this case, the core 100-1 can include the structures in the printed circuit board 100A described above, and thus can include substantially the same technical features as the technical features described above.

[0042] The printed circuit board 500A can further include a plurality of semiconductor chips 310 mounted on the first buildup portion 210. The plurality of semiconductor chips 310 can be surface mounted on the first buildup portion 210 by the plurality of first electrical connection metals 410, respectively. For example, a plurality of terminals P of each of the plurality of semiconductor chips 310 can be connected to an uppermost pad pattern of one or more first interconnection layers 212 of the first buildup portion 210 by the plurality of first electrical connection metals 410. If necessary, the printed circuit board 500A can further include a molding material 320 covering the plurality of semiconductor chips 310, an underfill material 330 disposed between the plurality of semiconductor chips 310 and the first buildup portion 210 and surrounding the plurality of first electrical connection metals 410, and / or the plurality of second electrical connection metals 420 disposed on a lower side of the second buildup portion 220.

[0043] Hereinafter, components of the printed circuit board 500A will be explained in more detail with reference to the accompanying drawings.

[0044] The core portion 100-1 can include a glass core 110 (i.e., a glass layer as described above), a plurality of metal vias 130 penetrating the glass core 110, respectively, a plurality of first metal patterns 132 disposed on an upper surface of the glass core 110 and connected to upper sides of the plurality of metal vias 130, respectively, and a plurality of second metal patterns 134 disposed on a lower surface of the glass core 110 and connected to lower sides of the plurality of metal vias 130, respectively. For example, the core portion 100-1 can include the structure described above with respect to the printed circuit board 100A. In addition, Figures 3A to 3M The various shapes of the via holes h and the via holes v illustrated in the middle can also be applied to the core portion 100-1. Repetitive description thereof will be omitted.

[0045] The first buildup portion 210 can include a first insulating body 211 disposed on an upper side of the core portion 100-1, one or more first interconnection layers 212 arranged on or within the first insulating body 211, and one or more first via layers 213 disposed on or within the first insulating body 211. The second buildup portion 220 can include a second insulating body 221 disposed on a lower side of the core portion 100-1, one or more second interconnection layers 222 disposed on or within the second insulating body 221, and one or more second via layers 223 disposed on or within the second insulating body 221.

[0046] Each of the first and second insulating bodies 211 and 221 can include an organic insulating material. The organic insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including the above-described resin and an inorganic filler, an organic filler, and / or a glass fiber (for example, a glass fabric exemplified by a glass cloth). For example, each of the first and second insulating bodies 211 and 221 can include a prepreg (PPG), an Ajinomoto Build-up Film (ABF), a photosensitive dielectric (PID), and a solder resist (SR), but the present disclosure is not limited thereto. If necessary, each of the first and second insulating bodies 211 and 221 can be formed with a plurality of layers. In this case, the adjacent layers can have a boundary therebetween, but can also be integrated with each other without a boundary. Each layer can include substantially the same organic insulating material, but is not limited thereto, and can include different organic insulating materials.

[0047] Each of the first and second interconnection layers 212 and 222 can include a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. The first and second interconnection layers 212 and 222 can preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first and second interconnection layers 212 and 222 can perform various functions according to a design. For example, the first and second interconnection layers 212 and 222 can include a signal pattern, a power pattern, and a ground pattern. Each of the patterns can have various shapes such as a line, a plane, a pad, and a bump. Each of the first and second interconnection layers 212 and 222 can include a seed layer and a plated layer. The seed layer can be formed by electroless plating or sputtering, or can be formed using both electroless plating and sputtering. The plated layer can be formed by electrolytic plating. Each of the first and second interconnection layers 212 and 222 can be formed with a plurality of layers, and in this case, the first and second interconnection layers 212 and 222 can have the same number of layers, but the present disclosure is not limited thereto.

[0048] Each of the first via layer 213 and the second via layer 223 can include a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. The first via layer 213 and the second via layer 223 can preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first via layer 213 and the second via layer 223 can perform various functions according to design. For example, the first via layer 213 and the second via layer 223 can include signal vias, power vias, and ground vias. Each of the first via layer 213 and the second via layer 223 can include a fill via in which a via hole is filled with a metal, but can also include a conformal via in which a metal is disposed along a wall surface of a via hole. Each of the first via layer 213 and the second via layer 223 can provide an electrical path within the first build-up part 210 and the second build-up part 220, and can also provide an electrical path between the core part 100-1 and the first build-up part 210 and the second build-up part 220, respectively. Each of the first via layer 213 and the second via layer 223 can have a tapered shape in a cross-section, and for example, can have a shape tapered in opposite directions in a cross-section. The first via layer 213 can include the same seed layer and plating layer as the first interconnection layer 212, and the second via layer 223 can include the same seed layer and plating layer as the second interconnection layer 222. Each of the first via layer 213 and the second via layer 223 can be formed with a plurality of layers.

[0049] The semiconductor chip 310 can include an integrated circuit (IC) die in which hundreds to millions of elements are integrated into a single chip. In this case, the integrated circuit die can be, for example, an application processor (e.g., AP) such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, a logic chip such as a field-programmable gate array (FPGA), an analog-to-digital converter, and an application-specific IC (ASIC), but the present disclosure is not limited thereto, and the integrated circuit die can be a memory chip such as a volatile memory (e.g., DRAM, high bandwidth memory (HBM)), a non-volatile memory (e.g., ROM, flash memory), or another type of chip such as a power management IC (PMIC).

[0050] The semiconductor chip 310 can be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like can be used as a base material forming each main body. Various circuits can be formed on the main body. A connection pad can be formed on the main body, and the connection pad can include a conductive material such as aluminum (Al), copper (Cu). The semiconductor chip 310 can be a bare die, and in this case, a terminal P such as a metal bump can be disposed on the connection pad. The semiconductor chip 200 can be a packaged die, and in this case, a redistribution layer can be additionally formed on the connection pad, and a terminal P such as a metal bump can be disposed on the redistribution layer.

[0051] The molding material 320 can protect the semiconductor chip 310 and can provide mechanical strength in a semiconductor packaging process. In this regard, the molding material 320 can include an epoxy molding compound (EMC) having excellent protection performance, thermal performance, mechanical strength, electrical insulation, and environmental stability. However, the disclosure is not limited thereto, and other polymer materials can be used in addition to the epoxy molding compound.

[0052] The underfill material 330 can fill a gap between the semiconductor chip 310 and the first buildup portion 210 to improve mechanical strength in a semiconductor packaging process, and can increase resistance to thermal stress and mechanical stress. The underfill material 330 can include a resin material that can perform this function, such as capillary underfill (CUF), no-flow underfill (NUF), and mold underfill (MUF), but the disclosure is not limited thereto.

[0053] The first and second electric connection metals 410 and 420 can connect the printed circuit board 100B to other substrates or electronic components. Each of the first and second electric connection metals 410 and 420 can be formed with a conductive material such as solder, but this is only an example, and the material is not particularly limited thereto. The first and second electric connection metals 410 and 420 can be balls, pins, or the like, respectively. The first and second electric connection metals 410 and 420 can be formed as a multilayer structure or a single layer structure, respectively. When formed as a multilayer structure, the first and second electric connection metals 410 and 420 can include a copper pillar and solder formed on the copper pillar, and when formed as a single layer structure, the first and second electric connection metals 410 and 420 can include tin-silver solder or copper, but the disclosure is not limited thereto. The first and second electric connection metals 410 and 420 can be disposed as a plurality of, respectively.

[0054] Other descriptions can be substantially the same as those described with respect to the printed circuit board 100A.

[0055] Figure 6 is a cross-sectional view schematically illustrating another example of a printed circuit board.

[0056] Referring to Figure 6 In comparison with the printed circuit board 100A described above, the printed circuit board 100B can be configured such that the upper surface of the insulating material 120 can be recessed downward with respect to the upper surface of the glass layer 110, and the lower surface of the insulating material 120 can be recessed upward with respect to the lower surface of the glass layer 110. Thus, the first metal pattern 132 can have a stepped structure S on the upper surface of the insulating material 120 and the upper surface of the glass layer 110, and the second metal pattern 134 can have a stepped structure S on the lower surface of the insulating material 120 and the lower surface of the glass layer 110. For example, each of the first metal layer m1, the second metal layer m2, and the third metal layer m3 can have a stepped portion on the upper and lower surfaces of the insulating material 120 and the upper and lower surfaces of the glass layer 110.

[0057] In this way, the printed circuit board 100B has a structure substantially similar to that of the printed circuit board 100A described above, and thus can substantially include the technical effects described above. In addition, since the printed circuit board 100B has the stepped structure S, this can more effectively disperse thermal stress and mechanical stress, and can improve the characteristics of high-frequency signals by diversifying the electrical signal paths, and can help to reduce electromagnetic interference (EMI). In addition, the heat problem can be alleviated by allowing heat to spread over a wide area rather than being concentrated in one place, and the electrical contact resistance can be reduced by increasing the electrical contact area, and the reliability can be improved by increasing the physical contact area.

[0058] In addition, Figures 3A to 3M The various shapes of the via holes h and the via holes v shown in FIG. 1 can also be applied to the printed circuit board 100B. For example, the stepped structure S described above can be applied to the upper and lower surfaces of the glass layer 110 and the insulating material 120 including the via holes h and the via holes v having the various shapes described above. In addition, the contents described with respect to the printed circuit board 100A can be applied to the printed circuit board 100B according to the present embodiment in substantially the same manner.

[0059] Figure 7 is a process diagram schematically showing an example of manufacturing Figure 6 a printed circuit board.

[0060] Referring to Figure 7First, a via hole h can be formed in the glass layer 110. Next, the insulating material 120 can be coated to the glass layer 110 to fill the via hole h. Then, portions of the insulating material 120 disposed on the upper and lower surfaces of the glass layer 110 can be removed. In this case, the upper and lower surfaces of the insulating material 120 can have stepped portions with respect to the upper and lower surfaces of the glass layer 110, respectively, due to over-etching of the insulating material 120. Next, a through-hole v can be formed in the insulating material 120. Then, the first and second metal layers m1 and m2 can be formed on the glass layer 110 and inside the through-hole v. Next, the third metal layer m3 can be formed on the glass layer 110 and inside the through-hole v. Then, the first, second, and third metal layers m1, m2, and m3 on the glass layer 110 are patterned, whereby the metal via 130, the first and second metal patterns 132 and 134, and other metal patterns 136 and 138 can be formed. Through a series of processes, the above-described printed circuit board 100B can be manufactured. Other descriptions can be substantially the same as those described with respect to the printed circuit boards 100A and 100B and the manufacturing example of the printed circuit board 100A.

[0061] Figure 8 is a cross-sectional view schematically illustrating a modification example of the printed circuit board. Figure 6

[0062] Referring to Figure 8 In comparison with the above-described printed circuit board 500A, the printed circuit board 500B can be configured such that the structure in the above-described printed circuit board 100B, rather than the structure in the above-described printed circuit board 100A, can be included in the core 100-2. Accordingly, the printed circuit board 500B can include technical features and technical effects substantially the same as those of the above-described printed circuit boards 100A, 100B, and 500A. In addition, Figures 3A to 3M The various shapes of the via hole h and the through-hole v illustrated in FIG. 10 can be applied to the core 100-2. Repetitive descriptions thereof will be omitted. Further, other descriptions can be substantially the same as those described with respect to the printed circuit boards 100A, 100B, and 500A.

[0063] Figure 9 is a cross-sectional view schematically illustrating another example of a printed circuit board.

[0064] Referring to Figure 9 ​In comparison with the printed circuit board 100A described above, the printed circuit board 100C can be configured such that the glass layer 110 can also have a through portion H spaced apart from the via hole h, the second insulating material 120' having the plurality of second via holes V can be disposed within the via hole h, and the plurality of second metal vias 150 can be disposed within each of the plurality of second via holes V. Each of the plurality of second metal vias 150 can include a fourth metal layer ml' having at least a portion thereof disposed substantially conformally on each wall surface of the plurality of second via holes V, a fifth metal layer m2' having at least a portion thereof disposed substantially conformally on the fourth metal layer ml', and a sixth metal layer m3' disposed on the fifth metal layer m2' and filling each of the plurality of second via holes V. The fourth metal layer ml' and the fifth metal layer m2' can be seed metal layers, and the sixth metal layer m3' can be a fill plating metal layer.

[0065] In this way, since the printed circuit board 100C has a structure substantially similar to that of the printed circuit board 100A described above, the printed circuit board 100C can substantially include the technical effects described above. In addition, the second insulating material 120' can be disposed in the through portion H having a size greater than the via hole h, the plurality of second via holes V can be formed in the second insulating material 120', and the plurality of second metal vias 150 can be respectively disposed in the plurality of second via holes V. Such a structure can be easily applied to a via-dense region within a substrate. In addition, the structure can make control of via pitch easier.

[0066] In addition, the plurality of second metal vias 150 can each be connected to a corresponding third metal pattern 152 on the upper side. Each of the plurality of third metal patterns 152 can include a portion of the fourth metal layer ml' extending substantially conformally onto an upper surface of the second insulating material 120', a portion of the fifth metal layer m2' extending substantially conformally onto the fourth metal layer ml' from the upper surface of the second insulating material 120', and a portion of the sixth metal layer m3' extending onto the fifth metal layer m2' from the upper surface of the second insulating material 120' and protruding to the upper side of each of the plurality of second via holes V. An upper surface of each of the plurality of third metal patterns 152 can be substantially coplanar with the upper surface of the first metal pattern 132.

[0067] In addition, the plurality of second metal vias 150 can be respectively connected to a plurality of fourth metal patterns 154 on the lower side. Each of the plurality of fourth metal patterns 154 can include a portion of a fourth metal layer m1' extending substantially conformally onto a lower surface of the second insulating material 120', a portion of a fifth metal layer m2' extending substantially conformally onto the fourth metal layer m1' from the lower surface of the second insulating material 120', and a portion of a sixth metal layer m3' extending onto the fifth metal layer m2' from the lower surface of the second insulating material 120' and protruding to the lower side of each of the plurality of second via holes V. A lower surface of each of the plurality of fourth metal patterns 154 can be substantially coplanar with the lower surface of the second metal pattern 134.

[0068] Further, the second insulating material 120' can be substantially the same as the first insulating material 120, and for example, can also be formed based on the same material and process when the first insulating material 120 is formed. In addition, the fourth metal layer m1', the fifth metal layer m2', and the sixth metal layer m3' can be substantially the same as the first metal layer m1, the second metal layer m2, and the third metal layer m3, and for example, can also be formed based on the same material and process when the first metal layer m1, the second metal layer m2, and the third metal layer m3 are formed.

[0069] In addition, Figures 3A to 3M The various shapes of the via holes h and the via holes v shown in FIGS. 1A to 1C can also be applied to the printed circuit board 100C. For example, the above-described various shapes can be identically or similarly applied to the via holes h and the first via holes v and the through portions H and the plurality of second via holes V. Other descriptions can be substantially the same as those described with respect to the printed circuit boards 100A and 100B.

[0070] Figure 10 is a process diagram schematically showing an example of a process of manufacturing a printed circuit board. Figure 9

[0071] In addition, the left side drawings schematically show process cross sections, respectively, and the right side drawings schematically show top views of the process cross sections of the left side, respectively.

[0072] Referring to Figure 10 ​First, through-holes h and through portions H can be formed in the glass layer 110. Similar to through-holes h, through portions H can also be formed by chemical and / or mechanical methods such as etching, sandblasting, laser, or plasma. Through-holes h and through portions H can be formed together using the same process. Next, insulating materials 120 and 120' can be coated onto the glass layer 110 to fill through-holes h and through portions H. Then, portions of insulating materials 120 and 120' disposed on the upper and lower surfaces of the glass layer 110 can be removed. In this process, the portions of insulating materials 120 and 120' filling through-holes h can be first insulating material 120, and the portions of insulating materials 120 and 120' filling through portions H can be second insulating material 120'. Next, a first through-hole v can be formed in the first insulating material 120, and a plurality of second through-holes V can be formed in the through portions H. The processing of the first through-hole v and the plurality of second through-holes V can be performed using laser processing utilizing carbon dioxide gas. The first via v and the plurality of second vias V can be formed together using the same process. Next, by sequentially performing sputtering and electroless plating, a first metal layer m1 and a second metal layer m2 can be formed on the glass layer 110 and inside the first via v, and a fourth metal layer m1' and a fifth metal layer m2' can be formed on the second insulating material 120' and inside the plurality of second vias V. The first metal layer m1, the second metal layer m2, the fourth metal layer m1', and the fifth metal layer m2' can be formed together using the same process. Next, by a circuit process including electroless plating, a third metal layer m3 can be formed on the glass layer 110 and inside the first via v, and a sixth metal layer m3' can be formed on the second insulating material 120' and inside the plurality of second vias V. The third metal layer m3 and the sixth metal layer m3' can be formed together using the same process. Through a patterning process, a first metal via 130, a first metal pattern 132, a second metal pattern 134, a plurality of second metal vias 150, and a plurality of third metal patterns 152 and fourth metal patterns 154 can be formed. If desired, other metal patterns 136 and 138 described above can also be formed. The printed circuit board 100C described above can be manufactured through a series of processes. Other descriptions are substantially the same as those given for the examples of manufacturing printed circuit boards 100A and 100C, and for the description of printed circuit board 100A.

[0073] Figure 11 It is shown schematically. Figure 9 A cross-sectional view of a modified example of a printed circuit board.

[0074] Reference Figure 11Compared to the printed circuit board 500A described above, the printed circuit board 500C can be configured such that the structure in the printed circuit board 100C, but not the structure in the printed circuit board 100A, can be included in the core 100-3. Therefore, the printed circuit board 500C can include technical features and effects substantially the same as those described above regarding the printed circuit boards 100A, 100C, and 500A. Furthermore, Figures 3A to 3M The various shapes of through holes h and vias v shown are applicable to core 100-3. Redundant descriptions will be omitted. Other descriptions are substantially the same as those for printed circuit boards 100A, 100C, and 500A.

[0075] Figure 12 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0076] Reference Figure 12 Compared to the printed circuit board 100C described above, the printed circuit board 100D can be configured such that each of the upper and lower surfaces of the second insulating material 120' has a recess U, and at least one of the plurality of second via holes V can penetrate the region between the recessed upper and lower surfaces of the second insulating material 120'. Therefore, the upper surface of at least one of the plurality of third metal patterns 152 can be disposed below the upper surface of the first metal pattern 132. Additionally, the lower surface of at least one of the plurality of fourth metal patterns 154 can be disposed above the lower surface of the second metal pattern 134. Furthermore, the lower surface of at least one of the plurality of third metal patterns 152 can be inclined. Additionally, the upper surface of at least one of the plurality of fourth metal patterns 154 can be inclined.

[0077] In this way, since the printed circuit board 100D has a structure similar to that of the printed circuit board 100C described above, it can essentially include the aforementioned technical effects. Furthermore, each of the upper and lower surfaces of the second insulating material 120' can have a recess U, and a plurality of second metal vias 150 with a small height or thickness can be formed in the recess U. This structure can be more easily applied to via-dense regions, and can reduce the height or thickness of vias formed in via-dense regions, and can further reduce the via pitch.

[0078] Figures 3A to 3M The various shapes of through holes h and vias v shown can also be applied to printed circuit board 100D. For example, the various shapes described above can be applied in the same or similar way to through holes h and first vias v, as well as through portions H and multiple second vias V. Other descriptions are substantially the same as those described for printed circuit boards 100A and 100C.

[0079] Figure 13 It is a schematic representation of manufacturing.Figure 12 A process diagram of an example printed circuit board.

[0080] In addition, the attached diagrams on the left schematically show the process cross-sections, and the attached diagrams on the right schematically show the top view of the process cross-sections on the left.

[0081] Reference Figure 13 First, through-holes h and through portions H can be formed in the glass layer 110. Next, insulating materials 120 and 120' can be coated onto the glass layer 110 to fill the through-holes h and through portions H. Then, portions of the insulating materials 120 and 120' disposed on the upper and lower surfaces of the glass layer 110 can be removed. In this process, the portions of the insulating materials 120 and 120' filling the through-holes h can be the first insulating material 120, and the portions of the insulating materials 120 and 120' filling the through portions H can be the second insulating material 120'. In this case, during the process of filling the through portions H and / or removing a portion of the second insulating material 120', undulations may occur on the upper and / or lower surfaces of the second insulating material 120'. Next, first through-holes v can be formed in the first insulating material 120, and a plurality of second through-holes V can be formed in the through portions H. Next, a first metal layer m1 and a second metal layer m2 can be formed on the glass layer 110 and inside the first via v, and a fourth metal layer m1' and a fifth metal layer m2' can be formed on the second insulating material 120' and inside the plurality of second via v. Following this, a third metal layer m3 can be formed on the glass layer 110 and inside the first via v, and a sixth metal layer m3' can be formed on the second insulating material 120' and inside the plurality of second via v. Through a patterning process, a first metal via 130, a first metal pattern 132, a second metal pattern 134, a plurality of second metal vias 150, and a plurality of third metal patterns 152 and fourth metal patterns 154 can be formed. If desired, other metal patterns 136 and 138 can also be formed. The printed circuit board 100D described above can be manufactured through a series of processes. Other descriptions are substantially the same as those given for the examples of manufacturing printed circuit boards 100A, 100C, and 100D, and the descriptions of printed circuit boards 100A and 100C.

[0082] Figure 14 It is shown schematically. Figure 12 A cross-sectional view of a modified example of a printed circuit board.

[0083] Reference Figure 14Compared to the printed circuit board 500C described above, the printed circuit board 500D can be configured such that the structure in the printed circuit board 100D, but not the structure in the printed circuit board 100C, can be included in the core 100-4. Therefore, the printed circuit board 500D can include technical features and effects substantially the same as those described above regarding the printed circuit boards 100A, 100C, 100D, 500A, and 500C. Furthermore, Figures 3A to 3M The various shapes of through holes h and vias v shown can be applied to core 100-4. Repeated descriptions will be omitted. Additionally, other descriptions are substantially the same as those for printed circuit boards 100A, 100C, 100D, 500A, and 500C.

[0084] In this disclosure, “substantially conformally disposed” may, for example, mean that a thin film of a certain thickness is formed along the surface of the target component (e.g., wall surface, bottom surface, side surface, etc.), and the surface shape of the thin film is substantially the same as the shape of the corresponding surface on which it is disposed. According to one embodiment, for example, the thin film may have a thickness of about 1000 nm or less. That is, the thickness value of “1000 nm or less” only represents an exemplary range of the thin film, but is not limited thereto.

[0085] In this disclosure, the term "cover" can include covering a portion or the entirety of a component, and can also include direct or indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling. For example, "fill" can include the presence of holes or gaps. Additionally, the term "surround" can include not only complete surrounding but also partial surrounding. Furthermore, the term "expose" can include not only complete exposure but also partial exposure, and exposure can mean that a component is exposed from another component in which it is embedded. For example, exposing a pad through an opening can mean that the pad is exposed from beneath a solder resist layer, and a surface treatment layer or similar feature can be additionally formed on the exposed pad.

[0086] In this disclosure, "disposing of an object in a through portion, through hole, or through passage" can include not only situations where the object is completely disposed within the through portion, through hole, or through passage, but also situations where the object protrudes upward or downward in the cross-section. For example, when an object is disposed in a through portion, through hole, or through passage on a plane, it can be understood as either of the above two situations.

[0087] In this disclosure, the term "basic" can be a concept that includes process errors, positional deviations, measurement errors, etc., which may occur during the manufacturing process. For example, basic perpendicularity can include not only perfectly perpendicularity but also approximately perpendicularity. Furthermore, basic coplanarity can include not only perfectly coplanarity but also approximately coplanarity.

[0088] In this disclosure, "substantially identical insulating materials" can refer not only to the case of identical insulating materials, but also to the case of materials including the same type of insulating materials. Therefore, the composition of the insulating materials is substantially the same, but their specific composition ratios may differ slightly.

[0089] In this disclosure, "section" can refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is viewed from a side view. Furthermore, "plane" can refer to the planar shape when an object is cut horizontally, or the planar shape when the object is viewed from a top or bottom view.

[0090] In this disclosure, for convenience, "lower" in "lower side," "lower part," and "lower surface" refers to the downward direction relative to the cross-section of the drawing, and "upper" in "upper side," "upper part," and "upper surface" refers to the opposite direction. However, this definition of direction is for ease of explanation, and the scope of the claims is not specifically limited by the description of the direction, and the concepts of upper / lower can be changed at any time.

[0091] In this disclosure, "connection" is a concept that includes not only direct connections but also indirect connections via adhesive layers, etc. Additionally, the term "electrical connection" includes both physical and non-physical connections. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0092] In this disclosure, thickness, width, length, depth, linewidth, gap, pitch, spacing, surface roughness, etc., can be measured using a scanning microscope, optical microscope, or the like, based on a cross-section of a polished or cut printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the desired cut cross-section. For example, the width of the upper and / or lower portion of a via can be measured on a cross-section cut along the central axis of the via. In this case, when the value is not constant, it can be determined as the average of values ​​measured at any five points.

[0093] The term "example embodiment" as used in this disclosure does not imply the same embodiment and is provided to illustrate different unique features. However, the example embodiments presented above do not preclude implementation through combinations of features with other example embodiments. For example, even if matters described in a particular example embodiment are not described in other example embodiments, they may be understood as descriptions relating to other example embodiments unless there are descriptions that contradict or contradict matters in other example embodiments.

[0094] The terminology used in this disclosure is intended to describe exemplary embodiments only and is not intended to limit the scope of this disclosure. In the context, unless explicitly stated otherwise, singular terms also encompass their plural forms.

[0095] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a glass layer having a via; a first insulating material disposed within the via and having a first through-hole; and a first metal via disposed within the first through-hole, wherein the first metal via includes a first metal layer having at least a portion thereof disposed substantially conformally on a wall surface of the first through-hole, a second metal layer having at least a portion thereof disposed substantially conformally on the first metal layer, and a third metal layer disposed on the second metal layer and filling at least a portion of the first through-hole. the first insulating material includes an organic insulating material, 2. The printed circuit board of claim 1, wherein, the first metal layer includes a sputtered metal, the second metal layer includes electroless copper, and the third metal layer includes electrolytic copper. the first metal layer includes a first sputtered layer connected to the wall surface of the first through-hole and a second sputtered layer connected to the electroless copper, 3. The printed circuit board of claim 2, wherein, the first sputtered layer includes titanium, and the second sputtered layer includes copper. the second metal layer has a thickness greater than a thickness of the first metal layer.

4. The printed circuit board of claim 1, wherein, 5. The printed circuit board of claim 1, further comprising: a first metal pattern connected to an upper side of the first metal via; and a second metal pattern connected to a lower side of the first metal via, wherein the first metal pattern includes an extension of the first metal layer extending substantially conformally onto an upper surface of the first insulating material and an upper surface of the glass layer, an extension of the second metal layer extending substantially conformally onto the first metal layer from the upper surface of the first insulating material and the upper surface of the glass layer, and an extension of the third metal layer extending onto the second metal layer from the upper surface of the first insulating material and the upper surface of the glass layer and protruding to an upper side of the first through-hole, and the second metal pattern includes an extension of the first metal layer extending substantially conformally onto a lower surface of the first insulating material and a lower surface of the glass layer, an extension of the second metal layer extending substantially conformally onto the first metal layer from the lower surface of the first insulating material and the lower surface of the glass layer, and an extension of the third metal layer extending onto the second metal layer from the lower surface of the first insulating material and the lower surface of the glass layer and protruding to a lower side of the first through-hole. the extensions of the first metal layer are in direct contact with the upper surface of the first insulating material and the upper surface of the glass layer and the lower surface of the first insulating material and the lower surface of the glass layer, respectively. the upper surface of the first insulating material is substantially coplanar with the upper surface of the glass layer, and 6. The printed circuit board of claim 5, wherein, the lower surface of the first insulating material is substantially coplanar with the lower surface of the glass layer.

7. The printed circuit board of claim 5, wherein, the upper surface of the first insulating material is recessed downward relative to the upper surface of the glass layer, the lower surface of the first insulating material is recessed upward relative to the lower surface of the glass layer, 8. The printed circuit board of claim 5, wherein, ​ ​ the first metal pattern has a stepped structure on the upper surface of the first insulating material and the upper surface of the glass layer, and the second metal pattern has a stepped structure on the lower surface of the first insulating material and the lower surface of the glass layer.

9. The printed circuit board of claim 1, wherein, in a cross section passing through the via hole and the first through-hole, the shape of the via hole and the shape of the first through-hole are formed independently of each other.

10. The printed circuit board of claim 1, wherein, the glass layer further has a through portion spaced apart from the via hole, a second insulating material having a plurality of second through-holes is disposed within the through portion, and a plurality of second metal vias are respectively disposed within the plurality of second through-holes, wherein each of the plurality of second metal vias includes: a fourth metal layer, at least a portion of which is substantially conformally disposed on a wall surface of each of the plurality of second through-holes; a fifth metal layer, at least a portion of which is substantially conformally disposed on each of the fourth metal layers; and a sixth metal layer disposed on the fifth metal layer and filling at least a portion of each of the plurality of second through-holes.

11. The printed circuit board of claim 10, wherein, the second insulating material includes an organic insulating material, the fourth metal layer includes a sputtered metal, the fifth metal layer includes electroless copper, and the sixth metal layer includes electrolytic copper.

12. The printed circuit board of claim 10, wherein, the plurality of second metal vias are respectively connected to a plurality of third metal patterns on an upper side, and the plurality of second metal vias are respectively connected to a plurality of fourth metal patterns on a lower side, wherein each of the plurality of third metal patterns includes a portion of the fourth metal layer substantially conformally extending onto an upper surface of the second insulating material, a portion of the fifth metal layer substantially conformally extending onto the fourth metal layer from the upper surface of the second insulating material, and a portion of the sixth metal layer extending onto the fifth metal layer from the upper surface of the second insulating material and protruding to an upper side of each of the plurality of second through-holes, and each of the plurality of fourth metal patterns includes a portion of the fourth metal layer substantially conformally extending onto a lower surface of the second insulating material, a portion of the fifth metal layer substantially conformally extending onto the fourth metal layer from the lower surface of the second insulating material, and a portion of the sixth metal layer extending onto the fifth metal layer from the lower surface of the second insulating material and protruding to a lower side of each of the plurality of second through-holes.

13. The printed circuit board of claim 10, wherein, each of the upper surface and the lower surface of the second insulating material has a recessed portion, and at least one of the plurality of second through-holes penetrates an area between the recessed upper surface and the recessed lower surface of the second insulating material.

14. The printed circuit board of claim 13, further comprising: a plurality of third metal patterns respectively connected to an upper side of each of the plurality of second metal vias; a plurality of fourth metal patterns respectively connected to a lower side of each of the plurality of second metal vias; a first metal pattern connected to an upper side of the first metal via; and a second metal pattern connected to a lower side of the first metal via. ​ wherein an upper surface of at least one of the plurality of third metal patterns is disposed below an upper surface of the first metal pattern, and a lower surface of at least one of the plurality of fourth metal patterns is disposed above a lower surface of the second metal pattern.

15. The printed circuit board of claim 1, wherein, a portion of the second metal layer is disposed substantially conformally on the first metal layer, and another portion of the second metal layer is in direct contact with a portion of the first insulating material at a central portion of the first via hole.

16. A printed circuit board, comprising: a core including a glass core having a through-hole, an insulating material disposed within the through-hole and having a via hole, and a metal via disposed within the via hole; and a build-up portion including an insulating body disposed on the core, one or more interconnection layers respectively disposed on or within the insulating body, and one or more via layers respectively disposed within the insulating body, wherein the metal via includes a first metal layer having at least a portion thereof disposed substantially conformally on a wall surface of the via hole, a second metal layer having at least a portion thereof disposed substantially conformally on the first metal layer, and a third metal layer disposed on the second metal layer and filling at least a portion of the via hole.

17. The printed circuit board of claim 16, further comprising: a semiconductor chip mounted on the build-up portion.

18. A printed circuit board, comprising: a glass layer having a through-hole; a first insulating material disposed within the through-hole and having a first via hole; and a first metal via disposed within the first via hole, wherein the first metal via includes: a first metal layer having at least a portion thereof disposed substantially conformally on a wall surface of the first via hole; a second metal layer having at least a portion thereof disposed substantially conformally on the first metal layer; and a third metal layer disposed on the second metal layer and filling at least a portion of the first via hole, wherein a nanovoid is formed at a boundary between the second metal layer and the first metal layer.

19. The printed circuit board of claim 18, the first metal layer includes sputtered copper, and the second metal layer includes electroless plated copper. wherein 20. The printed circuit board of claim 18, the nanovoid is confirmable using a scanning electron microscope, a transmission electron microscope, a scanning transmission electron microscope, or a focused ion beam. wherein, ​

Images