Storage array, memory and electronic equipment

Abstract

The invention discloses a storage array, a memory and electronic equipment, which are used for compressing the sizes of the storage array in the vertical direction and the horizontal direction so as to improve the storage capacity and the storage density. The plurality of memory cell layers are stacked in the vertical direction, and each memory cell layer comprises the plurality of memory cells, so that the plurality of memory cells can be stacked in the vertical direction, and the memory capacity is improved. Moreover, the channel and the grid electrode in the transistor are arranged in different layers, so that the size of the storage unit in the horizontal direction can be compressed, more storage units can be arranged in the horizontal direction, and the storage capacity can be improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage array, memory, and electronic device. Background Technology

[0002] With the rapid development of chip technology, the demand for high-capacity storage is constantly increasing. Traditional planar dynamic random access memory (DRAM) has limited room for increasing capacity through miniaturization of memory cell size, and the process is difficult and costly. In contrast, three-dimensional (3D) DRAM uses a stacking method of memory cells to increase DRAM storage capacity, which is expected to break through the limitations of size miniaturization and further enhance its capacity competitiveness. Summary of the Invention

[0003] This application provides a storage array, a memory, and an electronic device for compressing the dimensions of the storage array in the vertical and horizontal directions to increase storage capacity and storage density.

[0004] In a first aspect, embodiments of this application provide a storage array comprising multiple storage cell layers and multiple word lines. The multiple storage cell layers are stacked vertically, and each storage cell layer includes multiple storage cells. This allows for the stacking of multiple storage cells in the vertical direction, increasing storage capacity. Each storage cell includes a channel and a capacitor arranged horizontally, with the channel connected to a first electrode plate of the capacitor. This horizontal arrangement of the channel and capacitor in the storage cell facilitates compressing the vertical dimension of the storage cell, enabling the stacking of more storage cell layers in the vertical direction and further increasing storage capacity. The horizontal direction is perpendicular to the vertical direction.

[0005] Each word line includes interconnected word line interconnect structures and multiple protrusions. The word line interconnect structures extend vertically, and the multiple protrusions extend horizontally. The protrusions serve as gates, thus effectively making the gates extend horizontally from the surface of the word line interconnect structures, making the word line interconnect structures and gates an integrated structure of the same material.

[0006] In this invention, a word line interconnect structure is constructed in which the channels of multiple memory cells stacked vertically in different memory cell layers at least partially surround a word line, and a protrusion serving as a gate is provided between two adjacent channels in the vertical direction. This allows the channels and gates to be stacked alternately in the vertical direction, so that the channels and gates are in different layers. This is beneficial for compressing the size of the memory cells in the horizontal direction, making it easier to set up more memory cells in the horizontal direction, and thus improving the storage capacity.

[0007] Furthermore, since the protrusion serving as the gate overlaps with the channel in the vertical direction, the protrusion serving as the gate and the channel can form a transistor, and the gate can be used to control the channel in order to control the switching on and off of the transistor.

[0008] Furthermore, a dielectric layer is provided between the channel and the protrusion and the word line interconnection structure, respectively, so as to isolate the protrusion and the word line interconnection structure from the channel using the dielectric layer.

[0009] In some embodiments, a first region of the channel is connected to a bit line, a second region of the channel is connected to a first electrode plate, and the first and second regions of the channel are spaced apart from each other.

[0010] In some embodiments, during the fabrication process, a memory array is typically formed on a substrate. Based on this, the memory array in this embodiment can be formed on a substrate, with the vertical direction perpendicular to the substrate and the horizontal direction parallel to the substrate, meaning the horizontal and vertical directions are perpendicular to each other. Furthermore, in this embodiment, the second direction and the first direction are both parallel to the horizontal direction. Exemplarily, the second direction intersects the first direction; for example, the second direction is perpendicular to the first direction.

[0011] In some embodiments, to reduce the horizontal dimensions of the memory cells and save the area occupied by the channels in the horizontal direction, the channels are configured as annular channels arranged in the horizontal direction. Furthermore, each channel can be arranged around the word line interconnect structure. Thus, in the horizontal direction, the annular channels surround the word line interconnect structure, allowing the word line interconnect structure to be located inside the annular structure of the annular channels, thereby further reducing the horizontal dimensions of the memory array. Furthermore, to improve gate control capability, the protrusions can also be arranged around the word line interconnect structure; that is, in the horizontal direction, the protrusions serving as gates also surround the word line interconnect structure. This maximizes the overlap area between the gate and the channel in the vertical direction, increasing the face-to-face area between the gate and the channel, thereby improving gate control capability.

[0012] In some embodiments, in each memory cell, the channel and capacitor can be arranged along a first direction parallel to the horizontal direction. Furthermore, the channel is located between the bit line and the capacitor connected thereto. This allows the first and second regions of the channel to be respectively positioned on opposite sides of the channel in the first direction, ensuring that the first and second regions do not contact each other and fully utilizing each region of the annular channel. Additionally, the channel and capacitor can be arranged closely in the horizontal direction, further compressing the horizontal dimensions of the memory cell.

[0013] In some embodiments, to further reduce the horizontal dimensions of the memory cells and save the area occupied by the channels in the horizontal direction, the channels can be configured as recessed channels arranged in the horizontal direction. Furthermore, to further reduce the horizontal dimensions of the memory array, word line interconnect structures can be disposed within the recesses of the channels, such that the channel partially surrounds the word line interconnect structures; that is, in the horizontal direction, the recessed channel partially surrounds the word line interconnect structures, for example, in the horizontal direction, the recessed channel surrounds half a circle of the word line interconnect structures. Moreover, to improve gate control capability, the protrusion serving as the gate can partially surround the word line interconnect structures; that is, in the horizontal direction, the protrusion serving as the gate also partially surrounds the word line interconnect structures, for example, in the horizontal direction, the protrusion serving as the gate surrounds half a circle of the word line interconnect structures. Thus, the overlap area between the gate and the channel in the vertical direction can be maximized, increasing the facing area between the gate and the channel, thereby improving gate control capability.

[0014] In some embodiments, to further improve gate control capability, the orthogonal projection of the channel on the substrate may overlap with the orthogonal projection of the protrusion serving as the gate on the substrate, or the orthogonal projection of the channel on the substrate may fall within the orthogonal projection of the protrusion serving as the gate on the substrate.

[0015] In some embodiments, within the same memory cell layer, the openings of the channels of two adjacent memory cells are aligned in the horizontal direction in a second direction parallel to the horizontal direction. Therefore, during the fabrication process, the annular channel can be divided into two by etching, which not only reduces the complexity of the fabrication process but also increases the memory cell density.

[0016] In some embodiments, in order to further compress the size of the memory cell in the horizontal direction, the distance between the channels of two adjacent memory cells in the second direction can be the same as the distance between the first electrode plates of two adjacent memory cells in the second direction.

[0017] In some embodiments, in the same memory cell, capacitors can be disposed on the side of the channel opposite to its horizontal opening, thereby further compressing the size of the memory cell in the first direction.

[0018] In some embodiments, to improve gate control capability, the channel may include a first channel portion, a second channel portion, and a third channel portion connected sequentially. The first and third channel portions extend horizontally, and the second channel portion extends vertically. This allows the first, second, and third channel portions to enclose a first groove extending horizontally, with the opening of the first groove facing the word line interconnect structure. Thus, the first and third channel portions form the sidewalls of the first groove, and the second channel portion forms the bottom of the first groove. Furthermore, without changing the overlap area between the gate protrusion and the channel in the vertical direction, the channel thickness can be reduced to improve gate control capability. Additionally, in two vertically stacked memory cells, a gate protrusion may be provided between the third channel portion of the channel of one memory cell and the first channel portion of the channel of the other memory cell. This allows the same gate to control the channels in the two vertically stacked memory cells, improving control synchronization and further compressing the vertical dimensions of the memory array.

[0019] In some embodiments, a bit line is further included in each memory cell layer, extending along a second direction parallel to the horizontal direction, and a bit line is connected to a channel in a memory cell layer arranged along the second direction. This extends the bit line horizontally. Furthermore, a bit line insulating layer or gas gap is provided between adjacent bit lines in the vertical direction. This reduces parasitic capacitance between bit lines and between a bit line and the gate, thereby reducing leakage current.

[0020] In some embodiments, the system further includes multiple plate lines extending vertically, with the second electrode plate of the capacitor in the vertically stacked memory cells connected to one of these plate lines. Furthermore, the first electrode plate of the capacitor in the vertically stacked memory cells is disposed around one of the plate lines, separated by an electrode dielectric layer. This allows the plate lines to be disposed within the memory cells in the vertical direction, eliminating the need for the plate lines to occupy additional horizontal area and further increasing the horizontal density of the memory cells.

[0021] In some embodiments, to increase the capacitance, the first electrode plate may have a second groove extending horizontally in the horizontal direction. The opening of the second groove faces the plate wire, and the plate wire extends into the second groove, so that the portion of the plate wire extending into the second groove serves as the second electrode plate of the capacitor. This not only increases the capacitance but also reduces manufacturing costs.

[0022] Secondly, embodiments of this application also provide a memory array comprising multiple memory cell layers stacked vertically, each memory cell layer comprising multiple memory cells, thereby enabling multiple memory cells to be stacked vertically to increase storage capacity. Each memory cell includes a transistor and a capacitor; the transistor includes a first channel, a second channel, and a gate, with the first and second channels stacked vertically. Furthermore, within the same memory cell, the first electrode plates of the gate and capacitor are arranged horizontally, thereby arranging the gate and capacitor in the memory cell horizontally, which helps to compress the vertical dimension of the memory cell, facilitating the stacking of more memory cell layers in the vertical direction and further increasing storage capacity. Additionally, the gate and the first electrode plate are respectively disposed between the first and second channels, with overlapping areas between the gate and the first and second channels in the vertical direction. Therefore, disposing the gate and the first and second channels on different layers further facilitates compressing the horizontal dimension of the memory cell, achieving a compact arrangement, and increasing storage density in the horizontal direction. In addition, a dielectric layer is provided between the gate and the first electrode plate, the first channel and the second channel respectively, so as to achieve the insulation between the gate and the first electrode plate, the first channel and the second channel respectively.

[0023] In some embodiments, in order to reduce the parasitic capacitance between the gate and the first electrode plate of the capacitor, the gate can be configured as a groove-shaped gate arranged in the horizontal direction, and the first electrode plate can be disposed at the open end of the gate in the horizontal direction.

[0024] In some embodiments, in order to reduce the size of the storage cell in the horizontal direction and save the area occupied by the first channel and the second channel in the horizontal direction, the first channel and the second channel can be respectively configured as annular channels arranged in the horizontal direction.

[0025] In some embodiments, the first channel and the second channel can be completely overlapped in the vertical direction, that is, the orthographic projection of the first channel on the substrate and the orthographic projection of the second channel on the substrate can be completely overlapped, thereby further saving the area occupied by the first channel and the second channel in the horizontal direction.

[0026] In some embodiments, the system further includes multiple bit lines extending in a vertical direction, wherein a first channel and a second channel in memory cells stacked vertically in different memory cell layers are connected to one of the multiple bit lines. Thus, the bit lines can be extended vertically to transmit signals, and when the transistor is turned on, the signal transmitted on the bit lines can be input to the first electrode plate of the capacitor.

[0027] In some embodiments, the system further includes a plurality of channel interconnect structures extending in a vertical direction. Furthermore, in two memory cells stacked in the vertical direction, a first channel of one memory cell is interconnected with a second channel of the other memory cell via the channel interconnect structures. Additionally, the channel interconnect structures are connected to bit lines and are spaced apart from the first electrode plate. Therefore, by improving the channel interconnect structures to connect the first and second channels to the bit lines, the contact area between the bit lines and the first and second channels can be increased.

[0028] In some embodiments, to achieve insulation between the channel interconnect structure and the first electrode plate, the channel interconnect structure can be configured as a groove-shaped channel interconnect structure arranged in the horizontal direction, and the first electrode plate can be disposed at the open end of the channel interconnect structure in the horizontal direction. Furthermore, the first electrode plate and the open end of the channel interconnect structure in the horizontal direction are spaced apart. Thus, for the first channel and the second channel connected to the same channel interconnect structure, the portions of the first channel and the second channel near the first electrode plate can be not interconnected in the vertical direction, achieving isolation between the first electrode plates of capacitors in adjacent memory cells in the vertical direction.

[0029] Furthermore, in order to achieve insulation between the channel interconnect structure and the first electrode plate, in some embodiments, the orthogonal projection of the channel interconnect structure on the substrate can fall within the orthogonal projection of the gate on the substrate.

[0030] In some embodiments, the interconnected first channel, channel interconnect structure, and second channel can be configured as an integral structure made of the same material, so that the first channel, channel interconnect structure, and second channel can be formed in the same process, reducing the number of fabrication steps. Furthermore, this can also improve the stability of the memory cell.

[0031] In some embodiments, the interconnected first channel, the channel interconnection structure, and the second channel can be enclosed to form a first groove extending in a horizontal direction. This allows for the formation of a thinner channel, improving gate control capability.

[0032] In some embodiments, the bit line has overlapping first bit line portions and second bit line portions in the vertical direction, wherein the width of the first bit line portion in the horizontal direction is greater than the width of the second bit line portion in the horizontal direction. Furthermore, the first bit line portion is connected to a channel interconnect structure, and the second bit line portion overlaps with the gate in the horizontal direction. Therefore, by increasing the distance between the second bit line portion and the gate without affecting the contact for signal transmission between the bit line and the first and second channels, the parasitic capacitance between the second bit line portion and the gate can be reduced.

[0033] In some embodiments, the system further includes multiple word lines extending along a first direction parallel to the horizontal direction, with one of the word lines disposed between a first channel and a second channel of the memory cell, and the portion of the word line overlapping the first channel and the second channel in the vertical direction serving as a gate. Thus, by extending the word lines horizontally and using a portion of the word lines as gates, the size of the memory array in both the horizontal and vertical directions can be further reduced.

[0034] In some embodiments, the system further includes multiple plate lines extending vertically, with first electrode plates in the vertically stacked memory cells in different memory cell layers surrounding one of the multiple plate lines via an electrode dielectric layer. Thus, by extending the bit lines vertically and using the plate lines as the second electrode plates of the capacitor, the plate lines are positioned inside the memory cells in the vertical direction, eliminating the need for the plate lines to occupy additional area in the horizontal direction, thereby further increasing the density of memory cells in the horizontal direction.

[0035] In some embodiments, to increase the capacitance, the first electrode plate may have a second groove extending horizontally in the horizontal direction. The opening of the second groove faces the plate wire, and the plate wire extends into the second groove, so that the portion of the plate wire extending into the second groove serves as the second electrode plate of the capacitor. This not only increases the capacitance but also reduces manufacturing costs.

[0036] In some embodiments, to improve the stability of the memory cell, the board line can have overlapping first board line portions and second board line portions in the vertical direction, wherein the width of the first board line portion in the horizontal direction is greater than the width of the second board line portion in the horizontal direction. Furthermore, a first electrode plate surrounds the first board line portion through an electrode dielectric layer to increase the capacitance. Additionally, the second board line portion overlaps with the first and second channels in the horizontal direction, and an electrode dielectric layer is disposed between the second board line portion and the first and second channels. Therefore, using the second board line portion as a support structure can improve the stability of the first and second channels.

[0037] Thirdly, embodiments of this application also provide a memory, which may include: a controller and at least one memory array, the controller being electrically connected to the memory array. The memory array may be the memory array described in the first aspect or embodiments thereof, or it may be the memory array described in the second aspect or embodiments thereof. Since the memory arrays described in the first or second aspect have larger storage capacity and storage density, the memory including the memory arrays described in the first or second aspect also has larger storage capacity and storage density.

[0038] Fourthly, embodiments of this application also provide an electronic device, which may include: a circuit board and the memory described in the third aspect above, wherein the memory is electrically connected to the circuit board. Since the memory described in the third aspect has a large storage capacity and storage density, the electronic device including any of the memories described in the third aspect also has a large storage capacity and storage density. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0040] Figure 2a This is a partial cross-sectional view of the storage array in an embodiment of this application;

[0041] Figure 2b for Figure 2a A schematic diagram of a partial top view of a structure along the AA' direction;

[0042] Figure 2c for Figure 2a A schematic diagram of a partial top view of a structure along the BB' direction;

[0043] Figure 3 for Figure 2a An equivalent circuit diagram of the storage array shown is presented.

[0044] Figure 4a This is a cross-sectional structural diagram of the storage array in the embodiment of this application during the fabrication process;

[0045] Figure 4b for Figure 4a A top view of the structure along the AA' direction;

[0046] Figure 5a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0047] Figure 5b for Figure 5a A top view of the structure along the AA' direction;

[0048] Figure 6a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0049] Figure 6b for Figure 6a A top view of the structure along the AA' direction;

[0050] Figure 7a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0051] Figure 7b for Figure 7a A top view of the structure along the AA' direction;

[0052] Figure 8a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0053] Figure 8b for Figure 8a A top view of the structure along the AA' direction;

[0054] Figure 9a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0055] Figure 9b for Figure 9a A top view of the structure along the AA' direction;

[0056] Figure 10a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0057] Figure 10b for Figure 10a A top view of the structure along the AA' direction;

[0058] Figure 11a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0059] Figure 11b for Figure 11a A top view of the structure along the AA' direction;

[0060] Figure 12a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0061] Figure 12b for Figure 12a A top view of the structure along the AA' direction;

[0062] Figure 13 for Figure 2a A schematic diagram of another partial top view structure along the AA' direction;

[0063] Figure 14 for Figure 2a A schematic diagram of another partial top view structure along the AA' direction;

[0064] Figure 15a This is a partial cross-sectional view of the storage array in an embodiment of this application.

[0065] Figure 15b for Figure 15a A schematic diagram of a partial top view of a structure along the AA' direction;

[0066] Figure 15c for Figure 15a A schematic diagram of a partial top view of a structure along the BB' direction;

[0067] Figure 15d for Figure 15b A schematic diagram of a partial top view of the structure along the DD' direction;

[0068] Figure 16 for Figure 15a An equivalent circuit diagram of the storage array shown is presented.

[0069] Figure 17a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0070] Figure 17b for Figure 17a A top view of the structure along the AA' direction;

[0071] Figure 18a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0072] Figure 18b for Figure 18a A top view of the structure along the AA' direction;

[0073] Figure 19a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0074] Figure 19b for Figure 19a A top view of the structure along the AA' direction;

[0075] Figure 20a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0076] Figure 20b for Figure 20a A top view of the structure along the AA' direction;

[0077] Figure 21a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0078] Figure 21b for Figure 21a A top view of the structure along the AA' direction;

[0079] Figure 22aThis is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0080] Figure 22b for Figure 22a A top view of the structure along the AA' direction;

[0081] Figure 23a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0082] Figure 23b for Figure 23a A top view of the structure along the AA' direction;

[0083] Figure 24a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0084] Figure 24b for Figure 24a A top view of the structure along the AA' direction;

[0085] Figure 25a This is another cross-sectional view of the storage array in the embodiment of this application during the fabrication process;

[0086] Figure 25b for Figure 25a A top view of the structure along the AA' direction. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0088] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0089] The storage array, memory, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0090] Figure 1This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 Electronic devices may include circuit boards ( Figure 1 (Not shown) and memory, which are electrically connected to the circuit board. Exemplarily, the electronic device may also include a processor, a cache, and a controller, etc.

[0091] For example, electronic devices include, but are not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, in-vehicle devices, or camera devices. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, and smart broadband devices. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited here. In addition, the electronic device may include only memory, or it may include both a processor and memory.

[0092] For example, the processor can be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, or a neural network processor, etc.

[0093] Reference Figure 1 The memory may include a controller and a memory array, with the controller electrically connected to the memory array, thereby enabling the controller to access the memory array. The controller may include one or more memory arrays. Exemplarily, the memory may include dynamic random access memory (DRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), etc., which will not be listed and described in detail in this application embodiment.

[0094] Figure 2a This is a partial cross-sectional view of the storage array in an embodiment of this application. Figure 2b for Figure 2a A schematic diagram of a partial top view of the structure along the AA' direction. Figure 2c for Figure 2a A partial top view of the structure along the BB' direction, see reference. Figures 2a to 2c The storage array in this embodiment may include a subarray 200, which may include multiple storage cell layers 100 stacked along the vertical direction Z. Each storage cell layer 100 includes multiple storage cells 110, thereby allowing multiple storage cells 110 to be stacked in the vertical direction Z, increasing storage capacity. Furthermore, each storage cell 110 includes a channel 111 and a capacitor 112 arranged in the horizontal direction, with the channel 111 connected to a first electrode plate 112a of the capacitor 112. This horizontal arrangement of the channel 111 and capacitor 112 in the storage cell 110 facilitates compressing the size of the storage cell 110 in the vertical direction Z, enabling the stacking of more storage cell layers 100 in the vertical direction Z, thus increasing storage capacity. Exemplarily, the storage array may include one or more subarrays 200. When multiple subarrays 200 are included, they may be arranged sequentially along a first direction X parallel to the horizontal direction.

[0095] The subarray 200 also includes multiple word lines 120, each word line 120 including interconnected word line interconnect structures 121 and multiple protrusions 122, wherein the word line interconnect structures 121 extend in the vertical direction Z, and the multiple protrusions 122 extend in the horizontal direction. The protrusions 122 can be used as gates, thereby the protrusions 122 serving as gates extend from the surface of the word line interconnect structures 121 in the horizontal direction, making the word line interconnect structures 121 and the multiple protrusions 122 an integral structure of the same material.

[0096] In this configuration, the channels 111 in the memory cells 110 stacked along the vertical direction Z in different memory cell layers 100 can be configured to at least partially surround a word line interconnect structure 121 of a word line 120, and a protrusion 122 serving as a gate is provided between two adjacent channels 111 along the vertical direction Z. This allows the channels 111 and gates to be alternately stacked in the vertical direction Z, placing them on different layers. This facilitates compressing the horizontal dimensions of the memory cells 110, enabling the arrangement of more memory cells 110 in the horizontal direction, and ultimately increasing storage capacity.

[0097] Furthermore, the protrusion 122, which serves as the gate, and the channel 111 have an overlapping area in the vertical direction Z, which allows the protrusion 122, which serves as the gate, and the channel 111 to form a transistor, and the gate is used to control the channel in order to control the switching on and off of the transistor.

[0098] Furthermore, a dielectric layer is provided between the channel 111 and the protrusion 122 and the word line interconnection structure 121, respectively, so as to isolate the protrusion 122 and the word line interconnection structure 121 from the channel 111.

[0099] Continue to refer to Figures 2a to 2c Each memory cell layer 100 also includes a bit line 130 extending along a second direction Y parallel to the horizontal direction. Channels 111 in memory cells 110 arranged along a first direction X in the same memory cell layer 100 are connected to a bit line 130. Furthermore, the subarray 200 may also include multiple board lines 140 extending along a vertical direction Z. The second electrode plates of capacitors 112 in multiple memory cells 110 stacked along the vertical direction Z are connected to a board line 140. Thus, by extending the word line 120 and board line 140 along the vertical direction Z and extending the bit line 130 along the horizontal direction, the size of the memory array in both the horizontal and vertical directions Z can be further reduced.

[0100] Figure 3 for Figure 2a An equivalent circuit diagram of the memory array shown is referenced. Figure 2a and Figure 3Word lines 120 and plate lines 140 extend vertically along the Z direction, and bit lines 130 extend along a first direction X parallel to the horizontal direction. A protrusion 122 and a channel 111 stacked along the vertical Z direction can form a transistor 111', with the protrusion 122 serving as the gate of the transistor 111'. Furthermore, a first region of the channel 111 contacts the bit line 130, establishing an electrical connection between the channel 111 and the bit line 130. A second region of the channel 111 contacts the first electrode plate 112a of the capacitor 112, also establishing an electrical connection between the channel 111 and the first electrode plate 112a of the capacitor 112. The first and second regions of the channel are spaced apart. Thus, the first region of the channel 111 can serve as the first electrode of the transistor 111', and the second region of the channel 111 can serve as the second electrode of the transistor 111'. This allows the first and second regions to remain separate, fully utilizing each region of the channel and improving the performance of the transistor 111'. Based on this, the protrusions 122 in the multiple memory cells 110 stacked along the vertical direction Z are connected to the same word line 120, and the channels 111 in the multiple memory cells 110 arranged along the first direction X in the same memory cell layer 100 are connected to the same bit line 130. Furthermore, the channels 111 in the multiple memory cells 110 arranged along the first direction X in the same memory cell layer 100 have different first electrode plates 112a of capacitors 112. During operation, if the gate control channel 111 is turned on, the transistor 111' is in the on state, and signals can be transmitted between the bit line 130 and the first electrode plate 112a of capacitor 112. This allows the signal on the bit line 130 to be transmitted to the first electrode plate 112a of capacitor 112, or the signal stored in the first electrode plate 112a to be output to the bit line 130, so as to read the signal stored in capacitor 112. If the gate control channel 111 is disconnected, the transistor 111' is in the off state, and no signal can be transmitted between the bit line 130 and the first electrode plate 112a of the capacitor 112. The capacitor 112 then retains the stored signal.

[0101] In some embodiments, refer to Figure 2aIn the vertical direction Z, the channel 111 and the protrusion 122 serving as the gate are alternately stacked, such that the protrusion 122 and the channel 111 are disposed on different layers, and the protrusion 122 is a portion of the word line 120. Therefore, during fabrication, the gate dielectric layer 115 can be fabricated first, followed by the channel 111 and the first dielectric layer 113, and then the word line 120. Since the gate dielectric layer 115 and the first dielectric layer 113 are located between the channel 111 and the word line 120, damage to the channel 111 can be avoided when forming the protrusion 122 serving as the gate. Based on this, in some embodiments, an oxide semiconductor material that is more sensitive to the growth atmosphere can be used to fabricate the channel 111 to meet performance requirements. In addition, the heat generated during the fabrication of the gate dielectric layer 115 can be avoided from affecting the channel layer. Therefore, the material of the channel 111 in the embodiments of this application can be set as an oxide semiconductor material, which may contain one or more of the elements such as In, Ga, Zn, Sn, W, Mg, Al, and Si. For example, the oxide semiconductor material may include, but is not limited to, IGZO, InGaZnO, InSnO, InGaO, InMgO, etc. During fabrication, atomic layer deposition can be used to form the oxide semiconductor material. Furthermore, the material of the channel 111 can be an amorphous structure or a partially crystalline structure (such as poly-IGZO, CAAC-IGZO). Of course, in other embodiments, the material of the channel 111 may also include other channel materials, such as polycrystalline silicon (poly-Si), amorphous silicon (a-Si), etc.

[0102] Since the protrusion 122, which serves as the gate, and the channel 111 are alternately stacked in the vertical direction Z, and the bit line 130 and the channel 111 are disposed in the same layer, in order to avoid short circuit between the protrusion 122 and the bit line 130, the surface of the protrusion 122 facing away from the word line interconnect structure 121 in the horizontal direction can also be covered by the gate dielectric layer 115 to achieve insulation.

[0103] It is understood that during the fabrication process, a memory array is typically formed on a substrate. Therefore, in this embodiment, the vertical direction Z can be perpendicular to the substrate, and the horizontal direction can be parallel to the substrate, making the horizontal direction and vertical direction Z perpendicular to each other. Furthermore, in this embodiment, the second direction Y and the first direction X are both parallel to the horizontal direction. For example, the second direction Y intersects the first direction X; for instance, the second direction Y is perpendicular to the first direction X.

[0104] Reference Figure 2aIn some embodiments of this application, to improve the adhesion of the metal and block hydrogen diffusion, the word line 120 can be configured as a stacked structure. For example, the word line 120 may include a word line metal layer 120a and a word line blocking layer 120b, with the word line blocking layer 120b disposed between the word line metal layer 120a, the gate dielectric layer 115, and the first dielectric layer 113. Thus, the protrusion 122 may include the word line metal layer 120a and the word line blocking layer 120b, and the word line interconnect structure 121 may also include the word line metal layer 120a and the word line blocking layer 120b. Exemplarily, the material of the word line metal layer 120a includes, but is not limited to, metals or alloys such as W, Ru, Ni, Mo, Ni, and Pt, and the material of the word line blocking layer 120b includes, but is not limited to, conductive nitrides (e.g., TiN, TaN) and conductive oxides (e.g., ITO, InSnO). In other embodiments of this application, the word line may be formed using the word line metal layer 120a instead of the word line blocking layer 120b. Furthermore, when the word line 120 is configured as a stacked structure, the thickness of the word line metal layer 120a in the protrusion 122 in the vertical direction Z can be 15nm to 60nm. For example, the thickness of the word line metal layer 120a in the vertical direction Z in the protrusion 122 can be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc., and is not limited here. Also, the critical dimension (CD) of the word line interconnect structure 121 in the horizontal direction is less than or equal to 150nm, which ensures that the overall area of ​​the memory cell 110 is small. For example, the CD of the word line interconnect structure 121 in the horizontal direction can be 50nm, 80nm, 100nm, 120nm, 150nm, etc., and is not limited here.

[0105] Exemplarily, capacitor 112 may have a first electrode plate 112a, a second electrode plate, and an electrode dielectric layer 112b. The electrode dielectric layer 112b is disposed between the first electrode plate 112a and the second electrode plate of capacitor 112 to isolate the first electrode plate 112a and the second electrode plate. Exemplarily, the material of electrode dielectric layer 112b may be a high dielectric constant (k) material, such as ZrO, HfO, TiO, AlO, NbO, or their stacked structures, such as ZrO / AlO / ZrO structure. Furthermore, the materials of the first electrode plate 112a and the second electrode plate include, but are not limited to, metals or alloys such as W, Ru, Ni, Mo, Ni, Pt, etc., or conductive nitrides (e.g., TiN, TaN, etc.) and conductive oxides (e.g., ITO). Furthermore, the thickness of the first electrode plate 112a can be set to 2nm to 15nm. For example, the thickness of the first electrode plate 112a can be set to 2nm, 5nm, 10nm, 15nm, etc., and is not limited here. The thickness of the electrode dielectric layer 112b can be set to 4nm to 10nm. For example, the thickness of the electrode dielectric layer 112b can be set to 4nm, 8nm, 10nm, etc., and is not limited here.

[0106] Exemplarily, the dielectric layer between the gate protrusion 122 and the channel 111 can be a gate dielectric layer 115, which isolates the gate protrusion 122 and the channel 111. Exemplarily, the gate dielectric layer 115 may be, for example, an oxide dielectric layer, a nitride dielectric layer, or a combination thereof. For example, the material of the oxide dielectric layer may include, for example, HfO2, Al2O3, SiO2, HfSiO, etc. The material of the nitride dielectric layer may include, for example, SiN. Furthermore, the thickness of the gate dielectric layer 115 may be set to 2nm to 10nm, for example, the thickness of the gate dielectric layer 115 may be set to 2nm, 5nm, 8nm, 10nm, etc., and is not limited herein.

[0107] Exemplarily, the dielectric layer between the word line interconnect structure 121 and the channel 111 can be a first dielectric layer 113, used to isolate the word line interconnect structure 121 and the channel 111. Exemplarily, the material of the first dielectric layer 113 is an insulating material, for example, including but not limited to one or more of oxides and nitrides. For example, the material of the first dielectric layer 113 includes but is not limited to SiO2, SiN, SiOC, SiON, SiCN, Ga2O3, Al2O3, etc. Furthermore, the thickness of the first dielectric layer 113 in the first direction X can be set to 5nm to 20nm, for example, the thickness of the first dielectric layer 113 in the first direction X can be set to 5nm, 10nm, 15nm, 20nm, etc., without limitation.

[0108] In some embodiments, the gate dielectric layer 115 is made of a different material than the first dielectric layer 113; for example, a material with a high degree of etching selectivity may be used. In other embodiments, the gate dielectric layer 115 and the first dielectric layer 113 may be made of the same material.

[0109] Reference Figure 2b To reduce the horizontal dimensions of the memory cells 110 and save the area occupied by the channels in the horizontal direction, the channels 111 can be configured as annular channels arranged in the horizontal direction. An annular channel refers to a channel whose cross-section parallel to the horizontal direction has a closed annular structure, which can be a circular ring, a square ring, or other feasible shapes. For example, each channel 111 can be arranged around the word line interconnect structure 121 with a first dielectric layer 113 in between; that is, in the horizontal direction, the channel 111 can be arranged to surround the word line interconnect structure 121 in a complete circle. Thus, multiple annular channels stacked in the vertical direction Z can be arranged around the word line interconnect structure 121, so that the word line interconnect structure 121 is located inside the annular structure of the channel 111, thereby further reducing the horizontal dimensions of the memory array.

[0110] To improve gate control capability, the protrusion 122 serving as the gate can be arranged to surround the word line interconnect structure 121, that is, the protrusion 122 is also arranged to surround the word line interconnect structure 121 in the horizontal direction. This maximizes the overlap area between the protrusion 122 serving as the gate and the channel 111 in the vertical Z direction, increasing the facing area between the protrusion 122 serving as the gate and the channel 111, thereby improving gate control capability.

[0111] Reference Figure 2a To further improve gate control capability, the orthographic projection of the channel 111 onto the substrate can fall within the orthographic projection of the protrusion 122 onto the substrate. For example, the thickness of the annular channel can be set to 5 nm to 20 nm, and the width between the outer and inner boundaries of the orthographic projection of the protrusion 122 onto the plane containing the first direction X and the second direction Y can be set to 10 nm to 100 nm. In some embodiments, the distance between the outer boundary of the orthographic projection of the channel onto the substrate and the outer boundary of the orthographic projection of the protrusion 122 onto the substrate can be no greater than 20 nm. Alternatively, the orthographic projection of the channel onto the substrate can overlap with the orthographic projection of the protrusion serving as the gate onto the substrate.

[0112] Reference Figure 2bIn each memory cell 110, the channel 111 and capacitor 112 can be arranged along a first direction X parallel to the horizontal direction. Furthermore, the channel 111 is located between the bit line 130 connected to it and the capacitor 112. Thus, the first and second regions of the channel 111 can be respectively positioned on opposite sides of the channel in the first direction X, allowing the first and second regions to remain non-contacting and fully utilizing each region of the annular channel. Furthermore, the channel 111 and capacitor 112 can be arranged closely in the horizontal direction, further compressing the horizontal dimensions of the memory cell 110.

[0113] Reference Figure 2b In the horizontal direction, the annular channel can be rectangular to shorten the spacing between adjacent memory cells 110 arranged in an array in the horizontal direction, achieving a compact arrangement and improving storage density in the horizontal direction. For example, the rectangle of the annular channel can have a first side 111_1, a second side 111_2, a third side 111_3, and a fourth side 111_4 connected in sequence. The first side 111_1 and the third side 111_3 are two sides arranged opposite each other along a first direction X, and the second side 111_2 and the fourth side 111_4 are two sides arranged opposite each other along a second direction Y. The first region of the channel may include the first side, and the second region may include the third side.

[0114] Reference Figure 2aTo improve gate control capability, the channel 111 can include a first channel portion 1111, a second channel portion 1112, and a third channel portion 1113 connected in sequence. The first channel portion 1111 and the third channel portion 1113 extend in the horizontal direction, and the second channel portion 1112 extends in the vertical direction Z. Thus, the first channel portion 1111, the second channel portion 1112, and the third channel portion 1113 can surround and form a first groove AX1 extending in the horizontal direction, and the opening of the first groove AX1 faces the word line interconnection structure 121. In other words, since the channel is a horizontally arranged annular channel, the first channel portion 1111 and the third channel portion 1113 extend horizontally to form an annular structure, and the first channel portion 1111 and the third channel portion 1113 are respectively arranged around the word line interconnection structure 121, so that the portion of the first channel portion 1111 and the third channel portion 1113 surrounding the inner side of the word line interconnection structure 121 can form the opening of the first groove AX1. Furthermore, the second channel portion 1112 extends in the vertical direction Z, and the second channel portion 1112 is also arranged around the word line interconnection structure 121, so that the second channel portion 1112 forms the bottom of the first groove AX1. Therefore, while keeping the overlap area between the protrusion 122 and the channel 111 in the vertical direction Z unchanged, the thickness of the channel can be reduced to improve gate control capability. For example, in two memory cells 110 stacked along the vertical direction Z, a protrusion 122 serving as a gate can be provided between the third channel portion 1113 of the channel 111 of one memory cell 110 and the first channel portion 1111 of the channel 111 of the other memory cell 110. This configuration allows the third channel portion 1113 of one channel 111 and the first channel portion 1111 of the other channel 111 to be controlled by the same protrusion 122 serving as a gate, so that the third channel portion 1113 and the first channel portion 1111 share the same gate, improving control synchronization and further reducing the size of the memory array in the vertical direction Z.

[0115] Reference Figure 2a By making the channel 111 include a first channel portion 1111, a second channel portion 1112 and a third channel portion 1113 connected in sequence, the cross section of the channel 111 parallel to the vertical direction Z can be a groove-shaped cross section, which can be a "U" shape, a "C" shape or other feasible shapes.

[0116] Reference Figure 2a and Figure 2bIn some embodiments of this application, the area where the channel 111 and the bit line 130 are in contact with each other can be the second channel portion 1112 in the first side, so that the interconnection between the channel 111 and the bit line 130 can be achieved without occupying the area of ​​the first channel portion 1111 and the third channel portion 1113.

[0117] Reference Figure 2a and Figure 2b The first groove AX1 may also be filled with a second dielectric layer 116 to improve the stability of the channel 111. Exemplarily, the material of the second dielectric layer 116 is an insulating material, for example, including but not limited to one or more of oxides and nitrides. For example, the material of the second dielectric layer 116 includes, but is not limited to, SiO2, SiN, SiOC, SiON, SiCN, Al2O3, etc. Furthermore, the materials of the first dielectric layer 113 and the second dielectric layer 116 may be the same or different.

[0118] In other embodiments of this application, the thickness of the second dielectric layer 116 in the vertical direction Z can be reduced, and a word line interconnect structure 121 can be used as the back gate of the channel 111 to provide additional gate control, increase the on-state current of the device, and reduce the leakage current of the transistor. Furthermore, when the thickness of the second dielectric layer 116 in the vertical direction Z is reduced to zero, it is equivalent to not having a second channel portion 1112 in the channel 111, meaning the first channel portion 1111 and the third channel portion 1113 are in contact with each other. This further increases the on-state current of the device and reduces the leakage current of the transistor.

[0119] Reference Figure 2a and Figure 2cIn some embodiments of this application, a bit line insulating layer 150 may be provided between two adjacent bit lines 130 in the vertical direction Z, which can reduce the parasitic capacitance between the bit lines 130 and between the bit lines 130 and the protrusion 122 serving as the gate, thereby reducing leakage current. Exemplarily, the material of the bit line insulating layer 150 is an insulating material, for example, including but not limited to one or more of oxides and nitrides. For example, the material of the bit line insulating layer 150 can be a high dielectric constant (k) material, such as, but not limited to, SiO2, SiOF, SiOC, SiON, SiCN, or their stacked structures. Furthermore, it is understood that, for SiOC material, due to its small dielectric constant, using SiOC as the bit line insulating layer 150 can result in extremely low parasitic capacitance between the bit lines and between the bit lines and the protrusion 122, achieving extremely low interlayer parasitic capacitance. In other embodiments of this application, since the dielectric constant of the gas is also low, a gas gap can also be provided between two adjacent bit lines 130 in the vertical direction Z, thereby effectively reducing the parasitic capacitance between bit lines 130 and between bit lines 130 and protrusions 122. Exemplarily, the gas in the gas gap can be air, making the gas gap an air gap. Alternatively, the gas in the gas gap can also be an inert gas or other chemically inert gas, which is not limited here.

[0120] In some embodiments of this application, the bit lines can be configured as a stacked structure to improve electrical contact performance. For example, refer to... Figure 2a and Figure 2bThe bit line 130 may include a bit line metal layer 131 and a bit line contact layer 132. The bit line contact layer 132 is disposed between the bit line metal layer 131 and the channel 111 to reduce contact resistance. Further, to improve the adhesion of the bit line metal layer 131, the bit line contact layer 132 may also be disposed between the bit line metal layer 131 and the bit line insulating layer 150 to improve the bonding force between the bit line metal layer 131 and the bit line insulating layer 150. Exemplarily, the material of the bit line metal layer 131 includes, but is not limited to, metals or alloys such as W, Ru, Ni, Mo, NiPt, and Pt. The material of the bit line contact layer 132 includes, but is not limited to, metal or nitride or alloy electrodes such as W, Ni, Mo, Ru, NiPt, and TiN. Conductive oxides may also be used as buffer contact layers, such as InSnO, AlZnO, and InGaO. In some other embodiments of this application, the bit line may not be provided with a bit line contact layer 132, and instead, the bit line may be formed using the bit line metal layer 131. Furthermore, when the bit line is configured as a stacked structure, the thickness of the bit line metal layer 131 in the vertical direction Z can be 15nm to 60nm. For example, the thickness of the bit line metal layer 131 in the vertical direction Z can be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc., and is not limited here.

[0121] Reference Figure 2a and Figure 2b In some embodiments of this application, to increase the capacitance value, the first electrode plate 112a of capacitor 112 can be configured as a ring-shaped electrode plate arranged in the horizontal direction. This allows the first electrode plate 112a of capacitor 112 in multiple memory cells 110 stacked along the vertical direction Z to be arranged around one of the multiple plate lines 140, separated by an electrode dielectric layer 112b, thereby achieving a larger capacitance in a limited area. Furthermore, the plate line 140 can be disposed inside the memory cell 110 in the vertical direction Z, eliminating the need for the plate line 140 to occupy additional area in the horizontal direction, further increasing the density of memory cells 110 in the horizontal direction. Additionally, the plate line 140 can be directly used as the second electrode plate of capacitor 112, reducing the area occupied by the capacitor in the horizontal direction. Exemplarily, a ring-shaped electrode plate refers to the first electrode plate 112a having a closed ring structure in the horizontal direction. This ring structure can be a circular ring, a square ring, or other feasible shapes. (Refer to...) Figure 2a and Figure 2b In the horizontal direction, the first electrode plate 112a is arranged around the plate line, and the plate line portion surrounded by the first electrode plate 112a can serve as the second electrode plate of the capacitor 112.

[0122] In some embodiments of this application, to improve the adhesion of the metal and block hydrogen diffusion, the board line can be configured as a stacked structure. For example, the board line may include a board line metal layer and a board line barrier layer, with the board line barrier layer disposed between the board line metal layer and the electrode dielectric layer. Exemplarily, the material of the board line metal layer includes, but is not limited to, metals or alloys such as W, Ru, Ni, Mo, NiPt, etc., and the material of the board line barrier layer includes, but is not limited to, metal or nitride or alloy electrodes such as W, Ni, Mo, Ru, NiPt, TiN, or conductive oxides as buffer contact layers, such as InSnO. In other embodiments of this application, a board line barrier layer may be omitted, and a board line metal layer may be used to form the bit line instead. Furthermore, a horizontal CD of less than or equal to 300 nm ensures a small overall area of ​​the memory cell. For example, the horizontal CD of the board line can be 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 250 nm, 300 nm, etc., and is not limited here.

[0123] Reference Figure 2a and Figure 2b In some embodiments of this application, in order to increase the capacitance, the first electrode plate 112a may have a second groove AX2 extending horizontally in the horizontal direction. The opening of the second groove AX2 faces the plate line 140, and the plate line 140 extends into the second groove AX2, so that the portion of the plate line 140 extending into the second groove AX2 serves as the second electrode plate of the capacitor 112. This not only increases the capacitance but also reduces manufacturing costs.

[0124] Figures 4a to 12b for Figure 2a The diagram shows the structure of the storage array after each step of the fabrication process.

[0125] Reference Figures 4a to 12b The storage array provided in this application embodiment can be fabricated using the following process flow, which may include:

[0126] Step 1, refer to Figure 4a and Figure 4bMultiple bit line insulating layers 150 and multiple channel insulating layers 311 are alternately deposited on a substrate. Then, word line vias 312 are formed penetrating the multiple bit line insulating layers 150 and the multiple channel insulating layers 311. Next, the bit line insulating layers 150 are selectively etched laterally within the word line vias 312, forming multiple first trenches GC1 within the word line vias 312. Then, gate dielectric layers 115 are deposited on the sidewalls and bottomwalls of the first trenches GC1. Then, dummy gate structures 313 are filled within the first trenches GC1 where the gate dielectric layers 115 are deposited. Exemplarily, the materials of the bit line insulating layers 150, channel insulating layers 311, and dummy gate structures 313 can be insulating materials, metallic materials, etc. For example, insulating materials include, but are not limited to, one or more of oxides and nitrides. For example, the materials include, but are not limited to, SiO2, SiN, SiOC, SiON, SiCN, etc. Furthermore, the materials of the bit line insulating layers 150, channel insulating layers 311, and dummy gate structures 313 can be different. To achieve a high etching selectivity, the bit line insulating layer 150, the channel insulating layer 311, and the dummy gate structure 313 can be made of materials with high etching selectivity. For example, the bit line insulating layer 150 can be made of SiO2, the channel insulating layer 311 can be made of SiN, and the dummy gate structure 313 can be made of W.

[0127] Step 2, refer to Figure 5a and Figure 5b The insulating layer 311 of the channel is selectively etched laterally within the word line hole 312 to form the channel groove 321.

[0128] Step 3, refer to Figure 6a and Figure 6b A first insulating sacrificial material layer 314 is filled into the word line hole 312. Then, the channel insulating layer 311 on one side of the word line hole 312 is etched away to form a bit line trench 322. Exemplarily, the first insulating sacrificial material layer 314 is an insulating material, for example, including but not limited to one or more of oxides and nitrides. For example, its material includes but is not limited to SiO2, SiN, SiOC, SiON, SiCN, etc. Furthermore, the materials of the first insulating sacrificial material layer 314, the bit line insulating layer 150, the channel insulating layer 311, and the dummy gate structure 313 are different. To achieve a high etching selectivity, the first insulating sacrificial material is a material with a high etching selectivity, respectively, as are the bit line insulating layer 150, the channel insulating layer 311, and the dummy gate structure 313.

[0129] Step 4, refer to Figure 7a and Figure 7bBit line contact layer 132 and bit line metal layer 131 are sequentially deposited in bit line trench 322 to form bit lines. Then, board line vias penetrating multiple bit line insulating layers 150 and multiple channel insulating layers 311 are formed on the other side of word line via 312. Channel insulating layers 311 are selectively etched laterally within the board line vias to form board line trenches. Then, electrode dielectric layer 112b and board line 140 are sequentially deposited in the board line vias.

[0130] Step 5, refer to Figure 8a and Figure 8b The first insulating sacrificial material layer 314 in the word line hole 312 is etched away. Then, a channel layer 511 is formed on the sidewall of the word line hole 312. Next, a second dielectric layer 116 is filled into the word line hole 312 where the channel layer 511 is formed. Exemplarily, an ALD process can be used to deposit an oxide semiconductor material on the sidewall of the word line hole 312 to form the channel layer 511.

[0131] Step 6, refer to Figure 9a and Figure 9b The second dielectric layer 116 in the word line hole 312 is etched away. Then, the channel layer 511 is selectively etched laterally within the word line hole 312, retaining the channel layer 511 between the second dielectric layer 116 and the gate dielectric layer 115 and the first electrode plate 112a, and removing the remaining area of ​​the channel layer 511. Exemplarily, the channel layer 511 can be further etched to form a channel recess 332 between the channel layer 511 and the second dielectric layer 116 and the primary gate dielectric layer 115, improving gate control capability. This forms the channel 111.

[0132] Step 7, refer to Figure 10a and Figure 10b A first dielectric layer 113 is deposited in the channel recess 332 to protect the channel 111. In some examples, the first dielectric layer 113 may also be deposited on the sidewall of the second dielectric layer 116 facing the word line hole 312.

[0133] Step 8, refer to Figure 11a and Figure 11b The pseudo-gate structure 313 is removed by selective lateral etching within the word line hole 312.

[0134] Step 9, refer to Figure 12a and Figure 12b A word line blocking layer 120b is deposited on the sidewall of the word line via 312, and then a word line metal layer 120a is deposited in the word line via 312 where the word line blocking layer 120b is deposited. The word line blocking layer 120b and the word line metal layer 120a filling the first trench GC1 are protrusions 122 serving as gates.

[0135] Therefore, the channel 111 and word line 120 can be integrated into the same word line via 312, and the channel 111 and the protrusion 122 serving as the gate can be disposed in different layers. This facilitates the reduction of the horizontal dimension of the memory cell 110, making it easier to accommodate more memory cells 110 in the horizontal direction and thus increasing storage capacity. Furthermore, by forming the gate dielectric layer 115 and the first dielectric layer 113 before forming the channel 111, damage to the channel 111 can be avoided when forming the word line 120.

[0136] Figure 13 for Figure 2a A schematic diagram of another partial top view structure along the AA' direction, see reference. Figure 13 This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated. For example, to further reduce the horizontal dimensions of the storage unit 110 and save the area occupied by the channel in the horizontal direction, the channel 111 can be configured as a groove-shaped channel arranged in the horizontal direction. A groove-shaped channel refers to a channel with an opening in the horizontal direction, i.e., an unclosed shape in the horizontal direction. This groove-shaped channel can be a "U"-shaped groove-shaped channel, a "C"-shaped groove-shaped channel, or other feasible shapes. Based on this, the cross-section of the channel 111 parallel to the horizontal direction can be a groove-shaped cross-section, which can be a "U"-shaped, "C"-shaped, or other feasible shapes.

[0137] Furthermore, to further reduce the size of the storage array in the horizontal direction, the word line interconnect structure 121 can be disposed in the groove of the channel 111, that is, in the horizontal direction, the channel 111 partially surrounds the word line interconnect structure 121. For example, in the horizontal direction, the channel 111 is disposed in a half-circle around the word line interconnect structure 121.

[0138] To improve gate control capability, the protrusion 122 serving as the gate can be partially disposed around the word line interconnect structure 121. For example, in the horizontal direction, the protrusion 122 can also be disposed half-circle around the word line interconnect structure 121. As a result, the overlap area between the protrusion 122 serving as the gate and the channel 111 in the vertical direction Z can be increased as much as possible, and the facing area between the protrusion 122 and the channel 111 can be increased, thereby improving gate control capability.

[0139] In some embodiments, refer to Figure 13 In the same memory cell layer 100, in the second direction Y, the openings of the channels 111 of two adjacent memory cells 110 are directly opposite each other in the horizontal direction. Thus, during the fabrication process, the annular channel can be divided into two by etching, which not only reduces the complexity of the fabrication process but also increases the density of the memory cells 110.

[0140] In some embodiments, in order to further compress the horizontal dimensions of the storage cell 110, refer to Figure 13 The distance h12 between the channels 111 of two adjacent memory cells 110 in the second direction Y can be the same as the distance h22 between the first electrode plates 112a of two adjacent memory cells 110 in the second direction Y. It is understood that due to limitations in process conditions or other factors, some deviations or errors may exist in actual processes, causing the "same" described above to be not entirely accurate. For example, the "same" described above can be the same as that allowed within the allowable error range. Of course, "same" can also be understood as "substantially the same" or "completely the same." Therefore, the "same" relationship described above is acceptable as long as it roughly meets the above conditions, and all fall within the scope of protection of this application.

[0141] In some embodiments, refer to Figure 13 Alternatively, the length h11 of the channel 111 in the second direction Y can be less than the length h21 of the first electrode plate 112a in the second direction Y. Or, the length h11 of the channel 111 in the second direction Y can be greater than or equal to the length h21 of the first electrode plate 112a in the second direction Y.

[0142] Figure 14 for Figure 2a A schematic diagram of another partial top view structure along the AA' direction, see reference. Figure 14 This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated. For example, in the same memory cell 110, the capacitor 112 can be disposed on the side of the channel 111 opposite to its horizontal opening, thereby further compressing the size of the memory cell 110 in the first direction X. In some embodiments, the width h13 of the channel 111 in the first direction X can be greater than the width h23 of the first electrode plate 112a of the capacitor 112 in the first direction X, thereby preventing short circuits between the first electrode plate 112a of the capacitor 112 and the bit lines, improving the security of the memory array.

[0143] Figure 15a This is a partial cross-sectional view of another storage array in an embodiment of this application. Figure 15b for Figure 15a A schematic diagram of a partial top view of the structure along the AA' direction. Figure 15c for Figure 15a A schematic diagram of a partial top view of the structure along the BB' direction. Figure 15d for Figure 15b A partial top-view structural diagram along the DD' direction, refer to... Figures 15a to 15dThis embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here. For example, the memory array in this application embodiment may include a subarray 200, which may include multiple memory cell layers 100 stacked along the vertical direction Z. Each memory cell layer 100 includes multiple memory cells 110, thereby allowing the multiple memory cells 110 to be stacked in the vertical direction Z, increasing storage capacity. Furthermore, each memory cell 110 includes a transistor and a capacitor 112. The transistor includes a first channel 111a, a second channel 111b, and a gate 123, with the first channel 111a and the second channel 111b stacked along the vertical direction Z. Furthermore, in the same memory cell 110, the first electrode plate 112a of the gate 123 and the capacitor 112 are arranged in the horizontal direction. This arrangement of the gate 123 and the capacitor 112 in the memory cell 110 in the horizontal direction is beneficial to compressing the size of the memory cell 110 in the vertical direction Z, which facilitates the stacking of more memory cell layers 100 in the vertical direction Z and helps to increase the storage capacity.

[0144] Furthermore, the gate 123 and the first electrode plate 112a are respectively disposed between the first channel 111a and the second channel 111b. Thus, by disposing the gate 123 and the first channel 111a and the second channel 111b on different layers, it is possible to further compress the size of the memory cell 110 in the horizontal direction, achieve a compact arrangement, and improve the storage density in the horizontal direction.

[0145] Furthermore, the gate 123 and the first electrode plate 112a overlap with the first channel 111a and the second channel 111b in the vertical direction Z, respectively. That is, the orthographic projection of the gate 123 onto the substrate overlaps with the orthographic projections of the first channel 111a and the second channel 111b onto the substrate, respectively. Similarly, the orthographic projection of the first electrode plate 112a onto the substrate also overlaps with the orthographic projections of the first channel 111a and the second channel 111b onto the substrate. Therefore, in the horizontal direction, at least a portion of the gate 123 and the first electrode plate 112a are embedded in the space between the first channel 111a and the second channel 111b. This further facilitates compressing the size of the memory cell 110 in the horizontal direction, achieving a compact arrangement, and thus improving the storage density in the horizontal direction.

[0146] Furthermore, a dielectric layer is disposed between the gate 123 and the first electrode plate 112a, the first channel 111a, and the second channel 111b, respectively, to insulate the gate 123 from the first electrode plate 112a, the first channel 111a, and the second channel 111b. For example, the dielectric layer between the gate 123 and the first electrode plate 112a, the first channel 111a, and the second channel 111b may be a gate dielectric layer 115.

[0147] Continue to refer to Figures 15a to 15d The memory array also includes multiple word lines 120 extending along a first direction X parallel to the horizontal direction. One of the word lines 120 is disposed between the first channel 111a and the second channel 111b of the memory cell 110. Furthermore, the portion of the word line 120 overlapping with the first channel 111a and the second channel 111b in the vertical direction Z is used as the gate 123. That is, using a portion of the word line 120 as the gate 123 can further compress the size of the memory array in both the horizontal and vertical directions Z.

[0148] In some embodiments of this application, to improve the adhesion of the metal and block hydrogen diffusion, the word line can be configured as a stacked structure. For example, the word line may include a word line metal layer and a word line blocking layer, with the word line blocking layer disposed between the word line metal layer and the gate dielectric layer. Thus, the gate may include a word line metal layer and a word line blocking layer. Exemplarily, the material of the word line metal layer includes, but is not limited to, metals or alloys such as W, Ru, Ni, Mo, Ni, and Pt, and the material of the word line blocking layer includes, but is not limited to, conductive nitrides (e.g., TiN, TaN) and conductive oxides (e.g., ITO, InSnO). In other embodiments of this application, the word line may be formed using a word line metal layer instead of a word line blocking layer. Furthermore, when the word line is configured as a stacked structure, the thickness of the word line metal layer in the vertical direction can be 15nm to 60nm. For example, the thickness of the word line metal layer in the vertical direction can be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc., and is not limited herein.

[0149] Continue to refer to Figures 15a to 15dThe memory array also includes multiple bit lines 130 and multiple board lines 140 extending along the vertical direction Z. The first channel 111a and the second channel 111b of multiple memory cells 110 stacked along the vertical direction Z in different memory cell layers 100 are connected to one of the bit lines 130. Furthermore, the second electrode plate of each capacitor 112 in the multiple memory cells 110 stacked along the vertical direction Z in different memory cell layers 100 is connected to one of the board lines 140. Thus, by extending the bit lines 130 and board lines 140 along the vertical direction Z and extending the word lines 120 along the horizontal direction, the size of the memory array in both the horizontal and vertical directions Z can be further reduced.

[0150] In some embodiments of this application, reference is made to Figure 15a To improve electrical contact performance, the bit line 130 can be configured as a stacked structure. For example, the bit line 130 may include a bit line metal layer 131 and a bit line contact layer 132. The bit line contact layer 132 is disposed between the bit line metal layer 131 and the first channel 111a and the second channel 111b, reducing contact resistance. Furthermore, to improve the adhesion of the bit line metal layer 131, the bit line contact layer 132 can be disposed between the bit line metal layer 131 and the bit line insulating layer 150, improving the bonding force between the bit line metal layer 131 and the bit line insulating layer 150. Exemplarily, the material of the bit line metal layer 131 includes, but is not limited to, metals or alloys such as W, Ru, Ni, Mo, NiPt, and Pt. The material of the bit line contact layer 132 includes, but is not limited to, metal or nitride or alloy electrodes such as W, Ni, Mo, Ru, NiPt, and TiN. Conductive oxides can also be used as buffer contact layers, such as InSnO, AlZnO, and InGaO. In other embodiments of this application, the bit line contact layer 132 may be omitted, and instead, a bit line metal layer 131 may be used to form the bit line 130. Furthermore, the CD (displacement density) of the bit line in the horizontal direction is less than or equal to 150 nm, which ensures a small overall area of ​​the memory cell 110. For example, the CD of the word line in the horizontal direction can be 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, etc., and is not limited here.

[0151] Figure 16 for Figure 15a An equivalent circuit diagram of the memory array shown is referenced. Figure 16Bit line 130 and plate line 140 extend along the vertical direction Z, and word line 130 extends along a first direction X parallel to the horizontal direction. Transistor 111' has a first channel 111a, a second channel 111b, and a gate disposed between the first channel 111a and the second channel 111b. The first channel 111a and the second channel 111b are connected between bit line 130 and the first electrode plate 112a of capacitor 112. Gate 123 is electrically connected to word line 120. Based on this, if gate 123 controls the first channel 111a and the second channel 111b to conduct, transistor 111' is in the conducting state and can transmit signals between bit line 130 and the first electrode plate 112a of capacitor 112, so as to transmit the signal on bit line 130 to the first electrode plate 112a of capacitor 112 or output the signal stored in the first electrode plate 112a to the bit line, so as to read the signal stored in capacitor 112. If the gate 123 controls the first channel 111a and the second channel 111b to be disconnected, then the transistor 111' is in the off state, and no signal can be transmitted between the bit line 130 and the first electrode plate 112a of the capacitor 112. Therefore, the capacitor 112 retains the stored signal.

[0152] In some embodiments, refer to Figure 15aIn the vertical Z direction, the first channel 111a, gate 123, and second channel 111b are alternately stacked, such that the gate 123 is disposed on a different layer from the first channel 111a and the second channel 111b, respectively. Therefore, during fabrication, the gate dielectric layer 115 and the gate 123 can be fabricated first, followed by the first channel 111a and the second channel 111b, avoiding damage to the first channel 111a and the second channel 111b during the formation of the gate dielectric layer 115 and the gate 123. Furthermore, oxide semiconductor materials, which are more sensitive to the growth atmosphere, can be used to fabricate the first channel 111a and the second channel 111b to meet performance requirements. Additionally, the heat generated during the fabrication of the word lines and the gate dielectric layer 115 can be avoided from affecting the first channel 111a and the second channel 111b. Based on this, the materials of the first channel 111a and the second channel 111b in the embodiments of this application can be set as oxide semiconductor materials. Oxide semiconductor materials can, for example, contain one or more elements selected from In, Ga, Zn, Sn, W, Mg, Al, and Si. Exemplarily, oxide semiconductor materials can include, but are not limited to, IGZO, InGaZnO, InSnO, InGaO, and InMgO. During fabrication, atomic layer deposition can be used to form the oxide semiconductor material. The materials of the first channel 111a and the second channel 111b can be amorphous or partially crystalline (e.g., poly-IGZO, CAAC-IGZO). Of course, in other embodiments, the materials of the first channel 111a and the second channel 111b can also include other channel materials, such as polycrystalline silicon (poly-Si) and amorphous silicon (a-Si).

[0153] In some embodiments, refer to Figure 15c To avoid a large parasitic capacitance between the gate 123 and the first electrode plate 112a of the capacitor 112, the gate 123 can be configured as a groove-shaped gate arranged in the horizontal direction, and the first electrode plate 112a can be disposed at the open end of the gate 123 in the horizontal direction. A groove-shaped gate refers to the gate 123 having a groove 1221 in its cross-section parallel to the horizontal direction. This groove-shaped gate can have a U-shape, a C-shape, or other feasible shapes in its cross-section parallel to the horizontal direction. Furthermore, insulating material is filled into the groove in the cross-section of the gate 123 parallel to the horizontal direction to improve the stability of the gate 123.

[0154] Furthermore, referring to Figures 15a to 15dThe gate 123 does not have a gate dielectric layer 115 disposed on the sidewall of the groove 1221 with a cross-section parallel to the horizontal direction. Exemplarily, the gate 123 can be formed from a portion of the word line 120. Since the gate 123 does not have a gate dielectric layer 115 disposed on the sidewall of the groove 1221 with a cross-section parallel to the horizontal direction, the gate dielectric layer 115 disposed between the word line 120 and the first electrode plate 112a can be discontinuous in the second direction Y, while the gate dielectric layer 115 disposed on the side of the word line 120 facing the bit line 130 can be continuous in the second direction Y. Furthermore, the gate dielectric layer 115 disposed on the upper and lower surfaces of the word line 120 in the vertical direction Z can also be continuous in the second direction Y and the first direction X.

[0155] In some embodiments, refer to Figure 15a To reduce the horizontal dimensions of the memory cell 110 and save the area occupied by the first channel 111a and the second channel 111b in the horizontal direction, the first channel 111a and the second channel 111b can be configured as annular channels arranged in the horizontal direction. An annular channel refers to a channel whose cross-section parallel to the horizontal direction has a closed annular structure; this annular structure can be a circular ring, a square ring, or other feasible shapes. In some examples, the first channel 111a and the second channel 111b completely overlap in the vertical direction Z, that is, the orthographic projection of the first channel 111a onto the substrate and the orthographic projection of the second channel 111b onto the substrate completely overlap, further saving the area occupied by the first channel 111a and the second channel 111b in the horizontal direction.

[0156] Reference Figure 15a In some embodiments of this application, the memory array may further include multiple channel interconnect structures 111c, which extend along the vertical direction Z. Furthermore, in two memory cells 110 stacked along the vertical direction Z, the first channel 111a of one memory cell 110 and the second channel 111b of the other memory cell 110 can be interconnected via the channel interconnect structures 111c. Additionally, the channel interconnect structures 111c are configured to contact the bit line 130, thereby connecting the first channel 111a and the second channel 111b to the bit line 130 via the channel interconnect structures 111c, thereby increasing the contact area between the bit line 130 and the first channel 111a and the second channel 111b.

[0157] To achieve insulation between the channel interconnect structure 111c and the first electrode plate 112a, refer to Figure 15a and Figure 15bThe channel interconnect structure 111c can be configured as a groove-shaped channel interconnect structure arranged in the horizontal direction, and the first electrode plate 112a can be disposed at the open end of the channel interconnect structure 111c in the horizontal direction. Furthermore, the first electrode plate 112a and the open end of the channel interconnect structure 111c in the horizontal direction are spaced apart, which can insulate the channel interconnect structure 111c from the first electrode plate 112a. Therefore, for the first channel 111a and the second channel 111b connected to the same channel interconnect structure 111c, the portions of the first channel 111a and the second channel 111b near the first electrode plate 112a can be not interconnected in the vertical direction, achieving isolation between the first electrode plates 112a of capacitors in adjacent memory cells in the vertical direction.

[0158] Reference Figure 15b By setting the channel interconnect structure 111c as a groove-shaped channel interconnect structure arranged in the horizontal direction, the cross section of the channel interconnect structure 111c parallel to the horizontal direction can be a groove-shaped cross section, which can be a "U" shape, a "C" shape, or other feasible shapes.

[0159] Furthermore, in order to achieve insulation between the channel interconnect structure 111c and the first electrode plate 112a, refer to Figure 15a , Figure 15b as well as Figure 15d The orthogonal projection of the channel interconnect structure 111c onto the substrate can fall within the orthogonal projection of the gate 112 onto the substrate.

[0160] Reference Figure 15a In some embodiments of this application, the interconnected first channel 111a, channel interconnect structure 111c, and second channel 111b are integral structures made of the same material, and can be formed in the same process, reducing the number of fabrication steps. Furthermore, making the first channel 111a, channel interconnect structure 111c, and second channel 111b an integral structure can improve the stability of the memory cell 110.

[0161] Reference Figure 15a In some embodiments of this application, the interconnected first channel 111a, channel interconnection structure 111c and second channel 111b surround and form a first groove BX1 extending in the horizontal direction, thereby forming a thinner channel and improving gate control capability.

[0162] Reference Figure 15aIn some embodiments of this application, the bit line 130 has an overlapping first bit line portion 130a and a second bit line portion 130b in the vertical direction Z. The width h31 of the first bit line portion 130a in the horizontal direction is greater than the width h32 of the second bit line portion 130b in the horizontal direction. Furthermore, connecting the first bit line portion 130a to the channel interconnect structure 111c does not affect the signal transmission between the bit line and the first and second channels. Additionally, the second bit line portion 130b and the gate 123 have an overlapping region in the horizontal direction; that is, the orthogonal projections of the second bit line portion 130b and the gate 123 onto the planes in the vertical direction Z and the second direction Y overlap. This allows for a certain distance between the second bit line portion 130b and the gate 123, reducing the parasitic capacitance between them.

[0163] Reference Figure 15a and Figure 15c In some embodiments of this application, while maintaining the capacitance, the area occupied by the plate lines in the horizontal direction can be saved. The first electrode plate 112a of the capacitor 112 can be configured as a ring-shaped electrode plate arranged in the horizontal direction. This allows the first electrode plates 112a of each capacitor 112 in the first unit group 210 to be arranged around one of the multiple plate lines 140, separated by the electrode dielectric layer 112b. This allows the plate lines to be placed inside the storage cell 110 in the vertical Z direction, eliminating the need for the plate lines 140 to occupy additional area in the horizontal direction, and further increasing the horizontal density of the storage cell 110. Alternatively, the plate lines can be directly used as the second electrode of the capacitor 112, reducing the area occupied by the capacitor in the horizontal direction. Exemplarily, a ring-shaped electrode plate refers to the first electrode plate 112a having a closed ring structure in the horizontal direction. This ring structure can be a circular ring, a square ring, or other feasible shapes. (Refer to...) Figure 15a and Figure 15b In the horizontal direction, the first electrode plate 112a completely surrounds the plate line, and the portion of the plate line surrounded by the first electrode plate 112a can serve as the second electrode plate of the capacitor 112.

[0164] In some embodiments of this application, to improve the adhesion of the metal and block hydrogen diffusion, the board line can be configured as a stacked structure. For example, the board line may include a board line metal layer and a board line barrier layer, with the board line barrier layer disposed between the board line metal layer and the electrode dielectric layer. Exemplarily, the material of the board line metal layer includes, but is not limited to, metals or alloys such as W, Ru, Ni, Mo, NiPt, etc., and the material of the board line barrier layer includes, but is not limited to, metal or nitride or alloy electrodes such as W, Ni, Mo, Ru, NiPt, TiN, or conductive oxides as buffer contact layers, such as InSnO. In other embodiments of this application, a board line barrier layer may be omitted, and a board line metal layer may be used to form the bit line instead. Furthermore, a horizontal CD of less than or equal to 300 nm ensures a small overall area of ​​the memory cell. For example, the horizontal CD of the board line can be 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 250 nm, 300 nm, etc., and is not limited here.

[0165] Reference Figure 15a and Figure 15c In some embodiments of this application, to increase the capacitance, the first electrode plate 112a may have a second groove BX2 extending horizontally in the horizontal direction. The opening of the second groove BX2 faces the plate line 140, and the plate line 140 extends into the second groove BX2, so that the portion of the plate line 140 extending into the second groove BX2 serves as the second electrode plate of the capacitor 112. This not only increases the capacitance but also reduces manufacturing costs. Furthermore, the region of the first electrode plate 112a at the bottom of the second groove BX2 is disposed between the first channel 111a and the second channel 111b, and the region of the first electrode plate 112a at the bottom of the second groove BX2 overlaps with the first channel 111a and the second channel 111b in the vertical direction Z.

[0166] Reference Figure 15aIn some embodiments of this application, to improve the stability of the memory cell 110, the board lines can have overlapping first board line portions 140a and second board line portions 140b in the vertical direction Z, and the width h41 of the first board line portion 140a in the horizontal direction is greater than the width h42 of the second board line portion 140b in the horizontal direction. The first electrode plate 112a surrounds the first board line portion 140a through the electrode dielectric layer 112b to increase the capacitance of the capacitor 112. Furthermore, the second board line portion 140b overlaps with the first channel 111a and the second channel 111b in the horizontal direction, and the electrode dielectric layer 112b is disposed between the second board line portion 140b and the first channel 111a and the second channel 111b. Therefore, the second board line portion 140b can be used as a support structure to support the first channel 111a and the second channel 111b, thereby improving the stability of the first channel 111a and the second channel 111b.

[0167] Figures 17a to 25b for Figure 15a The diagram shows the structure of the storage array after each step of the fabrication process.

[0168] Reference Figures 17a to 25b The storage array provided in this application embodiment can be fabricated using the following process flow, which may include:

[0169] Step 1, refer to Figure 17a and Figure 17b Multiple word line insulating layers 611 and multiple channel insulating layers 311 are alternately deposited on a substrate. Then, channel vias 412 are formed penetrating the multiple word line insulating layers 611 and the multiple channel insulating layers 311. Next, the channel insulating layers 311 are selectively etched laterally within the channel vias 412, forming multiple channel accommodating trenches GG1 within the word line vias 312. Then, channel sacrificial layers 612 are filled into the channel accommodating trenches GG1. Finally, a first protective dielectric layer 413 is filled into the channel vias 412. Exemplarily, the materials of the word line insulating layers 611, channel insulating layers 311, channel sacrificial layers 612, and the first protective dielectric layer 413 are insulating materials, including, but not limited to, one or more of oxides and nitrides. For example, the materials include, but are not limited to, SiO2, SiN, SiOC, SiON, SiCN, etc. Furthermore, the word line insulating layer 611, the channel insulating layer 311, the channel sacrificial layer 612, and the first protective dielectric layer 413 are made of different materials. In order to achieve a higher etching selectivity, the word line insulating layer 611, the channel insulating layer 311, the channel sacrificial layer 612, and the first protective dielectric layer 413 can be made of materials with high etching selectivity.

[0170] Step 2, refer to Figure 18a and Figure 18bA bit line via 414 is formed on one side of the channel via 412, penetrating multiple word line insulating layers 611 and multiple channel insulating layers 311. Then, a bit line sacrificial layer is filled into the bit line via 414. For example, the material of the bit line sacrificial layer is an insulating material, including but not limited to one or more of oxides and nitrides. For example, its material includes but is not limited to SiO2, SiN, SiOC, SiON, SiCN, etc.

[0171] Step 3, refer to Figure 19a and Figure 19b A board wire via 415 is formed on the other side of the channel via 412, penetrating multiple word line insulating layers 611 and multiple channel insulating layers 311. Then, a board wire sacrificial layer is filled into the board wire via 415. For example, the material of the board wire sacrificial layer is an insulating material, such as, but not limited to, one or more of oxides and nitrides. For example, its material includes, but is not limited to, SiO2, SiN, SiOC, SiON, SiCN, etc.

[0172] Step 4, refer to Figure 20a and Figure 20b The first protective dielectric layer 413 filling the channel via 412 is etched away. Then, the word line insulating layer 611 is selectively etched laterally within the channel via 412, forming a plurality of word line trenches 441 within the channel via 412. Next, a gate dielectric layer 115 is deposited on the sidewalls and bottomwalls of the word line trenches 441. Then, word lines 120 are filled into the word line trenches 322 where the gate dielectric layer 115 is deposited, forming a recessed gate 123.

[0173] Step 5, refer to Figure 21a and Figure 21b A second protective dielectric layer 411 is filled into the channel via 412. Then, the bit line sacrificial layer filling the bit line via 414 is etched away. Next, the channel insulating layer 311 is selectively etched laterally within the bit line via 414. Then, a bit line contact layer 132 and a bit line metal layer 131 are sequentially deposited in the bit line via 414 to form a bit line 130. Similarly, the board line sacrificial layer filling the board line via 415 is etched away. Then, a word line insulating layer 611 is selectively etched laterally within the board line via 415 to form a capacitor trench. Next, a first electrode plate 112a, an electrode dielectric layer 112b, and a portion of the board line 140 are sequentially deposited in the capacitor trench. Finally, a board line sacrificial layer is filled into the board line via 415.

[0174] In some embodiments, steps 4 and 5 may be interchanged, and this application does not limit the specific order of steps 4 and 5.

[0175] Step 6, refer to Figure 22a and Figure 22bThe second protective dielectric layer 411 filling the channel via 412 is etched away. Then, the channel sacrificial layer 612 is etched away, exposing the sidewalls of the channel accommodating trench GG1. Next, an oxide semiconductor material is deposited by ALD on the sidewalls of the channel via 412 to form the channel layer 511.

[0176] Step 7, refer to Figure 23a and Figure 23b The channel layer 511 is selectively etched, retaining the channel layer 511 on the sidewalls and bottom wall of the channel accommodating trench GG1, while removing the channel layer 511 in the remaining areas. Then, a channel spacer layer 114 is filled into the channel hole 412. Exemplarily, the channel spacer layer 114 is made of an insulating material, including, but not limited to, one or more of oxides and nitrides. For example, its material includes, but is not limited to, SiO2, SiN, SiOC, SiON, SiCN, etc.

[0177] Step 8, refer to Figure 24a and Figure 24b The sacrificial layer filling the via 415 is etched away. Then, the channel insulating layer 311 is selectively etched laterally within the via 415 to expose the sidewall of the channel layer 511 facing away from the bit line. Next, the exposed sidewall of the channel layer 511 facing away from the bit line is etched away to form the first channel 111a, the second channel 111b, and the channel interconnect structure 111c.

[0178] Step 9, refer to Figure 25a and Figure 25b A capacitor dielectric layer 112b and a board line 140 are sequentially formed in the board line hole 415.

[0179] Therefore, the first channel 111a, the second channel 111b, and the word line 120 can be integrated into the same channel via 412, and the first channel 111a, the second channel 111b, and the gate 123 can be disposed in different layers. This facilitates the reduction of the horizontal dimensions of the memory cell 110, making it easier to accommodate more memory cells 110 in the horizontal direction and thus increasing storage capacity. Furthermore, by forming the gate dielectric layer 115 and the word line 120 before forming the first channel 111a and the second channel 111b, damage to the channel can be avoided during the formation of the gate 123.

[0180] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A memory array comprising: The application relates to a memory device, comprising: a plurality of memory cell layers stacked along a vertical direction, each of the memory cell layers comprising a plurality of memory cells, each of the memory cells comprising a channel and a capacitor arranged along a horizontal direction, the channel connecting a first electrode plate of the capacitor, the horizontal direction being perpendicular to the vertical direction; a plurality of word lines, each of the word lines comprising a word line interconnection structure and a plurality of protrusions connected to each other, the protrusions being used as gates, the word line interconnection structure extending along the vertical direction, and the plurality of protrusions extending along the horizontal direction; wherein the plurality of channels stacked along the vertical direction at least partially surround the word line interconnection structure of one of the word lines, and one of the protrusions is arranged between two adjacent channels along the vertical direction, the protrusion and the channel having an overlapping region along the vertical direction, and the channel has a dielectric layer between the protrusion and the word line interconnection structure.

2. The storage array of claim 1, wherein, The channel is a ring-shaped channel arranged along the horizontal direction, each of the channels surrounds the word line interconnection structure, and the protrusion surrounds the word line interconnection structure.

3. The storage array of claim 2, wherein, In each of the memory cells, the channel and the capacitor are arranged along a first direction parallel to the horizontal direction, the channel is connected to a bit line, and the channel is located between the bit line connected to the channel and the capacitor.

4. The storage array of claim 1, wherein, The channel is a groove-shaped channel arranged along the horizontal direction, the word line interconnection structure is arranged in the groove of the channel, and the protrusion partially surrounds the word line interconnection structure.

5. The storage array of claim 4, wherein, In the same memory cell layer, in a second direction parallel to the horizontal direction, the openings of the channels of two adjacent memory cells along the horizontal direction are arranged opposite to each other.

6. The storage array of claim 5, wherein, The distance between the channels of the two adjacent memory cells along the second direction is the same as the distance between the first electrode plates of the two adjacent memory cells along the second direction. Alternatively, in the same memory cell, the capacitor is arranged on the side of the channel away from the opening of the channel along the horizontal direction.

7. The storage array of any one of claims 1-6, wherein, The channel comprises a first channel portion, a second channel portion and a third channel portion connected in sequence, the first channel portion and the third channel portion extend along the horizontal direction, the second channel portion extends along the vertical direction, the first channel portion, the second channel portion and the third channel portion enclose a first groove extending along the horizontal direction, and the opening of the first groove faces the word line interconnection structure. Between the third channel portion of the channel of one of the memory cells and the first channel portion of the channel of another of the memory cells stacked along the vertical direction, the protrusion is arranged.

8. The storage array of any of claims 1-7, wherein, The application further relates to a bit line arranged in each of the memory cell layers, the bit line extending along a second direction parallel to the horizontal direction, and the channels of the memory cells arranged along the second direction in the memory cell layer are connected to the bit line. A bit line insulating layer or a gas gap is arranged between two adjacent bit lines along the vertical direction.

9. The storage array of any of claims 1-8, wherein, Further comprising a plurality of plate lines extending along the vertical direction, a first electrode plate of the capacitor in the memory cell stacked along the vertical direction is disposed around one of the plate lines through an electrode dielectric layer.

10. A memory array comprising: Further comprising: a plurality of memory cell layers stacked along a vertical direction, each of the memory cell layers comprising a plurality of memory cells, each of the memory cells comprising a transistor and a capacitor, the transistor comprising a first channel, a second channel, and a gate, the first channel and the second channel being disposed stacked along the vertical direction; in the same memory cell, the gate and the first electrode plate of the capacitor are arranged along a horizontal direction, the gate and the first electrode plate are disposed between the first channel and the second channel respectively, the gate and the first electrode plate have overlapping regions with the first channel and the second channel along the vertical direction respectively, and a dielectric layer is disposed between the gate and the first electrode plate, the first channel, and the second channel respectively.

11. The storage array of claim 10, wherein, the gate is a groove-shaped gate arranged along the horizontal direction, and the first electrode plate is disposed at an opening end of the gate along the horizontal direction.

12. The storage array of claim 10 or 11, wherein, the first channel and the second channel are ring-shaped channels arranged along the horizontal direction respectively.

13. The storage array of any of claims 10-12, wherein, Further comprising a plurality of bit lines extending along the vertical direction, the first channel and the second channel in the memory cell stacked along the vertical direction are connected to one of the bit lines.

14. The storage array of claim 13, wherein, Further comprising a plurality of channel interconnection structures extending along the vertical direction, in two memory cells stacked along the vertical direction, the first channel of one of the memory cells and the second channel of the other of the memory cells are interconnected through the channel interconnection structure; the channel interconnection structure is connected to the bit line, and the channel interconnection structure is spaced apart from the first electrode plate.

15. The storage array of claim 14, wherein, the channel interconnection structure is a groove-shaped channel interconnection structure arranged along the horizontal direction; the first electrode plate is disposed at an opening end of the channel interconnection structure along the horizontal direction, and the first electrode plate is spaced apart from the opening end of the channel interconnection structure along the horizontal direction.

16. The storage array of claim 14 or 15, wherein, the interconnected first channel, channel interconnection structure, and second channel are an integrated structure of the same material, or the interconnected first channel, channel interconnection structure, and second channel enclose a first groove extending along the horizontal direction.

17. The storage array of any of claims 14-16, wherein, the bit line has a first bit line portion and a second bit line portion disposed overlappingly along the vertical direction, a width of the first bit line portion along the horizontal direction is greater than a width of the second bit line portion along the horizontal direction; the first bit line portion is connected to the channel interconnection structure, and the second bit line portion has an overlapping region with the gate along the horizontal direction.

18. The storage array of any of claims 10-17, wherein, Further comprising: A plurality of word lines extending in a first direction parallel to the horizontal direction, one of the word lines being disposed between the first and second channels in the memory cell and the portion of the word line overlapping the first and second channels in the vertical direction serving as the gate.

19. The storage array of any of claims 10-18, wherein, Further comprising a plurality of plate lines extending in the vertical direction, the first electrode plate in the memory cell stacked in the vertical direction being disposed around one of the plate lines via an electrode dielectric layer.

20. The storage array of claim 19, wherein, The plate line has a first plate line portion and a second plate line portion disposed in overlap in the vertical direction, the first plate line portion having a width in the horizontal direction greater than the width of the second plate line portion in the horizontal direction; The first electrode plate is disposed around the first plate line portion via the electrode dielectric layer, the second plate line portion having an overlapping region with the first and second channels in the horizontal direction and the electrode dielectric layer disposed between the second plate line portion and the first and second channels.

21. A memory, comprising: Comprising: A controller and at least one memory array, the controller being electrically connected with the at least one memory array; The at least one memory array is the memory array of any one of claims 1-9, or the at least one memory array is the memory array of any one of claims 10-19.

22. An electronic device, comprising: Comprising: A circuit board and the memory of claim 21, the memory being electrically connected with the circuit board.

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