Semiconductor memory device

Abstract

A semiconductor memory device includes: a back gate electrode on a substrate including a first conductive pattern; a first gate electrode on the back gate electrode including a second conductive pattern; and a first semiconductor pattern between the back gate electrode and the first gate electrode, wherein the first conductive pattern and the second conductive pattern include respective materials different from each other and / or have respective physical properties different from each other.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device in which an electrical characteristic is improved. BACKGROUND

[0002] In order to satisfy the excellent performance and low price required by consumers, it is necessary to increase the integration of semiconductor devices. Since the integration of semiconductor devices is an important factor in determining the price of products, there is a particular need for increased integration.

[0003] In the case of a two-dimensional or planar semiconductor device of the related art, since the integration of the two-dimensional or planar semiconductor device is mainly determined by the area occupied by a unit memory cell, the two-dimensional or planar semiconductor device is greatly affected by the level of technology for forming a fine pattern. However, since a fine pattern requires an ultra-high-priced apparatus, the integration of a two-dimensional semiconductor device is increasing, but is still limited. Accordingly, a three-dimensional semiconductor memory device having a three-dimensionally arranged memory cell has been proposed. SUMMARY

[0004] An object of the present disclosure is to provide a semiconductor memory device including a back gate electrode and a gate electrode having their respective materials or physical properties different from each other.

[0005] Objects of the present disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand additional objects of the present disclosure not mentioned herein from the following description of the present disclosure.

[0006] According to an example embodiment of the present disclosure, a semiconductor memory device includes a back gate electrode including a first conductive pattern on a substrate, a first gate electrode including a second conductive pattern on the back gate electrode, and a first semiconductor pattern between the back gate electrode and the first gate electrode, wherein the first conductive pattern and the second conductive pattern include their respective materials different from each other, and / or have their respective physical properties different from each other.

[0007] According to an example embodiment of the present disclosure, a semiconductor memory device includes: a plurality of structures stacked on a substrate in a first direction perpendicular to an upper surface of the substrate; and a bit line extending in the first direction, wherein each of the plurality of structures includes: a back gate electrode including a first conductive pattern; a first semiconductor pattern on the back gate electrode; a first gate electrode on the first semiconductor pattern, which includes a second conductive pattern; and a data storage element on the first semiconductor pattern, the bit line is connected to one end portion of the first semiconductor pattern, the data storage element is connected to another end portion of the first semiconductor pattern, and the first conductive pattern and the second conductive pattern include their respective materials different from each other and / or have their respective physical properties different from each other.

[0008] According to an example embodiment of the present disclosure, a semiconductor memory device includes: a plurality of structures stacked on a substrate in a first direction perpendicular to an upper surface of the substrate; and a bit line extending in the first direction, wherein each of the plurality of structures includes: a back gate electrode including a first conductive pattern; a first semiconductor pattern on the back gate electrode; a first gate electrode on the first semiconductor pattern, which includes a second conductive pattern; and a data storage element on the first semiconductor pattern, the bit line is connected to one end portion of the first semiconductor pattern, the data storage element is connected to another end portion of the first semiconductor pattern, and the first conductive pattern and the second conductive pattern include their respective materials different from each other and / or have their respective physical properties different from each other. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals (when used) designate corresponding elements in the several views, and wherein:

[0010] Figure 1 is an exemplary schematic perspective view illustrating a semiconductor memory device according to some embodiments;

[0011] Figure 2 is an exemplary schematic cross-sectional view illustrating a semiconductor memory device according to some embodiments;

[0012] Figure 3 is an enlarged view of a region R of Figure 2

[0013] Figure 4 and Figure 5 are schematic views illustrating​Figure 2 a schematic view of a portion of the first and second conductive patterns;

[0014] Figure 6 and Figure 7 is a schematic cross-sectional view illustrating a semiconductor storage device according to some embodiments;

[0015] Figures 8 to 22 is a schematic view illustrating an intermediate process in an example method for manufacturing a semiconductor storage device according to some embodiments;

[0016] Figure 23 is an example schematic cross-sectional view illustrating a semiconductor storage device according to some embodiments; and

[0017] Figures 24 to 31 is a schematic view illustrating an intermediate process in an example method for manufacturing a semiconductor storage device according to some embodiments;

[0018] Figure 32 is an example schematic cross-sectional view illustrating a semiconductor storage device according to some embodiments; and

[0019] Figures 33 to 41 is a schematic view illustrating an intermediate process in an example method for manufacturing a semiconductor storage device according to some embodiments. DETAILED DESCRIPTION

[0020] Figure 1 is an example perspective view illustrating a semiconductor storage device according to some embodiments.

[0021] Referring to Figure 1 , a subcell array SCA can be provided on a substrate 100. Although not shown, a plurality of subcell arrays SCA can be arranged along a second direction D2.

[0022] The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 can be a silicon substrate, or can include another material, for example, silicon-germanium-on-insulator (SGOI), indium-antimony, a tellurium acid lead compound, indium arsenide, indium phosphide, gallium arsenide, or gallium-antimony, but is not limited thereto. The following description will assume that the substrate 100 is a substrate including silicon.

[0023] In this case, the first direction D1, the second direction D2, and the third direction D3 can cross each other. Further, the first direction D1 and the second direction D2 can be parallel to an upper surface of the substrate 100, and the third direction D3 can be perpendicular to the upper surface of the substrate 100. The upper surface, the lower surface, the upper portion, and the lower portion can be defined based on the third direction D3.

[0024] The structure ST can be stacked on the substrate 100 in the third direction D3. There is no limitation on the number of structures ST that can be included in the sub-cell array SCA.

[0025] In some embodiments, the structure ST can include a plurality of first semiconductor patterns SP1, a plurality of data storage elements DS, a back gate electrode BG, and a gate electrode GE.

[0026] The first semiconductor pattern SP1 can have a line shape or a bar shape that extends in the second direction D2. A plurality of semiconductor patterns SP1 positioned at the same level with respect to the upper surface of the substrate 100 can be arranged in the first direction D1. For example, the first semiconductor patterns SP1 of the structure ST can be positioned at the same level and arranged in the first direction D1.

[0027] The first semiconductor pattern SP1 can include a semiconductor material such as silicon, germanium, or silicon germanium, although embodiments are not limited thereto. For example, the first semiconductor pattern SP1 can include at least one of polysilicon, polysilicon germanium, single-crystal silicon, or single-crystal silicon germanium.

[0028] Each first semiconductor pattern SP1 can include a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH can be interposed between the first impurity region SD1 and the second impurity region SD2. The channel region CH, the first impurity region SD1, and the second impurity region SD2 can correspond to a channel of a storage cell transistor, a first source / drain, and a second source / drain, respectively. A gate of the storage cell transistor can be connected to the gate electrode GE.

[0029] The first impurity region SD1 and the second impurity region SD2 can be regions doped with impurities in the first semiconductor pattern SP1. Accordingly, the first impurity region SD1 and the second impurity region SD2 can have n-type or p-type conductivity. The first impurity region SD1 can be formed adjacent to a first end portion of the first semiconductor pattern SP1, and the second impurity region SD2 can be formed adjacent to a second end portion of the first semiconductor pattern SP1. The second end portion can face the first end portion in the second direction D2.

[0030] The bit line BL can be a conductive pattern (e.g., a metal conductive line) extending in a direction perpendicular to the substrate, i.e., the third direction D3. The bit line BL can have a line shape or a column shape that extends in the third direction D3. The bit lines BL in one sub-cell array SCA can be arranged in the first direction D1. The bit lines BL adjacent to each other can be spaced apart from each other in the first direction D1.

[0031] The bit line BL can include a conductive material, for example, at least one of a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound, but is not limited thereto.

[0032] The first impurity region SD1 may be adjacent to the bit line BL. The first impurity region SD1 may be connected to the bit line BL. As may be used herein, the term "connection" (or "connecting") or similar terms such as "contact" or "contacting") is intended to refer to a physical and / or electrical connection between two or more elements and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Each bit line BL may be electrically connected to the first impurity region SD1 of the vertically stacked first semiconductor pattern SP. The second impurity region SD2 may be adjacent to the data storage element DS. The second impurity region SD2 may be connected to the data storage element DS.

[0033] Data storage element DS can be a memory element capable of storing data. Each of the data storage elements DS can be a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a memory element using a variable resistor containing a phase change material.

[0034] The back gate electrode BG can be a conductive pattern (e.g., a metal conductive line) stacked on a substrate in a third direction D3. The back gate electrodes BG can be stacked and spaced apart from each other along the third direction D3. Each of the back gate electrodes BG can extend in a first direction D1. The back gate electrode BG can have a line shape or a strip shape extending in the first direction D1. The back gate electrode BG can be disposed on at least a portion of the outer peripheral surface of the channel region CH of the first semiconductor pattern SP1. The back gate electrode BG can extend in the first direction D1 while intersecting with the first semiconductor pattern SP1 in a structure ST.

[0035] The gate electrode GE can be a conductive pattern (e.g., a metal conductive line) stacked on a substrate in a third direction D3. The gate electrodes GE can be stacked and spaced apart from each other in the third direction D3. Each of the gate electrodes GE can extend in a first direction D1. The gate electrode GE can have a line shape or a strip shape extending in the first direction D1. The gate electrode GE can be disposed on at least a portion of the outer peripheral surface of the channel region CH of the first semiconductor pattern SP1. The gate electrode GE can extend in the first direction D1 while intersecting the first semiconductor pattern SP1 in a structure ST.

[0036] The first semiconductor pattern SP1 of the structure ST can be arranged in a first direction D1. Each bit line BL can be connected to each first semiconductor pattern SP1 of the structure ST, and the back gate electrode BG and gate electrode GE of the structure ST can extend in the first direction D1 to intersect with the channel region CH of each first semiconductor pattern SP1 of the structure ST. The first semiconductor pattern SP1 can be disposed between the back gate electrode BG and the gate electrode GE.

[0037] Each of the back gate electrode BG and the gate electrode GE may include a conductive material. For example, each of the back gate electrode BG and the gate electrode GE may include at least one of the following: doped semiconductor material (doped silicon, doped silicon-germanium, doped germanium, etc.), conductive metal nitride (titanium nitride, tantalum nitride, etc.), metal (tungsten, titanium, tantalum, etc.), or metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.), but is not limited thereto.

[0038] Figure 2 This is an exemplary cross-sectional view showing a semiconductor memory device according to some embodiments. Figure 3 It is shown Figure 2 A magnified view of region R. Figure 4 and Figure 5 It is shown Figure 2 A view of the first and second conductive patterns. For reference, Figure 2 This is a cross-sectional view showing the first semiconductor pattern SP1 and the second semiconductor pattern SP2 taken along the second direction D2. For ease of description, a brief description will be provided with reference to... Figure 1 The redundant parts of the description, and the description will be based on the Figure 1 The differences in description.

[0039] refer to Figure 2 A semiconductor memory device according to some embodiments includes a substrate 100 and a structure ST stacked on the substrate 100 in a third direction D3. The structure ST may be repeatedly stacked on the substrate 100. The embodiments are not limited to any particular number of structures ST included in the semiconductor memory device.

[0040] In some embodiments, the structure ST may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a back gate electrode BG, a first gate electrode GE1, a second gate electrode GE2, a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, an interlayer insulating layer ILD, a first spacer pattern SS1, a second spacer pattern SS2, a first cover pattern CP1, a second cover pattern CP2, and a capacitor CAP. Figure 1 The gate electrode GE may include a first gate electrode GE1 and a second gate electrode GE2. Figure 1 The data storage element DS can be a capacitor CAP.

[0041] In structure ST, the second semiconductor pattern SP2, the back gate electrode BG, the first semiconductor pattern SP1, the first gate electrode GE1, the interlayer insulating layer ILD, and the second gate electrode GE2 can be stacked sequentially along the third direction D3. The second semiconductor pattern SP2, the first semiconductor pattern SP1, and the interlayer insulating layer ILD can be sequentially arranged to be spaced apart from each other on the third direction D3.

[0042] A first semiconductor pattern SP1 can be disposed between a back gate electrode BG and a first gate electrode GE1. The back gate electrode BG can be disposed on the lower surface of the first semiconductor pattern SP1, and the first gate electrode GE1 can be disposed on the upper surface of the first semiconductor pattern SP1. An interlayer insulating layer (ILD) can be disposed between the first gate electrode GE1 and a second gate electrode GE2. The first gate electrode GE1 can be disposed on the lower surface of the interlayer insulating layer (ILD), and the second gate electrode GE2 can be disposed on the upper surface of the interlayer insulating layer (ILD). A second semiconductor pattern SP2 of the first structure can be disposed between the back gate electrode BG of the first structure and the second gate electrode GE2 of the second structure disposed below the first structure. The back gate electrode BG of the first structure can be disposed on the upper surface of the second semiconductor pattern SP2 of the first structure, and the second gate electrode GE2 of the second structure can be disposed on the lower surface of the second semiconductor pattern SP2 of the first structure.

[0043] Each of the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may extend in the second direction D2. Each of the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may include a first impurity region SD1, a channel region CH, and a second impurity region SD2. The first end of the second semiconductor pattern SP2 and the first semiconductor pattern SP1 (i.e., the first impurity region SD1) may be connected to the bit line BL. The second end of the second semiconductor pattern SP2 and the first semiconductor pattern SP1 (i.e., the second impurity region SD2) may be connected to each of the memory electrodes SE.

[0044] Each of the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may include a semiconductor material such as silicon, germanium, or silicon-germanium, although the implementation is not limited thereto. For example, each of the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may include at least one of polycrystalline silicon, polycrystalline silicon-germanium, monocrystalline silicon, or monocrystalline silicon-germanium.

[0045] In some embodiments, the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may comprise the same material. In other embodiments, the second semiconductor pattern SP2 and the first semiconductor pattern SP1 may comprise their respective materials that are different from each other.

[0046] The interlayer insulating layer (ILD) may include an insulating material. For example, the interlayer insulating layer (ILD) may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxide nitride layer, although the embodiments are not limited thereto. For example, the interlayer insulating layer (ILD) may include a silicon oxide layer.

[0047] In some embodiments, the length W1 of the back gate electrode BG in the second direction D2 may differ from the length W2 of the first gate electrode GE1 and the length W3 of the second gate electrode GE2 in the second direction D2. A portion of the back gate electrode BG may overlap with the first gate electrode GE1 and the second gate electrode GE2 in the third direction D3. As used herein, "element A overlaps with element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting both elements A and B. The length W2 of the first gate electrode GE1 in the second direction D2 may be substantially the same as the length W3 of the second gate electrode GE2 in the second direction D2. In this context, "substantially the same" means either identical or differing within a range of deviations occurring during manufacturing, and this meaning can be interpreted even if the expression "substantially" is omitted.

[0048] In some other embodiments, the length W1 of the back gate electrode BG in the second direction D2 may be substantially the same as the length W2 of the first gate electrode GE1 in the second direction D2 and the length W3 of the second gate electrode GE2 in the second direction D2.

[0049] In some embodiments, the thickness T1 of the back gate electrode BG in the third direction D3 may be different from the thickness T2 of the first gate electrode GE1 in the third direction D3 and the thickness T3 of the second gate electrode GE2 in the third direction D3. The thickness T2 of the first gate electrode GE1 in the third direction D3 may be substantially the same as the thickness T3 of the second gate electrode GE2 in the third direction D3.

[0050] In some other embodiments, the thickness T1 of the back gate electrode BG on the third direction D3 can be substantially the same as the thickness T2 of the first gate electrode GE1 on the third direction D3 and the thickness T3 of the second gate electrode GE2 on the third direction D3.

[0051] In some embodiments, each of the back gate electrode BG, the first gate electrode GE1, and the second gate electrode GE2 may be a single layer. The back gate electrode BG may be formed from a first conductive pattern M1. Each of the first gate electrode GE1 and the second gate electrode GE2 may be formed from a second conductive pattern M2. Each of the first conductive pattern M1 and the second conductive pattern M2 may include at least one of TiN, TiAlC, TiAlN, TiSiN, TiWN, Mo, MoSi, MoSiN, MoN, W, Ta, TaN, LaN, Al, Cu, Ru, or compounds thereof, although embodiments are not limited thereto.

[0052] In some embodiments, the first conductive pattern M1 and the second conductive pattern M2 may comprise materials that are different from each other. For example, the first conductive pattern M1 may comprise TiN, and the second conductive pattern M2 may comprise TiAlC.

[0053] In some embodiments, the first conductive pattern M1 and the second conductive pattern M2 may have different physical properties (e.g., shape, size, etc.). Physical properties may also include, for example, composition, crystal orientation (i.e., orientation) and / or average grain size.

[0054] In some embodiments, the first conductive pattern M1 and the second conductive pattern M2 may comprise the same material, but their respective compositions may differ from each other. For example, when the first conductive pattern M1 and the second conductive pattern M2 comprise TiN, the Ti to N composition ratio of the first conductive pattern M1 may differ from the Ti to N composition ratio of the second conductive pattern M2.

[0055] In some embodiments, the shape of the first grain of the first conductive pattern M1 may be different from the shape of the second grain of the second conductive pattern M2. For example, the crystal orientation of the first conductive pattern M1 may be different from the crystal orientation of the second conductive pattern M2. For example, the average grain size of the first conductive pattern M1 may be different from the average grain size of the second conductive pattern M2.

[0056] For example, refer to Figure 4 and Figure 5 The first conductive pattern M1 may include a plurality of first grains G1. The crystal orientation CX1 of the first grains G1 may be a direction parallel to the upper surface of the substrate 100. The crystal orientation CX1 of the first grains G1 may be a second direction D2. The first grains G1 may be aligned in the second direction D2. The first conductive pattern M1 may have a crystal structure comprising columnar grains G1 extending longitudinally in the second direction D2.

[0057] The second conductive pattern M2 may include a plurality of second grains G2. The second grains G2 may have a random crystal orientation CX2. The second grains G2 may be arranged in a random orientation. The second conductive pattern M2 may have a crystal structure including the random grains G2.

[0058] The average grain size of the first conductive pattern M1 can be the average of the dimensions of the first grain G1 in the second direction D2, and the average grain size of the second conductive pattern M2 can be the average of the dimensions of the second grain G2 in the second direction D2. The dimension of the first grain G1 in the second direction D2 can be larger than the dimension of the second grain G2 in the second direction D2.

[0059] The first conductive pattern M1 and the second conductive pattern M2 can be easily analyzed by transmission electron microscopy (TEM), time-of-flight secondary ion mass spectrometry (ToF-SIMS), transmission Kikuchi diffraction (TKD), energy-dispersive X-ray spectroscopy (EDS), etc.

[0060] Return to reference Figure 2 and Figure 3 The first gate insulating layer GI1 can extend along the upper and lower surfaces of the back gate electrode BG. The second gate insulating layer GI2 can extend along the lower surface of the first gate electrode GE1. The third gate insulating layer GI3 can extend along the upper surface of the second gate electrode GE2. The first gate insulating layer GI1 can be located between the back gate electrode BG and the second semiconductor pattern SP2, and between the back gate electrode BG and the first semiconductor pattern SP1. The second gate insulating layer GI2 can be located between the first gate electrode GE1 and the first semiconductor pattern SP1. The third gate insulating layer GI3 can be located between the second gate electrode GE2 and the second semiconductor pattern SP2. The second gate insulating layer GI2 may not be located on the upper surface of the first gate electrode GE1, and the third gate insulating layer GI3 may not be located on the lower surface of the second gate electrode GE2.

[0061] Each of the first to third gate insulating layers GI1, GI2, and GI3 may include at least one of, for example, a high-dielectric-constant insulating layer, a silicon oxide layer, a silicon nitride layer, or a silicon nitride layer. The second gate insulating layer GI2 and the third gate insulating layer GI3 may include the same material. In some embodiments, the first gate insulating layer GI1 may include the same material as the second gate insulating layer GI2 and the third gate insulating layer GI3. In some other embodiments, the first gate insulating layer GI1 may include a material different from the materials of the second gate insulating layer GI2 and the third gate insulating layer GI3.

[0062] The first overlay pattern CP1 can be located between the second semiconductor pattern SP2 and the first semiconductor pattern SP1. The first overlay pattern CP1 can also be located between the first impurity region SD1 of the second semiconductor pattern SP2 and the first impurity region SD1 of the first semiconductor pattern SP1. The first overlay pattern CP1 can be located between the back gate electrode BG and the bit line BL. The first overlay pattern CP1 can spatially separate the back gate electrode BG from the bit line BL.

[0063] The second overlay pattern CP2 can be located between the first semiconductor pattern SP1 of the first structure and the second semiconductor pattern SP2 of the second structure disposed above the first structure. The second overlay pattern CP2 can also be located between the first impurity region SD1 of the first semiconductor pattern SP1 of the first structure SP1 and the first impurity region SD1 of the second semiconductor pattern SP2 of the second structure. The second overlay pattern CP2 can spatially separate the first gate electrode GE1 and the second gate electrode GE2 from the bit line BL.

[0064] The first spacer pattern SS1 can be disposed on the back gate electrode BG. The first spacer pattern SS1 can protrude more than the second semiconductor pattern SP2 and the first semiconductor pattern SP1 in the second direction D2. The first spacer pattern SS1 can be disposed between the back gate electrode BG and the capacitor CAP. The back gate electrode BG and the first gate insulating layer GI1 can be disposed between the first cover pattern CP1 and the first spacer pattern SS1.

[0065] The second spacer pattern SS2 can be disposed on the first gate electrode GE1 and the second gate electrode GE2. The second spacer pattern SS2 can protrude more than the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the second direction D2. The second spacer pattern SS2 can be between the first gate electrode GE1 and the second gate electrode GE2 and the capacitor CAP. The second spacer pattern SS2 can be between the interlayer insulating layer ILD and the capacitor CAP. The first gate electrode GE1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the second gate electrode GE2, and the third gate insulating layer GI3 can be between the second cover pattern CP2 and the second spacer pattern SS2.

[0066] Each of the first overlay pattern CP1, the second overlay pattern CP2, the first spacer pattern SS1, and the second spacer pattern SS2 may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, a silicon nitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon nitride layer, although embodiments are not limited thereto. The second overlay pattern CP2, the first spacer pattern SS1, and the second spacer pattern SS2 may include the same material. In some embodiments, the first overlay pattern CP1 may include a material different from the materials of the second overlay pattern CP2 and the first spacer patterns SS1 and SS2.

[0067] A capacitor CAP may include a capacitor dielectric layer (CIL), multiple storage electrodes (SE), and a plate electrode (PE). The capacitor CAP may be defined by each storage electrode (SE).

[0068] Storage electrodes SE can be formed in each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Each storage electrode SE can be disposed between first spacer patterns SS1 and second spacer patterns SS2 that are adjacent to each other along the third direction D3. Storage electrodes SE included in each capacitor CAP are separated from each other. In a structure ST, storage electrodes SE that are adjacent to each other along the third direction D3 can be separated from each other by the first spacer pattern SS1. Storage electrodes SE that are adjacent to each other along the third direction D3 can be separated from each other by the first spacer pattern SS1 or the second spacer pattern SS2.

[0069] A capacitor dielectric layer CIL can be disposed on the storage electrode SE. The capacitor dielectric layer CIL can extend along the contour of the plurality of storage electrodes SE. A plate electrode PE can be disposed on the capacitor dielectric layer CIL. The capacitor dielectric layer CIL and the plate electrode PE can be disposed sequentially on the storage electrode SE. The capacitor dielectric layer CIL can be between a first spacer pattern SS1 and the plate electrode PE, and between a second spacer pattern SS2 and the plate electrode PE.

[0070] Each of the storage electrode SE and the plate electrode PE may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, or tantalum), and conductive metal oxides (e.g., iridium oxide or niobium oxide). For example, the storage electrode SE may include conductive metal nitrides, metals, and conductive metal oxides. The conductive metal nitrides, metals, and conductive metal oxides may be included in a metal conductive layer.

[0071] The capacitor dielectric layer (CIL) may include, for example, a high dielectric constant material (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof). In semiconductor memory devices according to some embodiments, the capacitor dielectric layer (CIL) may include a stacked layer structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In semiconductor memory devices according to some embodiments, the capacitor dielectric layer (CIL) may include hafnium (Hf).

[0072] A semiconductor memory device according to some embodiments includes a back gate electrode BG. A voltage different from the voltage applied to the first gate electrode GE1 and the second gate electrode GE2 can be applied to the back gate electrode BG. Since the channel region CH of the memory cell transistor can be a floating body, and the back gate electrode BG can control the charge (e.g., holes) accumulated in the channel region CH, the floating body effect can be suppressed or controlled, and threshold voltage variations of the memory cell transistor can be prevented. Therefore, the back gate electrode BG can improve the electrical characteristics of the memory cell transistor.

[0073] In the example, considering the interlayer characteristic distribution of the memory cell transistors disposed in each layer, the back gate electrode BG can be controlled independently and separately. Alternatively, at least some of the back gate electrodes BG can be electrically connected to each other and controlled together.

[0074] Furthermore, in a semiconductor memory device according to some embodiments, each of the back gate electrode BG and the first gate electrode GE1 and the second gate electrode GE2 includes a first conductive pattern M1 and a second conductive pattern M2, which may comprise different materials or have different physical properties. That is, since the materials of the back gate electrode BG and the first gate electrode GE1 and the second gate electrode GE2 can be adjusted separately, gate controllability can be increased.

[0075] Figure 6 and Figure 7 This is a view illustrating a semiconductor memory device according to some embodiments. For reference, Figure 6 and Figure 7 It is shown Figure 2 A magnified view of region R. For ease of description, a brief description will be provided (refer to [reference]). Figures 1 to 5 The redundant parts of the description, and the description will be based on the Figures 1 to 5 The differences in the descriptions.

[0076] refer to Figure 6In a semiconductor memory device according to some embodiments, the back gate electrode BG may be a multilayer structure. For example, the back gate electrode BG may include a first conductive pattern M1 and a third conductive pattern M3 that are in contact with each other in a second direction D2.

[0077] For example, the third conductive pattern M3 may be located between the first conductive pattern M1 and the first spacer pattern SS1. The first gate insulating layer GI1 may extend along the upper and lower surfaces of the first conductive pattern M1 and the third conductive pattern M3 in the second direction D2.

[0078] The third conductive pattern M3 may include at least one of TiN, TiAlC, TiAlN, TiSiN, TiWN, Mo, MoSi, MoSiN, MoN, W, Ta, TaN, LaN, Al, Cu, Ru, or a compound thereof, although the embodiments are not limited thereto.

[0079] In some embodiments, the first conductive pattern M1 and the third conductive pattern M3 may comprise materials that are different from each other. For example, the first conductive pattern M1 may comprise TiN, and the third conductive pattern M3 may comprise TiAlC.

[0080] In some embodiments, the first conductive pattern M1 and the third conductive pattern M3 may have different physical properties from each other.

[0081] In some embodiments, the first conductive pattern M1 and the third conductive pattern M3 may comprise the same material, but may have different compositions from each other.

[0082] In some embodiments, the shape of the first grain of the first conductive pattern M1 may be different from the shape of the second grain of the third conductive pattern M3. For example, the crystal orientation of the first conductive pattern M1 may be different from the crystal orientation of the third conductive pattern M3. For example, the average grain size of the first conductive pattern M1 may be different from the average grain size of the third conductive pattern M3.

[0083] refer to Figure 7 In a semiconductor memory device according to some embodiments, each of the first gate electrode GE1 and the second gate electrode GE2 may be a multilayer structure. For example, each of the first gate electrode GE1 and the second gate electrode GE2 may include a second conductive pattern M2 and a fourth conductive pattern M4 that are in contact with each other on a third-direction D3.

[0084] For example, the fourth conductive pattern M4 may be located between the second conductive pattern M2 and the interlayer insulating layer (ILD). The first gate electrode GE1 may include the second conductive pattern M2 and the fourth conductive pattern M4 on the upper surface of the second conductive pattern M2. The second gate electrode GE2 may include the fourth conductive pattern M4 and the second conductive pattern M2 on the upper surface of the fourth conductive pattern M4.

[0085] The fourth conductive pattern M4 may include at least one of TiN, TiAlC, TiAlN, TiSiN, TiWN, Mo, MoSi, MoSiN, MoN, W, Ta, TaN, LaN, Al, Cu, Ru, or compounds thereof, although the embodiments are not limited thereto.

[0086] In some embodiments, the second conductive pattern M2 and the fourth conductive pattern M4 may have different materials.

[0087] In some embodiments, the second conductive pattern M2 and the fourth conductive pattern M4 may have different physical properties from each other.

[0088] In some embodiments, the second conductive pattern M2 and the fourth conductive pattern M4 may comprise the same material, but may have different compositions from each other.

[0089] In some embodiments, the shape of the first grain of the second conductive pattern M2 may differ from the shape of the second grain of the fourth conductive pattern M4. For example, the crystal orientation of the second conductive pattern M2 may differ from the crystal orientation of the fourth conductive pattern M4. For example, the average grain size of the second conductive pattern M2 may differ from the average grain size of the fourth conductive pattern M4.

[0090] In some other embodiments, each of the back gate electrode BG, the first gate electrode GE1, and the second gate electrode GE2 may be a multilayer structure.

[0091] Figures 8 to 22 This is a schematic diagram illustrating intermediate processes in an example method for manufacturing a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided with reference to... Figures 1 to 6 The redundant parts of the description, and the description will be based on the Figures 1 to 6 The differences in the descriptions.

[0092] refer to Figure 8 A preliminary structure pST, repeatedly stacked along the third direction D3, can be formed on the substrate 100. The preliminary structure pST can be stacked on the substrate 100 along the third direction D3. The number of preliminary structure pSTs is not limited to... Figure 8 Examples.

[0093] In some implementations, the preliminary structure pST may include a (1-1) material layer 101a, a second material layer 102, a (1-2) material layer 101b and a third material layer 103, which are stacked sequentially on the third direction D3.

[0094] Material layer 101a (1-1) and material layer 101b (1-2) may comprise the same material. Material layer 101a (1-1) and material layer 101b (1-2) may comprise, for example, silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO), although the implementation is not limited thereto. Material layer 102 and material layer 103 may be formed of a material having etch selectivity relative to material layer 101a (1-1) and material layer 101b (1-2). Material layer 102 may be formed of a material having etch selectivity relative to material layer 103.

[0095] refer to Figure 9 One or more first openings OP1 can be formed extending through multiple preliminary structures pST in the third direction D3. The first openings OP1 can be spaced apart from each other in the second direction D2.

[0096] refer to Figure 10 A support member 105 can be formed to fill the first opening OP1. The term "filling" (or "fill" or similar terms) is intended to mean completely filling the defined space (e.g., the first opening OP1) or partially filling the defined space; that is, the defined space does not need to be completely filled, but may be partially filled or always have gaps or other spaces. The support member 105 can be formed of a material that has etch selectivity relative to the second material layer 102 and the third material layer 103.

[0097] One or more second openings OP2 may be formed extending through multiple preliminary structures pST in the third direction D3. Each of the second openings OP2 may be formed between adjacent support members 105 in the second direction D2.

[0098] refer to Figure 10 and Figure 11The second material layer 102 exposed by the second opening OP2 can be removed, allowing a first recessed region RS1 to be formed between adjacent first (1-1) material layers 101a and (1-2) material layers 101b. The term "exposed" (or "expose" or similar terms) may be used herein to describe relationships between elements and / or to refer to intermediate processes in the manufacture of semiconductor devices, but may not require the exposure of a specific element in the completed device. Similarly, the term "not exposed" may be used to describe relationships between elements and / or to refer to intermediate processes in the manufacture of semiconductor devices, but may not require a specific element to be unexposed in the completed device.

[0099] The second material layer 102 can be etched isotropically using an etching process that is selective for etching relative to the first (1-1) material layer 101a, the first (1-2) material layer 101b, the third material layer 103, and the support member 105. When the second material layer 102 is removed, the first (1-1) material layer 101a, the first (1-2) material layer 101b, and the third material layer 103 can be supported by the support member 105.

[0100] The thickness of the first recessed region RS1 in the third direction D3 (i.e., the distance between adjacent material layers 101a and 101b) can be substantially the same as the thickness of the second material layer 102.

[0101] refer to Figure 11 and Figure 12 A first gate insulating layer GI1 and a back gate electrode BG can be formed, which fill a portion of the first recessed region RS1. For example, the back gate electrode BG may include a first conductive pattern M1.

[0102] For example, a first gate insulating layer GI1 can be formed extending along the first recessed region RS1 and the second opening OP2. A preliminary conductive pattern for filling the first recessed region RS1 and the second opening OP2 can be formed on the first gate insulating layer GI1. The first gate insulating layer GI1 and the preliminary conductive layer can be partially etched to form the first gate insulating layer GI1 and the back gate electrode BG, which fills a portion of the first recessed region RS1. The first gate insulating layer GI1 can extend along the upper surface of the back gate electrode BG and the side and lower surfaces of the back gate electrode BG facing the support 105. Partial etching of the first gate insulating layer GI1 and the preliminary conductive layer can be performed using an etch-back technique.

[0103] Since the thickness of the first recessed region RS1 in the third direction D3 is determined according to the second material layer 102 (see...), Figure 10The thickness of the second material layer 102 varies in the third direction D3, thus allowing adjustment of the thickness of the back gate electrode BG formed in the first recessed region RS1 in the third direction D3. The thickness of the second material layer 102 can be, for example, from about 10 Å to 600 Å.

[0104] refer to Figure 12 and Figure 13 A first gap filling layer 110 can be formed to fill a portion of the first recessed region RS1 and the second opening OP2. The first gap filling layer 110 can be made of an insulating material that has etch selectivity relative to the (1-1) material layer 101a, the (1-2) material layer 101b and the third material layer 103.

[0105] refer to Figure 13 and Figure 14 A portion of the first gap filler layer 110 in the second opening OP2 can be removed, allowing the formation of a first cover pattern CP1 for filling the first recessed region RS1. Removal of the first gap filler layer 110 can be performed using an etch-back technique. The side surfaces of the first cover pattern CP1 can be coplanar with the side surfaces of the (1-1) material layer 101a and the (1-2) material layer 101b in the third direction D3.

[0106] The first cover pattern CP1 may be a first gap fill layer 110 for filling the first recessed region RS1. The first cover pattern CP1 may be formed between adjacent (1-1) material layers 101a and (1-2) material layers 101b. The first cover pattern CP1 may fill the first recessed region RS1 on the first gate insulating layer GI1 and the back gate electrode BG (see...). Figure 11 and Figure 12 ).

[0107] refer to Figure 14 and Figure 15 The third material layer 103 exposed by the second opening OP2 can be removed, allowing a second recessed region RS2 to be formed between adjacent first (1-2) material layers 101b and (1-1) material layers 101a. The third material layer 103 can be isotropically etched using an etching process that is selective for etching relative to the first (1-1) material layer 101a, the first (1-2) material layer 101b, the support 105, and the first cover pattern CP1.

[0108] The thickness of the second recessed region RS2 in the third direction D3 (i.e., the distance between adjacent material layers 101b and 101a, the (1-2)th material layer 101b) can be substantially the same as the thickness of the third material layer 103.

[0109] refer to Figure 15 and Figure 16 A preliminary gate insulating layer pGI can be formed extending along the second recessed region RS2 and the second opening OP2. A preliminary gate electrode pGE extending along the preliminary gate insulating layer pGI can be formed on the preliminary gate insulating layer pGI. The preliminary gate insulating layer pGI and the preliminary gate electrode pGE can partially fill the second recessed region RS2 and the second opening OP2. For example, the preliminary gate electrode pGE may include a second conductive pattern M2.

[0110] Since the thickness of the second recessed region RS2 in the third direction D3 varies depending on the thickness of the third material layer 103 in the third direction D3, the thickness of the third material layer 103 can be adjusted so that the thickness of the initial gate electrode pGE, which will subsequently become the first gate electrode GE1 and the second gate electrode GE2 in the second recessed region RS2, can be adjusted. The thickness of the third material layer 103 can be, for example, from about 10 Å to 600 Å.

[0111] refer to Figure 16 and Figure 17 A preliminary interlayer insulating layer (pILD) for filling the second recessed region RS2 and the second opening OP2 can be formed on the preliminary gate electrode pGE. The preliminary interlayer insulating layer pILD can fill the space between the preliminary gate electrodes pGE that are adjacent to each other on the third direction D3 in the second recessed region RS2.

[0112] refer to Figure 17 and Figure 18 A portion of the initial interlayer insulation layer pILD filled in the second recessed region RS2 and the initial interlayer insulation layer pILD in the second opening OP2 can be removed to form an interlayer insulation layer ILD.

[0113] refer to Figure 19 The initial gate insulating layer pGI and the initial gate electrode pGE extending along the sidewall of the second opening OP2 can be etched. Therefore, the initial gate insulating layer pGI and the initial gate electrode pGE filling a portion of the second recessed region RS2 can be retained. When the initial gate insulating layer pGI and the initial gate electrode pGE are etched, the first gate insulating layer GI1 and the back gate electrode BG may not be etched by the first overlay pattern CP1. Etching a portion of the initial gate insulating layer pGI and the initial gate electrode pGE can be performed using an etch-back technique.

[0114] refer to Figure 19 and 20 The support member 105 can be removed, allowing the first opening to be formed again. Figure 9 (OP1). The first gate insulating layer GI1 and the preliminary gate insulating layer pGI can be exposed through the first opening OP1.

[0115] refer to Figure 20 and Figure 21 A portion of the first gate insulating layer GI1 and the back gate electrode BG can be removed through the first opening OP1, allowing a third recessed region RS3 to be formed between the (1-1) material layer 101a and the (1-2) material layer 101b, which are adjacent to each other along the third direction D3. The first gate insulating layer GI1 can be formed on the upper and lower surfaces of the back gate electrode BG.

[0116] A portion of the initial gate insulating layer pGI and the initial gate electrode pGE can be removed through the first opening OP1, allowing a fourth recessed region RS4 to be formed between adjacent material layers 101b and 101a (1-2). A portion of the initial gate insulating layer pGI and the initial gate electrode pGE can also be removed through the first opening OP1, allowing the formation of a first gate electrode GE1 and a second gate electrode GE2 spaced apart by interlayer insulating layers (ILDs), a second gate insulating layer GI2 on the lower surface of the first gate electrode GE1, and a third gate insulating layer GI3 on ​​the upper surface of the second gate electrode GE2. Etching of the initial gate insulating layer pGI and the initial gate electrode pGE can be performed using an etch-back technique.

[0117] refer to Figure 21 and Figure 22 A second gap filling layer 120 can be formed to fill the first opening OP1, the second opening OP2, the second recessed region RS2, the third recessed region RS3 and the fourth recessed region RS4.

[0118] refer to Figure 22 and Figure 23 The second gap filler layer 120 in the first opening OP1 and the second opening OP2 can be removed, so that the second overlay pattern CP2, the first spacer pattern SS1, and the second spacer pattern SS2 can be formed. Removal of a portion of the second gap filler layer 120 can be performed using an etch-back technique.

[0119] The second cover pattern CP2 may be a second gap fill layer 120 for filling the second recessed region RS2. The second cover pattern CP2 may be formed between the (1-2)th material layer 101b and the (1-1)th material layer 101a, which are adjacent to each other along the third direction D3. The second cover pattern CP2 may fill the second recessed region RS2 on the second gate insulating layer GI2, the first gate electrode GE1, the interlayer insulating layer ILD, and the second gate electrode GE2.

[0120] The first spacer pattern SS1 may be a second gap filler layer 120 for filling the third recessed region RS3. The first spacer pattern SS1 may be formed between the (1-1) material layer 101a and the (1-2) material layer 101b that are adjacent to each other on the third-direction D3. The first spacer pattern SS1 may fill the third recessed region RS3 on the first gate insulating layer GI1 and the back gate electrode BG.

[0121] The second spacer pattern SS2 can be a second gap filler layer 120 used to fill the fourth recessed region RS4. The second spacer pattern SS2 can be formed between adjacent first (1-2) material layers 101b and (1-1) material layers 101a. The second spacer pattern SS2 can fill the fourth recessed region RS4 on the second gate insulating layer GI2, the first gate electrode GE1, the interlayer insulating layer ILD, and the second gate electrode GE2.

[0122] The lengths of the first overlay pattern CP1, the second overlay pattern CP2, the first spacer pattern SS1, and the second spacer pattern SS2 in the second direction D2 can be adjusted, thereby allowing adjustment of the lengths of the back gate electrode BG, the first gate electrode GE1, and the second gate electrode GE2 in the second direction D2. The lengths of the back gate electrode BG, the first gate electrode GE1, and the second gate electrode GE2 in the second direction D2 can be, for example, from about 10 Å to 600 Å.

[0123] Subsequently, a portion of the (1-1) material layer 101a and the (1-2) material layer 101b can be removed through the first opening OP1, allowing the formation of a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The first spacer pattern SS1 and the second spacer pattern SS2 may protrude (i.e., extend) further than the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the second direction D2. A gap can be formed between the first spacer pattern SS1 and the second spacer pattern SS2.

[0124] The capacitor CAP can be formed in the first opening OP1. The storage electrode SE can be formed in the gap.

[0125] Bit line BL can be formed in the second opening OP2.

[0126] In a method for manufacturing a semiconductor memory device according to some embodiments, the back gate electrode BG can be formed by a process separate from that of the first gate electrode GE1 and the second gate electrode GE2. Therefore, the back gate electrode BG and each of the first gate electrode GE1 and the second gate electrode GE2 can be formed of a suitable material and can include various film materials. Furthermore, various relationships can exist between the length of the back gate electrode BG in the second direction D2 and the lengths of the first gate electrode GE1 and the second gate electrode GE2 in the second direction D2, and various relationships can exist between the thickness of the back gate electrode BG in the third direction D3 and the thicknesses of the first gate electrode GE1 and the second gate electrode GE2 in the third direction D3.

[0127] The first gate insulating layer GI1 can be formed by a process separate from that of the second gate insulating layer GI2 and the third gate insulating layer GI3. Therefore, each of the first to third gate insulating layers GI1, GI2, and GI3 can be formed from a suitable material. Furthermore, various relationships can exist between the thickness of the first gate insulating layer GI1 and the thicknesses of the second and third gate insulating layers GI2 and GI3 on ​​the third direction D3.

[0128] The first covering pattern CP1 and the second covering pattern CP2 can be formed by separate processes. Therefore, each of the first covering pattern CP1 and the second covering pattern CP2 can be formed from a suitable material. Furthermore, various relationships can exist between the length of the first covering pattern CP1 in the second direction D2 and the length of the second covering pattern CP2 in the second direction D2, and various relationships can exist between the thickness of the first covering pattern CP1 in the third direction D3 and the thickness of the second covering pattern CP2 in the third direction D3.

[0129] Figure 23 This is an exemplary schematic cross-sectional view illustrating a semiconductor memory device according to some embodiments. For reference, Figure 23 It shows cross-sectional views of the first to third semiconductor patterns SP1, SP2 and SP3 taken along the second direction D2.

[0130] refer to Figure 23In a semiconductor memory device according to some embodiments, the structure ST may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, a back gate electrode BG, a first gate electrode GE1, a second gate electrode GE2, a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, a first spacer pattern SS1, a second spacer pattern SS2, a third spacer pattern SS3, a first cover pattern CP1, a second cover pattern CP2, a third cover pattern CP3, and a capacitor CAP. In the structure ST, the back gate electrode BG, the first semiconductor pattern SP1, the first gate electrode GE1, the second semiconductor pattern SP2, the second gate electrode GE2, and the third semiconductor pattern SP3 may be stacked sequentially along a third direction D3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other sequentially along a third direction D3.

[0131] A first semiconductor pattern SP1 may be located between a back gate electrode BG and a first gate electrode GE1. The back gate electrode BG may be disposed on the lower surface of the first semiconductor pattern SP1, and the first gate electrode GE1 may be disposed on the upper surface of the first semiconductor pattern SP1. A second semiconductor pattern SP2 may be located between the first gate electrode GE1 and the second gate electrode GE2. The first gate electrode GE1 may be disposed on the lower surface of the second semiconductor pattern SP2, and the second gate electrode GE2 may be disposed on the upper surface of the second semiconductor pattern SP2. A third semiconductor pattern SP3 may be located between the second gate electrode GE2 of the first structure and the back gate electrode BG of the second structure disposed above the first structure. The second gate electrode GE2 of the first structure may be disposed on the lower surface of the third semiconductor pattern SP3 of the first structure, and the back gate electrode BG of the second structure may be disposed on the upper surface of the third semiconductor pattern SP3 of the first structure.

[0132] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may extend in the second direction D2. Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include a first impurity region, a channel region, and a second impurity region. The first impurity region of each of the first to third semiconductor patterns may be electrically connected to the bit line BL. The second impurity region of each of the first to third semiconductor patterns SP1, SP2, and SP3 may be electrically connected to each memory electrode SE.

[0133] The third semiconductor pattern SP3 may include semiconductor materials such as silicon, germanium, or silicon-germanium, although the implementation is not limited thereto. For example, the third semiconductor pattern SP3 may include at least one of polycrystalline silicon, polycrystalline silicon-germanium, monocrystalline silicon, or monocrystalline silicon-germanium. In some embodiments, the first semiconductor patterns to the third semiconductor patterns SP1, SP2, and SP3 may include the same material.

[0134] The second gate insulating layer GI2 can extend along the lower and upper surfaces of the first gate electrode GE1. The third gate insulating layer GI3 can extend along the lower and upper surfaces of the second gate electrode GE2. The first gate insulating layer GI1 can be located between the back gate electrode BG and the first semiconductor pattern SP1, and between the back gate electrode BG and the third semiconductor pattern SP3. The second gate insulating layer GI2 can be located between the first gate electrode GE1 and the first semiconductor pattern SP1, and between the first gate electrode GE1 and the second semiconductor pattern SP2. The third gate insulating layer GI3 can be located between the second gate electrode GE2 and the second semiconductor pattern SP2, and between the second gate electrode GE2 and the third semiconductor pattern SP3.

[0135] The second overlay pattern CP2 can be located between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The second overlay pattern CP2 can also be located between the first gate electrode GE1 and the bit line BL. The third overlay pattern CP3 can be located between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The third overlay pattern CP3 can also be located between the second gate electrode GE2 and the bit line BL.

[0136] The second spacer pattern SS2 may be located between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The second spacer pattern SS2 may also be located between the first gate electrode GE1 and the capacitor CAP. The third spacer pattern SS3 may be located between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The third spacer pattern SS3 may also be located between the second gate electrode GE2 and the capacitor CAP. The first to third spacer patterns SS1, SS2, and SS3 may protrude further than the first to third semiconductor patterns SP1, SP2, and SP3 in the second direction D2.

[0137] Storage electrodes SE can be formed on each of the first to third semiconductor patterns SP1, SP2, and SP3. Each storage electrode SE can be between first spacer patterns SS1 and second spacer patterns SS2 that are adjacent to each other on the third direction D3, between second spacer patterns SS2 and third spacer patterns SS3 that are adjacent to each other on the third direction D3, and between third spacer patterns SS3 and first spacer patterns SS1 that are adjacent to each other on the third direction D3. Storage electrodes SE included in each capacitor CAP are separated from each other. In a structure ST, storage electrodes SE that are adjacent to each other on the third direction D3 can be separated from each other by first spacer pattern SS1, second spacer pattern SS2, or third spacer pattern SS3.

[0138] Each of the back gate electrode BG and the first gate electrode GE1 and the second gate electrode GE2 can be a single layer or multiple layers. For example, the back gate electrode BG may include a first conductive pattern M1 and a third conductive pattern.

[0139] Figures 24 to 31 This is a schematic diagram illustrating intermediate processes in an example method for manufacturing a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided with reference to... Figures 1 to 23 The redundant parts of the description, and the description will be based on the Figures 1 to 23 The differences in the descriptions.

[0140] refer to Figure 24 A preliminary structure pST can be formed on the substrate 100, which is repeatedly stacked along the third direction D3. The preliminary structure pST may include a first material layer 201, a (2-1) material layer 202a, a (3-1) material layer 203a, a (2-2) material layer 202b, a (3-2) material layer 203b, and a (2-3) material layer 202c, which are stacked sequentially on the third direction D3.

[0141] Material layers 202a, 202b, and 202c (2-1), (2-2), and (2-3) may include the same material, and material layers 203a (3-1) and 203b (3-2) may include the same material. Material layers 202a, 202b, and 202c (2-1), (2-2), and (2-3) may include materials different from those of material layers 203a (3-1) and 203b (3-2). Material layers 202a, 202b, and 202c (2-1), (2-2), and (2-3) may include, for example, silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The first material layer 201 may be formed of a material having etch selectivity relative to the (2-1), (2-2), and (2-3) material layers 202a, 202b, and 202c, and the (3-1) and (3-2) material layers 203a and 203b. The (2-1), (2-2), and (2-3) material layers 202a, 202b, and 202c may be formed of a material having etch selectivity relative to the (3-1) material layer 203a and the (3-2) material layer 203b.

[0142] refer to Figure 25 It can form one or more first openings OP1 extending through multiple preliminary structures pST on the third-party D3.

[0143] refer to Figure 26 A support 105 for filling the first opening OP1 can be formed. The support 105 can be formed of a material that has etch selectivity relative to the second material layer 102 and the third material layer 103.

[0144] One or more second openings OP2 may be formed extending through multiple preliminary structures pST in the third direction D3. Each of the second openings OP2 may be formed between adjacent support members 105 in the second direction D2.

[0145] refer to Figure 26 and Figure 27 The first material layer 201 exposed by the second opening OP2 can be removed, so that a first recessed region RS1 can be formed between the (2-3) material layers 202c and (2-1) material layers 202a that are adjacent to each other on the third direction D3.

[0146] The first material layer 201 can be isotropically etched using an etching process that is selective for etching relative to the (2-1) to (2-3) material layers 202a, 202b and 202c, the (3-1) and (3-2) material layers 203a and 203b, and the support member 105. When the first material layer 201 is removed, the (2-1) to (2-3) material layers 202a, 202b and 202c and the (3-1) and (3-2) material layers 203a and 203b can be supported by the support member 105.

[0147] The thickness of the first recessed region RS1 in the third direction D3 (i.e., the distance between the adjacent (2-3) material layer 202c and (2-1) material layer 202a) can be substantially the same as the thickness of the first material layer 201.

[0148] refer to Figure 27 and Figure 28 A first gate insulating layer GI1 and a back gate electrode BG disposed on the first gate insulating layer GI1 can be formed, which fill a portion of the first recessed region RS1.

[0149] Since the thickness of the first recessed region RS1 in the third direction D3 varies depending on the thickness of the first material layer 201 in the third direction D3, the thickness of the back gate electrode BG formed in the first recessed region RS1 in the third direction D3 can also vary. The thickness of the first material layer 201 can be adjusted so that the thickness of the back gate electrode BG can be adjusted accordingly. The thickness of the first material layer 201 can be, for example, from about 10 Å to 600 Å.

[0150] refer to Figure 28 and Figure 29 A first gap filling layer 110 can be formed to fill the first recessed region RS1 and the second opening OP2. The first gap filling layer 110 can be formed of an insulating material having etch selectivity relative to the (2-1) material layers to the (2-3) material layers 202a, 202b and 202c and the (3-1) material layer 203a and the (3-2) material layer 203b.

[0151] refer to Figure 30 At least a portion of the first gap filling layer 110 in the second opening OP2 can be removed, so that a first cover pattern CP1 for filling the first recessed region RS1 can be formed. The first cover pattern CP1 may be the remaining portion of the first gap filling layer 110 for filling the first recessed region RS1.

[0152] Subsequently, the (3-1) material layer 203a exposed by the second opening OP2 can be removed, so that a (2-1) recessed region RS2a can be formed between the (2-1) material layer 202a and the (2-2) material layer 202b, and the (3-2) material layer 203b can be removed, so that a (2-2) recessed region RS2b can be formed between the (2-2) material layer 202b and the (2-3) material layer 202c. The (3-1) material layer 203a and the (3-2) material layer 203b can be etched isotropically by an etching process that has etching selectivity relative to the (2-1) to (2-3) material layers 202a, 202b and 202c, the support 105 and the first cover pattern CP1.

[0153] The thickness of each of the (2-1) recessed region RS2a and the (2-2) recessed region RS2b in the third direction D3 can be substantially the same as the thickness of each of the (3-1) material layer 203a and the (3-2) material layer 203b.

[0154] refer to Figure 30 and Figure 31 A second gate insulating layer GI2 and a first gate electrode GE1 can be formed to fill a portion of the (2-1) recessed region RS2a, and a third gate insulating layer GI3 and a second gate electrode GE2 can be formed to fill a portion of the (2-2) recessed region RS2b. The first gate electrode GE1 and the second gate electrode GE2 may include a second conductive pattern M2. The second gate insulating layer GI2 may extend along the upper surface of the first gate electrode GE1 and the side and lower surfaces of the first gate electrode GE1 facing the support 105. The third gate insulating layer GI3 may extend along the upper surface of the second gate electrode GE2 and the side and lower surfaces of the second gate electrode GE2 facing the support 105.

[0155] For example, a preliminary gate dielectric layer extending along the second opening OP2 and the (2-1) recessed regions RS2a and RS2b, and a preliminary gate electrode extending along the preliminary gate dielectric layer, can be formed. The preliminary gate electrode can fill the (2-1) recessed regions RS2a and RS2b on the preliminary gate dielectric layer. A portion of the preliminary gate electrode and the preliminary gate dielectric layer can be etched to form a second gate insulating layer GI2 and a third gate insulating layer GI3, as well as a first gate electrode GE1 and a second gate electrode GE2 to partially fill the (2-1) recessed regions RS2a and RS2b. The etching of the preliminary gate dielectric layer and a portion of the preliminary gate electrode can be performed using an etch-back technique.

[0156] The thickness of the (3-1) material layer 203a can be adjusted so that the thickness of the first gate electrode GE1 formed in the (2-1) recessed region RS2a can be adjusted. The thickness of the (3-2) material layer 203b can be adjusted so that the thickness of the second gate electrode GE2 formed in the (2-2) recessed region RS2b can be adjusted. The thickness of each of the (3-1) material layer 203a and the (3-2) material layer 203b can be, for example, from about 10 Å to 600 Å.

[0157] refer to Figure 31 and Figure 23 The support member 105 can be removed, allowing the first opening to be formed again. Figure 25 (OP1). The first gate insulating layer to the third gate insulating layers GI1, GI2 and GI3 can be exposed through the first opening OP1.

[0158] A portion of the first gate insulating layer GI1 and the back gate electrode BG, a portion of the second gate insulating layer GI2 and the first gate electrode GE1, and a portion of the third gate insulating layer GI3 and the second gate electrode GE2 can be removed through the first opening OP1. A first spacer pattern SS1 can be formed in the space where the first gate insulating layer GI1 and a portion of the back gate electrode BG have been removed; a second spacer pattern SS2 can be formed in the space where the second gate insulating layer GI2 and a portion of the first gate electrode GE1 have been removed; and a third spacer pattern SS3 can be formed in the space where the third gate insulating layer GI3 and a portion of the second gate electrode GE2 have been removed.

[0159] A second cover pattern CP2 for filling the (2-1) recessed region RS2a can be formed on the second gate insulating layer GI2 and the first gate electrode GE1. A third cover pattern CP3 for filling the (2-2) recessed region RS2b can be formed on the third gate insulating layer GI3 and the second gate electrode GE2.

[0160] Subsequently, a portion of the (2-1) to (2-3) material layers 202a, 202b, and 202c can be removed through the first opening OP1, allowing the formation of the first to third semiconductor patterns SP1, SP2, and SP3. Gaps can be formed between the first spacer pattern SS1 and the second spacer pattern SS2, between the second spacer pattern SS2 and the third spacer pattern SS3, and between the third spacer pattern SS3 and the first spacer pattern SS1, respectively.

[0161] A capacitor CAP can be formed in the first opening OP1. A storage electrode SE can be formed in each gap. A bit line BL can be formed in the second opening OP2.

[0162] Figure 32This is an exemplary schematic cross-sectional view illustrating a semiconductor memory device according to some embodiments. For reference, Figure 32 This is a cross-sectional view showing the first semiconductor pattern SP1 taken along the second direction D2. For ease of description, a brief description will be provided with reference to... Figures 1 to 31 The redundant parts of the description, and the description will be based on the Figures 1 to 31 The differences in the descriptions.

[0163] refer to Figure 32 In a semiconductor memory device according to some embodiments, the structure ST may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a back gate electrode BG, a first gate electrode GE1, a first gate insulating layer GI1, a second gate insulating layer GI2, a first spacer pattern SS1, a second spacer pattern SS2, a first cover pattern CP1, a second cover pattern CP2, and a capacitor CAP. In the structure ST, the back gate electrode BG, the first semiconductor pattern SP1, the first gate electrode GE1, and the second semiconductor pattern SP2 may be stacked sequentially along a third direction D3. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be spaced apart from each other sequentially along a third direction D3.

[0164] In some embodiments, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may comprise their respective materials, which are different from each other, and / or may have their respective physical properties (e.g., shape, size, etc.), which are different from each other. Physical properties may also include, for example, composition, crystal orientation (i.e., orientation), and average grain size. For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may comprise the same material, but may have their respective compositions, which are different from each other.

[0165] Figures 33 to 41 This is a schematic diagram illustrating intermediate processes in an example method for manufacturing a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided with reference to... Figures 1 to 32 The redundant parts of the description, and the description will be based on the Figures 1 to 32 The differences in the descriptions.

[0166] refer to Figure 33 A preliminary structure pST, which is repeatedly stacked along the third direction D3, can be formed on the substrate 100. The preliminary structure pST may include a first material layer 301, a second material layer 302, a third material layer 303, and a fourth material layer 304, which are sequentially stacked on the third direction D3.

[0167] The second material layer 302 and the fourth material layer 304 may comprise different materials and / or have different physical properties. Each of the second material layer 302 and the fourth material layer 304 may comprise, for example, silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The first material layer 301 and the third material layer 303 may be formed of materials that are etch-selective relative to the second material layer 302 and the fourth material layer 304. The second material layer 302 may be formed of a material that is etch-selective relative to the fourth material layer 304.

[0168] refer to Figure 34 This can form a first opening OP1 extending through multiple preliminary structures pST in the third direction D3. The multiple first openings OP1 can be arranged spaced apart from each other in the second direction D2.

[0169] refer to Figure 35 A support 105 for filling the first opening OP1 can be formed. The support 105 can be formed of a material that has etch selectivity relative to the first material layer 301 and the third material layer 303.

[0170] A second opening OP2 can be formed extending through multiple preliminary structures pST in the third direction D3. The second opening OP2 can be formed between adjacent support members 105. Multiple second openings OP2 can be formed, spaced apart from each other in the second direction D2.

[0171] refer to Figure 35 and Figure 36 The first material layer 301 exposed by the second opening OP2 can be removed, so that a first recessed region RS1 can be formed between the fourth material layer 304 and the second material layer 302 that are adjacent to each other on the third direction D3.

[0172] The first material layer 301 can be isotropically etched using an etching process that is selective for etching relative to the second to fourth material layers 302, 303, and 304 and the support member 105. When the first material layer 301 is removed, the second to fourth material layers 302, 303, and 304 can be supported by the support member 105.

[0173] The thickness of the first recessed region RS1 in the third direction D3 (i.e., the distance between adjacent fourth material layers 304 and second material layers 302) can be substantially the same as the thickness of the first material layer 301.

[0174] refer to Figure 36 and Figure 37 A first gate insulating layer GI1 and a back gate electrode BG can be formed, which fill a portion of the first recessed region RS1. For example, the back gate electrode BG may include a first conductive pattern M1.

[0175] Since the thickness of the first recessed region RS1 in the third direction D3 varies depending on the thickness of the first material layer 301 in the third direction D3, the thickness of the back gate electrode BG formed in the first recessed region RS1 in the third direction D3 can also vary. The thickness of the first material layer 301 can be adjusted so that the thickness of the back gate electrode BG can be adjusted. The thickness of the first material layer 301 can be, for example, from about 10 Å to 600 Å.

[0176] refer to Figure 37 and Figure 38 A first gap-filling layer 110 can be formed to fill the first recessed region RS1 and the second opening OP2. The first gap-filling layer 110 can be formed of an insulating material that has etch selectivity relative to the third material layer 303.

[0177] refer to Figure 39 At least a portion of the first gap filling layer 110 in the second opening OP2 can be removed, so that a first cover pattern CP1 for filling the first recessed region RS1 can be formed. The first cover pattern CP1 may be the remaining portion of the first gap filling layer 110 for filling the first recessed region RS1.

[0178] refer to Figure 39 and Figure 40 The third material layer 303 can be removed through the second opening OP2, allowing a second recessed region RS2 to be formed between the second material layer 302 and the fourth material layer 304, which are adjacent to each other in the third direction D3. The third material layer 303 can be isotropically etched using an etching process that is selective for etching relative to the second and fourth material layers 302 and 304, the support 105, and the first overlay pattern CP1.

[0179] refer to Figure 40 and Figure 41 A second gate insulating layer GI2 and a first gate electrode GE1 can be formed to fill a portion of the second recessed region RS2. The first gate electrode GE1 may include a second conductive pattern M2. The second gate insulating layer GI2 may extend along the upper surface of the first gate electrode GE1 and the side and lower surfaces of the first gate electrode GE1 facing the support 105.

[0180] refer to Figure 41 and Figure 32 The support member 105 can be removed, allowing the first opening to be formed again. Figure 34 (OP1). The first gate insulating layer GI1 and the second gate insulating layer GI2 can be exposed through the first opening OP1.

[0181] A portion of the first gate insulating layer GI1 and the back gate electrode BG, as well as a portion of the second gate insulating layer GI2 and the first gate electrode GE1, can be removed through the first opening OP1. A first spacer pattern SS1 can be formed in the space where a portion of the first gate insulating layer GI1 and the back gate electrode BG has been removed, and a second spacer pattern SS2 can be formed in the space where a portion of the second gate insulating layer GI2 and the first gate electrode GE1 has been removed.

[0182] A second cover pattern CP2 for filling the second recessed region RS2 can be formed on the second gate insulating layer GI2 and the first gate electrode GE1.

[0183] Subsequently, a portion of the second material layer 302 and the fourth material layer 304 can be removed through the first opening OP1, allowing the formation of a first semiconductor pattern SP1 and a second semiconductor pattern SP2. Gaps can be formed between the first spacer pattern SS1 and the second spacer pattern SS2, and between the second spacer pattern SS2 and the first spacer pattern SS1, respectively.

[0184] A capacitor CAP can be formed in the first opening OP1. A storage electrode SE can be formed in each gap. A bit line BL can be formed in the second opening OP2.

[0185] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present disclosure can be made in various forms and is not limited to the embodiments described above, and can be embodied in other specific forms without departing from the technical spirit and essential characteristics of the present disclosure. Therefore, the above embodiments are to be considered illustrative rather than restrictive in all respects.

[0186] Cross-references to related applications

[0187] Related Application This application claims priority and all benefits to Korean Patent Application No. 10-2024-0116220, filed on August 28, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device comprising: a back gate electrode on a substrate, including a first conductive pattern; a first gate electrode on the back gate electrode, including a second conductive pattern; and a first semiconductor pattern between the back gate electrode and the first gate electrode, wherein the first conductive pattern and the second conductive pattern include respective materials different from each other and / or have respective physical properties different from each other. The first conductive pattern has a composition different from a composition of the second conductive pattern.

2. The semiconductor memory device according to claim 1, wherein, A first size of an average grain of the first conductive pattern is different from a second size of an average grain of the second conductive pattern.

3. The semiconductor memory device according to claim 1, wherein, A first crystal direction of the first conductive pattern is different from a second crystal direction of the second conductive pattern.

4. The semiconductor memory device according to claim 1, wherein, The back gate electrode and the first gate electrode extend in a first direction parallel to an upper surface of the substrate, and 5. The semiconductor memory device according to claim 1, wherein, a length of the back gate electrode in a second direction parallel to the upper surface of the substrate and intersecting the first direction is different from a length of the first gate electrode in the second direction. A first thickness of the back gate electrode in a third direction perpendicular to the upper surface of the substrate is different from a second thickness of the first gate electrode in the third direction.

6. The semiconductor memory device according to claim 1, wherein, The back gate electrode further includes a third conductive pattern including a material different from the first conductive pattern and / or having a physical property different from the first conductive pattern.

7. The semiconductor memory device according to claim 1, wherein, The first gate electrode further includes a third conductive pattern including a material different from the second conductive pattern and / or having a physical property different from the second conductive pattern.

8. The semiconductor memory device according to claim 1, wherein, 9. A semiconductor memory device comprising: a plurality of structures stacked on a substrate in a third direction perpendicular to an upper surface of the substrate; and a bit line extending in the third direction, wherein each of the plurality of structures includes: a back gate electrode including a first conductive pattern; a first semiconductor pattern on the back gate electrode; a first gate electrode on the first semiconductor pattern, including a second conductive pattern; and a data storage element on the first semiconductor pattern, wherein the bit line is electrically connected to a first end portion of the first semiconductor pattern, wherein the data storage element is electrically connected to a second end portion of the first semiconductor pattern, and wherein the first conductive pattern and the second conductive pattern include respective materials different from each other and / or have respective physical properties different from each other.

10. The semiconductor memory device according to claim 9, wherein each of the plurality of structures further includes a second semiconductor pattern, a second gate electrode on the first gate electrode, and an interlayer insulating layer between the first gate electrode and the second gate electrode, the back gate electrode is between the second semiconductor pattern and the first semiconductor pattern, the bit line is electrically connected to a first end portion of the second semiconductor pattern, and the data storage element is electrically connected to a second end portion of the second semiconductor pattern. The second gate electrode includes a second conductive pattern. ​ 11. The semiconductor memory device according to claim 10, wherein, ​ 12. The semiconductor memory device according to claim 9, wherein each of the plurality of structures further includes a second semiconductor pattern on the first gate electrode, the first gate electrode is between the first semiconductor pattern and the second semiconductor pattern, the bit line is electrically connected to a first end portion of the second semiconductor pattern, the data storage element is electrically connected to a second end portion of the second semiconductor pattern, and the first semiconductor pattern and the second semiconductor pattern include the same material.

13. The semiconductor memory device according to claim 9, wherein each of the plurality of structures further includes a second semiconductor pattern on the first gate electrode, the first gate electrode is between the first semiconductor pattern and the second semiconductor pattern, the bit line is electrically connected to a first end portion of the second semiconductor pattern, the data storage element is electrically connected to a second end portion of the second semiconductor pattern, and the first semiconductor pattern and the second semiconductor pattern include respective materials different from each other.

14. The semiconductor memory device according to claim 9, wherein each of the plurality of structures further includes a second semiconductor pattern on the first gate electrode, a second gate electrode on the second semiconductor pattern, and a third semiconductor pattern on the second gate electrode, the bit line is electrically connected to a first end portion of the second semiconductor pattern and a first end portion of the third semiconductor pattern, and the data storage element is electrically connected to a second end portion of the second semiconductor pattern and a second end portion of the third semiconductor pattern.

15. The semiconductor memory device according to claim 14, wherein, the second gate electrode includes the second conductive pattern.

16. The semiconductor memory device according to claim 9, wherein each of the plurality of structures further includes a first spacer pattern between the back gate electrode and the data storage element, and a second spacer pattern between the first gate electrode and the data storage element, the data storage element includes a storage electrode, a plate electrode, and a capacitor dielectric layer between the storage electrode and the plate electrode, and the storage electrode is between the first spacer pattern and the second spacer pattern.

17. A semiconductor memory device, comprising: a plurality of structures stacked on a substrate in a third direction perpendicular to an upper surface of the substrate; and a bit line extending in the third direction, wherein each of the plurality of structures includes: a back gate electrode extending in a first direction parallel to the upper surface of the substrate, including a first conductive pattern; a first gate insulating layer on an upper surface and a lower surface of the back gate electrode, a first gate electrode on the back gate electrode, extending in the first direction and including a second conductive pattern; a second gate insulating layer on a lower surface of the first gate electrode; a first semiconductor pattern between the back gate electrode and the first gate electrode, extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; and a data storage element on the first semiconductor pattern, wherein the bit line is electrically connected to a first end portion of the first semiconductor pattern. ​ wherein the data storage element is electrically connected to a second end portion of the first semiconductor pattern, and wherein the first conductive pattern and the second conductive pattern comprise respective materials different from each other and / or have respective physical properties different from each other.

18. The semiconductor memory device according to claim 17, wherein each of the plurality of structures further comprises: a second gate electrode over the first gate electrode; an interlayer insulating layer between the first gate electrode and the second gate electrode; a first spacer pattern between the back gate electrode and the data storage element; a first cover pattern between the back gate electrode and the bit line; a second spacer pattern between the first gate electrode, the interlayer insulating layer, and the second gate electrode and the data storage element; and a second cover pattern between the first gate electrode, the interlayer insulating layer, and the second gate electrode and the bit line.

19. The semiconductor memory device according to claim 17, wherein each of the plurality of structures further comprises a second semiconductor pattern over the first gate electrode, the first gate electrode is between the first semiconductor pattern and the second semiconductor pattern, and the second gate insulating layer is on an upper surface of the first gate electrode.

20. The semiconductor memory device according to claim 17, wherein each of the plurality of structures further comprises: a second semiconductor pattern over the first gate electrode; a first spacer pattern between the back gate electrode and the data storage element; a first cover pattern between the back gate electrode and the bit line; a second spacer pattern between the first gate electrode and the data storage element; and a second cover pattern between the first gate electrode and the bit line. ​ ​

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