Semiconductor memory device and electronic system including the same

Abstract

A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device includes: a substrate; a mold structure including a dummy pattern on a partial region of the substrate, a plurality of mold insulating layers and a plurality of gate electrodes alternately stacked in a first direction on the substrate over the dummy pattern; and a first word line contact extending into the molded structure and extending in a first direction. The plurality of gate electrodes includes a first gate electrode electrically connected to the first word line contact. The first gate electrode includes a first conductive plate portion extending in parallel with a surface of the substrate, a second conductive plate portion extending in parallel with the surface of the substrate and disposed at a different vertical level from the first conductive plate portion, and a conductive connection portion connecting the first conductive plate portion to the second conductive plate portion. The conductive connection portion connects the first conductive plate portion to the second conductive plate portion.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices and electronic systems including semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices capable of storing large amounts of data are in high demand in electronic systems requiring data storage. Therefore, some recent development efforts have focused on methods to increase the data capacity of semiconductor memory devices. For example, semiconductor devices characterized by three-dimensionally arranged memory cells have been proposed, replacing conventional semiconductor devices characterized by two-dimensionally arranged memory cells. Summary of the Invention

[0003] In general, in some aspects, this disclosure relates to semiconductor memory devices and electronic systems having improved electrical characteristics and / or reliability.

[0004] According to some embodiments, this disclosure relates to a semiconductor memory device, comprising: a substrate; a molding structure including a dummy pattern, a plurality of molding insulating layers, and a plurality of gate electrodes, the dummy pattern being on a portion of the substrate, the plurality of molding insulating layers and the plurality of gate electrodes being alternately stacked on the substrate in a first direction above the dummy pattern; and a first word line contact configured to penetrate the molding structure (extend into the molding structure) and extend in the first direction, wherein the plurality of gate electrodes includes a first gate electrode electrically connected to the first word line contact, wherein the first gate electrode includes a first conductive plate portion, a second conductive plate portion, and a conductive connection portion, the first conductive plate portion extending parallel to a surface of the substrate, the second conductive plate portion extending parallel to a surface of the substrate and disposed at a different vertical level from the first conductive plate portion, the conductive connection portion for connecting the first conductive plate portion to the second conductive plate portion, wherein the thickness of the conductive connection portion is greater than the thickness of the first conductive plate portion and the thickness of the second conductive plate portion, wherein the inner surface of the conductive connection portion contacts the outer surface of the first word line contact.

[0005] According to some embodiments, this disclosure relates to a semiconductor memory device, including: a peripheral circuit structure; and a cell structure stacked on the peripheral circuit structure, wherein the cell structure includes: a substrate including a cell array region and an extension region; a molding structure including a dummy pattern, a plurality of molded insulating layers, and a plurality of gate electrodes, the dummy pattern being on a portion of the substrate, the plurality of molded insulating layers and the plurality of gate electrodes being alternately stacked on the substrate in a first direction above the dummy pattern; a channel structure disposed in the cell array region, penetrating the molding structure and extending in the first direction; and a first word line contact disposed in the extension region, penetrating the molding structure. The plurality of gate electrodes are configured to extend in a first direction, wherein the plurality of gate electrodes include a first gate electrode electrically connected to a first word line contact, wherein the first gate electrode includes a first conductive plate portion, a second conductive plate portion, and a conductive connection portion, wherein the first conductive plate portion extends parallel to the surface of the substrate, the second conductive plate portion extends parallel to the surface of the substrate and is disposed at a different vertical level from the first conductive plate portion, the conductive connection portion is configured to connect the first conductive plate portion to the second conductive plate portion, wherein the thickness of the conductive connection portion is greater than the thickness of the first conductive plate portion and the thickness of the second conductive plate portion, and wherein the inner surface of the conductive connection portion contacts the outer surface of the first word line contact.

[0006] According to some embodiments, this disclosure relates to an electronic system comprising: a main substrate; a semiconductor memory device including a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate; and a controller electrically connected to the semiconductor memory device on the main substrate, wherein the cell structure includes: a substrate including a cell array region and an extension region; a molding structure including a dummy pattern, a plurality of molding insulating layers, and a plurality of gate electrodes, the dummy pattern being on a portion of the substrate, the plurality of molding insulating layers being configured to cover the dummy pattern and to be alternately stacked on the substrate in a first direction; a channel structure disposed in the cell array region, penetrating the molding structure, and extending in the first direction; and a first word line. A contact element, disposed in the extension region, penetrates the molded structure and extends in a first direction, wherein the plurality of gate electrodes includes a first gate electrode electrically connected to a first word line contact element, wherein the first gate electrode includes a first conductive plate portion, a second conductive plate portion and a conductive connection portion, the first conductive plate portion extending parallel to the surface of the substrate, the second conductive plate portion extending parallel to the surface of the substrate and disposed at a different vertical level from the first conductive plate portion, the conductive connection portion being configured to connect the first conductive plate portion to the second conductive plate portion, wherein the thickness of the conductive connection portion is greater than the thickness of the first conductive plate portion and the thickness of the second conductive plate portion, and wherein the inner surface of the conductive connection portion contacts the outer surface of the first word line contact element.

[0007] According to some embodiments, this disclosure relates to improving the reliability of semiconductor memory devices by simplifying process steps through maintaining etch stop levels for forming substantially identical multiple word line contacts. Attached Figure Description

[0008] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a plan view illustrating an example of a semiconductor memory device according to some embodiments.

[0010] Figure 2 It is based on some implementation methods along Figure 1 The sectional view taken by line AA.

[0011] Figure 3 It is based on some implementation methods along Figure 1 The sectional view taken by line BB.

[0012] Figure 4 This illustrates according to some embodiments. Figure 2 A magnified view of an example of region Q1.

[0013] Figure 5 This illustrates according to some embodiments. Figure 2 A magnified view of an example of region Q2.

[0014] Figure 6 This illustrates according to some embodiments. Figure 5 A magnified view of an example of region Q3.

[0015] Figures 7 to 9 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments.

[0016] Figure 10 and Figure 11 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments.

[0017] Figure 12 and Figure 13 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments.

[0018] Figure 14 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments.

[0019] Figure 15 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments.

[0020] Figures 16 to 21This is an intermediate stage diagram illustrating an example of a method for manufacturing a semiconductor memory device according to some embodiments.

[0021] Figure 22 This is a block diagram illustrating an example of an electronic system according to some implementations.

[0022] Figure 23 This is a perspective view illustrating an example of an electronic system including a semiconductor memory device according to some embodiments.

[0023] Figure 24 It is based on some implementation methods along Figure 23 A schematic cross-sectional view taken from line VV. Detailed Implementation

[0024] In the following text, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a plan view illustrating an example of a semiconductor memory device according to some embodiments. Figure 2 It is based on some implementation methods along Figure 1 The sectional view taken by line AA. Figure 3 It is based on some implementation methods along Figure 1 The sectional view taken by line BB. Figure 4 This illustrates according to some embodiments. Figure 2 A magnified view of an example of region Q1. Figure 5 This illustrates according to some embodiments. Figure 2 A magnified view of an example of region Q2. Figure 6 This illustrates according to some embodiments. Figure 5 A magnified view of an example of region Q3.

[0026] exist Figures 1 to 6 In this semiconductor memory device, a cell structure (CELL) and a peripheral circuit structure (PERI) may be included. The cell structure (CELL) may include a cell substrate 100, a first molding structure (MS1), a channel structure (CH), a bit line (BL), word line contacts 160, and contact spacers 170. In addition to the components shown in the figures, the cell structure (CELL) may also include components required for the semiconductor memory device.

[0027] The cell substrate 100 may include a cell array region CAR, an extension region EXT, and a through region THR. A memory cell array including multiple memory cells may be formed in the cell array region CAR. Channel structures CH, first molding structures MS1, bit lines BL, etc., may be disposed in the cell array region CAR. According to some embodiments, the description of component B being formed or disposed on component A is not limited to component B being formed or disposed in contact with component A. For example, according to some embodiments, component C may be placed between component B and component A. In the drawings, the description of component B being formed or disposed on component A is not limited to component B being placed above component A. For example, component B may be disposed below, to the right, or to the left of component A.

[0028] The extension region EXT can be placed around the cell array region CAR. For example, the extension region EXT can surround the cell array region CAR. Word line contacts 160, contact spacers 170, and support structures 150 can be placed within the extension region EXT.

[0029] The through-region THR can be placed outside the extension region EXT. For example, the through-region THR can be placed on one side of the extension region EXT, but this disclosure is not limited thereto. The source contact 180, input and output contacts, etc., can be placed in the through-region THR.

[0030] The cell substrate 100 may be disposed in the peripheral circuit structure PERI. The cell substrate 100 may include a semiconductor substrate (such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate). In some embodiments, the cell substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some embodiments, the cell substrate 100 may include polycrystalline silicon (polycrystalline Si).

[0031] Source structures 102 and 104 may be formed on cell substrate 100. Source structures 102 and 104 may be positioned between cell substrate 100 and first molded structure MS1. For example, source structures 102 and 104 may extend along the upper surface of cell substrate 100. Source structures 102 and 104 may be formed as semiconductor patterns of contact channel structure CH. For example, a second source layer 104 of source structures 102 and 104 may penetrate information storage layer 144 (e.g., extend into information storage layer 144) to contact the semiconductor pattern. Source structures 102 and 104 may be configured as a common source line of the semiconductor memory device (e.g., ...). Figure 22 (CSL). Source structures 102 and 104 may include, but are not limited to, doped metal or polysilicon.

[0032] According to some embodiments, the channel structure CH can penetrate the source structures 102 and 104. For example, the lower part of the channel structure CH can penetrate the source structures 102 and 104 to be disposed in the cell substrate 100.

[0033] According to some embodiments, source structures 102 and 104 may be formed of multiple layers. For example, source structures 102 and 104 may include a first source layer 102 and a second source layer 104 sequentially stacked on a cell substrate 100. The first source layer 102 and the second source layer 104 may each include impurity-doped polysilicon or impurity-free polysilicon, but this disclosure is not limited thereto. The first source layer 102 may be configured as a common source line of a semiconductor memory device that contacts a semiconductor pattern (e.g., Figure 22 The second source layer 104 can be used as a support layer to prevent the molded stack (e.g., molded structures MS1 and MS2) from collapsing or tipping over during the replacement process that forms the first source layer 102.

[0034] In some embodiments, a base insulating film may be placed between the cell substrate 100 and the source structures 102 and 104. The base insulating film may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

[0035] The molded structure MS1 may include a dummy pattern DP, a molded insulating layer 110, and a gate electrode 120. The dummy pattern DP may be disposed on a portion of the cell substrate 100. The dummy pattern DP may extend parallel to one side of the cell substrate 100 (e.g., in a first direction D1 and a second direction D2). According to some embodiments, the dummy pattern DP may be disposed in the cell array region CAR.

[0036] The dummy pattern DP can extend along the first direction D1 into the interior of the cell array region CAR or the boundary between the cell array CAR and the extended region EXT. Figure 2 The diagram shows that the thickness of the dummy pattern DP is substantially the same as the thickness of the molded insulating layer 110, but it is not limited to this. The thickness of the dummy pattern DP may differ from the thickness of the molded insulating layer 110.

[0037] The dummy pattern DP may include an insulating material. The dummy pattern DP may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. According to some embodiments, the dummy pattern DP may include the same material as the molded insulating layer 110. In this case, an interface may not be visible between the dummy pattern DP and the molded insulating layer 110 adjacent to the dummy pattern DP.

[0038] The molded insulating layer 110 and the gate electrode 120 may cover the dummy pattern DP to be alternately stacked on the third direction D3. The dummy pattern DP may protrude on the third direction D3 in the cell array region CAR, and the molded insulating layer 110 and the gate electrode 120 stacked on top of the dummy pattern DP may form a stepped structure. Due to such a stepped structure, the molded insulating layer 110 and the gate electrode 120 may have a step difference (e.g., a height difference) (that is, each of the molded insulating layers 110 may have a step difference surface, and each of the gate electrodes 120 may have a step difference surface), and the step difference may be formed in the extended region EXT.

[0039] The molded insulating layer 110 may include an insulating material. The molded insulating layer 110 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. The gate electrode 120 may include a conductive material. The gate electrode 120 may include, for example, a metal (such as tungsten (W), cobalt (Co), nickel (Ni)), or a semiconductor material (such as silicon), but this disclosure is not limited thereto.

[0040] According to some embodiments, a portion of the plurality of gate electrodes 120 may be configured as a ground select line (GSL) of a semiconductor memory device. Another portion of the plurality of gate electrodes 120 may be configured as a string select line (SSL) of a semiconductor memory device. For example, the gate electrode 120 adjacent to the source structures 102 and 104 among the plurality of gate electrodes 120 may be configured as a ground select line (GSL). The gate electrode 120 adjacent to the bit line BL among the plurality of gate electrodes 120 may be configured as a string select line (SSL). However, this disclosure is not limited thereto. The arrangement and number of ground select lines GSL and string select lines SSL may vary.

[0041] An interlayer insulating layer 125 may be disposed on the first molded structure MS1 to cover the first molded structure MS1. The interlayer insulating layer 125 may include at least one of a low-k material having a dielectric constant lower than that of silicon oxide and silicon oxynitride, but this disclosure is not limited thereto.

[0042] A channel structure CH may be disposed in the cell array region CAR of the cell substrate 100. The channel structure CH may extend in a third direction D3 perpendicular to the surface of the cell substrate 100. The channel structure CH may penetrate the first molding structure MS1. For example, the channel structure CH may penetrate and intersect each of the plurality of gate electrodes 120. According to some embodiments, a dummy pattern DP may be disposed between the cell substrate 100 and the first molding structure MS1 in the cell array region CAR. In this case, a portion of the plurality of channel structures CH may extend in the third direction D3 to penetrate the first molding structure MS1 and the dummy pattern DP. In some embodiments, the channel structure CH may extend into the dummy pattern DP.

[0043] The channel structure CH may have a columnar shape (e.g., a cylindrical shape) extending in a third direction D3. According to some embodiments, the cross-section of the channel structure CH may have an inclined side, the width of which narrows as the channel structure approaches the unit base 100. However, this disclosure is not limited thereto.

[0044] exist Figure 4 In the design, the channel structure CH may include a filling insulating layer 140, a semiconductor pattern 142, and an information storage layer 144. The semiconductor pattern 142 may extend in a third direction D3 to penetrate the molded structure MS. The semiconductor pattern 142 is shown to have a cup shape, but this disclosure is not limited thereto. The semiconductor pattern 142 may have various shapes (e.g., cylindrical, square, solid-filled, etc.). The semiconductor pattern 142 may include semiconductor materials (such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures), but this disclosure is not limited thereto.

[0045] An information storage layer 144 may be disposed between the semiconductor pattern 142 and each gate electrode 120. For example, the information storage layer 144 may extend along the outer surface of the semiconductor pattern 142. The information storage layer 144 may include at least one of a high-k material having a dielectric constant higher than that of silicon nitride, silicon oxynitride, and silicon oxide. The high-k material may include at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0046] According to some implementations, the channel structure can be configured in an offset shape. For example, as... Figure 1 As shown, the channel structure CH can be arranged in an alternating manner in the first direction D1 and the second direction D2. The channel structure CH with an offset shape can improve the integration density of the semiconductor device. According to some embodiments, the channel structure CH can be arranged in a honeycomb shape.

[0047] According to some embodiments, the information storage layer 144 may be formed of multiple layers. The information storage layer 144 may include a tunnel insulating layer 144_1, a charge storage layer 144_2, and a barrier insulating layer 144_3 sequentially stacked on the outer surface of the semiconductor pattern 142.

[0048] The tunnel insulation layer 144_1 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). The charge storage layer 144_2 may include, for example, silicon nitride. The barrier insulation layer 144_3 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)).

[0049] According to some embodiments, the channel structure CH may also include a filling insulating layer 140. The filling insulating layer 140 may fill the interior of the semiconductor pattern 142 in a cup shape. The filling insulating layer 140 may include, for example, silicon oxide, but is not limited thereto.

[0050] According to some embodiments, a channel pad 132 may be disposed in a channel structure CH. The channel pad 132 may be formed to contact a semiconductor pattern 142. For example, the channel pad 132 may be disposed inside an interlayer insulating layer 125 to contact one end of the semiconductor pattern 142. The channel pad 132 may comprise, for example, polysilicon doped with impurities, but this disclosure is not limited thereto.

[0051] The first molded structure MS1 can be divided by the word line cut region WCF to form memory cell blocks (e.g., Figure 1 (BLK). The word line cut area WCF may include, for example, silicon oxide, silicon nitride, and silicon oxynitride, but is not limited to these.

[0052] Bit lines BL can be formed on the first molding structure MS1. Bit lines BL can intersect with word line cutting regions WCF. For example, each of the bit lines BL can extend in the second direction D2. Bit lines BL can be arranged spaced apart from each other along the first direction D1.

[0053] The bit line BL can contact the channel structure CH arranged along the second direction D2. The bit line contact 136 can be formed inside the interlayer insulation layer 125. The bit line BL can be electrically connected to the channel structure CH through the bit line contact 136 and the channel pad 132.

[0054] Word line contacts 160 may be disposed on the cell substrate 100 in the extended region EXT. Word line contacts 160 may extend in a third direction D3 perpendicular to the surface of the cell substrate 100. Word line contacts 160 may penetrate the first molding structure MS1. For example, word line contacts 160 may penetrate and intersect each of the plurality of gate electrodes 120. Word line contacts 160 may contact a corresponding gate electrode 120 (e.g., a selected gate electrode). Word line contacts 160 may disconnect from non-corresponding gate electrodes (e.g., non-selected gate electrodes).

[0055] The letter contact 160 may include at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0056] According to some embodiments, the corresponding heights of the plurality of word line contacts 160 may correspond to each other. For example, the plurality of word line contacts 160 may include a first word line contact 162 and a second word line contact 164, the second word line contact 164 being spaced apart from the first word line contact 162 in a direction parallel to one side of the cell substrate 100. The height 162_H of the first word line contact 162 may be the same as the height 164_H of the second word line contact 164. In some embodiments, the first word line contact 162 may extend into the first molding structure MS1 and extend in the third direction D3.

[0057] Contact spacer 170 may be disposed on a portion of the side surface of word line contact 160. Contact spacer 170 may be disposed between word line contact 160 and non-select gate electrode. Contact spacer 170 may include insulating material. Contact spacer 170 may include insulating material such as silicon oxide.

[0058] exist Figure 5 The shape of the stepped structure of the molded insulating layer 110 and the gate electrode 120, as well as the shape of the first word line contact 162, will be described in detail below. Each of the plurality of molded insulating layers 110 may have a stepped structure. For example, each of the plurality of molded insulating layers 110 may include a step difference surface 110_SS formed by the thickness of the dummy pattern DP.

[0059] The molded insulating layer 110 may include a first insulating plate portion 110_PLa, a second insulating plate portion 110_PLb, and an insulating connecting portion 110_CP. The first insulating plate portion 110_PLa may extend parallel to the surface of the unit substrate 100. The second insulating plate portion 110_PLb may extend parallel to the surface of the unit substrate 100, but at a different vertical level from the first insulating plate portion 110_PLa. The insulating connecting portion 110_CP may connect the first insulating plate portion 110_PLa and the second insulating plate portion 110_PLb. The insulating connecting portion 110_CP may extend in a third direction D3.

[0060] Each of the plurality of gate electrodes 120 may have a stepped structure. For example, each of the plurality of gate electrodes 120 may include a step difference surface 120_SS formed by the thickness of the dummy pattern DP. The gate electrode 120 may include a first conductive plate portion 120_PLa, a second conductive plate portion 120_PLb, and a conductive connection portion 120_CP.

[0061] The first conductive plate portion 120_PLa may extend parallel to the surface of the unit substrate 100. The second conductive plate portion 120_PLb may extend parallel to the surface of the unit substrate 100 and may be located at a different vertical level from the first conductive plate portion 120_PLa. For example, the second conductive plate portion 120_PLb may be located at a lower vertical level than the first conductive plate portion 120_PLa. However, this disclosure is not limited thereto.

[0062] The conductive connection portion 120_CP can be connected to the first conductive plate portion 120_PLa and the second conductive plate portion 120_PLb. The conductive connection portion 120_CP can extend onto the third direction D3. A portion of one side surface of the conductive connection portion 120_CP can be connected to one side surface of the first conductive plate portion 120_PLa. A portion of the other side surface of the conductive connection portion 120_CP can be connected to one side surface of the second conductive plate portion 120_PLb.

[0063] The thickness H1 of the conductive connection portion 120_CP can be greater than the thickness H2 of the first conductive plate portion 120_PLa and the thickness H3 of the second conductive plate portion 120_PLb. For example, the thickness H1 of the conductive connection portion 120_CP can be the same as the distance between the top of the first conductive plate portion 120_PLa and the bottom of the second conductive plate portion 120_PLb. The terms "upper part," "lower part," "upper surface," and "lower surface" are used for ease of explanation, but this disclosure is not limited thereto. The terms "upper part," "lower part," "upper surface," and "lower surface" are described with reference to the accompanying drawings, but the terms indicating the vertical relationship may change when the drawings are rotated vertically.

[0064] The first word line contact 162 may indicate any one of a plurality of word line contacts 160. The plurality of gate electrodes 120 may include a first gate electrode 122 electrically connected to the first word line contact 162, and a second gate electrode 124 not electrically connected to the first word line contact 162. The first gate electrode 122 may be a select gate electrode, and the second gate electrode 124 may be a non-select gate electrode. In some embodiments, the first word line contact 162 may extend into the second gate electrode 124.

[0065] The first word line contact 162 may include a vertical direct contact 162_V, a first horizontal contact 162_Ha, and a second horizontal contact 162_Hb. The vertical direct contact 162_V may penetrate a plurality of molded insulating layers 110. The first word line contact 162 may include a first horizontal contact 162_Ha that penetrates a first gate electrode 122 and a second horizontal contact 162_Hb that penetrates other gate electrodes (e.g., a second gate electrode 124) among the plurality of gate electrodes 120. In some embodiments, the vertical direct contact 162_V may extend into the plurality of molded insulating layers 110, the first horizontal contact 162_Ha may extend into the first gate electrode 122, and the second horizontal contact 162_Hb may extend into other gate electrodes among the plurality of gate electrodes 120.

[0066] The first gate electrode 122 may include a 1-1 conductive plate portion 122_PLa, a 1-2 conductive plate portion 122_PLb, and a first conductive connection portion 122_CP. The 1-1 conductive plate portion 122_PLa, the 1-2 conductive plate portion 122_PLb, and the first conductive connection portion 122_CP may correspond to the first conductive plate portion 120_PLa, the second conductive plate portion 120_PLb, and the conductive connection portion 120_CP, respectively. The second gate electrode 124 may include a 2-1 conductive plate portion 124_PLa, a 2-2 conductive plate portion 124_PLb, and a second conductive connection portion 124_CP. The 2-1 conductive plate portion 124_PLa, the 2-2 conductive plate portion 124_PLb, and the second conductive connection portion 124_CP may correspond to the first conductive plate portion 120_PLa, the second conductive plate portion 120_PLb, and the conductive connection portion 120_CP, respectively.

[0067] The first word line contact 162 can penetrate the first conductive connection portion 122_CP. The inner surface of the first conductive connection portion 122_CP can contact the outer surface of the first word line contact 162. For example, the inner surface of the first conductive connection portion 122_CP can surround the outer surface of the first word line contact 162.

[0068] The first word line contact 162 can penetrate either the 2-1 conductive plate portion 124_PLa or the 2-2 conductive plate portion 124_PLb. For example, the first word line contact 162 can penetrate the 2-1 conductive plate portion 124_PLa of the second gate electrode 124 disposed on the upper part (e.g., a high vertical horizontal) of the first gate electrode 122. The first word line contact 162 can penetrate the 2-2 conductive plate portion 124_PLb of the second gate electrode 124 disposed on the lower part (e.g., a low vertical horizontal) of the first gate electrode 122. However, this disclosure is not limited thereto. The first word line contact 162 can penetrate both the 2-2 conductive plate portion 124_PLb of the second gate electrode 124 disposed on the upper part (e.g., a high vertical horizontal) of the first gate electrode 122 and the 2-1 conductive plate portion 124_PLa of the second gate electrode 124 disposed on the lower part (e.g., a low vertical horizontal) of the first gate electrode 122.

[0069] A contact spacer 170 may be disposed between the first word line contact 162 and the second gate electrode 124. For example, the contact spacer 170 may surround the first word line contact 162. The inner surface of the contact spacer 170 may contact the outer surface of the first word line contact 162. The outer surface of the contact spacer 170 may contact the inner surface of the second gate electrode 124.

[0070] exist Figure 6 The shape of the first letter contact 162 will be described in detail below. According to some embodiments, the width W1 of the first horizontal contact portion 162_Ha and the width W2 of the second horizontal contact portion 162_Hb may be greater than the width W3 of the vertical direct contact portion 162_V. For example, the width W1 of the first horizontal contact portion 162_Ha may be greater than the width W3 of the vertical direct contact portion 162_V. The width W2 of the second horizontal contact portion 162_Hb may be greater than the width W3 of the vertical direct contact portion 162_V.

[0071] According to some embodiments, the height H4 of the first horizontal contact portion 162_Ha may correspond to the distance between the top of the 1-1 conductive plate portion 122_PLa and the bottom of the 1-2 conductive plate portion 122_PLb.

[0072] According to some embodiments, the width W1 of the first horizontal contact portion 162_Ha may be smaller than the width W4 of the first conductive connection portion 122_CP. The width W1 of the first horizontal contact portion may be constant in the third direction D3, but is not limited thereto.

[0073] According to some embodiments, the barrier layer may also be disposed between the first horizontal contact portion 162_Ha and the first conductive connection portion 122_CP. The interface between the first horizontal contact portion 162_Ha and the first conductive connection portion 122_CP can be identified by the barrier layer. The barrier layer may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) materials.

[0074] exist Figures 1 to 3 In this configuration, a word line via (WLV) can be disposed on the word line contact 160. The word line via (WLV) can also be disposed inside the interlayer insulation layer 125. The word line contact 160 can be electrically connected to the wiring WLL via the word line via (WLV).

[0075] Support structure 150 may be disposed in the extended region EXT of unit base 100. Support structure 150 may be spaced apart from word line contact 160 in a direction parallel to the surface of unit base 100. For example, support structure 150 may be spaced apart from word line contact 160 in a direction perpendicular to a third direction D3. Support structure 150 may be disposed around word line contact 160. For example, four (4) support structures 150 may be disposed around one word line contact 160, but are not limited thereto. For example, three support structures 150 may be disposed around one word line contact 160. Support structure 150 may support first molded structure MS1 or word line contact 160 to prevent first molded structure MS1 or word line contact 160 from collapsing or tipping over.

[0076] The support structure 150 may include a vertical support portion 150_V penetrating a plurality of molded insulating layers 110 and a horizontal support portion 150_H penetrating a plurality of gate electrodes 120. In some embodiments, the vertical support portion 150_V may extend into the plurality of molded insulating layers 110, and the horizontal support portion 150_H may extend into the plurality of gate electrodes 120. The vertical support portion 150_V may extend in a third direction D3. The horizontal support portion 150_H may extend in a direction parallel to the surface of the cell substrate 100 (e.g., a first direction D1, a second direction D2, and a fourth direction D4). The vertical support portion 150_V of the support structure 150 may have a shape similar to that of the channel structure CH. The horizontal support portion 150_H of the support structure 150 may be stacked with the gate electrodes 120 in the horizontal direction. In some embodiments, the width of the horizontal support portion 150_H may be greater than the width of the vertical support portion 150_V.

[0077] The support structure 150 may include an insulating material. For example, the support structure 150 may include a silicon oxide-based insulating material, but is not limited thereto.

[0078] The peripheral circuit structure PERI may include a peripheral circuit substrate 300, peripheral circuit elements 360, and peripheral circuit wiring structure 380.

[0079] The peripheral circuit substrate 300 may include a semiconductor substrate (such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate). In some embodiments, the peripheral circuit substrate 300 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0080] Peripheral circuit element 360 may be formed on peripheral circuit substrate 300. Peripheral circuit element 360 may include peripheral circuitry for controlling the operation of a semiconductor memory device. For example, peripheral circuit element 360 may include… Figure 22 The logic circuit 1130, page buffer 1120, and decoder 1110 are included. The surface of the peripheral circuit substrate 300 on which the peripheral circuit elements 360 are disposed may be referred to as the front side of the peripheral circuit substrate 300. The surface of the peripheral circuit substrate 300 opposite to the front side of the peripheral circuit substrate 300 may be referred to as the back side of the peripheral circuit substrate 300.

[0081] Peripheral circuit element 360 may include, for example, transistors, but is not limited thereto. For example, in addition to various active elements such as transistors, peripheral circuit element 360 may also include various passive elements such as capacitors, resistors, inductors, etc.

[0082] Peripheral circuit wiring structure 380 may be formed on peripheral circuit element 360. For example, a second wiring insulating layer 340 may be formed on the front side of peripheral circuit substrate 300, and the peripheral circuit wiring structure 380 may be formed inside the second wiring insulating layer 340. The peripheral circuit wiring structure 380 may be electrically connected to peripheral circuit element 360. The number of layers or arrangement of the peripheral circuit wiring structure 380 are merely exemplary, but this disclosure is not limited thereto.

[0083] According to some implementations, the cell structure can be stacked on the peripheral circuit structure PERI. For example, the cell structure can be stacked on the second wiring insulation layer 340.

[0084] Figures 7 to 9 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments. Figures 7 to 9 Corresponding to Figure 5 An enlarged view of area Q3. Besides the specific shape of the first letter contact 162... Figures 7 to 9 The semiconductor memory device can be compared with a reference Figures 1 to 6 The semiconductor memory devices described are essentially the same. For ease of explanation, the description will focus on those similar to those in... Figures 1 to 6 The components described in the text are different from the components in the text.

[0085] exist Figure 7 In the first horizontal contact portion 162_Ha, the width W1 can correspond to the horizontal distance HL between the surface of the 1-1 conductive plate portion 122_PLa and the surface of the 1-2 conductive plate portion 122_PLb opposite to the surface of the 1-1 conductive plate portion 122_PLa.

[0086] exist Figure 8 In the first horizontal contact portion 162_Ha, the surface 162_HaS may have a convex shape protruding outward in the first horizontal contact portion 162_Ha. The width of the center of the first horizontal contact portion 162_Ha may be greater than the width of the edge portion. The inner surface of the first conductive connection portion 122_CP may have a concave shape corresponding to the shape of the first horizontal contact portion 162_Ha.

[0087] According to some embodiments, the surface 162_HbS of the second horizontal contact portion 162_Hb may have a convex shape protruding in the outward direction of the second horizontal contact portion 162_Hb. The width of the center of the second horizontal contact portion 162_Hb may be greater than the width of the edge portion. The inner surface 170_IS of the contact spacer 170 may have a concave shape corresponding to the shape of the second horizontal contact portion 162_Hb.

[0088] According to some embodiments, the outer surface of the contact spacer 170 may have a convex shape protruding in the outward direction of the contact spacer 170. The surface of the second gate electrode 124 may have a concave shape corresponding to the outer surface 170_OS of the contact spacer 170.

[0089] exist Figure 9 In the first horizontal contact portion 162_Ha, the surface 162_HaS may have a concave shape that is recessed inward in the internal direction of the first horizontal contact portion 162_Ha. The width of the center of the first horizontal contact portion 162_Ha may be smaller than the width of the edge portion. The inner surface of the first conductive connection portion 122_CP may have a convex shape corresponding to the shape of the first horizontal contact portion 162_Ha.

[0090] According to some embodiments, the surface 162_HbS of the second horizontal contact portion 162_Hb may have a concave shape that is recessed inward in the internal direction of the second horizontal contact portion 162_Hb. The width of the center of the second horizontal contact portion 162_Hb may be smaller than the width of the edge portion. The inner surface 170_IS of the contact spacer 170 may have a convex shape corresponding to the shape of the second horizontal contact portion 162_Hb.

[0091] According to some embodiments, the outer surface of the contact spacer 170 may have a concave shape that is recessed inward in the internal direction of the contact spacer 170. The surface of the second gate electrode 124 may have a convex shape that corresponds to the shape of the outer surface 170_OS of the contact spacer 170.

[0092] Figure 10 and Figure 11 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments. Except for the location of the dummy pattern DP, Figure 10 and Figure 11 Semiconductor memory devices can be used with Figures 1 to 6 The semiconductor memory devices are essentially the same. For ease of explanation, the description will focus on those in... Figures 1 to 6 The components described in the text are different from the components in the text.

[0093] According to some embodiments, the dummy pattern DP can be disposed in the extended region EXT. According to some embodiments, in the extended region EXT, the dummy pattern DP can be as follows: Figure 11 The dummy pattern DP is positioned between the cell substrate 100 and the first molding structure MS1. The dummy pattern DP may extend in the first direction D1 into the interior of the extension region EXT or the boundary of the cell array region CAR (e.g., the boundary between the extension region EXT and the cell array region CAR).

[0094] Since the dummy pattern DP protrudes in the third direction D3 within the extended region EXT, the molded insulating layer 110 and gate electrode 120 stacked on top of the dummy pattern DP can have a stepped structure. Due to this stepped structure, a step difference (e.g., a height difference) can exist on the surface of the molded insulating layer 110 and the surface of the gate electrode 120, and the step difference can be formed in the extended region EXT. In this case, the step difference may not be formed in the cell array region CAR.

[0095] Figure 12 and Figure 13 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments. Figure 12 It is based on some implementation methods along Figure 1 The sectional view taken by line AA. Figure 13 This explains the implementation methods. Figure 12 An enlarged view of region Q4. Except for the interface between the word line contact 160 and the first gate electrode 122. Figure 12 and Figure 13 The semiconductor memory device can be compared with a reference Figures 1 to 6 The semiconductor memory devices described are essentially the same. For ease of explanation, the description will focus on those similar to those in... Figures 1 to 6 The components described in the text are different from the components in the text.

[0096] exist Figure 12 and Figure 13 In this configuration, the first word line contact 162 and the first gate electrode 122 may be integrally formed. For example, the first word line contact 162 and the first gate electrode 122 may be formed using the same process. For example, the word line contact 160 and the gate electrode 120 (e.g., the first word line contact 162 and the first gate electrode 122) may comprise the same material, but are not limited thereto. The interface between the first word line contact 162 and the first gate electrode 122 may not be distinguished.

[0097] Figure 14 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments. Figure 14 It is based on some implementation methods along Figure 1 The cross-sectional view taken by line AA. Besides the multiple molded structures MS1 and MS2 having a stacked structure, Figure 14 The semiconductor memory device can be compared with a reference Figures 1 to 6 The semiconductor memory devices described are essentially the same. For ease of explanation, the description will focus on those similar to those in... Figures 1 to 6 The components described in the text are different from the components in the text.

[0098] exist Figure 14 In a semiconductor memory device according to an embodiment, a second molded structure MS2 and a first molded structure MS1 may be sequentially stacked on a cell substrate 100. The second molded structure MS2 may be disposed in the cell array region CAR and the extended region EXT of the cell substrate 100. The second molded structure MS2 may include a plurality of molded insulating layers 210 and a plurality of gate electrodes 220 alternately stacked on a third direction D3. The molded insulating layers 210 and the gate electrodes 220 may have a layered structure extending parallel to the surface of the cell substrate 100.

[0099] A first molded structure MS1 may be disposed below a second molded structure MS2. The first molded structure MS1 may include a plurality of molded insulating layers 110 and a plurality of gate electrodes 120 alternately stacked on a third direction D3. A unit insulating layer may be disposed between the first molded structure MS1 and the second molded structure MS2. The unit insulating layer may cover the lower surface of the second molded structure MS2. The second molded structure MS2 may be formed on the unit insulating layer.

[0100] The channel structure CH may extend in the third direction D3 and penetrate the first molding structure MS1 and the second molding structure MS2. The channel structure CH may have a bend between the first molding structure MS1 and the second molding structure MS2.

[0101] Word line contacts 160 may extend in the third direction D3 and penetrate the first molded structure MS1 and the second molded structure MS2. Multiple word line contacts 160 may be electrically connected to the gate electrode 120 of the first molded structure MS1 and the gate electrode 220 of the second molded structure MS2.

[0102] exist Figure 14 In the illustration, the number of molded structures MS1 and MS2 is shown as two (2), but this disclosure is not limited thereto. For example, the number of molded structures MS1 and MS2 may be three (3), four (4), or more.

[0103] Figure 15 This is a diagram illustrating an example of a semiconductor memory device according to some embodiments. Figure 15 It is based on some implementation methods along Figure 1 A cross-sectional view taken along line AA. Besides having a chip-to-chip (C2C) structure, Figure 15 Semiconductor memory devices can be used with Figures 1 to 6 The semiconductor memory devices in this context are essentially the same. For ease of explanation, the description will focus on those in... Figures 1 to 6 The components described in the text are different from the components in the text.

[0104] exist Figure 15 In this embodiment, the semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI). The cell structure (CELL) may be disposed on top of the peripheral circuit structure (PERI). Except that the peripheral circuit wiring structure 380 is electrically connected to the second bonding metal 385, the description of the peripheral circuit structure (PERI) may be consistent with... Figures 1 to 6 The description is the same as in the text. The cell structure may include a cell substrate 100, a common source plate 105, a molded structure MS1, a channel structure CH, a bit line BL, a word line contact 160, a contact spacer 170, a cell wiring structure 190, etc.

[0105] Cell substrate 100 may be disposed within a cell structure. Cell substrate 100 may include a semiconductor substrate (such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate). In some embodiments, cell substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some embodiments, cell substrate 100 may include impurities. For example, cell substrate 100 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0106] A common source plate 105 may be disposed on the surface of the cell substrate 100. The common source plate 105 may be disposed in the cell array region CAR, the extended region EXT, and the through region THR. The common source plate 105 may contact the channel structure CH. For example, the common source plate 105 may be electrically connected to a semiconductor pattern of the channel structure CH (e.g., Figure 4 (142). The common source plate 105 can access the source contacts in the through region THR of the cell substrate 100 (e.g., Figure 1 (180). The common source plate 105 may be configured as the common source line of a semiconductor memory device (e.g., Figure 22 (CSL). According to some embodiments, the common source plate 105 may contact a word line contact structure including word line contacts 160 and contact spacers 170. For example, one end of the word line contact structure may be disposed inside the common source plate 105. In this case, the contact spacers 170 may be disposed on one end of the word line contact structure. Therefore, the word line contacts 160 and the common source plate 105 may not be in direct contact with each other.

[0107] The common source plate 105 may include, for example, a metal or polysilicon doped with impurities, but this disclosure is not limited thereto.

[0108] The molded structure MS1 may be disposed on the common source plate 105. The molded structure MS1 may include a plurality of molded insulating layers 110 and a plurality of gate electrodes 120 alternately stacked on the third direction D3. The plurality of gate electrodes 120 may be spaced apart from each other and alternately stacked on the common source plate 105.

[0109] Cell wiring structure 190 may be formed on molded structure MS1. For example, a first wiring insulating layer 192 may be formed on interlayer insulating layer 125, and cell wiring structure 190 may be formed inside the first wiring insulating layer 192. Cell wiring structure 190 may be electrically connected to bit line BL and word line contact 160. Cell wiring structure 190 may be electrically connected to channel structure CH and gate electrode 120. The number of layers or arrangement of cell wiring structure 190 may be exemplary only, but is not limited thereto. In some embodiments, cell wiring structure 190 may be between bit line BL and peripheral circuit structure PERI, and between first word line contact 162 and peripheral circuit structure PERI.

[0110] In some embodiments, a semiconductor memory device may include a chip-to-chip (C2C) structure. The C2C structure may consist of an upper chip including a cell structure CELL on a first wafer (e.g., cell substrate 100) and a lower chip including a peripheral circuit structure PERI on a second wafer (e.g., peripheral circuit substrate 300) different from the first wafer, such that the upper chip and the lower chip are connected to each other by bonding.

[0111] According to some embodiments, the bonding method may be a method in which a first bonding metal 195 formed on the uppermost metal layer of the upper chip is electrically connected to a second bonding metal 385 formed on the uppermost metal layer of the lower chip. For example, when the first bonding metal 195 and the second bonding metal 385 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is merely exemplary, and the first bonding metal 195 and the second bonding metal 385 may be formed of various metals (such as aluminum (Al) or tungsten (W)).

[0112] When the first bonding metal 195 is bonded to the second bonding metal 385, the cell wiring structure 190 can be connected to the peripheral circuit wiring structure 380. The bit line BL and each of the plurality of gate electrodes 120 can be electrically connected to the peripheral circuit element 360.

[0113] Figures 16 to 21 This is an intermediate stage diagram illustrating an example of a method for manufacturing a semiconductor memory device according to some embodiments. Figure 16 In this process, a pre-stacked structure PMS can be formed on a cell substrate 100. The pre-stacked structure PMS may include a dummy pattern DP disposed on a portion of the cell substrate 100, a plurality of molded insulating layers 110 alternately stacked to cover the dummy pattern DP, and a plurality of molded sacrificial layers 112. The dummy pattern DP may protrude on a third direction D3 on the cell substrate 100. Therefore, the molded insulating layers 110 and molded sacrificial layers 112 stacked on top of the dummy pattern DP may have a stepped shape. The dummy pattern DP can be formed using various patterning techniques. For example, the dummy pattern DP can be formed using techniques such as nanoimprint lithography, photolithography, electron beam lithography, and X-ray lithography, but this disclosure is not limited thereto.

[0114] A channel structure CH can be formed in a pre-stacked structure PMS. A channel pad 132 can be formed in the channel structure CH.

[0115] Word line contact grooves 160_T can be formed in the pre-stacked structure PMS. Word line contact grooves 160_T can penetrate the pre-stacked structure PMS. According to some embodiments, word line contact grooves 160_T can be formed in regions of the molding sacrificial layer 112 where a step difference is formed. Word line contact grooves 160_T can be formed by penetrating the molding sacrificial layer 112, which is thickened due to the step difference.

[0116] According to some embodiments, the bottom surface of the word line contact trench 160_T may expose the cell substrate 100. The bottom surface of each of the plurality of word line contact trenches 160_T may be positioned at substantially the same vertical level. The etch stop level of each of the plurality of word line contact trenches 160_T may be substantially the same.

[0117] exist Figure 17 In this process, a portion of the molded sacrificial layer 112 on the sidewall of the word line contact groove 160_T can be removed in a direction parallel to the surface of the unit substrate 100. The width of the word line contact groove 160_T can extend outward at the same vertical level as the molded sacrificial layer 112. The width of the word line contact groove 160_T at the same vertical level as the molded sacrificial layer 112 can be greater than the width of the word line contact groove 160_T at the same vertical level as the molded insulating layer 110.

[0118] exist Figure 18 In this process, free contact spacers 170_P can be formed on the sidewalls or bottom surface of the letter contact groove 160_T. According to some embodiments, the thickness of the free contact spacers 170_P formed on the inner wall of the thick molded sacrificial layer 112 (e.g., thickened due to step differences) can be less than the thickness of the free contact spacers 170_P formed on the inner walls of other molded sacrificial layers 112. A filler sacrificial layer FS can be formed on the free contact spacers 170_P. A capping layer CAP can be formed on the filler sacrificial layer FS.

[0119] exist Figure 19 and Figure 20 In this process, the molding sacrificial layer 112 can be removed. The gate electrode 120 can be disposed between the molding insulating layers 110. The capping layer CAP and the filler sacrificial layer FS can be removed. A portion of the free contact spacer 170_P can be removed, and the contact spacer 170 can be formed. The free contact spacer 170_P on the sidewall of the thick gate electrode 120 formed at the step difference between the molding insulating layer 110 and the gate electrode 120 can be removed, while the free contact spacer 170_P on the sidewalls of other gate electrodes 120 can be retained, thereby forming the contact spacer 170.

[0120] exist Figure 21 In this process, word line contacts 160 can be formed in the area where the capping layer (CAP) and the filling sacrificial layer (FS) have been removed. The shape of the word line contacts 160 can be consistent with... Figures 1 to 6 The shape is the same as described in the text.

[0121] According to some embodiments, the word line contact 160 and the gate electrode 120 can be formed using the same process. The interface between the word line contact 160 and the gate electrode 120 may not be distinguished. The shapes of the word line contact 160 and the gate electrode 120 may be similar to... Figure 12 and Figure 13 They have the same shape.

[0122] Figure 22 This is a block diagram illustrating an example of an electronic system according to some embodiments. Figure 22 In this context, electronic system 1000 may include... Figures 1 to 15The semiconductor memory device 1100 and the controller 1200 electrically connected to the semiconductor memory device 1100 are described herein. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0123] Semiconductor memory device 1100 may be, for example, referenced to Figures 1 to 15 The NAND flash memory device described. Semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may be a peripheral circuit structure including decoder circuitry (or decoder) 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1, a second gate upper line UL2, a first gate lower line LL1, a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0124] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0125] According to some embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be connected to the gate electrodes of the lower transistors LT1 and LT2, respectively. Word line WL may be connected to the gate electrode of the memory cell transistor MCT, and gate upper lines UL1 and UL2 may be connected to the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0126] The common source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, the first upper gate line UL1, and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0127] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs) to select a memory cell transistor. The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor memory device 1100 can communicate with the controller 1200 via input and output pads 1101 electrically connected to the logic circuit 1130. The input and output pads 1101 can be electrically connected to the logic circuit 1130 via input and output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0128] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0129] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 operates according to predetermined firmware and controls NAND controller 1220 to access semiconductor memory device 1100. NAND controller 1220 may include a controller interface (e.g., NAND interface) 1221 for handling communication with semiconductor memory device 1100. Through NAND interface 1221, control commands for controlling semiconductor memory device 1100, data recorded in memory cell transistors (MCTs) of semiconductor memory device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor memory device 1100 can be sent. Host interface 1230 provides communication functionality between electronic system 1000 and an external host. When receiving control commands from an external host through host interface 1230, processor 1210 can control semiconductor memory device 1100 in response to the control commands.

[0130] Figure 23 This is a perspective view illustrating an example of an electronic system including a semiconductor memory device according to some embodiments. Figure 24 It is based on some implementation methods along Figure 23 A schematic cross-sectional view taken from line VV.

[0131] exist Figure 23 In the electronic system 2000, a main substrate 2001, a main controller 2002 embedded in the main substrate 2001, at least one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 are electrically connected to the main controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0132] The main substrate 2001 may include a connector 2006 comprising a plurality of pins for association with an external host. The number and arrangement of the plurality of pins may vary depending on the communication interface between the electronic system 2000 and the external host associated with the connector 2006. In some embodiments, the electronic system 2000 may communicate with the external host via one of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI Fast), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc. According to some embodiments, the electronic system 2000 may operate via power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for supplying power from the external host to the main controller 2002 and the semiconductor package 2003.

[0133] The main controller 2002 can record data in the semiconductor package 2003 and read data from the semiconductor package 2003, thereby improving the operating speed of the electronic system 2000.

[0134] DRAM 2004 can be a buffer memory used to reduce the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 can operate as a cache and provides space for arbitrarily storing data during the control operations of the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the main controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0135] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0136] The package substrate 2100 may be a printed circuit substrate including package pads 2130. Each of the semiconductor chips 2200 may include input and output pads 2210. The input and output pads 2210 may correspond to... Figure 22 The input and output pads 1101. Each of the semiconductor chips 2200 may include metal lines 3210 and channel structures 3220. Each of the semiconductor chips 2200 may include references. Figures 1 to 15 The semiconductor memory device described.

[0137] According to some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input and output pads 2210 to the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a bonding wire method and electrically connected to the package pad 2130 of the package substrate 2100. According to some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through-silicon via (TSV, or through-silicon via) instead of the connection structure 2400 in the bonding wire method.

[0138] According to some embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. According to some embodiments, the main controller 2002 and the semiconductor chip 2200 may be embedded in a main substrate 2001 and a separate intermediate substrate, and the main controller 2002 and the semiconductor chip 2200 may be electrically connected to each other via wires formed on the intermediate substrate.

[0139] According to some embodiments, the package substrate 2100 may be a printed circuit board substrate. The package substrate 2100 may include a package substrate body 2120, a top package pad 2130 disposed on the upper surface of the package substrate body 2120, a bottom pad 2125 disposed on or exposed through the lower surface of the package substrate body 2120, and internal wiring 2135 electrically connecting the top package pad 2130 to the bottom pad 2125 within the package substrate body 2120. The top package pad 2130 may be electrically connected to a connection structure 2400. The bottom pad 2125 may be connected via a conductive connection portion 2800 to, for example,... Figure 23 Wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 described herein.

[0140] In an electronic system according to some embodiments, each of the semiconductor chips 2200 may include a reference. Figures 1 to 15The semiconductor memory device described. For example, each of the semiconductor chip 2200 may include a peripheral circuit structure PERI and a cell structure CELL stacked on the peripheral circuit structure PERI. For example, the peripheral circuit structure PERI may include references Figures 1 to 15 The peripheral circuit substrate 300 and peripheral circuit wiring structure 380 are described. For example, the cell structure CELL may include references. Figures 1 to 15 The unit substrate 100, molding structure MS1, channel structure CH, bit line BL, word line contact 160, and contact spacer 170 are described.

[0141] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims, their equivalents, and the appended claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features derived from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. A semiconductor memory device, comprising: a substrate; a molded structure including a dummy pattern on a partial area of the substrate, a plurality of molded insulating layers, and a plurality of gate electrodes, the plurality of molded insulating layers and the plurality of gate electrodes being alternately stacked on the substrate over the dummy pattern in a first direction; and a first word line contact extending into the molded structure and extending in the first direction, wherein the plurality of gate electrodes include a first gate electrode electrically connected to the first word line contact, wherein the first gate electrode includes a first conductive plate portion extending in parallel with a surface of the substrate, a second conductive plate portion extending in parallel with the surface of the substrate and disposed at a different vertical level than the first conductive plate portion, and a conductive connection portion connecting the first conductive plate portion to the second conductive plate portion, wherein a thickness of the conductive connection portion is greater than a thickness of the first conductive plate portion and a thickness of the second conductive plate portion, and wherein an inner surface of the conductive connection portion contacts an outer surface of the first word line contact. The first word line contact includes a vertical contact portion extending into the plurality of molded insulating layers, a first horizontal contact portion extending into the first gate electrode, and a second horizontal contact portion extending into other gate electrodes among the plurality of gate electrodes, and 2. The semiconductor memory device according to claim 1, wherein, wherein respective widths of the first horizontal contact portion and the second horizontal contact portion are greater than a width of the vertical contact portion. The width of the first horizontal contact portion extends a horizontal distance between a surface of the first conductive plate portion and a surface of the second conductive plate portion facing the surface of the first conductive plate portion.

3. The semiconductor memory device of claim 2, wherein, The surface of the first horizontal contact portion has a convex shape protruding in an outward direction of the first horizontal contact portion.

4. The semiconductor memory device of claim 2, wherein, The surface of the first horizontal contact portion has a shape concave in an inward direction of the first horizontal contact portion.

5. The semiconductor memory device of claim 2, wherein, The first gate electrode and the first word line contact are integrally formed.

6. The semiconductor memory device of claim 1, wherein, 7.The semiconductor memory device of claim 1, the plurality of gate electrodes further include a second gate electrode, the second gate electrode including a non-selected gate electrode, and wherein, wherein the first word line contact extends into the second gate electrode. a contact spacer disposed between the first word line contact and the second gate electrode.

8. The semiconductor memory device of claim 7, further comprising: An outer surface of the contact spacer has a convex shape protruding in an outward direction of the contact spacer.

9. The semiconductor memory device of claim 8, wherein, The outer surface of the contact spacer has a shape concave in an inward direction of the contact spacer.

10. The semiconductor memory device of claim 8, wherein, a second word line contact spaced apart from the first word line contact in a direction parallel with the surface of the substrate, 11. The semiconductor memory device according to any one of claims 1 to 10, further comprising: wherein a height of the first word line contact is the same as a height of the second word line contact. a support structure spaced apart from the first word line contact in the direction parallel with the surface of the substrate, 12. The semiconductor memory device according to any one of claims 1 to 10, further comprising: wherein the support structure includes a vertical support portion extending into the plurality of molded insulating layers and a horizontal support portion extending into the plurality of gate electrodes, and wherein a width of the horizontal support portion is greater than a width of the vertical support portion. each of the plurality of molded insulating layers and each of the plurality of gate electrodes include a stepped surface formed by a thickness of the dummy pattern.

13. The semiconductor memory device according to any one of claims 1 to 10, wherein, each of the plurality of molded insulating layers includes:

14. The semiconductor memory device according to any one of claims 1 to 10, wherein, ​ a first insulating plate portion extending in parallel with a surface of the base, a second insulating plate portion extending in parallel with the surface of the base and disposed at a different vertical level than the first insulating plate portion, and an insulating connection portion connecting the first insulating plate portion to the second insulating plate portion.

15. A semiconductor memory device, comprising: a peripheral circuit structure; and a cell structure stacked on the peripheral circuit structure, wherein the cell structure includes: a base including a cell array region and an extension region; a mold structure including a dummy pattern on a partial region of the base, a plurality of mold insulating layers, and a plurality of gate electrodes stacked alternately on the base over the dummy pattern in a first direction; a channel structure disposed in the cell array region, the channel structure extending into the mold structure and extending in the first direction; and a first word line contact disposed in the extension region, the first word line contact extending into the mold structure and extending in the first direction, wherein the plurality of gate electrodes includes a first gate electrode electrically connected to the first word line contact, wherein the first gate electrode includes a first conductive plate portion extending in parallel with a surface of the base, a second conductive plate portion extending in parallel with the surface of the base and disposed at a different vertical level than the first conductive plate portion, and a conductive connection portion connecting the first conductive plate portion to the second conductive plate portion, wherein a thickness of the conductive connection portion is greater than a thickness of the first conductive plate portion and a thickness of the second conductive plate portion, and wherein an inner surface of the conductive connection portion contacts an outer surface of the first word line contact.

16. The semiconductor memory device of claim 15, wherein, The dummy pattern is disposed in the cell array region, and the channel structure extends into the dummy pattern.

17. The semiconductor memory device of claim 15, wherein, The dummy pattern is disposed in the extension region.

18. The semiconductor memory device of any one of claims 15 to 17, further comprising: a second word line contact spaced apart from the first word line contact in a direction parallel with the surface of the base, wherein a lower surface of the first word line contact is disposed on a same plane as a lower surface of the second word line contact.

19. The semiconductor memory device according to any one of claims 15 to 17, further comprising: a bit line contacting the channel structure, and a cell wiring structure between the bit line and the peripheral circuit structure, and between the first word line contact and the peripheral circuit structure.

20. An electronic system, comprising: a main base; a semiconductor memory device including a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main base; and a controller electrically connected to the semiconductor memory device on the main base, wherein the cell structure includes: a base including a cell array region and an extension region; a mold structure including a dummy pattern disposed on a partial region of the base, a plurality of mold insulating layers, and a plurality of gate electrodes stacked alternately on the base over the dummy pattern in a first direction; a channel structure disposed in the cell array region, the channel structure extending into the mold structure and extending in the first direction; and a first word line contact disposed in the extension region, the first word line contact extending into the mold structure and extending in the first direction, wherein the plurality of gate electrodes includes a first gate electrode electrically connected to the first word line contact, wherein the first gate electrode includes a first conductive plate portion extending in parallel with a surface of the base, a second conductive plate portion extending in parallel with the surface of the base and disposed at a different vertical level than the first conductive plate portion, and a conductive connection portion connecting the first conductive plate portion to the second conductive plate portion, wherein a thickness of the conductive connection portion is greater than a thickness of the first conductive plate portion and a thickness of the second conductive plate portion, and wherein an inner surface of the conductive connection portion contacts an outer surface of the first word line contact. wherein the plurality of gate electrodes includes a first gate electrode electrically connected to a first word line contact, wherein the first gate electrode includes a first conductive plate portion extending parallel to the surface of the substrate, a second conductive plate portion extending parallel to the surface of the substrate and disposed at a different vertical level than the first conductive plate portion, and a conductive connection portion connecting the first conductive plate portion to the second conductive plate portion, wherein a thickness of the conductive connection portion is greater than a thickness of the first conductive plate portion and a thickness of the second conductive plate portion, and wherein an inner surface of the conductive connection portion contacts an outer surface of the first word line contact.

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