Semiconductor memory device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor memory device includes the following steps. A container interlayer dielectric layer is formed on a substrate. An intermediate nitride layer is formed over the container interlayer dielectric layer. A container oxide layer is formed over the intermediate nitride layer. Ions of at least one of boron, carbon, germanium, and arsenic are implanted into the container oxide layer region to convert into an implanted oxide layer. A hard mask layer is formed over the implant oxide layer. A hard mask layer is patterned, and at least the implant oxide layer is dry etched using the patterned hard mask layer. High etching selectivity is achieved between the implanted oxide layer and the container oxide layer, the ion scattering effect can be reduced, and a small arc-shaped recess depth is achieved to avoid short circuit between containers.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory device and a method of manufacturing the same. BACKGROUND

[0002] Integrated circuit (IC) devices (also known as semiconductor wafers) can contain millions of transistors and other circuit elements fabricated on a single silicon crystal substrate (wafer). To improve integrated circuit device performance and reduce production costs, the dynamic random access memory (DRAM) industry has been striving to shrink device size.

[0003] However, as DRAM device size is further shrunk, one of the most challenging factors is to ensure sufficient capacitance and maintain minimum container bridge margin to avoid inter-container short leakage.

[0004] It is a challenge to perform high aspect ratio contact (HARC) etching without causing an enlarged container critical dimension (CD) due to ion scattering effects. SUMMARY

[0005] The present invention provides an innovative semiconductor memory device and a method of manufacturing the same to solve the problems in the background art.

[0006] In some embodiments of the present invention, a method of manufacturing a semiconductor memory device includes forming a container interlayer dielectric layer on a substrate; forming an intermediate nitride layer on the container interlayer dielectric layer; forming a container oxide layer on the intermediate nitride layer; implanting at least one of boron ions, carbon ions, germanium ions, and arsenic ions into a region of the container oxide layer to convert into an implanted oxide layer; forming a hard mask layer on the implanted oxide layer; and patterning the hard mask layer and performing dry etching on at least the implanted oxide layer using the patterned hard mask layer.

[0007] In some embodiments of the present invention, the implanted oxide layer has a thickness in a range of 30 nm to 40 nm.

[0008] In some embodiments of the present invention, the step of implanting at least one of boron ions, carbon ions, germanium ions, and arsenic ions includes implanting boron ions or carbon ions at an energy of 10 KeV to 30 KeV.

[0009] In some embodiments of the present invention, the step of implanting at least one of boron ions, carbon ions, germanium ions, and arsenic ions includes implanting germanium ions or arsenic ions at an energy of 55 KeV to 120 KeV.

[0010] In some embodiments of the present invention, the method further includes performing a heat treatment process to anneal the implanted oxide layer.

[0011] In some embodiments of the present invention, the method further includes forming a top nitride layer on the implanted oxide layer prior to forming the hard mask layer.

[0012] In some embodiments of the present invention, the interlayer dielectric layer of the container is a borosilicate glass layer.

[0013] In some embodiments of the present invention, the hard masking layer is a polycrystalline silicon hard masking layer.

[0014] In some embodiments of the present invention, the method further includes forming a bottom nitride layer on the substrate before forming the interlayer dielectric layer of the container.

[0015] In some embodiments of the present invention, a semiconductor memory device includes: a container interlayer dielectric layer disposed on a substrate; an intermediate nitride layer disposed on the container interlayer dielectric layer; a container oxide layer disposed on the intermediate nitride layer; an implanted oxide layer disposed on the container oxide layer, the implanted oxide layer comprising at least one of boron ions, carbon ions, germanium ions and arsenic ions; and a container trench penetrating at least the implanted oxide layer, the container oxide layer, the intermediate nitride layer and the container interlayer dielectric layer.

[0016] In some embodiments of the present invention, the implanted oxide layer has a thickness in the range of 30 nanometers to 40 nanometers.

[0017] In some embodiments of the present invention, the interlayer dielectric layer of the container is a borosilicate glass layer.

[0018] In some embodiments of the present invention, the arcuate recesses formed on the inner sidewall of the container groove have a maximum depth of 1 nanometer to 2 nanometers.

[0019] In some embodiments of the present invention, the semiconductor memory device further includes a top nitride layer disposed on the implanted oxide layer.

[0020] In some embodiments of the present invention, the semiconductor memory device further includes a bottom nitride layer located between the interlayer dielectric layer and the substrate.

[0021] In summary, the semiconductor memory device and its manufacturing method of the present invention include a container oxide layer implanted with a specific element (i.e., boron, carbon, germanium, or arsenic) at a specific dose. The implanted oxide layer, after ion implantation, exhibits a significantly lower dry etch rate compared to an unimplanted container oxide layer. The implanted oxide layer can serve as a hard mask for the container oxide layer. High etch selectivity exists between the implanted oxide layer and the container oxide layer, and ion scattering effects are reduced, thereby achieving a smaller arcuate cavity depth to avoid short circuits between containers.

[0022] The above description will be given in detail below with reference to the embodiments, and a further explanation of the technical solution of the present invention will be provided. Attached Figure Description

[0023] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below: Figures 1-6 A partial cross-sectional view illustrating some manufacturing steps of a semiconductor memory device according to some embodiments of the present invention; Figure 7 For illustration Figure 6 Enlarged cross-sectional view of the part; and Figure 8 A flowchart illustrating the process steps of a semiconductor memory technology according to some embodiments of the present invention is provided. Detailed Implementation

[0024] To provide a more detailed and complete description of the invention, reference can be made to the accompanying drawings and the various embodiments described below, in which the same numbers represent the same or similar elements. Furthermore, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention.

[0025] Reference Figures 1 to 8 It illustrates a cross-sectional schematic diagram of multiple steps in the semiconductor memory manufacturing process; Figure 7 Show Figure 6 A partially enlarged cross-sectional view, and Figure 8This diagram illustrates a flowchart of several steps in a semiconductor memory process 800 according to certain embodiments of the present invention. The cross-sectional schematic shows a portion of a memory device 100 including a container trench 130. A semiconductor substrate 102 is processed to form active regions. Semiconductor processes typically involve multiple steps. A suitable semiconductor substrate, such as silicon (Si), is selected based on the desired device specifications and requirements. A thin layer of silicon dioxide (SiO2) can be formed on the substrate surface, which can be achieved through thermal oxidation, i.e., exposing the substrate to an oxygen-rich environment at high temperatures, or through deposition techniques such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). A photosensitive material, called photoresist, is coated onto the oxide layer. Next, the photoresist, containing the desired pattern, is exposed to ultraviolet (UV) light using a photomask. This step transfers the pattern onto the photoresist. The exposed photoresist is developed using a suitable developer. This step selectively removes the exposed (positive photoresist) or unexposed (negative photoresist) areas, leaving the desired pattern. Next, an etching step, such as plasma etching or wet etching, is performed to selectively remove the exposed oxide layer to which the active regions are to be formed. Patterned photoresist acts as a mask to protect the areas where the oxide layer needs to be retained. Then, ion implantation is performed to implant p-type or n-type dopant atoms into the exposed semiconductor substrate areas where active devices will form. The dopant alters the substrate's electrical properties, creating regions with the desired conductivity. An annealing process initiates the implantation of dopant atoms and repairs lattice damage caused by the implantation. This step typically involves exposing the substrate to high temperatures for a specific period.

[0026] Transistor 102a is fabricated on semiconductor substrate 102. Transistors are fundamental components in dynamic random access memory (DRAM) devices. Each DRAM memory cell typically contains one transistor. A basic DRAM cell consists of one transistor and one capacitor, often referred to as a 1T1C (1 Transistor, 1 Capacitor) structure. The transistor acts as a switch controlling the access capacitor, allowing the memory cell to perform read or write operations when selected.

[0027] In step 802 of process 800 (refer to...) Figure 1 , Figure 8A container interlayer dielectric layer 106 is formed on a semiconductor substrate 102 containing the transistor 102a. In one or more embodiments, the container interlayer dielectric layer 106 may be a boron phosphosilicate glass (BPSG) layer. A BPSG layer is a doped silicon dioxide (SiO2) containing boron (B) and phosphorus (P), and is typically used as an interlayer dielectric (ILD) in integrated circuits (ICs). The BPSG layer can provide a flatter top surface for subsequent layers and act as an electrical insulator between metal layers and active layers to reduce parasitic capacitance effects. In one or more embodiments, the BPSG layer may be formed by chemical vapor deposition (CVD) or other suitable processes. In some embodiments, after CVD, the BPSG layer may undergo an annealing or reflow step to smooth the surface.

[0028] In one or more embodiments, a bottom nitride layer 104 may be formed on the substrate prior to the formation of the interlayer dielectric layer 106. This bottom nitride layer 104 refers to a thin film composed of silicon nitride (Si3N4) or other nitride compounds (e.g., titanium nitride TiN). The bottom nitride layer 104 plays a critical role in device isolation, masking, and protection. In one or more embodiments, the bottom nitride layer 104 may be formed by chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD) for ultrathin thickness control purposes. The bottom nitride layer 104 may serve as a passivation layer, a barrier layer, or an etch stop layer.

[0029] In step 804 of process 800 (refer to...) Figure 1 , Figure 8 An intermediate nitride layer 108 may be formed on top of the interlayer dielectric layer 106 of the container. In one or more embodiments, the intermediate nitride layer 108 refers to a thin film composed of silicon nitride (Si3N4) or other nitride compounds (such as titanium nitride TiN). The intermediate nitride layer 108 plays a critical role in device isolation, masking, and protection. In one or more embodiments, the intermediate nitride layer 108 may be formed by chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD) to achieve ultra-thin control. The intermediate nitride layer 108 may serve as a passivation layer, barrier layer, or etch stop layer.

[0030] In step 806 of process 800 (refer to...) Figure 1 , Figure 8A container oxide layer 110 can be formed on the intermediate nitride layer 108. This container oxide layer 110 is a layer composed of silicon dioxide (SiO2) or other metal oxides, widely used for insulation, isolation, shielding, and dielectric applications. In one or more embodiments, the container oxide layer 110 can be formed by methods such as thermal oxidation growth, chemical vapor deposition (including low-pressure CVD or plasma-enhanced CVD), spin-on glass (SOG), or atomic layer deposition (ALD). The container oxide layer 110 can be used as an interlayer dielectric (ILD) or field isolation layer. In one or more embodiments, the container oxide layer 110 has a thickness ranging from 300 nanometers to 500 nanometers.

[0031] In step 808 of process 800 (refer to...) Figure 1 , Figure 2 , Figure 8 An ion implantation process 120 is performed to implant at least one of boron, carbon, germanium, and arsenic ions into a region of the container oxide layer 110, transforming it into an implanted oxide layer 110a. In one or more embodiments, boron or carbon ions are implanted at a target implantation energy of 10 keV to 30 keV to form an implanted oxide layer 110a with a thickness of 34 nanometers. In one or more embodiments, germanium or arsenic ions are implanted at a target implantation energy of 55 keV to 120 keV to form an implanted oxide layer 110a with a thickness of 36 nanometers. In one or more embodiments, the implanted oxide layer 110a has a thickness h1 of 30 nanometers to 40 nanometers. In one or more embodiments, post-implantation annealing (e.g., rapid thermal annealing, RTA) is performed to repair lattice damage or activate dopant atoms (even if dopant atoms occupy lattice substitution sites and become electrically activated). The implanted oxide layer 110a will have a significantly lower dry etch rate compared to the unimplanted container oxide layer 110. In one or more embodiments, the ion implantation process 120 may perform a dose of 1.00E+16 (ion / cm²) or 3.00E+16 (ion / cm²).

[0032] In step 810 of process 800 (refer to...) Figure 3 , Figure 4 , Figure 8A hard mask layer 114 can be formed on the implanted oxide layer 110a. In one or more embodiments, the hard mask layer 114 can be a polysilicon hard mask layer. This polysilicon hard mask layer is a thin layer of doped or undoped polysilicon used in semiconductor manufacturing as a durable mask material in pattern transfer processes, particularly where photoresist alone is insufficient (e.g., high temperature or strong plasma environments) or where high etch selectivity and contour accuracy are required. In one or more embodiments, the hard mask layer 114 can be formed by low-pressure chemical vapor deposition (LPCVD), for example using silane (SiH4) or dichlorosilane (SiH2Cl2) as precursors.

[0033] In one or more embodiments, a top nitride layer 112 may be formed on the implanted oxide layer 110a prior to the formation of the hard mask layer 114. In one or more embodiments, the top nitride layer 112 refers to a thin film composed of silicon nitride (Si3N4) or other nitride compounds (e.g., titanium nitride TiN). The top nitride layer 112 plays a critical role in device isolation, masking, and protection. In one or more embodiments, the top nitride layer 112 may be formed by chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD) for ultrathin thickness control. The top nitride layer 112 may serve as a passivation layer, barrier layer, or etch stop layer.

[0034] In step 812 of process 800 (refer to...) Figure 5 , Figure 6 , Figure 7 , Figure 8 The hard mask layer 114 is patterned and dry-etched using the patterned hard mask layer 114 to form a container trench 130 that passes through the top nitride layer 112, the implanted oxide layer 110a, the container oxide layer 110, the intermediate nitride layer 108, the interlayer dielectric layer 106, and the bottom nitride layer 104, thereby exposing the underlying transistor 102a. The container trench 130 serves as a vertical space for forming a high aspect ratio capacitance structure.

[0035] In one or more embodiments, a photoresist layer may be spin-coated onto the polysilicon hard mask layer. The desired pattern of the polysilicon hard mask layer is defined on the photoresist layer using photolithography, followed by etching of the exposed polysilicon areas using plasma dry etching (e.g., Cl2, HBr chemical gases). The photoresist pattern is transferred to the patterned hard mask layer 114. After etching the exposed polysilicon areas, the remaining photoresist layer is removed. At this point, the patterned hard mask layer 114 serves as the hard mask for the dry-etched container trench 130.

[0036] Plasma dry etching 140 is configured to use a patterned hard mask layer 114 as a hard mask to etch the container trench 130 because it provides highly precise and selective anisotropic (directional) etching. Plasma dry etching 140 is a technique that uses reactive plasma (ionized gas) to chemically and / or physically remove material from a substrate. In one or more embodiments, plasma dry etching 140 may be reactive ion etching (RIE) or inductively coupled plasma (ICP), in which ions are vertically accelerated to the wafer surface under the influence of an electric field.

[0037] However, due to the ion scattering effect of plasma dry etching 140, damage may form on the sidewalls, specifically arcuate recesses 132 on the inner sidewall 130a of the container trench 130. The ion scattering effect can be mitigated by reducing the cavity pressure (i.e., reducing the number of gas molecules), as fewer ions colliding with gas molecules reduces scattering, thereby improving the mean free path of the ions. The ion scattering effect can also be mitigated by generating a high-density plasma at a low bias voltage, i.e., generating sufficient reactive species without over-accelerating the ions. These mitigation methods may reduce the throughput of plasma dry etching 140.

[0038] Reference Figure 7 The arcuate recesses 132 formed on the inner wall 130a of the container trench 130 due to ion scattering effects are magnified. The width W between two adjacent arcuate recesses 132 may be smaller than the bridge margin between two adjacent containers, which may result in an electrical short circuit between adjacent containers. In one or more embodiments, the arcuate recesses 132 formed on the inner wall 130a of the container trench 130 have a maximum depth D of 1 nanometer to 2 nanometers to avoid electrical short circuits between adjacent containers, that is, the width W between two adjacent arcuate recesses 132 may be smaller than the bridge margin between adjacent containers.

[0039] After ion implantation, the implanted oxide layer 110a, implanted with at least one of boron, carbon, germanium, and arsenic ions, exhibits a significantly lower dry etch rate. In one or more embodiments, the dry etch rate selectivity ratio between the implanted oxide layer 110a and the unimplanted container oxide layer 110 is greater than 2.48 and can be fine-tuned by adjusting the type and / or dosage of the implanted elements.

[0040] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 73.31 nm / min after boron implantation at a dose of 1.00E+16 (ion / cm²) and a dry etch rate of 51.03 nm / min after boron implantation at a dose of 3.00E+16 (ion / cm²).

[0041] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 82.81 nm / min after boron implantation at a dose of 1.00E+16 (ion / cm²) and a dry etch rate of 41.49 nm / min after boron implantation at a dose of 3.00E+16 (ion / cm²).

[0042] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 85.40 nm / min after carbon implantation at a dose of 1.00E+16 (ion / cm²) and a dry etch rate of 79.43 nm / min after carbon implantation at a dose of 3.00E+16 (ion / cm²).

[0043] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 88.58 nm / min after carbon implantation at a dose of 1.00E+16 (ion / cm²) and a dry etch rate of 70.55 nm / min after carbon implantation at a dose of 3.00E+16 (ion / cm²).

[0044] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 102.94 nm / min after a germanium implantation dose of 1.00E+16 (ion / cm²) and a dry etch rate of 84.98 nm / min after a germanium implantation dose of 3.00E+16 (ion / cm²).

[0045] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 107.70 nm / min after a germanium implantation dose of 1.00E+16 (ion / cm²) and a dry etch rate of 82.61 nm / min after a germanium implantation dose of 3.00E+16 (ion / cm²).

[0046] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 102.68 nm / min after arsenic implantation at a dose of 1.00E+16 (ion / cm²) and a dry etch rate of 90.46 nm / min after arsenic implantation at a dose of 3.00E+16 (ion / cm²).

[0047] In one or more embodiments, the unimplanted container oxide layer 110 has a dry etch rate of 102.87 nm / min, while the implanted oxide layer 110a has a dry etch rate of 105.85 nm / min after arsenic implantation at a dose of 1.00E+16 (ion / cm²) and a dry etch rate of 92.84 nm / min after arsenic implantation at a dose of 3.00E+16 (ion / cm²).

[0048] In summary, the semiconductor memory device and its manufacturing method of the present invention comprise a container oxide layer implanted with a specific element (i.e., boron, carbon, germanium, or arsenic) at a specific dose. The implanted oxide layer, after ion implantation, exhibits a significantly lower dry etch rate compared to an unimplanted container oxide layer. This implanted oxide layer can serve as a hard mask for the container oxide layer. High etch selectivity exists between the implanted oxide layer and the container oxide layer, and ion scattering effects are reduced, thereby achieving a smaller arcuate cavity depth to avoid short circuits between containers.

[0049] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0050] [Symbol Explanation] 100: Memory device 102: Semiconductor substrate 102a: Transistor 104: Bottom nitriding layer 106: Interlayer dielectric layer of the container 108: Intermediate nitride layer 110: Container oxide layer 110a: Implanted oxide layer 112: Top nitrided layer 114: Hard mask layer 120: Ion implantation process 130: Container trench 130a: Inner wall 132: Arc-shaped depression 140: Plasma dry etching 800: Process 802: Steps 804: Steps 806: Steps 808: Steps 810: Steps 812: Steps h1: Thickness W: Width D: Maximum depth.

Claims

1. A method of manufacturing a semiconductor memory device, characterized by, comprising: forming a container ILD layer on a substrate; forming an intermediate nitride layer on the container ILD layer; forming a container oxide layer on the intermediate nitride layer; implanting at least one of boron ions, carbon ions, germanium ions, and arsenic ions into a region of the container oxide layer to convert into an implanted oxide layer; forming a hardmask layer over the implanted oxide layer; and patterning the hardmask layer and using the patterned hardmask layer to perform dry etching on at least the implanted oxide layer. The implanted oxide layer has a thickness in a range from 30 nm to 40 nm.

2. The method of claim 1, wherein, The step of implanting at least one of boron ions, carbon ions, germanium ions, and arsenic ions includes implanting boron ions or carbon ions at an energy of 10 KeV to 30 KeV.

3. The method of claim 1, wherein, The step of implanting at least one of boron ions, carbon ions, germanium ions, and arsenic ions includes implanting germanium ions or arsenic ions at an energy of 55 KeV to 120 KeV.

4. The method of claim 1, wherein, further comprising:

5. The method of claim 1, wherein, performing a thermal treatment process to anneal the implanted oxide layer. further comprising:

6. The method of claim 1, wherein, forming a top nitride layer over the implanted oxide layer prior to forming the hardmask layer. The container ILD layer is a borophosphosilicate glass layer.

7. The method of claim 1, wherein, The hardmask layer is a polysilicon hardmask layer.

8. The method of claim 1, wherein, further comprising:

9. The method of claim 1, wherein, forming a bottom nitride layer on the substrate prior to forming the container ILD layer. comprising:

10. A semiconductor memory device, characterized by comprising: a container ILD layer disposed on a substrate; an intermediate nitride layer disposed on the container ILD layer; a container oxide layer disposed on the intermediate nitride layer; an implanted oxide layer disposed on the container oxide layer, the implanted oxide layer including at least one of boron ions, carbon ions, germanium ions, and arsenic ions; and a container trench penetrating at least the implanted oxide layer, the container oxide layer, the intermediate nitride layer, and the container ILD layer. The implanted oxide layer has a thickness in a range from 30 nm to 40 nm.

11. The semiconductor memory device according to claim 10, wherein The container ILD layer is a borophosphosilicate glass layer.

12. The semiconductor memory device of claim 10, wherein, An arcuate recess formed on an inner sidewall of the container trench has a maximum depth in a range from 1 nm to 2 nm.

13. The semiconductor memory device of claim 10, wherein, further comprising a top nitride layer disposed over the implanted oxide layer.

14. The semiconductor memory device of claim 10, wherein, further comprising a bottom nitride layer between the container ILD layer and the substrate.

15. The semiconductor memory device of claim 10, wherein, ​

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