Memory device with pass transistor circuit

Abstract

A memory device having a pass transistor circuit includes a substrate on which a first active region and a second active region adjacent to each other in a first horizontal direction are disposed. The first transfer transistor is disposed on the substrate and has a first gate electrode across the first active region in a first horizontal direction, and the second transfer transistor is disposed on the substrate and has a second gate electrode across the second active region in the first horizontal direction. In plan view, the first active region has a first recessed portion facing the second gate electrode on a side adjacent to the second active region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0120910, filed on September 5, 2024, in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Embodiments of the disclosure relate to a memory device having a pass transistor circuit. BACKGROUND

[0004] Memory devices can be classified into volatile memory devices and non-volatile memory devices. Non-volatile memory devices can include a flash memory device, and a resistive memory device such as a resistive RAM (ReRAM), a phase change RAM (PRAM), and a magnetic RAM (MRAM). A memory device can include an array of memory cells and a pass transistor circuit that transmits an operating voltage to a word line of the array of memory cells. SUMMARY

[0005] Embodiments of the disclosure can provide a memory device having a pass transistor circuit.

[0006] Embodiments of the disclosure can provide a memory device including a substrate on which a first active region and a second active region adjacent to each other in a first horizontal direction are disposed, a first pass transistor disposed on the substrate and having a first gate electrode spanning the first active region in the first horizontal direction, and a second pass transistor disposed on the substrate and having a second gate electrode spanning the second active region in the first horizontal direction, wherein the first active region has a first recessed portion facing the second gate electrode on a side adjacent to the second active region in the first horizontal direction in a plan view.

[0007] Embodiments of the disclosure can provide a memory device including an active region disposed on a substrate and recessed on a side in a first horizontal direction, and a pass transistor having a gate electrode disposed on the substrate and spanning a narrow portion of the active region shared by the recessed portion, wherein the active region has a "L" shape including a protrusion extending from the recessed portion in the first horizontal direction.

[0008] ​Embodiments of the disclosure can provide a memory device including a substrate having a first active region and a second active region adjacent to each other in a second horizontal direction perpendicular to a first horizontal direction, each of the first active region and the second active region being provided with a recessed portion and a protruding portion on one side; a first transfer transistor provided on the substrate and having a first gate electrode that straddles a narrow portion in which the recessed portion is formed in the first active region; and a second transfer transistor provided on the substrate and having a second gate electrode that straddles a narrow portion in which the recessed portion is formed in the second active region, wherein the protruding portion of the first active region extends in an opposite direction to the protruding portion of the second active region.

[0009] According to embodiments of the disclosure, a memory device having a transfer transistor circuit can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram of a memory device according to embodiments of the disclosure.

[0011] Figure 2 A memory device according to embodiments of the disclosure is schematically illustrated.

[0012] Figure 3 is illustrated Figure 1 a first memory block and a second memory block, a first transfer transistor group and a second transfer transistor group, a block selection circuit, and a global row line decoder.

[0013] Figure 4 is a plan view illustrating a transfer transistor according to embodiments of the disclosure.

[0014] Figure 5 is a cross-sectional view along line A-A' in Figure 4

[0015] Figure 6 and Figure 7 is a plan view illustrating a portion of a transfer transistor circuit according to embodiments of the disclosure.

[0016] Figure 8 is a plan view illustrating a transfer transistor according to embodiments of the disclosure.

[0017] Figure 9 is a plan view illustrating a transfer transistor and a contact according to embodiments of the disclosure.

[0018] Figure 10 is a plan view illustrating a portion of a transfer transistor circuit according to embodiments of the disclosure.

[0019] Figure 11 ​is a plan view showing a transfer transistor, a contact, and a wiring according to an embodiment of the present disclosure.

[0020] Figure 12 is a cross-sectional view along Figure 11 the B-B' line of

[0021] Figure 13 and Figure 14 is a plan view exemplarily showing a part of a transfer transistor circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions in the embodiments are provided only as examples to explain the concepts disclosed herein. Embodiments or examples according to the concepts of the present disclosure can be implemented in various forms, and the scope of the present disclosure is not limited to the embodiments or examples described herein.

[0023] The same hatching can be shown in the same way throughout the drawings, and does not indicate any correlation or correspondence between the regions.

[0024] When it is described that one element is "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or can be connected or coupled through one or more intermediate elements between the two elements. When it is described that two elements are "directly connected" or "directly coupled", one element is directly connected or coupled to the other element and there is no intermediate element between the two elements.

[0025] When it is described that one element is disposed "above" or "below" another element, the two elements can directly contact each other, or an intermediate element can be disposed between the two elements.

[0026] Terms such as "vertical", "horizontal", "up", "down", "above", "below", "top", "bottom", "front", "back", "side", "left and right", "column", "row", "horizontal", and other relative spatial relationships or directions are used only for convenience of description or reference to the drawings, and do not limit any specific meaning. Other spatial relationships or directions not shown in the drawings or described in the specification can also be within the scope of the present specification.

[0027] Terms such as "first", "second", and the like can be used to distinguish different elements, and do not imply the size, order, priority, number, or importance of the elements. For example, in some embodiments, a first element can be referred to as a second element, and in other embodiments, a second element can be referred to as a first element.

[0028] When elements included in embodiments of the present specification are described in the singular, the elements can be interpreted as including a plurality of elements unless otherwise specified.

[0029] Figure 1 is a block diagram of a memory device according to an embodiment of the present disclosure.

[0030] Referring to Figure 1 The memory device 10 can include a memory cell array 100 and a peripheral circuit 200. The peripheral circuit 200 can include a row decoder 210, a page buffer circuit 220, and control logic 230. Although not shown, the peripheral circuit 200 can further include a voltage generator, a data input / output circuit, a command decoder, an address decoder, etc.

[0031] The memory cell array 100 can include a plurality of memory blocks BLK1-BLKn. Each of the memory blocks BLK1-BLKn can include a plurality of memory cells. The memory cells can be, for example, flash memory cells. Hereinafter, the memory cells are described as NAND flash memory cells, but the present disclosure is not limited thereto. The memory cells can also be resistive memory cells, such as ReRAM, PRAM, or MRAM.

[0032] The memory cell array 100 can be connected to the row decoder 210 through row lines DSL, WL, and SSL. The row lines SSL, WL, and DSL can include a source select line SSL, a word line WL, and a drain select line DSL. The memory cell array 100 can be connected to the page buffer circuit 220 through a plurality of bit lines BL.

[0033] The row decoder 210 can include a block selection circuit 211, a global row line decoder 212, and a pass transistor circuit 213.

[0034] The block selection circuit 211 can be connected to the pass transistor circuit 213 through a block selection signal line BLKWL. The block selection circuit 211 can receive a row address X-ADDR from the control logic 230, and can output a block selection signal for selecting one of the plurality of memory blocks BLK1-BLKn to the one of the block selection signal lines BLKWL in response to the received row address X-ADDR.

[0035] The global row line decoder 212 can be connected to the pass transistor circuit 213 through global row lines GDSL, GWL, and GSSL. The global row lines GDSL, GWL, and GSSL can include a global drain select line GDSL, a global word line GWL, and a global source select line GSSL. The global row line decoder 212 can receive an operating voltage from a voltage generator (not shown) and output the operating voltage to the global drain select line GDSL, the global word line GWL, and the global source select line GSSL in response to a control signal received from the control logic 230.

[0036] The pass transistor circuit 213 can include a plurality of pass transistor groups PTG1-PTGn corresponding to the plurality of memory blocks BLK1-BLKn, respectively.

[0037] Each pass transistor group PTG can be connected to a corresponding memory block BLK through a drain select line DSL, a word line WL, and a source select line SSL. Each pass transistor group PTG can be connected to the global row line decoder 212 through a global drain select line GDSL, a global word line GWL, and a global source select line GSSL. The plurality of pass transistor groups PTG1-PTGn can be commonly connected to the global drain select line GDSL, the global word line GWL, and the global source select line GSSL. That is, the plurality of pass transistor groups PTG1-PTGn can share the global drain select line GDSL, the plurality of global word lines GWL, and the global source select line GSSL.

[0038] A selected one of the pass transistor groups PTG1-PTGn, i.e., a pass transistor group receiving a block selection signal from the block selection circuit 211, can transfer an operating voltage provided by the global row line decoder 212 to a corresponding memory block through the drain select line DSL, the word line WL, and the source select line SSL.

[0039] The page buffer circuit 220 can select some bit lines among the bit lines BL in response to a column address Y-ADDR. The page buffer circuit 220 can operate as a write driver or a sense amplifier according to an operating mode.

[0040] The control logic 230 can generally control various operations within the memory device 10. The control logic 230 can receive a command CMD, an address ADDR, and a control signal CTRL, and can generate various control signals based on the received command CMD, address ADDR, and control signal CTRL for programming data in the memory cell array 100, reading data from the memory cell array 100, or erasing data stored in the memory cell array 100. The control logic 230 can output a row address X-ADDR and a column address Y-ADDR.

[0041] Figure 2 A memory device according to an embodiment of the disclosure is schematically illustrated.

[0042] Referring to Figure 2 , the memory device 10 can include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 and the second semiconductor layer L2 can overlap each other in a vertical direction VD. In Figure 2 , the first semiconductor layer L1 and the second semiconductor layer L2 are illustrated as being spaced apart from each other in the vertical direction VD, but this is for illustrative purposes only, and it is understood that an upper surface of the first semiconductor layer L1 and a lower surface of the second semiconductor layer L2 can be in contact with each other.

[0043] In one embodiment, the peripheral circuit (200 in Figure 1 ) can be disposed on or in the first semiconductor layer L1, and the memory cell array (100 in Figure 1 ) can be disposed on or in the second semiconductor layer L2.

[0044] In the second semiconductor layer L2, a plurality of word lines WL can extend along a first horizontal direction HD1, and a plurality of bit lines BL can extend along a second horizontal direction HD2. The second semiconductor layer L2 can include a first cell region CA1, a second cell region CA2, and a narrowing region SA. The first cell region CA1 and the second cell region CA2 can be arranged along the first horizontal direction HD1, and the narrowing region SA can be arranged between the first cell region CA1 and the second cell region CA2.

[0045] Although not illustrated, the plurality of word lines WL can be stacked in the first cell region CA1 and the second cell region CA2 and the narrowing region SA along the vertical direction VD, thereby forming a stack. The word lines WL can be combined with semiconductor pillars that run through the stack along the vertical direction VD to form three-dimensionally arranged memory cells. The plurality of word lines WL can be implemented in a stepped or ladder shape in the narrowing region SA.

[0046] The first semiconductor layer L1 can include a substrate, and the peripheral circuit (200 in Figure 1 ) can be configured in the first semiconductor layer L1 by forming semiconductor elements such as transistors and patterns for wiring the semiconductor elements on the substrate.

[0047] The first semiconductor layer L1 can include a first region R1 overlapping the first cell region CA1 in the vertical direction VD, a second region R2 overlapping the second cell region CA2 in the vertical direction VD, and a third region R3 overlapping the narrowing region SA in the vertical direction VD. In one embodiment, the transfer transistor circuit 213 can be disposed in the third region R3, but embodiments are not limited thereto.

[0048] The first semiconductor layer L1 and the second semiconductor layer L2 can be manufactured on a single wafer. The first semiconductor layer L1 is formed first, and the second semiconductor layer L2 is built on the first semiconductor layer L1. In this case, the memory device 10 can be defined as having a Peri-Under-Cell (PUC) structure.

[0049] In other embodiments, the first semiconductor layer L1 and the second semiconductor layer L2 can be manufactured on different wafers, and then bonded to each other by a bonding technique. In this case, the memory device 10 can be defined as having a Peri-Over-Cell (POC) structure.

[0050] The memory device 10 according to the present disclosure can be provided as a PUC structure or a POC structure. Although not shown, a memory cell array (100) in Figure 1 and a peripheral circuit (200) in Figure 1 may be arranged in a planar manner on a single substrate.

[0051] Figure 3 The first storage block and the second storage block, the first transfer transistor group and the second transfer transistor group, the block selection circuit, and the global row line decoder of Figure 1 are shown.

[0052] Referring to Figure 3 , each of the first storage block BLK1 and the second storage block BLK2 can include a drain select line DSL, a plurality of word lines WL, and a source select line SSL.

[0053] The first transfer transistor group PTG1 can include a plurality of first transfer transistors TR11-TR16. The second transfer transistor group PTG2 can include a plurality of second transfer transistors TR21-TR26.

[0054] The gate electrodes of the first transfer transistors TR11-TR16 can be commonly connected to a first block selection signal line BLKWL1, and can be connected to the block selection circuit 211 through the first block selection signal line BLKWL1. The gate electrodes of the second transfer transistors TR21-TR26 can be commonly connected to a second block selection signal line BLKWL2, and can be connected to the block selection circuit 211 through the second block selection signal line BLKWL2.

[0055] The first transmission transistor TR11 can be connected between the global source select line GSSL and the source select line SSL. The first transmission transistors TR12-TR15 can be connected between the global word lines GWL1-GWLm and the word lines WL1-WLm, respectively. The first transmission transistor TR16 can be connected between the global drain select line GDSL and the drain select line DSL. When an active block select signal is provided through the first block select signal line BLKWL1, the first transmission transistors TR11-TR16 are turned on. Therefore, the operating voltage provided through the global source select line GSSL, the global word lines GWL1-GWLm, and the global drain select line GDSL can be transmitted to the first memory block BLK1 through the source select line SSL, the word lines WL1-WLm, and the drain select line DSL. The arrangement of the first transmission transistor group PTG1 also applies to the second transmission transistor group PTG2, therefore, a repeated description will be omitted.

[0056] Figure 4 This is a plan view illustrating a transmission transistor according to an embodiment of the present disclosure. Figure 5 It is along Figure 4 A cross-sectional view of line A-A' in the diagram.

[0057] Reference Figure 4 A first active region ACT1 and a second active region ACT2 can be disposed on the substrate, and the first active region ACT1 and the second active region ACT2 are adjacent to each other in the first horizontal direction HD1.

[0058] The first transmission transistor TR1 may include a first gate electrode GE1, which spans a first active region ACT1 in a first horizontal direction HD1. The second transmission transistor TR2 may include a second gate electrode GE2, which spans a second active region ACT2 in the first horizontal direction HD1. The first gate electrode GE1 and the second gate electrode GE2 may be arranged in a row along the first horizontal direction HD1.

[0059] The first active region ACT1 may have a first recessed portion RS1 on the side facing the second active region ACT2, and a first protrusion PS11 and a second protrusion PS12 arranged along the second horizontal direction HD2 on both sides or at both ends of the first recessed portion RS1. For example, the first active region ACT1 may have " Shape. In this specification, a recessed portion may be referred to as a concave part.

[0060] The width of the portion of the first active region ACT1 including the first recessed portion RS1 in the first horizontal direction HD1 may be smaller than the width of the portion of the first active region ACT1 shared by the first protrusion PS11 and the second protrusion PS12 in the first horizontal direction HD1. For example, the width of the portion of the first active region ACT1 having the first protrusion PS11 and the second protrusion PS12 in the first horizontal direction HD1 is W1, and the width of the portion of the first active region ACT1 having the first recessed portion RS1 in the first horizontal direction HD1 is W2, where W2 may be smaller than W1.

[0061] The first gate electrode GE1 may be a narrow portion of the first recessed portion RS1 formed in the first active region ACT1 across the first horizontal direction HD1.

[0062] The second active region ACT2 may have a second recessed portion RS2 on the side facing the first active region ACT1, and third protrusions PS21 and fourth protrusions PS22 arranged along the second horizontal direction HD2 on both sides or at both ends of the second recessed portion RS2. In an embodiment, the second active region ACT2 may have an anti-" "shape.

[0063] The width of the portion of the second active region ACT2 where the second recessed portion RS2 is formed in the first horizontal direction HD1 may be smaller than the width of the portions of the second active region ACT2 where the third protrusion PS21 and the fourth protrusion PS22 are formed in the first horizontal direction HD1. The second gate electrode GE2 may cross the narrow portion of the second active region ACT2 where the second recessed portion RS2 is formed in the first horizontal direction HD1.

[0064] The third gate electrode GE3 of the third transmission transistor TR3 can cross a narrow portion of the first active region ACT1 in the first horizontal direction HD1. The fourth gate electrode GE4 of the fourth transmission transistor TR4 can cross a narrow portion of the second active region ACT2 in the first horizontal direction HD1.

[0065] n-type or p-type impurities can be implanted into the first active region ACT1 on both sides of the first gate electrode GE1 and the third gate electrode GE3, and into the second active region ACT2 on both sides of the second gate electrode GE2 and the fourth gate electrode GE4, thereby forming junction regions Jn1-Jn6.

[0066] The first transmission transistor TR1 may include a first gate electrode GE1, and a first junction region Jn1 and a second junction region Jn2 located on both sides of the first gate electrode GE1. The second transmission transistor TR2 may include a second gate electrode GE2, and a third junction region Jn3 and a fourth junction region Jn4 located on both sides of the second gate electrode GE2. The third transmission transistor TR3 may include a third gate electrode GE3, and a second junction region Jn2 and a fifth junction region Jn5 located on both sides of the third gate electrode GE3. The fourth transmission transistor TR4 may include a fourth gate electrode GE4, and a fourth junction region Jn4 and a sixth junction region Jn6 located on both sides of the fourth gate electrode GE4.

[0067] The first transfer transistor TR1 and the third transfer transistor TR3 can be configured in the first active region ACT1 and can share the second junction region Jn2. The second transfer transistor TR2 and the fourth transfer transistor TR4 can be configured in the second active region ACT2 and can share the fourth junction region Jn4. Global row lines can be connected to the second junction region Jn2 and the fourth junction region Jn4, respectively.

[0068] The first transfer transistor TR1 and the second transfer transistor TR2 can be connected to different memory blocks. That is, the first transfer transistor TR1 and the second transfer transistor TR2 can be included in different transfer transistor groups. For example, the first transfer transistor TR1 can be included in a first transfer transistor group, and the second transfer transistor TR2 can be included in a second transfer transistor group. In this case, the first gate electrode GE1 can be connected to the first block select signal line, the first junction region Jn1 can be connected to the row line of the first memory block, the second gate electrode GE2 can be connected to the second block select signal line, and the third junction region Jn3 can be connected to the row line of the second memory block.

[0069] The third transfer transistor TR3 and the fourth transfer transistor TR4 can be connected to different memory blocks. That is, the third transfer transistor TR3 and the fourth transfer transistor TR4 can be included in different transfer transistor groups. For example, the third transfer transistor TR3 can be included in a third transfer transistor group, and the fourth transfer transistor TR4 can be included in a fourth transfer transistor group. In this case, the third gate electrode GE3 can be connected to the third block select signal line, the fifth junction region Jn5 can be connected to the row line of the third memory block, the fourth gate electrode GE4 can be connected to the fourth block select signal line, and the sixth junction region Jn6 can be connected to the row line of the fourth memory block.

[0070] The first protrusion PS11 of the first active region ACT1 can be spaced apart from the first gate electrode GE1 in the second horizontal direction HD2, and the second protrusion PS12 of the first active region ACT1 can be spaced apart from the third gate electrode GE3 in the second horizontal direction HD2. A first junction region Jn1 can be formed in the first protrusion PS11 of the first active region ACT1, and a fifth junction region Jn5 can be formed in the second protrusion PS12 of the first active region ACT1.

[0071] The third protrusion PS21 of the second active region ACT2 can be spaced apart from the second gate electrode GE2 in the second horizontal direction HD2, and the fourth protrusion PS22 of the second active region ACT2 can be spaced apart from the fourth gate electrode GE4 in the second horizontal direction HD2. A third junction region Jn3 can be formed in the third protrusion PS21 of the second active region ACT2, and a sixth junction region Jn6 can be formed in the fourth protrusion PS22 of the second active region ACT2.

[0072] Reference Figure 4 and Figure 5 The first active region ACT1 and the second active region ACT2 can be defined by a device isolation film ISO disposed on the substrate SUB. Device isolation trenches can be formed in the substrate SUB, and the device isolation film ISO can fill the device isolation trenches. The device isolation film ISO can surround the first active region ACT1 and the second active region ACT2. The first active region ACT1 and the second active region ACT2 can be separated from each other by the device isolation film ISO.

[0073] The first gate electrode GE1 and the second gate electrode GE2 can be disposed on the substrate SUB, and the device isolation film ISO is formed on the substrate SUB. A gate insulating layer GI can be disposed below the first gate electrode GE1 and the second gate electrode GE2 to separate the substrate SUB from each of the first gate electrode GE1 and the second gate electrode GE2.

[0074] A portion of the first gate electrode GE1 may overlap with the first active region ACT1 in the vertical direction VD. A portion of the second gate electrode GE2 may overlap with the second active region ACT2 in the vertical direction VD.

[0075] As described above, since the first gate electrode GE1 and the second gate electrode GE2 are connected to different memory blocks, when a high voltage is applied to one of the first gate electrode GE1 and the second gate electrode GE2, a ground voltage can be applied to the other. For example, if the second memory block is selected, a high voltage can be applied to the second gate electrode GE2, and a ground voltage can be applied to the first gate electrode GE1.

[0076] According to this disclosure, since the portion of the first recessed portion RS1 facing the second gate electrode GE2 is formed in the first active region ACT1, the gap or distance between the first active region ACT1 below the first gate electrode GE1 and the second gate electrode GE2 in the first horizontal direction HD1 can be larger compared to the case where the active region does not have a recessed portion RS1 or RS2. Therefore, the effect of the high voltage applied to the second gate electrode GE2 on the first active region ACT1 below the first gate electrode GE1 can be reduced, thereby reducing or mitigating leakage current generation when a channel is formed in the first active region ACT1 below the first gate electrode GE1 due to the high voltage applied to the second gate electrode GE2.

[0077] Figure 6 and Figure 7 This is a plan view showing a portion of a transmission transistor circuit according to an embodiment of the present disclosure. Figure 6 and Figure 7 The diagram shows the first, second, third, and fourth transmission transistor groups, which correspond to the first memory block BLK1, the second memory block BLK2, the third memory block BLK3, and the fourth memory block BLK4, in the transmission transistor circuit.

[0078] Reference Figure 6 The first storage block BLK1, the second storage block BLK2, the third storage block BLK3, and the fourth storage block BLK4 can be arranged in a row along the second horizontal direction HD2. The size of each of these blocks along the second horizontal direction HD2 can be P1. P1 can be defined as a single block spacing. Along the second horizontal direction HD2, the size of the first storage block BLK1 and the second storage block BLK2 can be P2. P2 can be defined as two block spacings. Similarly, the size of a combination of two adjacent third storage blocks BLK3 and fourth storage blocks BLK4 along the second horizontal direction HD2 can be two block spacings P2.

[0079] The first transfer transistor TR1 and the second transfer transistor TR2 in the first transfer transistor group and the second transfer transistor group can be arranged in an odd number of stages. For example, the first transfer transistor TR1 and the second transfer transistor TR2 can be arranged in the first stage STAGE1, the second stage STAGE2, and the third stage STAGE3.

[0080] For example, in Figure 6 and Figure 7In the first transfer transistor group, some of the first transfer transistors TR1 can be located in the first stage STAGE1, and the rest can be located in the third stage STAGE3. Similarly, some of the second transfer transistors TR2 in the second transfer transistor group can be located in the second stage STAGE2, and the rest can be located in the third stage STAGE3. The first and second transfer transistor groups can share the third stage STAGE3.

[0081] The third transfer transistor TR3 and the fourth transfer transistor TR4 in the third and fourth transfer transistor groups can be located in odd-numbered stages. For example, the third transfer transistor TR3 and the fourth transfer transistor TR4 can be located in the fourth stage (STAGE4), the fifth stage (STAGE5), and the sixth stage (STAGE6).

[0082] Some of the third transfer transistors TR3 in the third transfer transistor group can be placed in the fifth stage (STAGE 5), and the rest can be placed in the fourth stage (STAGE 4). Some of the fourth transfer transistors TR4 in the fourth transfer transistor group can be placed in the sixth stage (STAGE 6), and the rest can be placed in the fourth stage (STAGE 4). The third and fourth transfer transistor groups can share the fourth stage (STAGE 4).

[0083] The dimensions of the three consecutive stages in the second horizontal direction HD2 can be equal to P2, i.e., the two block spacings. In this case, the transmission transistor circuit can be defined as having a 3-stage-2-block structure.

[0084] In the embodiments, reference is made to Figure 6 The first transfer transistor TR1 of the third stage STAGE3 and the third transfer transistor TR3 of the fourth stage STAGE4 can share a first active region ACT1 and are arranged in a row along the second horizontal direction HD2. The second transfer transistor TR2 of the third stage STAGE3 and the fourth transfer transistor TR4 of the fourth stage STAGE4 can share a second active region ACT2 and are arranged in a row along the second horizontal direction HD2.

[0085] In the plan view, the first active region ACT1 may have a first recessed portion RS1 facing the second gate electrode GE2 and the fourth gate electrode GE4 on the side adjacent to the second active region ACT2. On the same side, the first active region ACT1 may have a first protrusion PS11 and a second protrusion PS12 along the second horizontal direction HD2 on both sides of the first recessed portion RS1. In the plan view, the second active region ACT2 may have a second recessed portion RS2 facing the first gate electrode GE1 and the third gate electrode GE3 on the side adjacent to the first active region ACT1. On the same side, the second active region ACT2 may have a third protrusion PS21 and a fourth protrusion PS22 along the second horizontal direction HD2 on both sides of the second recessed portion RS2.

[0086] One of the first transfer transistors TR1 in STAGE 1 and one of the second transfer transistors TR2 in STAGE 2 can be arranged in a row extending along the second horizontal direction HD2 and share a third active region ACT3. Similarly, one of the third transfer transistors TR3 in STAGE 5 and one of the fourth transfer transistors TR4 in STAGE 6 can be arranged in a row extending along the second horizontal direction HD2 and share a fourth active region ACT4. The third active region ACT3 and the fourth active region ACT4 can each have a rectangular structure.

[0087] Although not shown, the first storage block BLK1, the second storage block BLK2, the third storage block BLK3, and the fourth storage block BLK4 can be set. Figure 2 In the first semiconductor layer L1, the first stage STAGE1, the second stage STAGE2, and the third stage STAGE3 can be arranged in the vertical direction VD with... Figure 2 The word line step regions of the first and second memory blocks in the second semiconductor layer L2 overlap. The fourth stage (STAGE4), fifth stage (STAGE5), and sixth stage (STAGE6) can be configured to overlap with each other in the vertical direction VD. Figure 2 The word line step regions of the third and fourth memory blocks in the second semiconductor layer L2 overlap.

[0088] Reference Figure 7 The first transfer transistor TR1 of stage 3 and the third transfer transistor TR3 of stage 4 do not share the active region. The second transfer transistor TR2 of stage 3 and the fourth transfer transistor TR4 of stage 4 do not share the active region.

[0089] In STAGE 3, the first gate electrode GE1 of the first transfer transistor TR1 can cross the first separate active region ACT11 in the first horizontal direction HD1. In STAGE 3, the second gate electrode GE2 of the second transfer transistor TR2 can cross the second separate active region ACT21 in the first horizontal direction HD1.

[0090] In stage 4, the third gate electrode GE3 of the third transfer transistor TR3 can cross the third separate active region ACT12 in the first horizontal direction HD1. The fourth gate electrode GE4 of the fourth transfer transistor TR4 in stage 4 can cross the fourth separate active region ACT22 in the first horizontal direction HD1.

[0091] The first individual active region ACT11 may have a recessed portion RS11 facing the second gate electrode GE2 on the side adjacent to the second individual active region ACT21. The second individual active region ACT21 may have a recessed portion RS21 facing the first gate electrode GE1 on the side adjacent to the first individual active region ACT11.

[0092] The third individual active region ACT12 may have a recessed portion RS12 facing the fourth gate electrode GE4 on the side adjacent to the fourth individual active region ACT22. The fourth individual active region ACT22 may have a recessed portion RS22 facing the third gate electrode GE3 on the side adjacent to the third individual active region ACT12.

[0093] Figure 8 This is a plan view illustrating a transmission transistor according to an embodiment of the present disclosure.

[0094] Reference Figure 8 The first active region ACT1' may have a first recessed portion RS1a and a second recessed portion RS1b facing the second gate electrode GE2 and the fourth gate electrode GE4, respectively, on the side adjacent to the second active region ACT2'. The first active region ACT1' may have a first intermediate protrusion MPS1, which protrudes in a first horizontal direction HD1 and is disposed in a second horizontal direction HD2 between the first recessed portion RS1a and the second recessed portion RS1b, thereby separating the first recessed portion RS1a and the second recessed portion RS1b. In an embodiment, the first active region ACT1' may have an "E" shape.

[0095] The second active region ACT2' may have a third recessed portion RS2a and a fourth recessed portion RS2b facing the first gate electrode GE1 and the third gate electrode GE3, respectively, on the side adjacent to the first active region ACT1'. The second active region ACT2' may have a second intermediate protrusion MPS2, which protrudes in the first horizontal direction HD1 and is disposed between the third recessed portion RS2a and the fourth recessed portion RS2b to separate them. In an embodiment, the second active region ACT2' may have an inverted "E" shape.

[0096] Figure 9 This is a plan view showing the transmission transistor and contact points according to an embodiment of the present disclosure.

[0097] Reference Figure 9 The contact point CT can be disposed on the first protrusion PS11 of the first junction region Jn1. The contact point CT can be connected to the first protrusion PS11 and can extend vertically from the first protrusion PS11. The contact point CT can be spaced apart from a portion CHR1 of the first active region ACT1 (hereinafter referred to as the "first active region below the first gate electrode"), which vertically overlaps with the first gate electrode GE1. In plan view, the contact point CT can be spaced apart from the portion CHR1 in a diagonal direction (e.g., extending at a distance d1) intersecting the first horizontal direction HD1 and the second horizontal direction HD2.

[0098] An ohmic contact region OCR can be formed on the first protrusion PS11 of the first junction region Jn1 below the contact point CT. The ohmic contact region OCR can be formed to facilitate electrical connection between the contact point CT and the first junction region Jn1, and can be doped with a higher concentration of n-type or p-type impurities than the first junction region Jn1. The ohmic contact region OCR and the first active region below the first gate electrode CHR1 can be diagonally spaced from each other, and the gap between the ohmic contact region OCR and the first active region below the first gate electrode CHR1 can be a distance d1.

[0099] In a comparative case, contact points CTa can be arranged in the portion of the first junction region Jn1 excluding the first protrusion PS11, such as... Figure 9As shown by the dashed line in the diagram. Here, the contact point CTa can be spaced apart from the first active region below the first gate electrode CHR1 on the second horizontal direction HD2, and the gap between the ohmic contact region ORa below the contact point CTa and the first active region below the first gate electrode CHR1 can be a distance d2, where d2 is less than d1. If the gap between the ohmic contact region ORa and the first active region below the first gate electrode CHR1 is small, a larger depletion layer may be formed between the first active region below the first gate electrode CHR1 and the first junction region Jn1 due to the influence of the highly doped ohmic contact region ORa, thereby shortening the channel length. Therefore, in the comparative example, due to the reduced channel length, the threshold voltage of the first transfer transistor TR1 may decrease, which may lead to leakage current.

[0100] In contrast, according to embodiments of this disclosure, the contact point CT is disposed on the first protrusion PS11 of the first active region ACT1, thus the gap between the contact point CT and the first active region below the first gate electrode CHR1 is relatively large. The gap between the ohmic contact region OCR and the first active region below the first gate electrode CHR1 can be increased, thereby suppressing leakage current in the first transmission transistor TR1 caused by the influence of the ohmic contact region OCR.

[0101] Figure 10 This is a plan view illustrating a portion of a transmission transistor circuit according to an embodiment of the present disclosure.

[0102] Reference Figure 10 Each of the first active region ACT1, the second active region ACT2, the third active region ACT3, and the fourth active region ACT4 may have recessed portions RS facing each other in the first horizontal direction HD1. Each of the first active region ACT1, the second active region ACT2, the third active region ACT3, and the fourth active region ACT4 may have protrusions PS on both sides of the recessed portion RS, the protrusions PS protruding along the first horizontal direction HD1 and arranged along the second horizontal direction HD2. In an embodiment, each of the first active region ACT1 and the second active region ACT2 may have "mirror images" that are mirror images of each other in the first horizontal direction HD1. "The shape, each of the third active region ACT3 and the fourth active region ACT4, can have a shape that is mirrored to each other in the first horizontal direction HD1." "shape.

[0103] Each of the first active region ACT1, the second active region ACT2, the third active region ACT3, and the fourth active region ACT4 can have a structure that is symmetrical about left and right with respect to adjacent active regions in the second horizontal direction HD2. For example, the recessed portion RS and the protrusion PS of the first active region ACT1 can be disposed to the right of the first active region ACT1, and the recessed portion RS and the protrusion PS of the third active region ACT3, which is adjacent to the first active region ACT1 in the second horizontal direction HD2, can be disposed to the left of the third active region ACT3. Therefore, the protrusion PS of the active regions adjacent to each other in the second horizontal direction HD2 can protrude in opposite directions. Therefore, the active regions adjacent to each other in the second horizontal direction HD2 (e.g., Figure 10 The protrusions PS of ACT1 and ACT3 in the second horizontal direction can not overlap with each other in the second horizontal direction HD.

[0104] Figure 11 This is a plan view illustrating the transmission transistor, contact points, and wiring according to an embodiment of the present disclosure. Figure 12 It is along Figure 11 A cross-sectional view of line B-B'.

[0105] Reference Figure 11 and Figure 12 An interlayer insulating layer (ILD) can be formed on the substrate SUB to cover the transmission transistors TR1, TR2, and TR3.

[0106] A first wiring M1 and a second wiring M2 can be set on the interlayer insulation layer (ILD). The first wiring M1 and the second wiring M2 can be set on the same layer.

[0107] In the plan view, the first wiring M1 can extend along the second horizontal direction HD2 and intersect with the protrusion PS1 of the first active region ACT1. A first contact point CT1 can be provided in the area where the protrusion PS1 of the first active region ACT1 intersects with the first wiring M1. The first contact point CT1 can penetrate the interlayer insulating film ILD1 between the protrusion PS1 of the first active region ACT1 and the first wiring M1 along the vertical direction VD, and electrically connect the first active region ACT1 and the first wiring M1.

[0108] In the plan view, the second wiring M2 can extend along the second horizontal direction HD2 and intersect with the protrusion PS2 of the third active region ACT3. A second contact point CT2 can be provided in the area where the protrusion PS2 of the third active region ACT3 intersects with the second wiring M2. The second contact point CT2 can penetrate the interlayer insulating film ILD2 between the protrusion PS2 of the third active region ACT3 and the second wiring M2 along the vertical direction VD, and can electrically connect the third active region ACT3 and the second wiring M2.

[0109] In the comparative example, if the protrusions of the first active region and the third active region overlap in the second horizontal direction, the first and second wirings may be arranged as a line along the second horizontal direction. In this case, wiring spacing is difficult to manage, so it may be necessary to arrange the first and second wirings in different wiring layers.

[0110] However, according to embodiments of this disclosure, the protrusions PS1 and PS2 of the adjacent first active region ACT1 and third active region ACT3 in the second horizontal direction HD2 do not overlap with each other in the second horizontal direction HD2, and the first wiring M1 and the second wiring M2 can be arranged parallel to each other, such that the first wiring M1 and the second wiring M2 can be arranged in a single wiring layer, as shown below. Figure 12 As shown.

[0111] The above reference Figures 3 to 12 The described embodiment illustrates two groups of transfer transistors sharing a single stage, but other embodiments are not limited to this. For example, in some embodiments, only one group of transfer transistors may be provided in the single stage.

[0112] Figure 13 and Figure 14 This is a plan view illustrating a portion of a transmission transistor circuit according to an embodiment of the present disclosure.

[0113] Reference Figure 13 The transmission transistors of a transmission transistor group can be arranged in two stages. For example, the first transmission transistor TR1 of the first transmission transistor group can be arranged in the second stage STAGE2 and the third stage STAGE3. The dimensions of the two stages in the second horizontal direction HD2 can be the same as the single block spacing P1. Therefore, the transmission transistor circuit can have a 2-stage 1-block structure.

[0114] Reference Figure 14 Each transmission transistor group can have its transmission transistors located in its own stage. For example, the first transmission transistor TR1 of the first transmission transistor group can be located in the first stage STAGE1, the second transmission transistor TR2 of the second transmission transistor group can be located in the second stage STAGE2, the third transmission transistor TR3 of the third transmission transistor group can be located in the third stage STAGE3, and the fourth transmission transistor TR4 of the fourth transmission transistor group can be located in the fourth stage STAGE4.

[0115] The size of the first stage in the second horizontal direction HD2 can be equal to the single block spacing P1. Therefore, the transmission transistor circuit can have a 1-stage, 1-block structure.

[0116] The above description and accompanying drawings are provided for illustrative purposes only, illustrating the technical concepts of this disclosure. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure. Furthermore, since the embodiments disclosed herein are not intended to limit the technical concepts of this disclosure but rather to explain them, the scope of the technical concepts of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the following claims, and all technical concepts within the equivalent scope should be interpreted as included within the scope of the rights of this disclosure.

Claims

1. A memory device comprising: a substrate on which a first active region and a second active region are disposed adjacent to each other in a first horizontal direction; a first transfer transistor disposed on the substrate and having a first gate electrode that spans the first active region in the first horizontal direction; and a second transfer transistor disposed on the substrate and having a second gate electrode that spans the second active region in the first horizontal direction, wherein, in a plan view, the first active region has a first recessed portion on a side adjacent to the second active region in the first horizontal direction that faces the second gate electrode. The first transfer transistor and the second transfer transistor are connected to different memory blocks.

2. The memory device of claim 1, wherein, The first recessed portion is a narrow portion of the first active region in the first horizontal direction, and the first gate electrode spans the narrow portion of the first active region in the first horizontal direction.

3. The memory device of claim 1, wherein, The first gate electrode and the second gate electrode are arranged in a row along the first horizontal direction.

4. The memory device of claim 1, wherein, 5. The memory device according to claim 1, further comprising: a third transfer transistor disposed on the substrate and having a third gate electrode that spans the first active region in the first horizontal direction; and a fourth transfer transistor disposed on the substrate and having a fourth gate electrode that spans the second active region in the first horizontal direction. The third gate electrode spans a narrow portion of the first active region in the first horizontal direction. In a plan view, the first active region further includes a second recessed portion and a protrusion on a side adjacent to the second active region, and 6. The memory device of claim 5, wherein, the second recessed portion faces the fourth gate electrode in the first horizontal direction, and the protrusion extends from the first recessed portion and the second recessed portion in the first horizontal direction.

7. The memory device of claim 5, wherein, The first gate electrode spans a first narrow portion of the first active region in which the first recessed portion is formed, and the third gate electrode spans a second narrow portion of the first active region in which the second recessed portion is formed.

8. The memory device of claim 7, wherein, The second active region has a second recessed portion that faces the first gate electrode.

10. The memory device according to claim 1, further comprising:

9. The memory device of claim 1, wherein, a first memory block connected to the first transfer transistor; and a second memory block connected to the second transfer transistor, wherein the first transfer transistor and the second transfer transistor are included in a first semiconductor layer, and the first memory block and the second memory block are included in a second semiconductor layer, wherein the first semiconductor layer vertically overlaps the second semiconductor layer.

11. The memory device according to claim 1, further comprising: a first memory block connected to the first transfer transistor; and a second memory block connected to the second transfer transistor, ​ ​ ​ ​ The first transfer transistor and the second transfer transistor are included in a first wafer, and the first memory block and the second memory block are included in a second wafer which is bonded to the first wafer.

12. A memory device, comprising: an active region provided on a substrate, a side of the active region being recessed in a first horizontal direction; and a transfer transistor having a gate electrode, the gate electrode being provided on the substrate and straddling a narrow portion of the active region in which a recessed portion is formed, wherein the active region has a "U" shape including a protrusion extending from the recessed portion in the first horizontal direction. wherein the active region has a "U" shape including a protrusion extending from the recessed portion in the first horizontal direction.

13. The memory device according to claim 12, further comprising a contact point connected to one of the protrusions.

14. The memory device of claim 13, wherein, Portions of the active region which vertically overlap the gate electrode and the contact point are spaced apart from each other in a diagonal direction which intersects a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction in a plan view.

15. The memory device according to claim 13, further comprising an ohmic contact region provided on one of the protrusions of the active region, wherein the contact point being connected to the ohmic contact region.

16. A memory device, comprising: a substrate on which a first active region and a second active region are provided adjacent to each other in a second horizontal direction perpendicular to a first horizontal direction, the first active region and the second active region each being provided on a side with a recessed portion and a protrusion; a first transfer transistor provided on the substrate and having a first gate electrode, the first gate electrode extending in the first horizontal direction and straddling a narrow portion of the first active region in which the recessed portion is formed; and a second transfer transistor provided on the substrate and having a second gate electrode, the second gate electrode extending in the first horizontal direction and straddling a narrow portion of the second active region in which the recessed portion is formed, wherein the protrusion of the first active region and the protrusion of the second active region extend in opposite directions.

17. The memory device of claim 16, wherein, The protrusion of the first active region and the protrusion of the second active region do not overlap each other in the second horizontal direction.

18. The memory device according to claim 16, further comprising: a first contact point connected to the protrusion of the first active region; a second contact point connected to the protrusion of the second active region; a first wiring connected to the first contact point; and a second wiring connected to the second contact point, wherein the first wiring and the second wiring are arranged parallel to each other.

19. The memory device of claim 18, wherein, The first wiring and the second wiring extend in the second horizontal direction.

20. The memory device of claim 18, wherein, The first wiring and the second wiring are provided in the same layer.

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