Transistor based on two-dimensional material and preparation method thereof
By using a transistor structure based on the MoTe2 layer and the Fermi level pinning effect, the complexity of doping processes and the challenges of two-dimensional material integration in traditional CMOS logic circuits have been solved, realizing programmable p-type and n-type transistors and improving circuit stability and high-frequency switching performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-14
- Publication Date
- 2026-03-10
AI Technical Summary
The doping process in traditional CMOS logic circuits is complex and difficult to control precisely, which increases the variability of device performance, affects circuit stability and yield, and makes it difficult to achieve high-precision integration of pure p-type and n-type unipolar two-dimensional materials.
By employing a transistor structure based on the MoTe2 layer, programmable p-type and n-type transistors are realized through the Fermi level pinning effect and the gold semiconductor contact barrier modulation, avoiding the doping process, and using mechanical cleavage and atomic layer deposition techniques to prepare high-quality two-dimensional material layers.
It enables dynamic programming to p-type or n-type transistors without relying on doping, reducing technical complexity, improving device performance stability and high-frequency switching capability, and making it suitable for high-density integrated circuits.
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Figure CN121645927A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of optical materials technology, and in particular relates to a transistor based on two-dimensional materials and its fabrication method. Background Technology
[0002] Traditional CMOS logic circuits rely on doped n / p type unipolar devices, but as device size continues to shrink, the doping process faces severe challenges: the doping process is complex and difficult to control precisely, requiring a steep doping distribution, while random fluctuations in the amount of dopant in the channel lead to increased variability in device performance, seriously affecting circuit stability and yield.
[0003] Low-dimensional materials (such as graphene, TMDCs, and carbon nanotubes) have emerged as alternatives due to their superior surface properties and electrical performance. The passivated surfaces of two-dimensional materials, free of dangling bonds, can significantly reduce interfacial scattering and suppress mobility degradation at the nanoscale, making them strong candidates for next-generation electronic devices. However, unlike silicon, achieving pure p-type and n-type unipolarity in a single 2D material via conventional ion implantation is difficult, and directly integrating two different 2D semiconductor materials presents challenges in large-scale, high-precision alignment and interface manipulation. Summary of the Invention
[0004] To address the problems existing in the aforementioned related technologies, the present invention provides a transistor based on two-dimensional materials and its fabrication method, which can be dynamically programmed into a p-type transistor or an n-type transistor by applying an externally selected voltage. Moreover, the transistor is based on the control of the gold semi-contact barrier and has the advantage of not being dependent on doping, thereby reducing the technical complexity.
[0005] In a first aspect, embodiments of this application provide a transistor based on a two-dimensional material, comprising: a substrate, a first MoTe2 layer, a source metal layer, a drain metal layer, a second MoTe2 layer, and a gate layer. The first MoTe2 layer, the source metal layer, and the drain metal layer are sequentially disposed above the substrate. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect. The second MoTe2 layer and the gate layer are sequentially disposed above the first MoTe2 layer. The second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
[0006] Furthermore, the transistor further includes a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed between the first MoTe2 layer and the source metal layer and the drain metal layer. The first gate dielectric layer has a via, and the first MoTe2 layer penetrates the via to form an n-type contact with the source metal layer and the drain metal layer. The second gate dielectric layer is disposed between the second MoTe2 layer and the gate layer, so that the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
[0007] Furthermore, the substrate is a SiO2 / Si substrate, and the thickness of the substrate is 285 nm.
[0008] Furthermore, the source metal layer, the drain metal layer, and the gate layer are all made of gold.
[0009] Secondly, embodiments of this application provide a method for fabricating a transistor based on two-dimensional materials, used to fabricate a transistor based on two-dimensional materials as described in any of the above claims, comprising the following steps:
[0010] A first MoTe2 layer and a first gate dielectric layer are sequentially fabricated on a substrate;
[0011] Vias are etched into the first gate dielectric layer, and gold is deposited using a thermal evaporation metallization process to fill the vias, thereby forming the source metal layer and the drain metal layer. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect; and
[0012] A second MoTe2 layer, a second gate dielectric layer, and a gate layer are sequentially fabricated above the source metal layer and the drain metal layer, wherein the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
[0013] Further, the sequential fabrication of the first MoTe2 layer and the first gate dielectric layer on the substrate includes:
[0014] The few-layer 2H-MoTe2 was mechanically cleaved off the substrate to form the first MoTe2 layer; and
[0015] The first gate dielectric layer is prepared on top of the first MoTe2 layer using atomic layer deposition.
[0016] Further, the step of sequentially fabricating a second MoTe2 layer, a second gate dielectric layer, and a gate layer above the source metal layer and the drain metal layer includes:
[0017] A few-layer 2H-MoTe2 is obtained by mechanical cleaving and transferred over the source metal layer and the drain metal layer to form the second MoTe2 layer;
[0018] The second gate dielectric layer is fabricated above the second MoTe2 layer; and
[0019] The gate layer is formed above the second gate dielectric layer.
[0020] Further, the step of obtaining a few-layer 2H-MoTe2 through mechanical cleavage and transferring it over the source metal layer and the drain metal layer to form the second MoTe2 layer includes:
[0021] A few-layer 2H-MoTe2 is obtained by mechanical cleavage and then transferred to the source metal layer and the drain metal layer by PDMS-assisted dry transfer to form the second MoTe2 layer.
[0022] Further, the fabrication of the second gate dielectric layer above the second MoTe2 layer includes:
[0023] The second gate dielectric layer is prepared on top of the second MoTe2 layer using atomic layer deposition.
[0024] Further, forming the gate layer over the second gate dielectric layer includes:
[0025] The gate layer is formed above the second gate dielectric layer by patterning using electron beam lithography and depositing gold using thermal evaporation metallization.
[0026] In the two-dimensional material-based transistor provided in this application embodiment, the first MoTe2 layer, the source metal layer, and the drain metal layer are sequentially disposed above the substrate. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect. The second MoTe2 layer and the gate layer are sequentially disposed above the first MoTe2 layer. The second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer. Therefore, the two-dimensional material-based transistor provided in this application embodiment can realize the basic device of programmable circuits, and has the ability to configure electronic devices for customized functions after manufacturing. It can be dynamically programmed into a p-type transistor or an n-type transistor by applying an external selection voltage. Moreover, the transistor has the advantage of not relying on doping based on the control of the gold semiconductor contact barrier, thereby reducing technical complexity. Furthermore, the channels of the p-type transistor and the n-type transistor in the two-dimensional material-based transistor provided in this application embodiment are not the same, and there is no process of carrier rearrangement, which can reduce delay and is more conducive to high-frequency switching scenarios. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of the structure of a transistor based on two-dimensional materials provided in an embodiment of this application;
[0029] Figure 2 This is a schematic flowchart illustrating the fabrication method of a transistor based on two-dimensional materials provided in an embodiment of this application.
[0030] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0032] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0033] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. Those skilled in the art will be able to understand the specific meaning of the above terms in this application according to the specific circumstances.
[0034] Reference Figure 1 This application provides a transistor based on a two-dimensional material, comprising: a substrate, a first MoTe2 layer, and a source metal layer (V0). S ), drain metal layer (V DThe substrate comprises a first MoTe2 layer, a second MoTe2 layer, a source metal layer, and a drain metal layer, wherein the first MoTe2 layer, the source metal layer, and the drain metal layer are sequentially disposed above the substrate. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect. The second MoTe2 layer and the gate layer are sequentially disposed above the first MoTe2 layer, wherein the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
[0035] The MoTe2 layer used in the transistor based on two-dimensional materials provided in this application embodiment has a high carrier mobility (up to approximately 50 cm³ in a single layer). 2 MoTe2 has no dangling bonds on its surface and low interface scattering effect, making it suitable for high-performance transistors. Its vertical stacking characteristics make it suitable for high-density integrated circuits. Through van der Waals lamination, multilayer transistors can be stacked while maintaining excellent electrical performance.
[0036] Furthermore, many two-dimensional materials exhibit bipolar characteristics. The Schottky barrier height of the metal-semiconductor junction can be adjusted by changing the manufacturing process and contact metal, thereby controlling the polarity of two-dimensional transistors. When the electron Schottky barrier of the gold-semiconductor contact is much smaller than that of the hole, the transistor will exhibit N-type behavior; conversely, it will exhibit P-type behavior. MoTe2 is a typical transition metal chalcogenide compound with bipolar behavior. Ideally, according to Schottky's law, it will form a p-type contact with a high work function metal (hole injection barrier < electron injection barrier) and an n-type contact with a low work function metal. However, traditional thermal evaporation coating involves high-energy particles bombarding the semiconductor surface, leading to defects, lattice distortion, chemical bonding, and stress at the gold-semiconductor contact interface. This ultimately results in a strong Fermi level pinning effect, making the barrier height within the semiconductor almost independent of the work function of the metal, and essentially determined by the surface properties of the semiconductor. For MoTe2, it is more easily pinned into an n-type contact. If a high-quality gold-semiconductor contact interface can be manufactured, the Fermi level pinning effect will be weakened to the greatest extent, ensuring that MoTe2 and high work function contacts can form a p-type contact.
[0037] like Figure 1As shown, in the two-dimensional material transistor provided in this application embodiment, p-type contacts (hole injection barrier < electron injection barrier) and n-type contacts (electron injection barrier < hole injection barrier) of gold semi-metal contacts are respectively realized on the upper and lower surfaces of the thermally evaporated metal, i.e., the source metal layer and the drain metal layer. Specifically, the lower surface gold semi-metal contact is formed by thermal evaporation, resulting in a strong Fermi level pinning effect; the upper surface gold semi-metal contact is realized by a non-destructive transfer process, which is a relatively ideal van der Waals contact. Therefore, the upper channel is in the negative top gate (V P Under the influence of ) the hole inversion layer is induced. Since the hole injection barrier at the source and drain is smaller, it will exhibit p-type transport; the lower channel is in the positive back gate (V N Electrons are induced under the action of the source and drain. Since the electron injection barrier is smaller at the source and drain, it will exhibit n-type transport.
[0038] However, it should be noted that dual-gate V P and V N It cannot be in the enabled state simultaneously. When the device needs to be a p-type transistor, the gate V... P Enable operation, gate V N It is in a high-resistance off state, and vice versa.
[0039] In the two-dimensional material-based transistor provided in this application embodiment, the first MoTe2 layer, the source metal layer, and the drain metal layer are sequentially disposed above the substrate. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect. The second MoTe2 layer and the gate layer are sequentially disposed above the first MoTe2 layer. The second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer. Therefore, the two-dimensional material-based transistor provided in this application embodiment can realize the basic device of programmable circuits, and has the ability to configure electronic devices for customized functions after manufacturing. It can be dynamically programmed into a p-type transistor or an n-type transistor by applying an external selection voltage. Moreover, the transistor has the advantage of not relying on doping based on the control of the gold semiconductor contact barrier, thereby reducing technical complexity. Furthermore, the channels of the p-type transistor and the n-type transistor in the two-dimensional material-based transistor provided in this application embodiment are not the same, and there is no process of carrier rearrangement, which can reduce delay and is more conducive to high-frequency switching scenarios.
[0040] Furthermore, the transistor further includes a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed between the first MoTe2 layer and the source metal layer and the drain metal layer. The first gate dielectric layer has a via, and the first MoTe2 layer penetrates the via to form an n-type contact with the source metal layer and the drain metal layer. The second gate dielectric layer is disposed between the second MoTe2 layer and the gate layer, and the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
[0041] Furthermore, the substrate is a SiO2 / Si substrate with a thickness of 285 nm. The substrate can be made of SiO2 / Si, AlO3, or Si. The material of the substrate, due to its inherent properties, will have different effects on the interaction between the first MoTe2 layer and the substrate, and the specific material of the substrate is selected based on the actual situation. The substrate thickness of 285 nm is the thickness used for the insulating layer in silicon-based processes below the 90 nm node, and it can be seamlessly integrated with existing photolithography and thin film deposition equipment.
[0042] Furthermore, the source metal layer, the drain metal layer, and the gate layer are all made of gold. Gold has a good work function match with two-dimensional materials such as MoTe2, and Au has a work function of approximately 5.1 eV, which can reduce the Schottky barrier height and promote carrier injection, making it particularly suitable for N-type contacts.
[0043] In addition, refer to Figure 2 This application provides a method for fabricating a transistor based on two-dimensional materials, used to fabricate a transistor based on two-dimensional materials as described in any of the above claims, comprising the following steps:
[0044] A first MoTe2 layer and a first gate dielectric layer are sequentially fabricated on a substrate;
[0045] Vias are etched into the first gate dielectric layer, and gold is deposited using a thermal evaporation metallization process to fill the vias, thereby forming the source metal layer and the drain metal layer. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect; and
[0046] A second MoTe2 layer, a second gate dielectric layer, and a gate layer are sequentially fabricated above the source metal layer and the drain metal layer, wherein the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
[0047] In the method for fabricating a two-dimensional material transistor provided in this application embodiment, p-type (hole injection barrier < electron injection barrier) and n-type (electron injection barrier < hole injection barrier) gold semicontacts are respectively realized on the upper and lower surfaces of the thermally evaporated metal, i.e., the source metal layer and the drain metal layer. Specifically, the lower surface gold semicontact is formed by a thermal evaporation process, resulting in a strong Fermi level pinning effect, while the upper surface gold semicontact is achieved by a non-destructive transfer process, which is a relatively ideal van der Waals contact. Therefore, the upper channel has a negative top gate (V P Under the influence of ) the hole inversion layer is induced. Since the hole injection barrier at the source and drain is smaller, it will exhibit p-type transport; the lower channel is in the positive back gate (V N Electrons are induced under the action of the source and drain. Since the electron injection barrier is smaller at the source and drain, it will exhibit n-type transport.
[0048] In the method for fabricating a transistor based on two-dimensional materials provided in this application embodiment, the first MoTe2 layer, the source metal layer, and the drain metal layer are sequentially disposed above the substrate. The first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through the Fermi level pinning effect. The second MoTe2 layer and the gate layer are sequentially disposed above the first MoTe2 layer. The second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer. Therefore, the transistor generated by the fabrication method provided in this application embodiment is a basic device capable of realizing programmable circuits. It has the ability to configure electronic devices for customized functions after manufacturing. It can be dynamically programmed into a p-type transistor or an n-type transistor by applying an external selection voltage. Moreover, the transistor has the advantage of not relying on doping based on the control of the gold semiconductor contact barrier, thereby reducing technical complexity. Furthermore, the channels of the p-type transistor and the n-type transistor in the two-dimensional material-based transistor provided in this application embodiment are not the same, and there is no process of carrier rearrangement, which can reduce delay and is more conducive to high-frequency switching scenarios.
[0049] Furthermore, in some embodiments of this application, the sequential fabrication of the first MoTe2 layer and the first gate dielectric layer on the substrate includes:
[0050] The few-layer 2H-MoTe2 was mechanically cleaved off the substrate to form the first MoTe2 layer; and
[0051] The first gate dielectric layer is prepared on top of the first MoTe2 layer using atomic layer deposition.
[0052] Specifically, a few-layer 2H-MoTe2 is exfoliated onto a pretreated substrate using mechanical cleavage to form a high-quality, thickness-controllable two-dimensional layer. Subsequently, Al2O3 or HfO2 gate dielectric is deposited on the MoTe2 surface using low-temperature atomic layer deposition (ALD) technology, achieving conformal coverage and atomic-level thickness control. Mechanical cleavage preserves the intrinsic properties of the material, while ALD ensures the uniformity of the gate dielectric. The combination of the two can significantly reduce interface defects and contact resistance, thereby improving device mobility and stability.
[0053] Furthermore, in some embodiments of this application, the step of sequentially fabricating a second MoTe2 layer, a second gate dielectric layer, and a gate layer over the source metal layer and the drain metal layer includes:
[0054] A few-layer 2H-MoTe2 is obtained by mechanical cleaving and transferred over the source metal layer and the drain metal layer to form the second MoTe2 layer;
[0055] The second gate dielectric layer is fabricated above the second MoTe2 layer; and
[0056] The gate layer is formed above the second gate dielectric layer.
[0057] Specifically, a few-layer 2H-MoTe2 is mechanically cleaved and then precisely coated onto the source / drain metal layers using directional transfer technology to form a high-quality two-dimensional channel layer. Subsequently, an Al2O3 or HfO2 gate dielectric layer is prepared on the MoTe2 surface using low-temperature atomic layer deposition (ALD) to ensure interface uniformity. Finally, a metal gate is deposited using electron beam evaporation or sputtering to complete the device structure. The combination of mechanical cleaving and low-temperature ALD preserves the intrinsic properties of the materials, reduces interface defects, and improves device performance; directional transfer technology overcomes the limitations of micron-level dimensions, enabling precise patterning.
[0058] Furthermore, in some embodiments of this application, the step of obtaining a few-layer 2H-MoTe2 by mechanical cleaving and transferring it over the source metal layer and the drain metal layer to form the second MoTe2 layer includes:
[0059] A few-layer 2H-MoTe2 is obtained by mechanical cleavage and then transferred to the source metal layer and the drain metal layer by PDMS-assisted dry transfer to form the second MoTe2 layer.
[0060] In other words, a few-layer 2H-MoTe2 crystal is peeled off using adhesive tape to obtain a single-layer or few-layer (<10 layers) two-dimensional material, and the target thickness is screened using optical microscopy and Raman spectroscopy. Specifically, a PDMS film is attached to the cleaved MoTe2 surface and transferred to PDMS by mechanical peeling; then the PDMS film is aligned above the source / drain metal layer, a slight pressure is applied to bring the MoTe2 into contact with the metal layer, and the PDMS is slowly peeled off to complete the transfer.
[0061] Furthermore, in some embodiments of this application, the fabrication of the second gate dielectric layer above the second MoTe2 layer includes:
[0062] The second gate dielectric layer is prepared on top of the second MoTe2 layer using atomic layer deposition.
[0063] Specifically, a gate dielectric layer is grown layer by layer on the transferred second MoTe2 layer surface using atomic layer deposition (ALD) technology. During deposition, the precursor is alternately introduced into the reaction chamber in a pulsed manner, and atomic-level thickness control is achieved by utilizing self-confined surface reactions, ultimately forming a uniform second gate dielectric layer with a thickness of 5-10 nm. ALD can uniformly deposit on the step edges and surface of MoTe2, avoiding pinhole defects, and the gate dielectric thickness can be precisely controlled by the number of cycles, meeting the requirements for ultra-thin gate dielectrics.
[0064] Furthermore, in some embodiments of this application, forming the gate layer over the second gate dielectric layer includes:
[0065] The gate layer is formed above the second gate dielectric layer by patterning using electron beam lithography and depositing gold using thermal evaporation metallization.
[0066] Specifically, an electron beam resist (such as PMMA) is spin-coated onto the surface of the second gate dielectric layer. The gate pattern is defined by electron beam exposure, and a resist mask is formed after development. Then, a gold (Au) gate layer, typically 30-100 nm thick, is deposited in a vacuum chamber via thermal evaporation. The combination of electron beam lithography and thermal evaporation enables precise definition and high-quality deposition of the gate pattern. Furthermore, thermal evaporation is a physical deposition process, leaving no chemical etching residue, making it suitable for two-dimensional material devices.
[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A two-dimensional material-based transistor, characterized by, The transistor comprises a substrate, a first MoTe2 layer, a source metal layer, a drain metal layer, a second MoTe2 layer and a gate layer, the first MoTe2 layer, the source metal layer and the drain metal layer are sequentially arranged above the substrate, the first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through Fermi level pinning effect, and the second MoTe2 layer and the gate layer are sequentially arranged above the first MoTe2 layer, and the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer. The transistor further comprises a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer is arranged between the first MoTe2 layer and the source metal layer and the drain metal layer, the first gate dielectric layer is provided with a through hole, the first MoTe2 layer penetrates through the through hole to form an n-type contact with the source metal layer and the drain metal layer, and the second gate dielectric layer is arranged between the second MoTe2 layer and the gate layer, and the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer.
2. The transistor of claim 1, wherein The substrate is a SiO2 / Si substrate, and the thickness of the substrate is 285 nm.
3. The transistor of claim 2, wherein, The material of the source metal layer, the drain metal layer and the gate layer is gold.
4. The transistor according to any one of claims 1 to 3, wherein The method comprises the following steps:
5. A method for fabricating a two-dimensional material-based transistor according to any one of claims 1 to 4, wherein sequentially preparing a first MoTe2 layer and a first gate dielectric layer on a substrate; etching a through hole on the first gate dielectric layer, depositing gold by a thermal evaporation metallization process to fill the through hole, so as to form the source metal layer and the drain metal layer, and the first MoTe2 layer forms an n-type contact with the source metal layer and the drain metal layer through Fermi level pinning effect; and sequentially preparing a second MoTe2 layer, a second gate dielectric layer and a gate layer above the source metal layer and the drain metal layer, and the second MoTe2 layer forms a p-type contact with the source metal layer and the drain metal layer. The step of sequentially preparing a first MoTe2 layer and a first gate dielectric layer on a substrate comprises:
6. The method of claim 1, wherein, peeling off a few-layer 2H-MoTe2 on the substrate by mechanical cleavage to form the first MoTe2 layer; and preparing the first gate dielectric layer above the first MoTe2 layer by atomic layer deposition. The step of sequentially preparing a second MoTe2 layer, a second gate dielectric layer and a gate layer above the source metal layer and the drain metal layer comprises:
7. The method of claim 1, wherein, obtaining a few-layer 2H-MoTe2 by mechanical cleavage and transferring it above the source metal layer and the drain metal layer to form the second MoTe2 layer; preparing the second gate dielectric layer above the second MoTe2 layer; and forming the gate layer above the second gate dielectric layer. The step of obtaining a few-layer 2H-MoTe2 by mechanical cleavage and transferring it above the source metal layer and the drain metal layer to form the second MoTe2 layer comprises:
8. The method of claim 7, wherein, The few-layer 2H-MoTe2 is obtained by mechanical exfoliation, and is transferred above the source metal layer and the drain metal layer by a PDMS-assisted dry transfer method to form the second MoTe2 layer.
9. The method of claim 8, wherein, The preparation of the second gate dielectric layer above the second MoTe2 layer comprises: The second gate dielectric layer is prepared above the second MoTe2 layer by an atomic layer deposition method.
10. The method of claim 9, wherein, The formation of the gate layer above the second gate dielectric layer comprises: The gate layer is formed above the second gate dielectric layer by patterning using an electron beam lithography process and depositing gold using a thermal evaporation metallization process.