Semiconductor device and application

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and application. The semiconductor device comprises a heterojunction structure, a first metal layer or a third metal layer and / or a second metal layer or a fourth metal layer, at least part of the first metal layer or the third metal layer and a semiconductor lamination layer form Schottky contact, at least part of the second metal layer or the fourth metal layer and the semiconductor lamination layer form Schottky contact, and the heterojunction structure is arranged on the semiconductor lamination layer. The first metal layer or the third metal layer and the second metal layer or the fourth metal layer of a radio frequency signal directly pass through the heterojunction structure, so that stray capacitance and signal interference are reduced, and the high-frequency application efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a semiconductor device and its application that improves high-frequency efficiency. Background Technology

[0002] With the rapid growth in demand for high-power, high-frequency, and high-efficiency devices due to emerging applications such as new energy vehicles, communication systems, and renewable energy power generation, the industry has placed higher requirements on power devices. In order to meet the demand for high-frequency power electronics, it is necessary to further improve their performance.

[0003] In existing technologies, conventional GaN HEMT structures require high RF power conversion efficiency for high-frequency applications. Traditional designs use a single heterojunction to form a single channel for signal amplification and conduction, resulting in DC and RF signals sharing the same channel and source-drain spacing (Lgd). This shared structure causes problems at high frequencies: first, Lgd must be balanced between on-resistance (Rd) and off-state breakdown voltage, which cannot be optimized simultaneously; second, parasitic capacitance increases, leading to decreased high-frequency efficiency; and finally, signal interference is aggravated, affecting the amplifier's linearity and stability.

[0004] While existing technologies balance resistance and withstand voltage by adjusting the ligd (Lgd), they cannot fundamentally isolate DC and RF signals. For example, in high-frequency applications, the shared channel in conventional GaN HEMTs causes the RF signal to be affected by DC bias, resulting in harmonic distortion. Therefore, a new structure is urgently needed to solve these problems and improve high-frequency efficiency.

[0005] It should be noted that the information disclosed in this background section is intended only to enhance the understanding of the overall background of the present invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] To address the issue of low efficiency in the aforementioned high-frequency devices, this invention provides a semiconductor device comprising: a semiconductor stack, the semiconductor stack including a heterojunction structure, a source metal, and a drain metal, the source metal and the drain metal being disposed opposite to each other; a gate metal disposed on the semiconductor stack, located between the source metal and the drain metal; and a metal layer further comprising a metal layer stacked on the semiconductor stack, the metal layer forming a Schottky contact with the semiconductor stack; the metal layer being connected to the source metal and disposed between the source metal and the gate and / or the metal layer being connected to the drain metal and disposed between the drain metal and the gate.

[0007] In one specific embodiment, the semiconductor device further includes a source ion implantation region and a drain ion implantation region disposed within a semiconductor stack; the metal layer includes a first metal layer and / or a second metal layer; the first metal layer is stacked on the semiconductor stack, and the source metal is stacked on the first metal layer; the first metal layer includes a first portion and a second portion, the first portion of the first metal layer forming an ohmic contact with at least a portion of the source ion implantation region, the second portion of the first metal layer covering the semiconductor stack between the source metal and the gate metal, and forming a Schottky contact with the semiconductor stack; the second metal layer is stacked on the semiconductor stack, and the drain metal is stacked on the second metal layer; the second metal layer includes a third portion and a fourth portion, the third portion of the second metal layer forming an ohmic contact with at least a portion of the drain ion implantation region; the fourth portion of the second metal layer covering the semiconductor stack between the drain metal and the gate metal, and forming a Schottky contact with the semiconductor stack.

[0008] In an optional embodiment, the thickness of the first metal layer is 1~10nm; the thickness of the second metal layer is 1~10nm; the first metal layer is one of nickel, platinum, palladium, and gold, or a combination thereof; the second metal layer is one of nickel, platinum, palladium, and gold, or a combination thereof.

[0009] Furthermore, in an optional embodiment, the source ion implantation region and the drain ion implantation region are n-type nitrides.

[0010] In some embodiments, the gate metal includes a gate root, the distance from the gate root to the drain ion implantation region is a first distance, and the distance from the gate root to the second metal layer is a second distance; the first distance is greater than the second distance, and the difference between the first distance and the second distance is 0.2~5μm.

[0011] In an optional embodiment, the heterojunction structure includes a channel layer and a barrier layer. The material of the channel layer includes gallium nitride, aluminum gallium nitride, or indium gallium nitride, and the material of the barrier layer includes aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride, or aluminum indium gallium nitride.

[0012] In some embodiments, the first metal layer includes a comb handle portion and a comb tooth portion, the comb handle portion and the comb tooth portion forming a comb shape.

[0013] In some embodiments, the metal layer includes a third metal layer and / or a fourth metal layer; at least a portion of the third metal layer covers the semiconductor stack between the source metal and the gate metal and forms a Schottky contact with the semiconductor stack; at least a portion of the fourth metal layer covers the semiconductor stack between the drain metal and the gate metal and forms a Schottky contact with the semiconductor stack.

[0014] In an optional embodiment, the thickness of the third metal layer is 1~100nm; the thickness of the fourth metal layer is 1~100nm; the material of the third metal layer is a Schottky metal material with a work function greater than 4.3eV; the material of the fourth metal layer is a Schottky metal material with a work function greater than 4.3eV.

[0015] In some embodiments, the third metal layer is one of nickel, platinum, palladium, and gold, or a combination thereof; the fourth metal layer is one of nickel, platinum, palladium, and gold, or a combination thereof.

[0016] In some embodiments, the gate metal includes a gate portion, the distance from the gate root to the drain metal is a fourth distance, and the distance from the gate root to the fourth metal layer is a third distance; the fourth distance is greater than the third distance, and the difference between the fourth distance and the third distance is 0.2~5μm.

[0017] In some embodiments, the semiconductor stack may further include a source ion implantation region and / or a drain ion implantation region disposed within the semiconductor stack; the source metal is disposed on the source ion implantation region; and the drain metal is disposed on the drain ion implantation region.

[0018] In some embodiments, the distance from the gate root to the drain ion implantation region is a first distance, and the distance from the gate root to the fourth metal layer is a third distance; the first distance is greater than the third distance, and the difference between the first distance and the third distance is 0.2~5μm.

[0019] Accordingly, the present invention also provides an electronic device comprising the aforementioned semiconductor device.

[0020] In one embodiment, an electronic device includes a radio frequency amplifier.

[0021] The present invention, through the provision of a heterojunction structure, a first metal layer and / or a second metal layer, enables the radio frequency signal to pass through the first metal layer and / or the second metal layer in direct current through the heterojunction structure, thereby reducing parasitic capacitance and signal interference, and improving the efficiency of high-frequency applications.

[0022] Specifically, in the heterojunction structure, the two-dimensional electron gas is located below the gate, and the first metal layer and / or the second metal layer are located on both sides of the gate, thereby distinguishing between the DC and RF conduction circuits, reducing parasitic capacitance and signal interference, and improving high-frequency efficiency.

[0023] Other embodiments of the present invention employ a heterojunction structure, a third metal layer at least partially disposed on the source metal, and / or a fourth metal layer at least partially disposed on the drain metal. This allows the DC-DC conduction of the RF signal through the third and / or fourth metal layers to occur within the heterojunction structure, thereby reducing parasitic capacitance and signal interference, and improving high-frequency application efficiency. Specifically, the two-dimensional electron gas in the heterojunction structure is located below the gate, and the third and / or fourth metal layers are located on both sides of the gate, thereby distinguishing between the DC and RF conduction circuits, further reducing parasitic capacitance and signal interference, and improving high-frequency efficiency.

[0024] Other features and beneficial effects of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other beneficial effects of the invention can be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships shown in the drawings in the following description are based on the direction in which the components are drawn in the figure.

[0026] Figures 1-10 This is a schematic diagram of the fabrication process of a semiconductor device provided in Embodiment 1 of the present invention; Figure 11 This is a top view schematic diagram of another semiconductor device provided in Embodiment 1 of the present invention; Figure 12 for Figure 11 A cross-sectional view in the cc direction; Figures 13-20 This is a schematic diagram of the fabrication process of a semiconductor device provided in Embodiment 2 of the present invention; Figure 21 A schematic diagram of a semiconductor device provided in Embodiment 3 of the present invention; Figure 22 yes Figure 21 A top-down view; Figure 23 A schematic diagram of a semiconductor device provided in Embodiment 4 of the present invention; Figure 24 This is an equivalent circuit diagram of a semiconductor device provided in an embodiment of the present invention; Figure 25This is a schematic diagram of the conduction current of a semiconductor device provided in an embodiment of the present invention.

[0027] Figure label: 1. Substrate; 2. Nucleation layer; 3. Buffer layer; 41. Channel layer; 42. Barrier layer; 4. Heterojunction structure; 70. Source ion implantation region; 60. Drain ion implantation region; Protective layer; 50; First dielectric layer; 51; Second dielectric layer; 52; Third dielectric layer; 53; Fourth dielectric layer; 54; Fifth dielectric layer; 55; 711. First groove; 611. Second groove; 712. Third groove; 612. Fourth groove; 713. Fifth groove; 613. Sixth groove; 71. First metal layer; 71x. First part; 71y. Second part; 61. Second metal layer; 61x. Third part; 61y. Fourth part; 74. Third metal layer; 64. Fourth metal layer; 72. First source metal; 62. First drain metal; 73. Second source metal; 63. Second drain metal; 8. Gate metal; 81. Gate root; 82. Gate cap; L1. First distance; L2. Second distance; L3. Third distance; L4. Fourth distance. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0030] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto. Example 1

[0031] Please see Figures 1-10 As shown, Figure 9This is a schematic diagram of the structure of a semiconductor device provided in this embodiment, including: a semiconductor stack, the semiconductor stack including a heterojunction structure 4, a first source metal 72, and a first drain metal 62, the first source metal 72 and the first drain metal 62 being disposed opposite to each other; and a gate metal 8 disposed on the semiconductor stack, located between the first source metal 72 and the first drain metal 62. The semiconductor stack also includes a first metal layer 71 and a second metal layer 61; a source ion implantation region 70 and a drain ion implantation region 60 disposed within the semiconductor stack; the first metal layer 71 is stacked on the semiconductor stack, and the first source metal 72 is stacked on the first metal layer 71; the first metal layer 71 includes a first portion 71x and a second portion 71y; the source ion implantation region 70 of the first portion 71x of the first metal layer contacts the source ion implantation region 70 to form an ohmic contact; the second portion 71y of the first metal layer covers the semiconductor stack between the source ion implantation region 70 and the gate metal 8, and forms a Schottky contact with the semiconductor stack; the second metal layer 61 is stacked on the semiconductor stack, and the first drain metal 62 is stacked on the second metal layer 61. The second metal layer 61 includes a third portion 61x and a fourth portion 61y. The third portion 61x of the second metal layer contacts at least a portion of the drain ion implantation region 60, forming an ohmic contact. The fourth portion 61y of the second metal layer covers the semiconductor stack between the drain ion implantation region 60 and the gate metal 8, and forms a Schottky contact with the semiconductor stack. The specific fabrication process includes the following: Step 1, as shown in the attached document Figure 1 As shown, a semiconductor stack is fabricated on substrate 1, including a semiconductor stack heterojunction. The specific structure of the semiconductor stack is not limited in this embodiment, as long as it has the basic structure of a HEMT device, i.e., it includes a heterojunction and a two-dimensional electron gas exists at the heterojunction interface. The following details the process using a GaN HEMT device as an example. Specifically, the semiconductor stack includes a nucleation layer 2, a buffer layer 3, a channel layer 41, and a barrier layer 42 formed sequentially, wherein the channel layer 41 and the barrier layer 42 form a heterojunction structure 4. As an example, the barrier layer 42 can be a single layer or stack of aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride, or aluminum indium gallium nitride, specifically such as AlN, ScAlN, InScAlN, InAlN, AlGaN, or InAlGaN. Preferably, the thickness of the barrier layer 42 is between 1 and 35 nm. The material of the channel layer 41 can be gallium nitride, aluminum gallium nitride, indium gallium nitride, etc. Preferably, the thickness of the channel layer 41 is between 20 and 500 nm.

[0032] Step two, as shown in the attached document. Figure 2As shown, a protective layer 50 is deposited on the semiconductor stack. For example, the protective layer 50 is made of SiN material. Source ion implantation region 70 and drain ion implantation region 60 are formed in the source region and drain region, respectively. The source ion implantation region 70 and drain ion implantation region 60 are formed by ion implantation. The source ion implantation region 70 and drain ion implantation region 60 are formed in the barrier layer 42 by ion implantation, that is, an n-type nitride layer is formed to dope Si or dope Ge, which can effectively reduce the resistivity of the subsequent ohmic contact.

[0033] Step 3, as shown in the attached document Figure 3 As shown, the protective layer 50 is removed, and a first dielectric layer 51 is deposited, such as SiN material, with a thickness of 10~300nm. It should be noted that in other embodiments, the first dielectric layer 51 can also be formed after forming a semiconductor stack (without forming the protective layer 50), and the source ion implantation region 70 and the drain ion implantation region 60 can be formed by direct ion implantation.

[0034] Step four, as Figure 4 As shown, the first dielectric layer 51 is etched to form a first groove 711 and / or a second groove 611; the first groove 711 exposes at least a portion of the source ion implantation region 70 and the surface of the semiconductor stack; the second groove 611 exposes at least a portion of the drain ion implantation region 60 and the surface of the semiconductor stack.

[0035] Step 5, as Figure 5As shown, a metal layer with a thickness of 1-10 nm is deposited. The metal material includes a Schottky metal with a work function greater than 4.3 eV, such as one of nickel, platinum, palladium, and gold, or a combination thereof. Any combination of multiple metals or multiple metal stacks can be used. A first metal layer 71 and / or a second metal layer 61 are formed in a first groove 711. The first metal layer 71 includes a first portion 71x and a second portion 71y. The first portion 71x contacts at least a portion of the source ion implantation region 70, and the second portion 71y forms a Schottky contact with the semiconductor stack. The second metal layer 61 includes a third portion 61x and a fourth portion 61y. The third portion 61x contacts at least a portion of the drain ion implantation region 60, forming an ohmic contact, and the fourth portion 61y contacts the semiconductor stack, forming a Schottky contact. It should be noted that when the first metal layer 71 and the second metal layer 61 are composed of multiple metal stacks, the bottom metal layer is composed of a Schottky metal with a work function greater than 4.3 eV to ensure that a Schottky contact is formed with the semiconductor stack in the non-ion implantation region. The first metal layer 71 and the second metal layer 61 cannot be too thick; otherwise, it will be difficult for the first part 71x to form a good ohmic contact with the source ion implantation region 70, and it will be difficult for the third part 61x to form a good ohmic contact with the drain ion implantation region 60, thus affecting the performance of the semiconductor device. In some preferred embodiments, the thickness of the metal material deposited in this step is 2~5nm, for example, 2nm, 3nm, 4nm, 5nm. It should be noted that in other embodiments, the source ion implantation region 70 may partially contact the first metal layer 71, that is, a part of the source ion implantation region 70 may not contact the first metal layer 71; the drain ion implantation region 60 may partially contact the second metal layer 61, that is, a part of the drain ion implantation region 60 may not contact the second metal layer 61.

[0036] Step six, as follows Figure 6 As shown, a layer of metal material with a thickness of 50~500nm is deposited, such as a Ti / Pt / Au / Ti metal stack. A first source metal 72 is formed on the first metal layer 71, and a first drain metal 62 is formed on the second metal layer 61.

[0037] Step seven, as attached Figure 7 As shown, a second dielectric layer 52 is formed, covering the first source metal 72, the first metal layer 71, the first dielectric layer 51, the second metal layer 61, and the first drain metal 62.

[0038] Step eight, as attached Figure 8 As shown, a groove is formed in the gate region of the second dielectric layer to expose the semiconductor stack and a gate metal 8 is formed, for example, the gate is a T-type gate, including a gate root 81 and a gate cap 82.

[0039] Step nine, as attached Figure 9 As shown, a third dielectric layer 53 is formed. Figure 9for Figure 10 A cross-sectional diagram along the aa direction. Figure 10 To omit the first dielectric layer 51, the second dielectric layer 52, and the third dielectric layer 53 Figure 9 A top-view schematic diagram is provided. In this embodiment, the distance from the gate root 81 to the drain ion implantation region 60 is a first distance L1. Considering the shape variation of the drain ion implantation region 60, this first distance L1 can refer to the distance from the gate root 81 to the upper surface of the drain ion implantation region 60. The distance from the gate root 81 to the second metal layer 61 is a second distance L2, where the first distance L1 is greater than the second distance L2. Preferably, the difference between the first distance L1 and the second distance L2 (L1-L2) is 0.2~5μm, which is the size of the Schottky contact formed between the second metal layer 61 and the semiconductor stack in the gate length direction. By defining the dimensions of the first distance L1 and the second distance L2, the RF conduction capability and DC withstand voltage capability are designed. Optionally, the value range of the second distance L2 is 0.2~2μm. When the second distance L2 is less than 0.2μm, the parasitic capacitance will be relatively large because the corresponding Miller capacitance, i.e. the feedback capacitance between the first drain metal 62 and the gate metal 8, is large. The interference capability of the drain 16 to the RF input signal increases, resulting in the RF amplification gain of the device being too low. When the second distance L2 is greater than 2μm, the on-state impedance increases, the conduction loss increases, resulting in the RF amplification power of the device being too low.

[0040] The thickness of the first metal layer 71 and the second metal layer 61 is 1~10nm. This avoids excessive metal thickness, which would create large gate-source and gate-drain capacitances with the gate metal 8, reducing the device gain capability.

[0041] A top view of the semiconductor device in other embodiments is attached. Figure 11 As shown, the cross-sectional diagram along the bb direction and Figure 10 Similarly, the cross-sectional diagram in the cc direction is shown below. Figure 12 As shown, the first metal layer 71 includes a comb shank portion 71a and comb teeth portion 71b. The comb shank portion 71a and comb teeth portion 71b are comb-shaped. It should be noted that along the gate length direction, the length La of the comb shank portion at different positions can be the same or different, and the length Lb of the comb teeth portion at different positions can be the same or different, or can be arbitrarily varied. Adjusting the source resistance Rs of the RF path and reducing the bias dependence of Rs can improve the linearity of the RF. Optionally, in the direction perpendicular to the gate length direction, the dimensions of the comb teeth portion 71b can be the same or different. The spacing between adjacent comb teeth portion 71b can be the same or different. Example 2

[0042] This embodiment provides a semiconductor device; please refer to [link / reference]. Figures 13-20 As shown, Figure 20This is a schematic diagram of the structure of a semiconductor device provided in this embodiment, including: a semiconductor stack, the semiconductor stack including a heterojunction structure 4; a second source metal 73 disposed on the semiconductor stack; a second drain metal 63 disposed on the semiconductor stack; the second source metal 73 and the second drain metal 63 are disposed opposite to each other; and a gate metal 8 disposed on the semiconductor stack, located between the second source metal 73 and the second drain metal 63. It also has a third metal layer 74 and a fourth metal layer 64; At least a portion of the third metal layer 74 covers the semiconductor stack between the second source metal 73 and the gate metal 8, and forms a Schottky contact with the semiconductor stack; the third metal layer 74 is connected to the second source metal 73. At least a portion of the fourth metal layer 64 covers the semiconductor stack between the second drain metal 63 and the gate metal 8, and forms a Schottky contact with the semiconductor stack.

[0043] The specific structure of the semiconductor stack is described in Example 1 and will not be repeated here.

[0044] The specific manufacturing processes for semiconductor devices include the following: Step 1: Fabricate a semiconductor stack on substrate 1, which is the same as in Example 1. The detailed steps will not be repeated here.

[0045] Step two, as shown in the attached document. Figure 13 As shown, a source ion implantation region 70, a drain ion implantation region 60, and a fourth dielectric layer 54 are formed in the semiconductor stack; the implementation method is described in Example 1, and the detailed steps will not be repeated here.

[0046] Step 3, as Figure 14 As shown, the first dielectric layer 51 is etched to form a third groove 712 and a fourth groove 612; the third groove 712 exposes the source ion implantation region 70; and the fourth groove 612 exposes the drain ion implantation region 60. Optionally, the projected area of ​​the third groove 712 in the substrate direction is smaller than the projected area of ​​the source ion implantation region 70 in the substrate direction, and the projected area of ​​the fourth groove 612 in the substrate direction is smaller than the projected area of ​​the drain ion implantation region 60 in the substrate direction.

[0047] Step four, as Figure 15As shown, a layer of metal material with a thickness of 50-500 nm is deposited. The metal material includes an ohmic metal material with a work function less than or equal to 4.3 eV, such as titanium, tantalum, and their alloys, such as tantalum nitride. The third groove 712 and the fourth groove 612 form the second source metal 73 and the second drain metal 63, respectively. The second source metal 73 forms an ohmic contact with the source ion implantation region 70, and the second drain metal 63 forms an ohmic contact with the drain ion implantation region 60. Preferably, the projected area of ​​the contact surface between the second source metal 73 and the source ion implantation region 70 in the substrate direction is less than or equal to the projected area of ​​the source ion implantation region 70 in the substrate direction. The projected area of ​​the contact surface between the second drain metal 63 and the drain ion implantation region 60 in the substrate direction is less than or equal to the projected area of ​​the drain ion implantation region 60 in the substrate direction. It should be noted that the deposited metal material is a multi-layer metal material stack. The initial metal layer material only needs to include an ohmic metal material with a work function less than or equal to 4.3 eV, such as titanium, tantalum, and their alloys, such as tantalum nitride.

[0048] Step 5, as Figure 16 As shown, a fourth dielectric layer 54 is etched between the second source metal 73 and the gate region to form a fifth groove 713, and / or a fourth dielectric layer 54 is etched between the second drain metal 63 and the gate region to form a sixth groove 613.

[0049] Step six, as attached Figure 17 As shown, a metal layer is deposited, the material being a Schottky metal with a work function greater than 4.3 eV, such as nickel, platinum, palladium, gold, or an alloy of these metals, with a thickness of less than 100 nm. A third metal layer 74 is formed at the fifth groove 713, and a fourth metal layer 64 is formed at the sixth groove 613. The third metal layer 74 covers the surface of the second source metal 73 and the semiconductor stack, and the fourth metal layer 64 covers the surface of the second drain metal 63 and the semiconductor stack. The third metal layer 74 forms a Schottky contact with the semiconductor stack that has not undergone ion implantation; the fourth metal layer 64 forms a Schottky contact with the semiconductor stack that has not undergone ion implantation.

[0050] Step seven, as attached Figure 18 As shown, a fifth dielectric layer 55 is deposited, and a hole is opened in the gate region to form the gate metal 8, as shown in the attached figure. Figure 19 As shown; for example, the gate is a T-type gate, including gate root 81 and gate cap 82.

[0051] Step 8: Deposit the sixth dielectric layer 56, as shown in the attached diagram. Figure 20As shown. In this embodiment, the distance from the gate root 81 to the drain ion implantation region 60 is the first distance L1. Considering the shape variation of the drain ion implantation region 60, this first distance L1 can refer to the distance from the gate root 81 to the upper surface of the drain ion implantation region 60. The distance from the gate root 81 to the fourth metal layer 64 is the third distance L3, and the first distance L1 is greater than the third distance L3. Preferably, the difference between the first distance L1 and the third distance L3 (L1-L3) is 0.2~5μm, that is, the size of the Schottky contact formed between the fourth metal layer 64 and the semiconductor stack in the gate length direction. By defining the dimensions of the first distance L1 and the third distance L3, the RF conduction capability and DC withstand voltage capability are designed. Optionally, the value range of the third distance L3 is 0.2~2μm. When the third distance L3 is less than 0.2μm, the parasitic capacitance will be relatively large because the corresponding Miller capacitance, i.e. the feedback capacitance between the second drain metal 63 and the gate metal 8, is large. The drain's ability to interfere with the RF input signal increases, resulting in the device's RF amplification gain being too low. When the third distance L3 is greater than 2μm, the on-state impedance increases, the conduction loss increases, resulting in the device's RF amplification power being too low.

[0052] The thickness of the third metal layer 74 and the fourth metal layer 64 is 1~100nm to avoid excessive metal thickness, which would create large gate-source and gate-drain capacitances with the gate metal 8 and reduce the device gain. In some preferred embodiments, the thickness of the third metal layer 74 and the fourth metal layer 64 is 10~30nm, for example 10nm, 20nm, and 30nm.

[0053] In other alternative embodiments, the upper surface of the second source metal 73 may also be partially covered by the third metal layer 74, and the upper surface of the second drain metal 63 may also be partially covered by the fourth metal layer 64. Example 3

[0054] The difference from Embodiment 2 is that the semiconductor device provided in this embodiment does not have a source ion implantation region 70 and a drain ion implantation region 60. (See attached diagram) Figure 21 and attached Figure 22 As shown, Figure 22 The fourth dielectric layer 54, the fifth dielectric layer 55, and the sixth dielectric layer 53 are omitted. Figure 21 A top-view schematic diagram. In this embodiment, the distance from the gate root 81 to the second drain metal 63 is the fourth distance L4. The semiconductor device in this embodiment does not have a source ion implantation region 70 and a drain ion implantation region 60. After forming the second source metal 73 and the second drain metal 63, a high-temperature annealing process is required to form good ohmic contact between the second source metal 73, the second drain metal 63, and the semiconductor stack.

[0055] The fourth distance L4 is greater than the third distance L3. Preferably, the difference between the fourth distance L4 and the third distance L3 (L4-L3) is 0.2~5μm, which is the size of the Schottky contact formed between the fourth metal layer 64 and the semiconductor stack in the gate length direction. By defining the dimensions of the fourth distance L4 and the third distance L3, the RF conduction capability and DC withstand voltage capability are designed. Optionally, the value of the third distance L3 is in the range of 0.2~2μm. If the third distance L3 is less than 0.2μm, the parasitic capacitance will be relatively large because the corresponding Miller capacitance, i.e., the feedback capacitance between the second drain metal 63 and the gate metal 8, is large, increasing the interference capability of the drain 16 to the RF input signal, resulting in too low gain of the device's RF amplification; if the third distance L3 is greater than 2μm, the on-state impedance increases, the conduction loss increases, resulting in too low power of the device's RF amplification.

[0056] The materials of the second source metal 73 and the second drain metal 63 include ohmic metal materials with a work function of less than or equal to 4.3 eV, such as titanium, tantalum and their alloys, such as tantalum nitride. The second source metal 73 and the second drain metal 63 form an ohmic contact with the semiconductor stack.

[0057] The thickness of the third metal layer 74 and the fourth metal layer 64 is 1~100nm to avoid excessive metal thickness, which would create large gate-source and gate-drain capacitances with the gate metal 8, reducing the device gain. The third metal layer 74 and the fourth metal layer 64 form a Schottky contact with the semiconductor stack. In some preferred embodiments, the thickness of the third metal layer 74 and the fourth metal layer 64 is 10~30nm, for example, 10nm, 20nm, or 30nm. Example 4

[0058] The difference from Embodiment 3 is that the dimensions of the third metal layer 74 and / or the fourth metal layer 64 are different in the gate length direction. In this embodiment, the third metal layer 74 does not completely cover the second source metal 73, and the fourth metal layer 64 does not completely cover the second drain metal 63. The third metal layer 74 and the fourth metal layer 64 are disposed in the same layer, and the second source metal 73 and the second drain metal 63 are disposed in the same layer. (See attached...) Figure 23 As shown, in this embodiment, the third metal layer 74 does not cover the second source metal 73, and the fourth metal layer 64 does not cover the second drain metal 63. Because there is a step difference in height between the second source metal 73 and the third metal layer 74, and a step in height between the second drain metal 63 and the fourth metal layer 64, in order to ensure that the second source metal 73 and the third metal layer 74 do not break, and the second drain metal 63 and the fourth metal layer 64 do not break, the third metal layer 74 partially covers the second source metal 73, and the fourth metal layer 64 partially covers the second drain metal 63.

[0059] It should be noted that other embodiments can be improved. For example, in Embodiment 2, the third metal layer 74 may partially cover the second source metal 73, or it may not cover the second source metal 73. Similarly, the fourth metal layer 64 may partially cover the second drain metal 63, or it may not cover the second drain metal 63, as long as good contact is formed between the second source metal 73 and the third metal layer 74, and between the fourth metal layer 64 and the second drain metal 63. The deposition order of the third metal layer 74 and the fourth metal layer 64 may be before or after the second source metal 73 and the second drain metal 63. To avoid excessively high steps that could lead to breakage, the third metal layer 74 and the fourth metal layer 64 are deposited first, followed by the deposition of the second source metal 73 and the second drain metal 63.

[0060] Reference Appendix Figure 24 , attached Figure 24 A schematic diagram of the equivalent circuit of a semiconductor device according to the above embodiment is shown, in which S is the source, G is the gate, and D is the drain. In the equivalent distributed RC equivalent circuit network of the semiconductor device of the present invention, a DC path Y1 is formed within the heterojunction structure 4, and a radio frequency path Y is formed by the first metal layer 71 or the third metal layer 74 forming a Schottky contact with the semiconductor stack. GS The second metal layer 61 or the fourth metal layer 64, which forms a Schottky contact with the semiconductor stack, constitutes the radio frequency path Y. GD .

[0061] Connect DC path Y1 and RF path Y GS RF path Y GD Divided into multiple equivalent units, where R cs R is the source contact resistance; cd R is the drain contact resistance; g R is the gate resistor; UD_1 The first sub-resistor of the second metal layer 61 or the fourth metal layer 64; R UD_n The nth sub-resistor of the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack; R US_1 The first sub-resistor is the first metal layer 71 or the third metal layer 74 that forms a Schottky contact with the semiconductor stack; R US_m R is the m-th sub-resistance of the first metal layer 71 or the third metal layer 74 that forms a Schottky contact with the semiconductor stack; L1 R is the first sub-resistor of heterojunction structure 4; Lm R is the m-th sub-resistance of heterojunction structure 4; Lm+1 R is the (m+1)th sub-resistor of heterojunction structure 4; Lm+2 R is the (m+2)th sub-resistor of heterojunction structure 4; Lm+n+2For the (m+n+2)th sub-resistor of heterojunction structure 4; C S_1 The first sub-capacitor is a first metal layer 71 or third metal layer 74 that forms a Schottky contact with the semiconductor stack and is coupled to the heterojunction structure 4; C S_m The m-th sub-capacitor is the first metal layer 71 or the third metal layer 74 forming a Schottky contact with the semiconductor stack and coupled to the heterojunction structure 4; C S_m+1 The (m+1)th sub-capacitor is formed by coupling the first metal layer 71 or the third metal layer 74, which forms a Schottky contact with the semiconductor stack, to the heterojunction structure 4; C D_1 The first sub-capacitor is a second metal layer 61 or fourth metal layer 64 that forms a Schottky contact with the semiconductor stack and is coupled to the heterojunction structure 4; C D_n The nth sub-capacitor is the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack and coupled to the heterojunction structure 4; C D_n+1 The (n+1)th sub-capacitor is formed between the second metal layer 61 or the fourth metal layer 64, which forms a Schottky contact with the semiconductor stack, and the heterojunction structure 4; C gs1 C represents the horizontal gate-source parasitic capacitance. gd1 C is the horizontal gate-drain parasitic capacitance. gs2 C is the gate-source parasitic capacitance in the vertical horizontal direction; gd2 This represents the vertical gate-drain parasitic capacitance.

[0062] When the device is operating under RF power amplification conditions, the RF signal can be effectively transmitted and amplified by fully utilizing the entire RC network through the coupling effect of the series of capacitors between the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack and the heterojunction structure 4, as well as the series of capacitors between the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack and the first metal layer 71 or the third metal layer 74. The DC signal is isolated by the series of capacitors between the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack and the heterojunction structure 4, as well as the series of capacitors between the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack and the first metal layer 71 or the third metal layer 74. The DC signal can only be transmitted through the DC path (i.e., the series of resistors of the heterojunction structure 4), thereby reducing DC power consumption and improving the efficiency of the device in power amplification operation.

[0063] In other embodiments, a cap layer may be provided on the heterojunction structure near the surface, that is, the heterojunction structure 4 does not have a cap layer (the gate is in direct contact with the first barrier layer), and the first metal layer 71 or the third metal layer 74 and the second metal layer 61 or the fourth metal layer 64 that form a Schottky contact with the semiconductor stack may be provided with a cap layer, which may be a GaN layer.

[0064] In other embodiments, the heterojunction structure 4 has an insertion layer between the channel layer 41 and the barrier layer 42. For example, the channel layer 41 is a GaN layer, the barrier layer 42 is an AlGaN layer, and the insertion layer is an AlN layer.

[0065] Accordingly, one embodiment of the present invention also provides a radio frequency amplifier, which includes the semiconductor device of any of the foregoing embodiments. Another embodiment of the present invention also provides a communication device, wherein the radio frequency amplifier can be applied in communication devices such as microwave systems, radar, wireless communication modules, and network devices.

[0066] In summary, this invention utilizes a heterojunction structure 4, a first metal layer 71 or a third metal layer 74 forming a Schottky contact with the semiconductor stack to form a radio frequency (RF) path, and a second metal layer 61 or a fourth metal layer 64 forming a Schottky contact with the semiconductor stack to form another RF path. This allows RF signals to travel through the RF path, while DC-DC signals travel through the heterojunction structure 4, thereby reducing parasitic capacitance and signal interference and improving high-frequency application efficiency. Specifically, the two-dimensional electron gas in the heterojunction structure 4 is located below the gate metal 8, while the second metal layer 61 or the fourth metal layer 64 forming a Schottky contact with the semiconductor stack, and the first metal layer 71 or the third metal layer 74 forming a Schottky contact with the semiconductor stack, are located on both sides of the gate metal 8, thereby distinguishing between the DC and RF conduction circuits. RF signals travel through the RF path, while DC-DC signals travel through the two-dimensional electron gas through the heterojunction structure 4, thus reducing parasitic capacitance and signal interference and improving high-frequency efficiency.

[0067] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device comprising: A semiconductor stack includes a heterojunction structure, a source metal, and a drain metal, the source metal and the drain metal being oppositely arranged; A gate metal is arranged on the semiconductor stack between the source metal and the drain metal; characterized in that, A metal layer is further arranged on the semiconductor stack, and a Schottky contact is formed between the metal layer and the semiconductor stack; The metal layer is connected with the source metal and arranged between the source metal and the gate, and / or the metal layer is connected with the drain metal and arranged between the drain metal and the gate.

2. The semiconductor device of claim 1, further comprising, a source ion implantation region and a drain ion implantation region arranged in the semiconductor stack; The metal layer includes a first metal layer and / or a second metal layer; The first metal layer is arranged on the semiconductor stack, and the source metal is arranged on the first metal layer; The first metal layer includes a first part and a second part, the first part of the first metal layer forms an ohmic contact with at least part of the source ion implantation region, and the second part of the first metal layer covers the semiconductor stack between the source metal and the gate metal and forms a Schottky contact with the semiconductor stack; The second metal layer is arranged on the semiconductor stack, and the drain metal is arranged on the second metal layer; The second metal layer includes a third part and a fourth part, the third part of the second metal layer forms an ohmic contact with at least part of the drain ion implantation region, The fourth part of the second metal layer covers the semiconductor stack between the drain metal and the gate metal and forms a Schottky contact with the semiconductor stack.

3. The semiconductor device of claim 1, wherein, The metal layer is one of nickel, platinum, palladium, gold, or a combination thereof.

4. The semiconductor device of claim 2, wherein The thickness of the first metal layer is 1-10 nm, and the thickness of the second metal layer is 1-10 nm.

5. The semiconductor device of claim 2, wherein the first and second semiconductor layers are formed of a same material. The source ion implantation region and the drain ion implantation region are n-type nitrides.

6. The semiconductor device of claim 2, wherein The gate metal includes a gate root, the distance from the gate root to the drain ion implantation region is a first distance, and the distance from the gate root to the second metal layer is a second distance; the first distance is greater than the second distance, and the difference between the first distance and the second distance is 0.2-5 μm.

7. The semiconductor device of claim 1, wherein The heterojunction structure includes a channel layer and a barrier layer, the material of the channel layer includes gallium nitride, aluminum gallium nitride, or indium gallium nitride, and the material of the barrier layer includes aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride, or aluminum indium gallium nitride.

8. The semiconductor device of claim 2, wherein, The first metal layer includes a handle portion and a tooth portion, and the handle portion and the tooth portion form a comb shape.

9. The semiconductor device of claim 1, wherein, The metal layer includes a third metal layer and / or a fourth metal layer; At least part of the third metal layer covers the semiconductor stack between the source metal and the gate metal and forms a Schottky contact with the semiconductor stack. At least a portion of the fourth metal layer covers the semiconductor stack between the drain metal and the gate metal, and forms a Schottky contact with the semiconductor stack.

10. The semiconductor device of claim 9, wherein, The third metal layer has a thickness of 1-100 nm; and the fourth metal layer has a thickness of 1-100 nm.

11. The semiconductor device of claim 9, wherein the first and second semiconductor layers are formed of a same material. The gate metal includes a gate portion, a distance from the gate root to the drain metal is a fourth distance, and a distance from the gate root to the fourth metal layer is a third distance; the fourth distance is greater than the third distance, and a difference between the fourth distance and the third distance is 0.2-5 μm.

12. The semiconductor device of claim 9, wherein, The semiconductor device further includes a source ion implantation region and / or a drain ion implantation region arranged in the semiconductor stack; the source metal is arranged on the source ion implantation region; and the drain metal is arranged on the drain ion implantation region.

13. The semiconductor device of claim 12, wherein, A distance from the gate root to the drain ion implantation region is a first distance, and a distance from the gate root to the fourth metal layer is a third distance; the first distance is greater than the third distance, and a difference between the first distance and the third distance is 0.2-5 μm.

14. An electronic device, comprising: The electronic device includes the semiconductor device as claimed in any one of claims 1-13.

15. The electronic device of claim 14, wherein: The electronic device includes a radio frequency amplifier.

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