P-type sensing-memory integrated device based on single crystal Bi2O2Se

Abstract

The invention provides a p-type sensing, storage and calculation integrated device based on single crystal Bi2O2Se, and belongs to the technical field of semiconductor device preparation. According to the device, a strong p-type Bi2O2Se thin film which is stable in air is selected as a base material of the device, and effective capture of photon-generated carriers is realized by utilizing a stable and controllable oxygen defect injection technology and intrinsic ferroelectricity of the material, so that stable non-volatile photoelectric response is realized in the single Bi2O2Se thin film, and then the stable sensing, storage and calculation integrated device is prepared. According to the invention, a new normal form for realizing a complex function by a single material is created: by utilizing a collaborative mechanism of defect engineering and ferroelectricity, the electrically erasable nonvolatile photoelectric response is realized in the single material, the complex and uncontrollable heterojunction problem in the traditional scheme is fundamentally avoided, the process is greatly simplified, and the cost is reduced. And the uniformity, the stability and the yield of the device are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor device preparation, and particularly relates to a p-type sensing and storage integrated device based on single-crystal Bi2O2Se. BACKGROUND

[0002] With the semiconductor industry entering the "post-Moore era", the "von Neumann bottleneck" problem based on the traditional silicon-based computing architecture is increasingly prominent, especially in the field of edge computing and artificial intelligence that needs to process massive and unstructured visual data. Frequent data transfer between separate sensing, storage and computing units results in huge power consumption and delay, which has become a core obstacle to system energy efficiency and real-time performance. In this context, the "sensing, storage and computing integrated" architecture has emerged, aiming to integrate light sensing, information storage and analog computing functions in a single device, thereby realizing the localization and efficiency of data processing at the physical level. This approach is considered a disruptive technology path to break through the above bottleneck.

[0003] Among the many candidate materials for implementing sensing, storage and computing integrated devices, two-dimensional layered semiconductor materials have attracted much attention due to their atomic thickness, excellent electrical / optical properties and rich tunability. Among them, devices with non-volatile photoelectric response (i.e., the property that the change in conductance after light exposure is maintained after the light is removed) can simulate the short-term / long-term plasticity of biological synapses and are ideal foundations for dynamic visual processing and pulse neural network computing. To achieve non-volatile photoelectric response, current mainstream solutions usually rely on artificially stacking two or more different two-dimensional materials to form a van der Waals heterojunction, and capturing photo-generated carriers through interfacial tunneling, charge transfer or floating gate effect. For example, CN120321967A discloses a programmable non-volatile ferroelectric Schottky diode and a manufacturing method thereof, which realizes a core control structure by achieving Schottky contact between a semimetal layer and a ferroelectric semiconductor layer; CN120417449A discloses a multifunctional floating gate transistor based on two-dimensional material heterojunction and a preparation method thereof, which constructs a non-volatile memory based on a multifunctional floating gate transistor of two-dimensional material heterojunction.

[0004] However, the above methods have the following two weaknesses: first, the process is extremely difficult: the preparation of heterojunctions faces a series of difficulties such as interlayer bubbles, interface contamination, stress mismatch and precise alignment, which will introduce uncontrollable interface states, leading to device performance degradation and dramatic deterioration of uniformity. Second, the scalability is insufficient: this solution relies heavily on the combination of specific "material pairs", and two-dimensional material systems that can achieve high-quality, large-area epitaxy are rare. This dependence on heterojunctions makes the entire technical route lack universality and scalability, making it difficult to become a stable and reliable engineering solution.

[0005] A few two-dimensional materials, such as molybdenum disulfide, black phosphorus, and indium selenide, can achieve non-volatile photoelectric responses from a single material. However, molybdenum disulfide and indium selenide are both n-type semiconductors, and although black phosphorus is a p-type semiconductor, its extreme instability in air poses many challenges to device integration and applications. To realize CMOS integrated optoelectronic non-volatile arrays, stable n-type and p-type non-volatile devices are needed simultaneously. The ability to achieve non-volatile photoelectric responses from a single material and to be a stable p-type semiconductor in air is key to realizing this revolutionary technology.

[0006] Therefore, the key to promoting the application of inductive-memory-computing integrated devices lies in how to fabricate non-volatile p-type inductive-memory-computing integrated devices based on a single material. Summary of the Invention

[0007] To address the problems existing in the background technology, the purpose of this invention is to provide a p-type inductive-memory-computing integrated device based on single-crystal Bi2O2Se. This device uses a stable, strong p-type Bi2O2Se thin film in air as the basic material. By utilizing stable and controllable oxygen defect injection technology and the intrinsic ferroelectricity of the material, effective capture of photogenerated carriers is achieved, thereby realizing a stable non-volatile photoelectric response in a single Bi2O2Se thin film, and thus fabricating a stable inductive-memory-computing integrated device.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows:

[0009] A p-type in-memory computing device based on single-crystal Bi2O2Se includes a substrate, a Bi2O2Se functional layer, source and drain electrodes, a gate dielectric layer, and a gate electrode; the substrate, Bi2O2Se functional layer, and source and drain electrodes are arranged sequentially from bottom to top, and the gate dielectric layer and gate electrode are disposed between the substrate and the Bi2O2Se functional layer, or on the surface of the source and drain electrodes.

[0010] The Bi2O2Se functional layer is a Bi2O2Se thin film with an oxygen-rich defect layer exhibiting ferroelectric properties.

[0011] Furthermore, the process of introducing the oxygen-rich defect layer of the Bi2O2Se functional layer is as follows: the Bi2O2Se film is subjected to surface ozone treatment to introduce an oxygen-rich defect layer on its surface.

[0012] Furthermore, the ozone treatment time is 30 seconds to 5 minutes, preferably 2 minutes.

[0013] Furthermore, the Bi2O2Se functional layer was obtained by epitaxial growth on the substrate using chemical vapor deposition.

[0014] Furthermore, the thickness of the Bi2O2Se functional layer is 10-100 nm.

[0015] Furthermore, the gate dielectric layer is made of hafnium oxide (HfO2) or aluminum oxide (Al2O3) and has a thickness of 10-50 nm.

[0016] Furthermore, the gate electrode is a top gate electrode or a bottom gate electrode.

[0017] Furthermore, if the device is a top-gate structure, then the device consists of, from bottom to top, a substrate, a Bi2O2Se functional layer, source and drain electrodes, a gate dielectric layer, and a top-gate electrode.

[0018] If the device is a bottom-gate structure, then from bottom to top the device consists of a substrate, a bottom gate electrode, a gate dielectric layer, a Bi2O2Se functional layer, and source / drain electrodes.

[0019] Furthermore, the substrate is a SrTiO3 single crystal substrate, a silicon substrate with an oxide layer on the surface, or a fluorinated phlogopite substrate.

[0020] This invention also provides the application process of the above-mentioned p-type inductive-in-memory computing device:

[0021] By utilizing the synergistic effect of the ferroelectricity of the Bi2O2Se thin film and the oxygen-rich defect layer, a non-volatile photoelectric response is achieved on the thin film; by applying a gate voltage to the Bi2O2Se thin film, the ferroelectricity of the film enables the electrical erasure of the non-volatile photoelectric response.

[0022] The mechanism of this invention is as follows: This invention can controllably introduce oxygen vacancies, which can realize the arrangement of oxygen vacancies barrier wells in the carrier relaxation path. Through the in-situ strong field localization effect of the ferroelectric field, the carriers are bound in the oxygen vacancies energy barrier of the high potential well, realizing a non-volatile response. Furthermore, by performing reverse strong field dragging, photogenerated carriers can be dragged through tunneling to break through the high potential barrier of oxygen vacancies, realizing the erasure of the non-volatile response.

[0023] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0024] This invention pioneers a new paradigm for achieving complex functions with a single material: by utilizing the synergistic mechanism of defect engineering and ferroelectricity, an electrically erasable non-volatile photoelectric response is realized within a single material. This fundamentally avoids the complex and uncontrollable heterojunction problems of traditional solutions, greatly simplifying the process and improving device uniformity, stability, and yield. This invention breaks through the complex fabrication process of traditional two-dimensional material devices based on heterojunctions, achieving highly uniform (>90% yield) and low-power (energy consumption reduced to the fJ level) integrated sensing, storage, and computing functions, suitable for edge intelligence applications such as dynamic visual recognition and neuromorphic computing. Attached Figure Description

[0025] Figure 1This is a micrograph of the single-domain splicing of the Bi2O2Se thin film prepared in Example 1 of the present invention.

[0026] Figure 2 This is a single-domain AFM image of the Bi2O2Se thin film prepared in Example 1 of the present invention.

[0027] Figure 3 XPS image of O element after Bi2O2Se ozone treatment in Example 1 of this invention.

[0028] Figure 4 Non-volatile photoresponse for a 2-inch single-crystal Bi2O2Se thin film array.

[0029] Figure 5 This is a multi-pulse write-erase state diagram for a non-volatile optoelectronic device with a Bi2O2Se thin film array.

[0030] Figure 6 The accuracy of dynamic handwritten digit recognition for the MNIST non-volatile optoelectronic device based on Bi2O2Se thin film array. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0032] Example 1

[0033] A method for fabricating a p-type inductive-in-memory computing device with a top-gate structure includes the following steps:

[0034] Step 1. Cleaning and pretreatment of the substrate: Select SrTiO3(001) single crystal substrate, ultrasonically clean it in acetone and isopropanol for 10 minutes each, dry it with nitrogen, and then perform oxygen plasma treatment. The oxygen plasma treatment power is 100W and the treatment time is 2 minutes to obtain a superhydrophilic surface (water contact angle <3°).

[0035] Step 2. Preparation of single-crystal Bi₂O₂Se thin film using CVD: The STO substrate obtained in Step 1, along with Bi₂O₃ and Bi₂Se₃ precursors, was placed in a tubular CVD reaction chamber. Under an argon atmosphere, the temperature was raised to 600°C, and the growth pressure was 200 Pa, to obtain a single-crystal Bi₂O₂Se thin film with a thickness of approximately 10 nm. The micrograph of the Bi₂O₂Se single-domain splicing obtained in this embodiment is shown below. Figure 1 As shown, the AFM of a single domain is as follows: Figure 2 As shown in the figure, the thickness of the Bi2O2Se film is approximately 10 nm.

[0036] Step 3. Preparation of the Bi2O2Se functional layer with an oxygen-rich defect layer: The grown single-crystal Bi2O2Se film was treated with ozone at a concentration of 100 g / m³ and a temperature of 150 °C for 30 minutes to form the Bi2O2Se functional layer with an oxygen-rich defect layer; the O element XPS image after ozone treatment is shown below. Figure 3 As shown in the figure, the peak position of oxygen binding energy deviates from the standard peak position of oxygen, indicating that oxygen defects were generated after treatment.

[0037] Step 4. Fabrication of source and drain electrodes: After array etching (ICP) of the Bi2O2Se functional layer obtained in step 3, the source and drain electrode array (channel length 5μm, width 20μm) is defined on the thin film by ultraviolet photolithography. Then, 5nm Ti / 50nm Au are deposited sequentially by electron beam evaporation, and the source and drain electrodes are formed by lift-off process.

[0038] Step 5. Preparation of gate dielectric layer: A 10 nm HfO2 top gate dielectric layer is prepared on the surface of the source and drain electrodes using plasma-assisted atomic layer deposition (PE-ALD). TDMAH is used as the precursor and H2O is used as the oxygen source for PE-ALD, which is deposited at 80 °C.

[0039] Step 6. Fabrication of top gate electrode: A 30 nm ITO transparent top gate electrode is fabricated on the surface of the gate dielectric layer using photolithography and sputtering processes.

[0040] Example 2

[0041] A method for fabricating a p-type inductive-in-memory computing array device with a bottom-gate structure includes the following steps:

[0042] Step 1. Cleaning the substrate: A 2-inch thermally oxidized silicon wafer with a SiO2 thickness of 90nm was selected as the substrate. The silicon wafer was then subjected to RCA standard cleaning.

[0043] Step 2. Fabrication of bottom gate electrodes: An Au / Ti (20 / 5nm) bottom gate electrode array was fabricated by photolithography and electron beam evaporation;

[0044] Step 3. Prepare a gate dielectric layer on the bottom gate electrode surface: Deposit 25 nm HfO2 as the gate dielectric layer using PE-ALD at 250 °C;

[0045] Step 4. Transfer the oxygen-rich defect layer Bi2O2Se functional layer to the surface of the gate dielectric layer:

[0046] A 300 nm thick PMMA support layer was spin-coated onto the surface of the oxygen-rich defect layer Bi2O2Se functional layer prepared in Example 1. The sample was then immersed in deionized water, and the film was peeled off using the superhydrophilic effect. The Bi2O2Se functional layer / PMMA support layer was then removed from the deionized water and transferred to the surface of the gate dielectric layer obtained in step 3. The adhesion was enhanced by heating at 60°C for 5 minutes. Finally, PMMA was removed with acetone.

[0047] Step 5. Fabrication of source and drain electrodes: After array etching (ICP) of the Bi2O2Se functional layer obtained in step 3, the source and drain electrode array (channel length 5μm, width 20μm) is defined on the thin film by ultraviolet photolithography. Then, 5nm Ti / 50nm Au are deposited sequentially by electron beam evaporation, and the source and drain electrodes are formed by lift-off process.

[0048] Step 6. Array the entire device thin film: Pattern the continuous thin film into an independent 20×20 device array by reactive ion etching. The reactive ion etching parameters are CF4:O2=20:5 sccm and the power is 80W.

[0049] Figure 4 This is the non-volatile photoelectric response diagram of the array device fabricated in this embodiment. Testing of the fabricated 400 device units shows that under 1550 nm illumination (power density 0.1 mW / cm²), the response is... 2 After being stimulated by a light pulse ranging from 10ms to 10000ms, the photocurrent of the device rises rapidly, and the current retention rate remains above 90% after 1 minute following the removal of the light. Applying a -10V gate voltage pulse can completely erase the non-volatile state.

[0050] The multi-pulse write-erase state diagram of the array device prepared in this embodiment is as follows: Figure 5 As shown, under continuous stimulation by a 0.1s light pulse, there are more than 200 monotonically increasing resistance states; by applying a -10V gate voltage pulse (width 0.1s), non-volatile states can be erased, and hundreds of erase stable states are available, realizing the storage of hundreds of states / pixels and the function of dynamic erasure.

[0051] Example 3

[0052] An application of the integrated sensing, storage, and computing array device prepared according to Example 2 in dynamic target recognition specifically includes the following steps:

[0053] S1. The sensing, storage, and computing integrated array device obtained in Example 2 and the silicon-based read / write control circuit are integrated and packaged in a three-dimensional heterogeneous manner using micro-bump technology; when the system is working, the dynamic light input is directly projected onto the device array to generate and maintain the corresponding conductivity distribution map.

[0054] S2: Application Verification: This system was used to process MNIST handwritten digit dynamic video streams. The device's inherent non-volatile characteristics naturally enabled the fusion of inter-frame information and contrast enhancement.

[0055] Testing showed that the system achieved a 96.5% accuracy rate in recognizing dynamically handwritten digits, while consuming only 1 / 50th the power of traditional CMOS image sensor + GPU solutions. This fully demonstrates the superior advantages of the integrated sensor-memory-computing architecture in low-power dynamic vision processing. The digit recognition accuracy in this embodiment is as follows: Figure 6 As shown, after training, the recognition accuracy is as high as 96.5%, and the root mean square error is close to 0.

[0056] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A p-type neuromorphic and memory integrated device based on single-crystal Bi 2 O 2 Se, characterized in that, The device comprises a substrate, a Bi2O2Se functional layer, source and drain electrodes, a gate dielectric layer and a gate electrode; the substrate, the Bi2O2Se functional layer and the source and drain electrodes are sequentially arranged from bottom to top, the gate dielectric layer and the gate electrode are arranged between the substrate and the Bi2O2Se functional layer or on the surface of the source and drain electrodes. The Bi2O2Se functional layer is a Bi2O2Se thin film with an oxygen-rich defect layer having ferroelectric properties. 2.The p-type neuromorphic device of claim 1, wherein The Bi2O2Se functional layer is an oxygen-rich defect layer introduced by surface ozone treatment of the Bi2O2Se thin film. 3.The p-type neuromorphic device of claim 2, wherein, The ozone treatment is performed for 30 seconds to 5 minutes. 4.The p-type neuromorphic device of claim 1, wherein The Bi2O2Se functional layer is obtained by epitaxial growth on a substrate by chemical vapor deposition. 5.The p-type neuromorphic device of claim 1, wherein The thickness of the Bi2O2Se functional layer is 10-100 nm. 6.The p-type neuromorphic device of claim 1, wherein, The gate dielectric layer is made of hafnium oxide or aluminum oxide and has a thickness of 10-50 nm. 7.The p-type neuromorphic device of claim 1, wherein The device is a top-gate structure or a bottom-gate structure. 8.The p-type olfactory memory and computing integrated device of claim 7, wherein, If the device is a top-gate structure, the gate electrode is a top gate electrode; the device sequentially comprises a substrate, a Bi2O2Se functional layer, source and drain electrodes, a gate dielectric layer and a top gate electrode from bottom to top. If the device is a bottom-gate structure, the gate electrode is a bottom gate electrode; the device sequentially comprises a substrate, a bottom gate electrode, a gate dielectric layer, a Bi2O2Se functional layer and source and drain electrodes from bottom to top. 9.The p-type neuromorphic device of claim 1, wherein, The substrate is a SrTiO3 single crystal substrate, a silicon substrate with an oxide layer on the surface or a fluorophlogopite substrate.

10. The p-type neuromorphic device of any one of claims 1-9, wherein, The application process of the p-type sensing and computing integrated device is as follows: The ferroelectricity of the Bi2O2Se thin film and the synergistic effect of the oxygen-rich defect layer are utilized to realize non-volatile photoelectric response on the thin film; by applying a gate voltage to the Bi2O2Se thin film, the ferroelectricity is utilized to realize electrical erasing of the non-volatile photoelectric response.

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