Packaging structure and forming method thereof

Abstract

A package structure includes a package substrate, a semiconductor module on the package substrate, a composite thermal interface material (TIM) layer including a liquid metal in a polymer matrix and on the semiconductor module, a package cap substrate on which the composite thermal interface material (TIM) layer is disposed, and a reactive interface layer on which the composite thermal interface material (TIM) layer is disposed. A package cover is on the composite thermal interface material layer and attached to the package substrate, and a reactive interface layer is in contact with the composite thermal interface material layer on at least one of the semiconductor module or the package cover.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to a package structure including a composite thermal interface material layer and a method of forming the same. BACKGROUND

[0002] Semiconductor packages (package structures) can include a metal thermal interface material (TIM) layer to enhance heat transfer between a semiconductor die and a heat sink or other cooling component. The metal TIM layer can help maintain the performance and reliability of the semiconductor package by ensuring effective heat dissipation.

[0003] The metal TIM layer can include a variety of different types of metal TIMs. Designers can select the type of metal TIM based on factors such as thermal conductivity, ease of application, operating temperature range, and compatibility with other materials in the semiconductor package. SUMMARY

[0004] It is an object of the present disclosure to provide a package structure and a method of forming the same to address at least one of the problems described above.

[0005] In one embodiment, the present disclosure provides a package structure. The package structure includes a package substrate; a semiconductor module on the package substrate; a composite thermal interface material (TIM) layer including a liquid metal in a polymer matrix on the semiconductor module; a package lid on the composite TIM layer and attached to the package substrate; and a reactive interface layer in contact with the composite TIM layer on at least one of the semiconductor module or the package lid.

[0006] In another embodiment, the present disclosure provides a method of forming a package structure. The method includes attaching a semiconductor module to a package substrate; forming a composite thermal interface material (TIM) layer on the semiconductor module; forming an encapsulant around the composite TIM layer; and attaching a package lid to the package substrate such that the package lid deforms the composite TIM layer and the encapsulant, and such that the composite TIM layer is in contact with a reactive interface layer on at least one of the semiconductor module or the package lid.

[0007] In yet another embodiment, the present disclosure provides a package structure. The package structure includes a package substrate; a semiconductor module including a first reactive interface layer and located on the package substrate; a package cap including a second reactive interface layer and located on the semiconductor module; a composite thermal interface material (TIM) layer located between the package cap and the semiconductor module and contacting the first reactive interface layer and the second reactive interface layer, wherein the composite TIM layer includes a polymer matrix, a metal-based filler, and a particulate filler, the particulate filler having a size smaller than the metal-based filler in the polymer matrix; and an encapsulant formed around the composite TIM layer, contacting an outer sidewall of the composite TIM layer, and configured to form a hermetic seal around the composite TIM layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] The following detailed description can be read in connection with the drawings in which various features are shown. It should be noted that the features are not necessarily drawn to scale and that the dimensions of the various features can be arbitrarily expanded or reduced for the sake of clarity.

[0009] FIG. 1A is a schematic vertical cross-sectional view of a package structure according to one or more embodiments.

[0010] FIG. 1B is a schematic vertical cross-sectional view of a package structure according to one or more embodiments. FIG. 1A is a zoomed-in vertical cross-sectional view of region B of the package structure in

[0011] FIG. 1C is a schematic vertical cross-sectional view of a package structure according to one or more embodiments. FIG. 1A is a zoomed-in vertical cross-sectional view of region C of the package structure in

[0012] FIG. 1D is a schematic vertical cross-sectional view of a package structure according to one or more embodiments. FIG. 1A is a zoomed-in vertical cross-sectional view of region D of the package structure in

[0013] FIG. 2 is a schematic view of a composite thermal interface material (TIM) layer in a package structure according to one or more embodiments.

[0014] FIG. 3 is a schematic top view of a package structure according to one or more embodiments.

[0015] FIG. 4 is a schematic top view of a package cap portion according to one or more embodiments.

[0016] FIG. 5A is a schematic vertical cross-sectional view of an intermediate structure including a package substrate having an upper bonding pad on the package substrate and a lower bonding pad on the package substrate according to one or more embodiments.

[0017] FIG. 5B A vertical cross-sectional schematic of an intermediate structure is shown, in which a semiconductor module can be mounted on a package substrate, according to one or more embodiments.

[0018] FIG. 5C A vertical cross-sectional schematic of an intermediate structure is shown, in which a package underfill layer can be formed on a package substrate, according to one or more embodiments.

[0019] FIG. 5D A vertical cross-sectional schematic of an intermediate structure is shown, in which a surface mount device (SMD) can be mounted on a package substrate, according to one or more embodiments.

[0020] FIG. 5E A vertical cross-sectional schematic of an intermediate structure is shown, in which a composite thermal interface material (TIM) layer can be formed on a semiconductor module, according to one or more embodiments.

[0021] FIG. 5F A vertical cross-sectional schematic of an intermediate structure is shown, after application of a sealant and an adhesive layer, according to one or more embodiments.

[0022] FIG. 5G A vertical cross-sectional schematic of an intermediate structure is shown, in which a package lid can be attached to a package substrate (e.g., mounted on a package substrate), according to one or more embodiments.

[0023] FIG. 5H A vertical cross-sectional schematic of an intermediate structure is shown, in which a ball grid array (BGA) containing a plurality of solder balls can be formed on a package substrate, according to one or more embodiments.

[0024] FIG. 6 A flowchart of a method of forming a package structure is shown, according to one or more embodiments.

[0025] FIG. 7 A vertical cross-sectional schematic of a package structure is shown, with a first alternative design, according to one or more embodiments.

[0026] FIG. 8 A vertical cross-sectional schematic of a package structure is shown, with a second alternative design, according to one or more embodiments.

[0027] FIG. 9 A vertical cross-sectional schematic of a package structure is shown, with a third alternative design, according to one or more embodiments.

[0028] FIG. 10 A vertical cross-sectional schematic of a package structure is shown, with a fourth alternative design, according to one or more embodiments.

[0029] Reference signs are as follows: 10: mediator 12: polymer layer 12a: redistribution layer 13: upper passivation layer 13a: upper bond pad 14: lower passivation layer 14a: lower bond pad 100: package structure 110: package substrate 110a: package substrate upper passivation layer 110b: package substrate lower passivation layer 112: core 112a: via 114: package substrate upper dielectric layer 114a: package substrate upper bond pad 114b: metal interconnect structure 116: package substrate lower dielectric layer 116a: package substrate lower bond pad 116b: metal interconnect structure 119: package underfill layer 119o: outer portion 120: semiconductor module 121: C4 bump 127: upper molding layer 130: package lid 130a: package lid foot portion 130p: package lid plate portion 130s: package lid step portion 130sR: recess 135: bottom surface 140: semiconductor die 140a: semiconductor die upper surface 141: first semiconductor die 142: second semiconductor die 145: die bond film 145a: die bond pad 150: reactive interface layer 151: first reactive interface layer 152: second reactive interface layer 160: adhesive layer 170: composite thermal interface material (TIM) layer 171: polymer 172: metal strip filler 172a: intermetallic compound (IMC) 173: particulate filler 180: ball grid array 181: solder ball 190: surface mount component 200: encapsulant 200b: encapsulant bottom portion 200u: encapsulant upper portion 500: board under support 610, 620, 630, 640: steps 900: plug 901: first plug 902: second plug 930h, 930o 110a ,O 110b : opening 930hi: first opening 930h2: second opening A-A': line B, C, D: regions T130p, T130s, T151, T152, T170, T200u: thickness W119o, W130s, W200, W200b, W200u: width DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments, or examples, for implementing different components of the provided subject matter. Each of the various embodiments and its configurations are described in the context of specific examples to provide a complete description of embodiments of the present application. It should be noted that these are simply examples and are not intended to limit the scope of the embodiments of the present application. For example, when a first element is referred to as being formed on a second element, this can include embodiments where the first and second elements are in direct contact, and can also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the present application can repeatedly refer to numerical values and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent a relationship between the different embodiments and / or configurations being discussed.

[0031] Furthermore, where spatially relative terms are used, such as "beneath", "below", "lower", "above", "upper", and the like, they are used for ease of describing the aspects of one (or more) components or features to another (or more) components or features. The spatially relative terms are used to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. The spatially relative terms are used to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. Where a device is turned over (rotated 90 degrees or other orientation), the spatially relative descriptors are interpreted accordingly. Unless otherwise noted, each element having a given reference numeral has a counterpart having the same reference numeral but having a different suffix.

[0032] Metallic thermal interface material (TIM) layers can include, for example, solder materials, phase change metallic materials, metallic foils, metallic particle-filled materials, or liquid metal materials. Solder materials can include, for example, indium, tin-silver alloys, or tin-bismuth alloys. Indium has a high coefficient of thermal conductivity and a relatively low melting point, which can help to form a reliable bond between components. Tin-silver alloys have good thermal and electrical conductivity, such that tin-silver alloys can be used in electronic applications. Tin-silver alloys are also lead-free, which can be advantageous for compliance with environmental regulations. Tin-bismuth alloys have a low melting point, which can be useful for applications requiring minimal thermal stress to be applied to components.

[0033] Phase change metallic materials (metallic phase change materials) can begin in a solid state, but transition to a liquid phase at a particular temperature, filling gaps and reducing thermal resistance when heated. Phase change metallic materials can include, for example, alloys with low melting points, such as bismuth-based alloys, or indium-based alloys.

[0034] Metallic foils can include, for example, indium foils or silver foils. Indium foils can provide good thermal conductivity, and can conform to irregular surfaces under pressure. Silver foils have high thermal conductivity, and can be used in high performance applications.

[0035] Metallic particle-filled thermal interface materials can include, for example, pastes filled with metallic particles, such as silver or aluminum. The particles can enhance thermal conductivity, while the paste can ensure good contact with a surface.

[0036] Among various types of metal thermal interface materials, liquid metal thermal interface materials are preferred for semiconductor package structures. The main component of most liquid metal thermal interface materials is gallium. Gallium has a low melting point (about 29.8°C or 85.6°F) and excellent thermal conductivity. The ability of gallium to remain liquid at room temperature makes it a key component of liquid metal thermal interface materials. This can help gallium conform closely to surfaces and fill micro-gaps to achieve excellent heat transfer. Indium is often combined with gallium to form an alloy to enhance the overall properties of the liquid metal thermal interface material. Indium can lower the melting point of the alloy and enhance the wettability of indium. The wettability property enables the liquid metal thermal interface material to spread evenly on surfaces. Tin is another common component in liquid metal thermal interface materials. Tin can further lower the melting point of the alloy and enhance the mechanical properties of the material. Tin can also contribute to the wetting and bonding ability of the alloy to various surfaces, such as copper and aluminum. A common formulation of liquid metal thermal interface materials is a gallium-indium-tin alloy (often referred to as Galinstan), which is typically composed of about 68-69% gallium, 21-22% indium, and 9-10% tin.

[0037] Liquid metal thermal interface materials can include other metals in addition to gallium, indium, and tin. In particular, zinc can be added to adjust the melting point and thermal properties. Bismuth can also be added to change the mechanical and thermal properties. Trace amounts of silver can sometimes be added to enhance thermal conductivity.

[0038] However, liquid metal thermal interface materials are susceptible to oxidation, and thus there can be some issues with using liquid metal thermal interface materials. In particular, gallium in the liquid metal thermal interface material can be oxidized in an oxygen-containing environment. Gallium oxidation can result in poor interface adhesion during reliability endurance testing.

[0039] Embodiments of the present disclosure can include liquid metal thermal interface material designs that can mitigate the extent of oxidation and enhance the reliability of the interposer package. In particular, one embodiment can include a composite thermal interface material (e.g., a liquid metal composite thermal interface material). At least one embodiment can include a liquid metal composite material in a polymer matrix, a reactive interface layer, and a perimeter sealant design to enhance reliability.

[0040] At least one embodiment can include a package structure including a semiconductor module and a surface mount device (SMD) on a package substrate. The semiconductor module can include an interposer, a plurality of dies including a system on chip (SoC) die and a high bandwidth memory (HBM) die on the interposer, and a molding layer surrounding the plurality of dies. The semiconductor module can be attached to the package substrate by a controlled collapse chip connection (C4) bump interconnect technology with a controlled solder bump height, and an underfill material can be formed on the package substrate around the C4 bumps. A thermal interface material layer can be placed on the semiconductor module, and an encapsulant can be formed around the thermal interface material layer and the semiconductor module. A ball grid array (BGA) including a plurality of solder balls can be formed on the package substrate.

[0041] In at least one embodiment, the thermal interface material layer can include a liquid metal composite having a polymer matrix. The package structure can further include a reactive interface layer to enhance thermal interface material adhesion and reliability. In at least one embodiment, the thermal interface material layer can be composed of a liquid metal composite including a gallium-based strip filler, a zinc oxide (ZnO x ) particulate filler, and a polymer matrix, and the reactive interface layer can include a gallium / indium / nickel reactive interface layer on the package lid and the semiconductor module. The total thermal interface material bond line thickness (BLT) can be equal to a thickness (T1) of the first reactive interface layer on the semiconductor module plus a thickness (T2) of the composite thermal interface material layer plus a thickness (T3) of the second reactive interface layer on the package lid. In at least one embodiment, T1+T3≤70% of the thermal interface material bond line thickness.

[0042] In at least one embodiment, on a side of the package lid, a width (W1) of the package lid side encapsulant footprint can be greater than a width (W1OH) of an over-head encapsulant footprint. Further, a height (H1) of a step portion on a bottom surface of the package lid (underlying structure) can be less than a height (H1OH) of the over-head encapsulant.

[0043] In at least one embodiment, on a side of the package substrate, the encapsulant can be on the underfill material. A width (W2) of the substrate side encapsulant footprint can be less than or equal to a width (FW) of a peripheral portion of the underfill material. The width (W2) of the substrate side encapsulant footprint can also be less than or equal to the width (W1) of the package lid side encapsulant footprint.

[0044] FIG. 1Ais a schematic illustration of a vertical cross-section of a package structure 100 according to one or more embodiments. FIG. 1B is a schematic illustration of a vertical cross-section of a package structure 100 according to one or more embodiments. FIG. 1A is a zoomed-in vertical cross-section schematic illustration of region B of the package structure 100 in FIG. 1C is a schematic illustration of a vertical cross-section of a package structure 100 according to one or more embodiments. FIG. 1A is a zoomed-in vertical cross-section schematic illustration of region C of the package structure 100 in FIG. 1D is a schematic illustration of a vertical cross-section of a package structure 100 according to one or more embodiments. FIG. 1A is a zoomed-in vertical cross-section schematic illustration of region D of the package structure 100 in

[0045] As shown in FIG. 1A , the package structure 100 can include a package substrate 110, a semiconductor module 120 located on the package substrate 110, a composite thermal interface material (TIM) layer 170 including a liquid metal in a polymer matrix and located on the semiconductor module 120, and a package lid 130 located on the composite TIM layer 170 and attached to the package substrate 110. The package structure 100 can also include a reactive interface layer 150 in contact with the composite TIM layer 170 on at least one of the semiconductor module 120 or the package lid 130.

[0046] The package substrate 110 can include a cored substrate or a coreless substrate. In at least one embodiment, for example, the package substrate 110 can include a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., on a first side or chip-side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board-side of the package substrate 110). In particular, the package substrate 110 can include a build-up film substrate such as an ABF film (ajinomoto build-up film) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 can be described as an ABF film layer.

[0047] The core 112 can provide rigidity to the package substrate 110. For example, the core 112 can include an epoxy such as bismaleimide triazine epoxy (BT epoxy) and / or a woven glass laminate. The core 112 can alternatively or additionally include an organic material such as a polymeric material. In particular, the core 112 can include a dielectric polymeric material such as polyimide (PI), benzocyclo-butene (BCB) polymer, or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the scope of the disclosure.

[0048] The core 112 can include one or more vias 112a. The vias 112a can extend from a lower surface of the core 112 to an upper surface of the core 112. The vias 112a can allow for electrical connections between the upper dielectric layer 114 and the lower dielectric layer 116 of the package substrate. For example, the vias 112a can include one or more film layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the scope of the disclosure.

[0049] The upper dielectric layer 114 of the package substrate can be formed on the upper surface of the core 112. The upper dielectric layer 114 of the package substrate can include multiple film layers and, in particular, can include a build-up film (e.g., ABF). The upper dielectric layer 114 of the package substrate can also include an organic material such as a polymeric material. In particular, the upper dielectric layer 114 of the package substrate can include a dielectric polymeric material such as polyimide (PI), benzocyclo-butene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the scope of the disclosure.

[0050] The dielectric layer 114 on package substrate can include one or more bond pads 114a on package substrate on a wafer-side surface of the dielectric layer 114 on package substrate. The bond pads 114a on package substrate can be exposed from the wafer-side surface of the dielectric layer 114 on package substrate. The dielectric layer 114 on package substrate can also include one or more metal interconnect structures 114b. The metal interconnect structures 114b can be connected to the bond pads 114a on package substrate and the vias 112a in the core 112. The metal interconnect structures 114b can include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The metal interconnect structures 114b can constitute a redistribution layer (RDL) structure. For example, the bond pads 114a on package substrate and the metal interconnect structures 114b can include one or more film layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the scope of the disclosure.

[0051] The package substrate 110 can also include a passivation layer 110a on package substrate on a wafer-side surface of the dielectric layer 114 on package substrate. The passivation layer 110a on package substrate can partially cover the bond pads 114a on package substrate. The passivation layer 110a on package substrate can include silicon oxide, silicon nitride, low dielectric constant (low-k) dielectric materials such as carbon-doped oxides, extremely low-k dielectric materials such as porous carbon doped silicon dioxide, combinations thereof, or other suitable materials.

[0052] The dielectric layer 116 under package substrate can be formed on a lower surface of the core 112. The dielectric layer 116 under package substrate can also include multiple film layers and, in particular, can include a build-up film (e.g., ABF). The dielectric layer 116 under package substrate can also include organic materials such as polymeric materials. In particular, the dielectric layer 116 under package substrate can include dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are within the scope of the disclosure.

[0053] The under-encapsulation substrate dielectric layer 116 can include one or more under-encapsulation substrate bond pads 116a on the board side surface of the under-encapsulation substrate dielectric layer 116. In particular, the under-encapsulation substrate bond pads 116a can be exposed from the board side surface of the under-encapsulation substrate dielectric layer 116. The under-encapsulation substrate dielectric layer 116 can also include one or more metal interconnect structures 116b. The metal interconnect structures 116b can be connected to the under-encapsulation substrate bond pads 116a and the through-vias 112a in the core 112. The metal interconnect structures 116b can include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The metal interconnect structures 116b can constitute a redistribution layer (RDL) structure. For example, the under-encapsulation substrate bond pads 116a and the metal interconnect structures 116b can include one or more film layers and can include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the scope of the disclosure.

[0054] The encapsulation substrate 110 can also include an under-encapsulation substrate passivation layer 110b on the board side surface of the under-encapsulation substrate dielectric layer 116. The under-encapsulation substrate passivation layer 110b can partially cover the under-encapsulation substrate bond pads 116a. The under-encapsulation substrate passivation layer 110b can include silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, ultra-low-k dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials.

[0055] The encapsulation structure 100 can also include a ball grid array (BGA) 180 including a plurality of solder balls 181 formed on the board side surface of the under-encapsulation substrate dielectric layer 116. The solder balls 181 can allow the encapsulation structure 100 to be securely mounted on and electrically coupled to a substrate such as a printed circuit board (PCB). The solder balls 181 can respectively contact the under-encapsulation substrate bond pads 116a. Thus, the solder balls 181 can be electrically connected to the on-encapsulation substrate bond pads 114a through the metal interconnect structures 116b, the through-vias 112a, and the metal interconnect structures 114b.

[0056] Semiconductor module 120 may include an interposer 10 and one or more semiconductor dies 140 (141, 142) located on the interposer 10. Semiconductor module 120 is not limited to any particular configuration. For example, semiconductor module 120 may include a flip chip-chip scale package (FC-CSP) design, a chip-on-wafer-on-substrate (CoWoS®) design, an integrated fan-out (InFO_oS) design, etc. In at least one embodiment, the interposer 10 may be omitted from semiconductor module 120, in which case the semiconductor dies 140 may be directly attached to package substrate 110.

[0057] Semiconductor module 120 can be bonded and electrically coupled to package substrate 110 via C4 bumps 121 on the board-side surface of intermediate 10. Specifically, C4 bumps 121 can be formed on lower bonding pads 14a on the board-side surface of intermediate 10. Solder reflow, compression bonding, thermocompression bonding, etc., can be used to bond C4 bumps 121 to upper bonding pads 114a of package substrate 110. In at least one embodiment, C4 bumps 121 may include an underbump metallurgy (UBM) layer located on the lower bonding pad 14a and the upper bonding pad 114a of package substrate. C4 bumps 121 may also include contact pads (e.g., copper / nickel contact pads) on the UBM layer and solder bumps (e.g., SnAg solder bumps) on the contact pads.

[0058] like FIG. 1A As shown, the packaging substrate 110 may have a length in the x-direction, which may be greater than the length of the semiconductor module 120 in the x-direction. The packaging substrate 110 may also have a width in the y-direction, which may be greater than the width of the semiconductor module 120 in the y-direction.

[0059] An underfill layer 119 may be formed on and around the package substrate 110 below and around the semiconductor module 120. The underfill layer 119 may also be formed around the C4 bump 121. Thus, the underfill layer 119 securely fixes the semiconductor module 120 to the package substrate 110. The underfill layer 119 may be formed of an epoxy-based polymeric material.

[0060] The interposer 10 need not be limited to any particular material or configuration. For example, the interposer 10 can include an organic material (e.g., a dielectric polymer), an inorganic material (e.g., silicon), a glass substrate, etc. In at least one embodiment, the interposer 10 can include a plurality of polymer layers 12 and a plurality of redistribution layers 12a in an alternating stack. The number of polymer layers 12 and / or the number of redistribution layers 12a in the interposer 10 is not limited by this disclosure.

[0061] For example, in at least one embodiment, the polymer layers 12 can include polyimide (PI), epoxy, acrylic, phenol formaldehyde, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the redistribution layers 12a can include a conductive material. The conductive material can include a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals.

[0062] The redistribution layers 12a can include a metal connection structure, that is, a metal structure that provides electrical connections between nodes in the structure. The redistribution layers 12a can include a metal seed layer and a metal fill material on the metal seed layer. For example, the metal seed layer can include a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer can have a thickness in a range of 50 nm to 500 nm, and the copper seed layer can have a thickness in a range of 50 nm to 500 nm. The metal fill material for the redistribution layers 12a can include copper, nickel, or copper and nickel. Other suitable metal fill materials are within the scope of the disclosure. The thickness of the metal fill material deposited for each redistribution layer 12a can be in a range of 2 microns to 40 microns, such as 4 microns to 10 microns, although lesser or greater thicknesses can also be used.

[0063] In at least one embodiment, the redistribution layers 12a can include a plurality of traces and a plurality of vias connecting the plurality of traces to one another. The traces can be located on the polymer layers 12, respectively, and can extend in an x-direction (a first horizontal direction) and a y-direction (a second horizontal direction) on the upper surfaces of the polymer layers 12.

[0064] An upper passivation layer 13 can be formed on the wafer side surface of the interposer 10. The upper passivation layer 13 can include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials.

[0065] One or more upper bond pads 13a can be formed in an upper passivation layer 13 on a wafer-side surface of the interposer 10. The upper passivation layer 13 can at least partially cover the upper bond pads 13a. That is, the upper bond pads 13a can be at least partially exposed to the wafer-side surface of the interposer 10. The upper bond pads 13a can be connected to the redistribution layer 12a. For example, the upper bond pads 13a can include one or more film layers, and can include a metal, a metal alloy, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplated scope of the disclosure.

[0066] A lower passivation layer 14 can be formed on a board-side surface of the interposer 10. The lower passivation layer 14 can also include silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, ultra-low-k dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials.

[0067] Lower bond pads 14a can be located in the lower passivation layer 14, and electrically connected to the redistribution layer 12a. The lower passivation layer 14 can at least partially cover the lower bond pads 14a. That is, the lower bond pads 14a can be at least partially exposed to the board-side surface of the interposer 10. For example, the lower bond pads 14a can include one or more film layers, and can include a metal, a metal alloy, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplated scope of the disclosure.

[0068] A semiconductor die 140 can be attached to an upper surface of the interposer 10. The semiconductor die 140 can include a die bond film 145 on a frontside of the semiconductor die 140. For example, the die bond film 145 can be formed of silicon dioxide, silicon nitride, silicon carbonitride, etc. The semiconductor die 140 can also include die bond pads 145a located in the die bond film 145. For example, the die bond pads 145a can include one or more film layers, and can include a metal, a metal alloy, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials that can be used for the die bond film 145 and the die bond pads 145a are within the contemplated scope of the disclosure.

[0069] In at least one embodiment, the semiconductor dies 140 can be attached to the interposer 10 through hybrid bonding. Hybrid bonding can include metal-metal bonds between the die bond pads 145a and the upper bond pads 13a of the interposer 10. Hybrid bonding can also include dielectric-dielectric bonds between the die bond film 145 and the upper passivation layer 13 of the interposer 10.

[0070] Alternative structures (not shown) can be used to attach the semiconductor dies 140 to the interposer 10. In particular, the semiconductor dies 140 can be attached to the interposer 10 through a plurality of micro-bumps. In such embodiments, a module underfill layer can be formed on the interposer 10, around the micro-bumps, and under and around the semiconductor dies 140.

[0071] The plurality of semiconductor dies 140 can include a first semiconductor die 141 and a second semiconductor die 142. Although the semiconductor module 120 is shown as including a particular number of semiconductor dies 140 having a particular configuration and particular dimensions, the number of semiconductor dies 140, the dimensions of the semiconductor dies 140, and the configuration of the semiconductor dies 140 are not limited to any particular number, dimensions, and configuration. In particular, the semiconductor module 120 can include any number, dimensions, and configuration of semiconductor dies 140.

[0072] Generally, the thickness of each semiconductor die 140 in the z-direction can be substantially the same. Thus, the upper surface of each of the first semiconductor die 141 and the second semiconductor die 142 can be substantially coplanar (e.g., formed in the same x-y plane) and collectively referred to as the semiconductor die upper surface 140a.

[0073] For example, each semiconductor die 140 can include a single-die structure, a system on chip (SoC) die, or a system integrated on chip (SoIC) die, and can be implemented by a chip on wafer on substrate (CoWoS) technology or an integrated fan-out (InFO_oS) technology. In particular, each semiconductor die 140 can include a semiconductor chip or chiplet for a high performance computing (HPC) application, an artificial intelligence (AI) application, and a 5G cellular network application, a logic die (e.g., a processor for a mobile application, a microcontroller, etc.), or a memory die (e.g., a high bandwidth memory (HBM) die, a hybrid memory cube (HMC), a dynamic random access memory (DRAM) die, a Wide I / O die, a magnetoresistive random access memory (M-RAM) die, a resistive random access memory (R-RAM) die, a NAND die, a static random access memory (SRAM), etc.), a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, a field-programmable gate array (FPGA) chip, a networking chip, an application-specific integrated circuit (ASIC) chip, an artificial intelligence / deep neural network (DNN) chip, etc.semiconductor die 141 can include a primary die (e.g., a SOC die), and the second semiconductor die 142 can include an ancillary die (e.g., a memory / SOC die, an HBM die, etc.). Other suitable semiconductor dies are within the scope of the disclosure.

[0074] The semiconductor module 120 can also include an upper molding layer 127 formed around the semiconductor dies 140. The upper molding layer 127 can have an outer sidewall that is substantially aligned with the outer sidewall of the interposer 10. The upper molding layer 127 can also have an upper surface that is substantially uniform (e.g., planar) and substantially coplanar with the upper surface 140a of the semiconductor dies 140. The upper molding layer 127 can be formed on the outer sidewall of each semiconductor die 140. The upper molding layer 127 can be bonded to the outer sidewall of each semiconductor die 140.

[0075] In at least one embodiment, the upper molding layer 127 can be formed from a curable material that can be cured to form a rigid solid structure. For example, the upper molding layer 127 can include an epoxy molding compound (EMC). In at least one embodiment, the upper molding layer 127 can include substantially similar material as the package underfill layer 119. In at least one embodiment, the upper molding layer 127 can include a polymeric material, and in particular an epoxy-based polymeric material. Other suitable molding materials can be used.

[0076] In at least one embodiment, the upper molding layer 127 can have a coefficient of thermal expansion (CTE) that is substantially similar to a coefficient of thermal expansion (CTE) of the interposer 10. In at least one embodiment, the upper molding layer 127 can include an additive material (e.g., a filler material added to a polymeric material) to improve properties (e.g., a thermal conductivity, a coefficient of thermal expansion, etc.) of the upper molding layer 127.

[0077] The reactive interface layer 150 can include a first reactive interface layer 151 located on the semiconductor die stack 120. In particular, the first reactive interface layer 151 can be formed on an upper surface of the upper molding layer 127 and an upper surface 140a of the semiconductor die 140. The first reactive interface layer 151 can cover substantially an entire upper surface of the semiconductor die stack 120. As shown, both ends of the first reactive interface layer 151 can be substantially aligned with opposing lateral walls of the upper molding layer 127. The first reactive interface layer 151 can include one or more metals or metal alloys. In at least one embodiment, the first reactive interface layer 151 can include one or more of gallium, indium, and nickel. In at least one embodiment, the first reactive interface layer 151 can include an alloy of gallium, indium, and nickel. In at least one embodiment, the first reactive interface layer 151 can include a nickel coating. Other materials can be used for the first reactive interface layer 151. FIG. 1A

[0078] The composite thermal interface material layer 170 can be formed on the first reactive interface layer 151. The first reactive interface layer 151 can help to enhance adhesion (e.g., between the composite thermal interface material layer 170 and the semiconductor die stack 120) and reliability of the composite thermal interface material layer 170. The composite thermal interface material layer 170 can cover substantially an entire first reactive interface layer 151. In at least one embodiment, the composite thermal interface material layer 170 can contact an entire upper surface of the first reactive interface layer 151.

[0079] The composite thermal interface material layer 170 can be formed on the semiconductor die stack 120 to dissipate thermal energy generated during operation of the package structure 100 (e.g., operation of the semiconductor die 140). The composite thermal interface material layer 170 can have a low bulk thermal impedance and a high thermal conductivity. The composite thermal interface material layer 170 can be composed of a metal material in a polymeric matrix (e.g., an organic polymer). The polymer can include a silicone-based polymeric material or an epoxy-based polymeric material. In at least one embodiment, the polymer can include one or more of polyimide, polyethylene terephthalate, polypropylene, polycarbonate, polyether sulfone, polytetrafluoroethylene, polyurethane, etc. ​

[0080] In at least one embodiment, the composite thermal interface material layer 170 can include a polymer and a liquid metal (e.g., gallium, indium, etc.) embedded in the polymer. In at least one embodiment, the composite thermal interface material layer 170 can include a polymer and at least two types of filler materials having different sizes and / or shapes. In particular, the composite thermal interface material layer 170 can include a polymer, a first filler having a first size located in the polymer, and a second filler having a second size smaller than the first size located in the polymer.

[0081] In at least one embodiment, the composite thermal interface material layer 170 can include a polymer and a metallic strip filler and a particulate filler located in the polymer. The metallic strip filler can include a metal having a melting point lower than 100 °C. For example, the metallic strip filler can include one or more metals (liquid metal), such as indium, gallium, tin, bismuth, etc. In at least one embodiment, the particulate filler can include oxide particles and / or nitride particles. The oxide particles can include metal oxide particles, such as ZnO x , AIO x , AgO x , etc. The nitride particles can include metal nitride particles, such as AIN x , BN x , etc. In at least one embodiment, the composite thermal interface material layer 170 can be composed of a liquid metal composite, where the liquid metal composite is composed of a polymer and a gallium-based strip filler and zinc oxide (ZnO x ) particulate filler located in the polymer (e.g., polymer matrix). Other materials can be used for the composite thermal interface material layer 170 within the scope of the disclosure contemplated.

[0082] In at least one embodiment, the amount of the polymer in the composite thermal interface material layer 170 (by weight) can be less than the total amount of the metallic strip filler and the particulate filler in the composite thermal interface material layer 170. In at least one embodiment, the amount of the polymer in the composite thermal interface material layer 170 can be in a range of 10 wt% to 60 wt%. In at least one embodiment, the amount of the metallic strip filler in the composite thermal interface material layer 170 can be in a range of 30 wt% to 90 wt%. In at least one embodiment, the amount of the particulate filler in the composite thermal interface material layer 170 can be less than the amount of the metallic strip filler in the composite thermal interface material layer 170. In at least one embodiment, the amount of the particulate filler in the composite thermal interface material layer 170 can be in a range of 10 wt% to 70 wt%. Other suitable amounts of the polymer, the metallic strip filler, and the particulate filler can be used.

[0083] For example, the composite thermal interface material layer 170 can be formed by mixing metal strip fillers and granular fillers into the polymer. Specifically, materials primarily composed of liquid metals (e.g., gallium, indium, etc.) can be dispersed into particles (e.g., metal strip filler particles). These particles can be coated with an oxide or nitride coating. In at least one embodiment, the particles can be coated with an oxide by a native oxide shell formation process. Then, appropriate amount control can be used to mix the coated particles into the polymer.

[0084] A package cover 130 may be located above the semiconductor module 120 and connected to the package substrate 110. The package cover 130 may include a package cover portion 130p, which is formed on a composite thermal interface material layer 170 above the semiconductor module 120. The package cover 130 may also include a package cover step portion 130s projecting downward from the bottom surface 135 of the package cover portion 130p. The package cover step portion 130s may be integrally formed with the package cover portion 130p. The package cover step portion 130s may have a width W130s greater than the width of the semiconductor module 120 (e.g., the distance between the outer sidewalls of the upper molding layer 127). The composite thermal interface material layer 170 may be compressed between the package cover step portion 130s and the semiconductor module 120.

[0085] The reactive interface layer 150 may include a second reactive interface layer 152 located on the encapsulation cap step portion 130s. The second reactive interface layer 152 may have a width substantially the same (in the x-direction) as the first reactive interface layer 151. FIG. 1A As shown, the width of the second reactive interface layer 152 may be smaller than the width W130s of the encapsulation cap step portion 130s. In at least one embodiment, the width of the second reactive interface layer 152 may be substantially the same as the width W130s of the encapsulation cap step portion 130s. The second reactive interface layer 152 may be substantially aligned with the first reactive interface layer 151.

[0086] The second reactive interface layer 152 can contact substantially the entire upper surface of the composite thermal interface material layer 170. The second reactive interface layer 152 can enhance the adhesion (e.g., the adhesion between the composite thermal interface material layer 170 and the encapsulation cap step portion 130s) and reliability of the composite thermal interface material layer 170. FIG. 1AAs shown, the two ends of the second reactive interface layer 152 can be substantially aligned with the opposite sidewalls of the composite thermal interface material layer 170. The second reactive interface layer 152 can be formed of the same or different material as the first reactive interface layer 151. The second reactive interface layer 152 can include one or more metals or metal alloys. In at least one embodiment, the second reactive interface layer 152 can include one or more of gallium, indium, and nickel. In at least one embodiment, the second reactive interface layer 152 can include an alloy of gallium, indium, and nickel. In at least one embodiment, the second reactive interface layer 152 can include a nickel coating. Other suitable materials can be used for the second reactive interface layer 152.

[0087] The package lid 130 can also include a package lid foot portion 130a located at the outer periphery of the package lid plate portion 130p. The package lid foot portion 130a can be integrally formed with the package lid plate portion 130p. The package lid foot portion 130a can be secured to the package substrate 110 by an adhesive layer 160.

[0088] For example, the package lid 130 can be formed of a metal, ceramic, or polymeric material. In at least one embodiment, the material of the package lid 130 can include copper with a nickel coating surface (e.g., in addition to the second reactive interface layer 152). The nickel coating surface can have a thickness in the range of 1 µm to 10 µm. The package lid plate portion 130p can have a plate shape (e.g., planar shape) and be substantially parallel to the upper surface of the package substrate 110. For example, the package lid plate portion 130p can extend in the x-y plane of the package substrate 110. The package lid plate portion 130p can include an outer sidewall that is substantially aligned with the outer sidewall of the package lid foot portion 130a. The center of the package lid plate portion 130p can be substantially aligned with the center of the semiconductor module 120 in the z-direction. The upper surface of the package lid plate portion 130p can be substantially parallel to the bottom surface 135 of the package lid plate portion 130p. FIG. 1A

[0089] The adhesive layer 160 can be formed on the package substrate 110 proximate to the sidewall of the semiconductor module 120. The adhesive layer 160 can bond the package lid foot portion 130a to the package substrate 110. The thickness of the adhesive layer 160 can be in the range of 50 µm to 200 µm. For example, the adhesive layer 160 can include a silicone adhesive (e.g., containing alumina, zinc oxide, resin, etc.) or an epoxy adhesive. Other suitable adhesives can be used. The adhesive layer 160 can contact the backside metal layer or the dished upper surface of the upper molding material layer.

[0090] ​The package structure 100 can also include an encapsulant 200 formed around the composite thermal interface material layer 170. The encapsulant 200 can also be formed around the first reactive interface layer 151 and the second reactive interface layer 152. In at least one embodiment, the encapsulant 200 can inhibit (e.g., prevent) oxidation of the composite thermal interface material layer 170, the first reactive interface layer 151, and the second reactive interface layer 152.

[0091] As shown, the encapsulant 200 can also be formed around the package cap step portion 130s and the semiconductor module 120. The encapsulant 200 can also be formed around the package underfill layer 119. In at least one embodiment, a top end of the encapsulant 200 can contact a bottom surface 135 of the package cap plate portion 130p. In at least one embodiment, a bottom end of the encapsulant 200 can contact the package substrate 110. In at least one embodiment, the encapsulant 200 can extend continuously between the bottom surface 135 of the package cap plate portion 130p and the package substrate 110. FIG. 1B

[0092] The encapsulant 200 can be composed of a material substantially similar to that of the molding layer 127 or the package underfill layer 119. In at least one embodiment, the encapsulant 200 can be formed of an epoxy-based polymeric material. In at least one embodiment, the encapsulant 200 can include one or more of a silicone encapsulant, a polyurethane encapsulant, an acrylic encapsulant, a fluoropolymer encapsulant, etc. Other suitable materials can be used for the encapsulant 200.

[0093] One or more surface mount devices (SMDs) 190 can also be located on the wafer side surface of the package substrate 110 under the package cap 130. The surface mount devices 190 can be located on the package substrate 110 between the package cap leg portion 130a and the semiconductor module 120. In at least one embodiment, the surface mount devices 190 can be located substantially equidistantly (e.g., in the x-direction) between the interposer 10 of the semiconductor module 120 and the package cap leg portion 130a. The surface mount devices 190 can be attached to the package substrate 110 by surface mount technology (SMT). The surface mount devices 190 can be bonded to one or more package substrate on-bond pads 114a, thereby electrically connected to metal interconnect structures 114b in the package substrate on-dielectric layer 114. Thus, the surface mount devices 190 can be electrically coupled to the semiconductor die 140 through the package substrate 110 and the interposer 10.

[0094] ​By way of example, the surface mount components 190 can include integrated circuits, passive components such as resistors, capacitors, and inductors, active components such as two-terminal devices, diodes, and three-terminal devices, and electromechanical devices such as switches / relays, connectors, and micro-motors. In at least one embodiment, the surface mount components 190 can include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), rectifiers, and voltage regulators for power management applications.

[0095] Referring again to FIG. 1C The encapsulation lid step portion 130s can have a thickness T130s that is less than the thickness T130p of the encapsulation lid plate portion 130p. In at least one embodiment, the thickness T130s of the encapsulation lid step portion 130s can be in a range of 10% to 50% of the thickness T130p of the encapsulation lid plate portion 130p.

[0096] The thickness T170 of the composite thermal interface material layer 170 can be in a range of 75 µm to 450 µm. The thickness T151 of the first reactive interface layer 151 can be in a range of 5 µm to 50 µm. The thickness T152 of the second reactive interface layer 152 can be substantially the same as the thickness T151 of the first reactive interface layer 151. The thickness T152 of the second reactive interface layer 152 can also be in a range of 5 µm to 50 µm.

[0097] The bond line thickness (BLT) (e.g., the distance between the encapsulation lid 130 and the semiconductor module 120) can be equal to the thickness (T151) of the first reactive interface layer 151, plus the thickness (T170) of the composite thermal interface material layer 170, plus the thickness (T152) of the second reactive interface layer 152. In at least one embodiment, the bond line thickness (BLT) can be in a range of 85 µm to 550 µm. In at least one embodiment, T151 + T152 ≤ 70% of the BLT.

[0098] Referring again to FIG. 1Dsealant 200 can have a width W200 (a first width) at the composite thermal interface material layer 170 and at the semiconductor module 120. The width W200 of the sealant 200 can be in a range from 50 pm to 500 pm. The sealant 200 can contact sidewalls of the composite thermal interface material layer 170 and sidewalls of the semiconductor module 120 (e.g., sidewalls of the upper molding layer 127). The sealant 200 can also contact an end of the first reactive interface layer 151 and an end of the second reactive interface layer 152. Thus, the sealant 200 can form a substantially air-tight seal around the composite thermal interface material layer 170 and inhibit (e.g., prevent) oxidation of the composite thermal interface material layer 170.

[0099] The sealant 200 can include a sealant upper portion 200u formed on one side of the package cap step portion 130s. The sealant upper portion 200u can contact an entire sidewall of the package cap step portion 130s. The sealant upper portion 200u can also contact the bottom surface 135 of the package cap plate portion 130p. The sealant upper portion 200u can have a width W200u (a second width) that is less than the width W200 of the sealant 200. In at least one embodiment, the width W200u of the sealant upper portion 200u can be at least 10% less than the width W200 of the sealant 200. The sealant upper portion 200u can also have a thickness T200u that is greater than the thickness T130s of the package cap step portion 130s. In at least one embodiment, the thickness T200u of the sealant upper portion 200u can be at least 10% greater than the thickness T130s of the package cap step portion 130s.

[0100] Referring again to FIG. 2 The sealant 200 can include a sealant bottom portion 200b on the peripheral portion 119o of the package underfill layer 119. The width of the sealant 200 can decrease in a direction toward the sealant bottom portion 200b. In at least one embodiment, the sealant bottom portion 200b can have a width W200b (a third width) that is less than or equal to the width W200 of the sealant 200.

[0101] The sealant bottom portion 200b can contact substantially an entire upper surface of the peripheral portion 119o of the package underfill layer 119. In this case, the sealant bottom portion 200b can contact the package substrate upper passivation layer 110a. In at least one embodiment, the sealant bottom portion 200b can only contact a portion (e.g., an uppermost portion) of the peripheral portion 119o of the package underfill layer 119. In at least one embodiment, the width W200b of the sealant bottom portion 200b can be less than or equal to the width W119o of the peripheral portion 119o of the underfill layer 119.

[0102] FIG. 2is a schematic diagram of a composite thermal interface material layer 170 in a package structure 100 according to one or more embodiments. As shown in FIG. 3 The composite thermal interface material layer 170 can include metal strip fillers 172 (e.g., metal-based fillers including liquid metal such as gallium) and particulate fillers 173 embedded in a polymer 171, a first reactive interface layer 151, and a second reactive interface layer 152, as shown. The metal strip fillers 172 can include substantially oblong-shaped particles (e.g., liquid metal particles). The particulate fillers 173 can include substantially spheroid-shaped particles or substantially oval-shaped particles. The particulate fillers 173 can have an average particle size that is less than the average particle size of the metal strip fillers. In at least one embodiment, the average particle size of the particulate fillers 173 can be at least 50% less than the average particle size of the metal strip fillers 172.

[0103] In at least one embodiment, the metal strip fillers 172 in the polymer 171 can be bonded to the first reactive interface layer 151 and the second reactive interface layer 152. In at least one embodiment, the metal strip fillers 172 can react with the first reactive interface layer 151 (e.g., a nickel-based coating) and the second reactive interface layer 152 (e.g., a nickel-based coating) to form intermetallic compounds (IMCs) 172a. The intermetallic compounds (IMCs) 172a can help bond the composite thermal interface material layer 170 to the first reactive interface layer 151 and the second reactive interface layer 152.

[0104] FIG. 3 is a top-down schematic diagram of a package structure 100 according to one or more embodiments. For ease of understanding, FIG. 1A The package lid portion 130p and the package lid step portion 130s (including the second reactive interface layer 152) are omitted in FIG. 3 is a vertical cross-sectional schematic diagram along FIG. 3 the center line A-A’.

[0105] As shown in FIG. 4 The package substrate 110 can have a substantially square or rectangular shape. The semiconductor module 120 can have a substantially square or rectangular shape similar to that of the package substrate 110. The package lid foot portion 130a can be substantially frame-shaped. The width of the package lid foot portion 130a can be substantially uniform around the entire package lid foot portion 130a. The package lid foot portion 130a can be continuously formed around the semiconductor module 120 and the surface mount component 190. The distance between the package lid foot portion 130a and the semiconductor module 120 can be substantially uniform around the outer periphery of the semiconductor module 120.

[0106] The surface mount components 190 can be formed on both sides of the semiconductor module 120. The encapsulant 200 can be formed around the entire periphery of the composite thermal interface material layer 170 and the entire periphery of the semiconductor module 120. The width W200 of the encapsulant 200 can be substantially uniform around the entire periphery of the composite thermal interface material layer 170 and the entire periphery of the semiconductor module 120. The distance between the encapsulant 200 and the surface mount components can be substantially uniform on both sides of the semiconductor module 120.

[0107] FIG. 4 is a top view schematic of a package cap portion 130p according to one or more embodiments. The position of the encapsulant 200 relative to the package cap step portion 130s and the position of the encapsulant upper portion 200u are indicated in FIG. 4 by shading.

[0108] As shown in FIG. 3 , the center of the second reactive interface layer 152 can be substantially aligned with the center of the package cap step portion 130s. The shape of the second reactive interface layer 152 can be substantially the same as the shape of the first reactive interface layer 151 (see FIG. 5A to FIG. 5H ). Thus, the entire outer edge of the second reactive interface layer 152 can be coextensive with the entire outer edge of the first reactive interface layer 151.

[0109] Further, the shape of the package cap step portion 130s can be substantially the same as the shape of the second reactive interface layer 152. The outer sidewall of the encapsulant 200 can be substantially aligned with the outer sidewall of the package cap step portion 130s and around the entire periphery of the package cap step portion 130s. In addition, the width W200u of the encapsulant upper portion 200u can be substantially uniform around the entire periphery of the package cap step portion 130s.

[0110] FIG. 5A Various intermediate structures in a method of forming the package structure 100 are shown according to one or more embodiments. FIG. 5B is a vertical cross-sectional view schematic of an intermediate structure including a package substrate 110 having a package substrate upper bond pad 114a and a package substrate lower bond pad 116a according to one or more embodiments. The package substrate 110 can be provided including a core 112, a package substrate upper dielectric layer 114, and a package substrate lower dielectric layer 116.

[0111] For example, the package-on-pad 114a can be formed on the uppermost dielectric layer of the package-on-dielectric layers 114 on the package substrate. The package-on-pad 114a can be formed to contact the metal interconnect structure 114b. The package-on-pad 114a can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the upper surface of the package-on-dielectric layers 114 on the package substrate. The metal layer can then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the package-on-pad 114a. Other suitable metal layer materials and etching processes can be within the scope of the disclosure.

[0112] For example, the package-under-pad 116a can be formed on the lowermost dielectric layer of the package-under-dielectric layers 116 on the package substrate. The package-under-pad 116a can be formed to contact the metal interconnect structure 116b. The package-under-pad 116a can be formed in a similar manner as the package-on-pad 114a (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0113] After formation, the package-on-pad 114a and the package-under-pad 116a can be optionally subjected to a surface roughening process (e.g., a copper zarazara treatment). In the surface roughening process, a microetching solution of organic acids can be used to etch the surface (e.g., copper surface) of the package-on-pad 114a and the surface (e.g., copper surface) of the package-under-pad 116a to create a super-roughened surface (e.g., copper surface). The uniquely-roughened copper surface topography of the package-on-pad 114a and the package-under-pad 116a can help to achieve high copper-to-resin adhesion.

[0114] The package-on-passivation 110a and the package-under-passivation 110b can then be formed on the package-on-pad 114a and the package-under-pad 116a, respectively. In at least one embodiment, the package-on-passivation 110a can include a solder resist layer (e.g., a polymeric material), which is also referred to as a solder mask layer. The package-on-passivation 110a can also be referred to as an upper solder resist layer 110a, and the package-under-passivation 110b can also be referred to as a lower solder resist layer 110b.

[0115] The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied concurrently. For example, the passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied in the form of a liquid photo-imageable film. For example, the liquid photo-imageable film can be applied by silk-screening or by spraying the liquid photo-imageable film onto the surface of the package substrate 110. The liquid photo-imageable film can be applied over the package substrate over-bond pads 114a and the package substrate under-bond pads 116a. Alternatively, the passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied in the form of a dry-film photo-imageable film, which can be vacuum-laminated to the surface of the package substrate 110 and over the package substrate over-bond pads 114a and the package substrate under-bond pads 116a, respectively. Additionally or alternatively, the passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques.

[0116] The passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied to have a thickness that is slightly greater than the thickness of the package substrate over-bond pads 114a and the package substrate under-bond pads 116a, respectively. Alternatively, the passivation layer 110a over the package substrate and the passivation layer 110b under the package substrate can be applied to have an upper surface that is substantially coplanar with the upper surface of the package substrate over-bond pads 114a and the package substrate under-bond pads 116a, respectively.

[0117] Then, openings O 110a can be formed in the passivation layer 110a over the package substrate to expose the upper surface of the package substrate over-bond pads 114a. Openings O 110b can be formed in the passivation layer 110b under the package substrate to expose the upper surface of the package substrate under-bond pads 116a. For example, the openings O 110a and O 110b may be formed using photolithography processes. In at least one embodiment, the openings O 110a and O 110b may be formed in different photolithography processes.

[0118] The openings O 110aThe photolithography process (e.g., multiple processes) may include: forming a patterned photoresist mask (not shown) on a passivation layer 110a on a package substrate, and etching (e.g., wet etching, dry etching, etc.) the upper surface of the passivation layer 110a on the package substrate exposed through openings in the photoresist mask. Subsequently, the photoresist mask can be removed by ashing, dissolving, or by consuming the photoresist mask during the etching process.

[0119] Used to form an opening O 110b The photolithography process (e.g., multiple processes) may include: forming a patterned photoresist mask (not shown) on the passivation layer 110b of the package substrate, and etching (e.g., wet etching, dry etching, etc.) the upper surface of the passivation layer 110b of the package substrate exposed from the openings in the photoresist mask. Subsequently, the photoresist mask can be removed by ashing, dissolving, or by consuming the photoresist mask during the etching process.

[0120] An opening O is formed in the passivation layer 110a on the packaging substrate. 110a And an opening O is formed in the passivation layer 110b under the packaging substrate. 110b Subsequently, the passivation layer 110a (upper solder resist layer) on the packaging substrate and the lower passivation layer 110b (lower solder resist layer) on the packaging substrate can be cured, such as by thermal curing or ultraviolet (UV) curing.

[0121] FIG. 5C A vertical cross-sectional schematic diagram of an intermediate structure according to one or more embodiments is shown, wherein a semiconductor module 120 may be mounted on a package substrate 110. For example, the semiconductor module 120 may be mounted on the package substrate 110 by a flip chip bonding (FCB) process. The semiconductor module 120 may be positioned on the package substrate 110, for example, by a pick-and-place (PNP) machine. Then, a C4 bump 121 on the semiconductor module 120 may be lowered onto a package substrate bonding pad 114a of the package substrate 110 and heated to melt and fuse the C4 bump 121 to the package substrate bonding pad 114a.

[0122] FIG. 5C A vertical cross-sectional schematic diagram of an intermediate structure according to one or more embodiments is shown, wherein a package bottom filler layer 119 may be formed on a package substrate 110. The package bottom filler layer 119 may be formed of an epoxy-based polymeric material. FIG. 5DAs shown, the package underfill layer 119 can be formed (e.g., injected) under and around the semiconductor die 120 and C4 bumps 121 of the package substrate 110. The package underfill layer 119 can then be cured, for example, in a box oven at a temperature range from 120 °C to 180 °C for about 60 minutes to 120 minutes to provide the package underfill layer 119 with sufficient rigidity and mechanical strength.

[0123] FIG. 5E A vertical cross-sectional schematic of an intermediate structure according to one or more embodiments is shown, in which a surface mount device (SMD) 190 can be mounted on the package substrate 110. The surface mount device 190 can include bond pads (not shown) that can be bonded to the package substrate on-bond pads 114a of the package substrate 110. The surface mount device 190 can be mounted by surface mount technology (SMT). Solder paste (e.g., a mixture of tiny solder balls (e.g., SnAgCu) and flux) can be applied to the package substrate on-bond pads 114a by a stencil or a screen. An electromechanical pick-and-place (PnP) machine can then be used to pick up the surface mount device 190 (e.g., a resistor, a capacitor, an integrated circuit (IC)) and place them accurately onto the solder paste on the package substrate on-bond pads 114a. The package substrate 110 with the placed surface mount device 190 can then be passed through a reflow oven so that the solder paste melts and reflows, thereby forming solder joints between the surface mount device 190 and the package substrate on-bond pads 114a. An adhesive (not shown), similar to the adhesive layer 160, can be used as needed (in addition to the solder joints) to attach the surface mount device 190 to the package substrate 110.

[0124] FIG. 5F A vertical cross-sectional schematic of an intermediate structure according to one or more embodiments is shown, in which a composite thermal interface material (TIM) layer 170 can be formed on the semiconductor die 120. In at least one embodiment, the composite thermal interface material layer 170 can be placed onto the upper surface of the first reactive interface layer 151 on the semiconductor die 120 in a solid or semi-solid state. In at least one embodiment, the composite thermal interface material layer 170 can be dispensed onto the upper surface of the first reactive interface layer 151 on the semiconductor die 120 as a liquid in an uncured state. For example, an electromechanical dispenser (e.g., a pump-driven dispenser) can be used to dispense the uncured composite thermal interface material layer 170 using a metered amount of the uncured composite thermal interface material layer 170. Other suitable methods for dispensing the composite thermal interface material layer 170 can be used.

[0125] FIG. 1DA vertical cross-sectional schematic of the intermediate structure after the application of the encapsulant 200 and the adhesive layer 160 is shown in accordance with one or more embodiments. The encapsulant 200 and the adhesive layer 160 can be applied in the same process step or in different process steps.

[0126] The encapsulant 200 can be placed around the semiconductor die 120 in a solid or semi-solid state onto the upper surface of the package underfill layer 119. In at least one embodiment, the encapsulant 200 can be dispensed as a liquid in an uncured state onto the upper surface of the package underfill layer 119. The encapsulant 200 can be applied / dispensed in a central portion of the peripheral portion 119o of the package underfill layer 119. For example, the encapsulant 200 can be dispensed using a mechanical dispenser (e.g., a pump driven dispenser) that dispenses a metered amount of uncured encapsulant 200. In at least one embodiment, the encapsulant 200 can be dispensed using an auger valve dispensing tool.

[0127] The width (e.g., in the x-direction) of the encapsulant 200 applied / dispensed onto the upper surface of the package underfill layer 119 can be less than the width Wl 190 of the peripheral portion 119o of the package underfill layer 119 (see FIG. 1A ). The height of the encapsulant 200 applied / dispensed onto the upper surface of the package underfill layer 119 can be greater than the height of the first reactive interface layer 151. In at least one embodiment, the height of the encapsulant 200 applied / dispensed onto the upper surface of the package underfill layer 119 can be greater than the height of the composite thermal interface material layer 170. Other suitable methods for dispensing the encapsulant 200 can be used.

[0128] The adhesive layer 160 can also be dispensed using a mechanical dispenser (e.g., a pump driven dispenser, an automated dispensing tool) that dispenses a metered amount of adhesive material onto the package substrate 110. The dispenser can dispense the adhesive layer 160 in a frame shape around the semiconductor die 120. Upon application, the adhesive layer 160 can have sufficient rigidity to form a semi-solid bead on the surface of the package substrate 110. In at least one embodiment, the viscosity of each adhesive layer 160 upon application can be 50,000 centipoise (cp) or greater. The shape of the semi-solid bead can remain substantially unchanged between the time of application by the dispensing tool and the later time of attachment of the package lid 130. The frame shape position of the adhesive layer 160 can correspond to the position of the package lid foot portion 130a of the package lid 130 (see FIG. 5G ). Pressing the package lid 130 onto the adhesive layer 160 can deform the adhesive layer 160.

[0129] FIG. 5HA vertical cross-sectional schematic view showing an intermediate structure in accordance with one or more embodiments in which a package lid 130 can be attached to a package substrate 110 (e.g., mounted on the package substrate 110). The package substrate 110 can be placed on a rigid surface such as a board under support 500. The package lid 130 can then be positioned over the semiconductor die 120. In at least one embodiment, the package lid 130 can be positioned over the semiconductor die 120 by an electromechanical pick and place (PnP) machine.

[0130] The package lid 130 can be positioned over the semiconductor die 120 such that a center of the package lid step portion 130s is substantially aligned with a center of the semiconductor die 120. The package lid 130 can also be positioned over the semiconductor die 120 such that the package lid step portion 130s is positioned over the encapsulant 200. The package lid 130 can also be positioned over the semiconductor die 120 such that a package lid foot portion 130a of the package lid 130 can be substantially aligned with an adhesive layer 160 (e.g., a frame of adhesive material) formed on the package substrate 110.

[0131] The package lid 130 can then be lowered over the semiconductor die 120 and on the package substrate 110. A downward pressing force can then be applied to the package lid plate portion 130p. The downward pressing force can cause the package lid step portion 130s to compress and deform the composite thermal interface material layer 170 and the encapsulant 200. The downward pressing force can also cause the package lid foot portion 130a to compress and deform the adhesive layer 160.

[0132] In particular, the composite thermal interface material layer 170 can be deformed by the downward pressing force to flow over substantially the entire first reactive interface layer 151. In at least one embodiment, the composite thermal interface material layer 170 can be deformed to substantially fill a space between the first reactive interface layer 151 and the second reactive interface layer 152. The encapsulant 200 can be deformed by the downward pressing force to flow in a direction (shown by directional arrows) and around the package lid step portion 130s. The encapsulant 200 can also be deformed by the downward pressing force to flow along a direction toward the sidewall of the semiconductor die 120 and along a direction of a surface of the peripheral portion 119o of the package bottom fill layer 119. In at least one embodiment, the encapsulant 200 can be deformed to substantially surround the package lid step portion 130s, the composite thermal interface material layer 170, and the semiconductor die 120.

[0133] The package lid 130 can then be clamped to the package substrate 110 for a period of time to allow the composite thermal interface material layer 170, the encapsulant 200, and the adhesive layer 160 to cure (e.g., snap cure). The encapsulant 200 can cure to form a substantially air-tight seal around the composite thermal interface material layer 170. The adhesive layer 160 can cure to form a strong bond between the package substrate 110 and the package lid 130. For example, the package lid 130 can be clamped to the package substrate 110 by using a heat clamp module. The heat clamp module can apply a uniform force across the upper surface of the package lid portion 130p. In one or more embodiments, the heat clamp module can apply a downward pressing force on the package lid portion 130p.

[0134] FIG. 6 A vertical cross-sectional schematic of an intermediate structure according to one or more embodiments is shown, in which a ball grid array (BGA) 180 including a plurality of solder balls 181 can be formed on the package substrate 110. The plurality of solder balls 181 can be formed through openings O 110b on the package substrate lower bond pads 116a. For example, the solder balls 181 can be formed by an electroplating process. For example, the solder balls 181 can be formed such that they are located below the package lid foot portion 130a, and below and between the semiconductor module 120. The ball grid array (BGA) 180 including the plurality of solder balls 181 can allow the package structure 100 to be securely mounted (e.g., by surface mount technology (SMT)) on a substrate such as a printed circuit board, and electrically coupled to the substrate. The formation of the solder balls 181 can complete the formation of the package structure 100.

[0135] FIG. 7 A flowchart of a method of forming a package structure 100 according to one or more embodiments is shown. Step 610 includes attaching a semiconductor module to a package substrate. Step 620 includes forming a composite thermal interface material (TIM) layer on the semiconductor module. Step 630 includes forming an encapsulant around the composite thermal interface material layer. Step 640 includes attaching a package lid to the package substrate such that the package lid deforms the composite thermal interface material layer and the encapsulant, and such that the composite thermal interface material layer is in contact with a reactive interface layer on at least one of the semiconductor module or the package lid.

[0136] FIG. 7 A vertical cross-sectional schematic of a package structure 100 with a first alternative design according to one or more embodiments is shown. As FIG. 1A to FIG. 1DAs shown, in the first alternative design, the package structure 100 may include a first reactive interface layer 151. However, in the package structure 100 with the first alternative design, the second reactive interface layer 152 may be omitted. Therefore, in the first alternative design, the package cap step portion 130s can directly contact the composite thermal interface material layer 170. Using the first alternative design, with FIG. 8 Compared to the packaging structure, this reduces the number of process steps required to manufacture the packaging structure 100.

[0137] FIG. 8 This is a vertical cross-sectional schematic diagram of a packaging structure 100 having a second alternative design according to one or more embodiments. FIG. 1A to FIG. 1D As shown, in the second alternative design, the package structure 100 may include a second reactive interface layer 152. However, in the package structure 100 with the second alternative design, the first reactive interface layer 151 may be omitted. Therefore, in the second alternative design, the composite thermal interface material layer 170 may be directly formed on the upper surface 140a of the semiconductor die 140 and the upper surface of the upper molding layer 127. Using the second alternative design, with FIG. 9 Compared to the packaging structure, this reduces the number of process steps required to manufacture the packaging structure 100.

[0138] FIG. 9 This is a vertical cross-sectional schematic diagram of a packaging structure 100 having a third alternative design according to one or more embodiments. (See diagram below.) FIG. 9 As shown, in the third alternative design, the package cover portion 130p may include one or more openings 930h. After the package cover 130 is attached to the package substrate 110, the openings 930h allow access to the interior of the package structure 100. The package structure 100 may also include one or more plugs 900 that respectively fill the openings 930h. For example, the plugs 900 may be made of the same material as the sealant 200.

[0139] like FIG. 5A to FIG. 5H As shown, opening 930h may include a first opening 930h1 and a second opening 930h2, wherein the first opening 930h1 is on a first side of the semiconductor module 120, and the second opening 930h2 is on a second side of the semiconductor module 120 opposite to the first side. Plug 900 may include a first plug 901 located in the first opening 930h1 and a second plug 902 located in the second opening 930h2. In a third alternative design, sealant 200 may substantially fill the interior of the package structure 100. Therefore, sealant 200 can effectively form a substantially hermetically sealed area around the composite thermal interface material layer 170.

[0140] The package structure 100 with the third alternative design can be made by injecting the encapsulant 200 into the interior of the package structure 100 through the one or more openings 930h. Thus, the method of manufacturing the package structure 100 with the third alternative design can be different from the method of manufacturing the package structure 100 described above in FIG. 10 that the formation of the encapsulant 200 is after the package cap 130 is attached to the package substrate 110, instead of before the package cap 130 is attached to the package substrate 110. In particular, the encapsulant 200 can be injected into the one or more openings 930h while the interior of the package structure is vacuumed through the one or more openings 930h.

[0141] Thus, for example, the encapsulant 200 (e.g., in an uncured state) can be injected into the package structure 100 through the first opening 930hi while the interior of the package structure 100 is vacuumed through the second opening 930h2 to form the encapsulant 200 in the package structure 100. For example, the injection of the encapsulant 200 can be ended when the encapsulant 200 becomes visible in the second opening 930h2.

[0142] FIG. 10 is a vertical cross-sectional view of a package structure 100 with a fourth alternative design according to one or more embodiments. As shown in FIG. 1A to FIG. 10 , in the fourth alternative design, the package cap step portion 130s can include a plurality of recesses 130sR. In at least one embodiment, the plurality of recesses 130sR can be formed as a plurality of rows and columns constituting a two-dimensional array. The second reactive interface layer 152 can be formed in the plurality of recesses 130sR.

[0143] In manufacturing the package structure 100 with the fourth alternative design, when the package cap step portion 130s is pressed onto the composite thermal interface material layer 170, the composite thermal interface material layer 170 can be pressed into the plurality of recesses 130sR. In at least one embodiment, the composite thermal interface material layer 170 can substantially fill the plurality of recesses 130sR. With the fourth alternative design of the package structure 100, the surface area of the second reactive interface layer 152 can be significantly increased. Thus, the interfacial area between the composite thermal interface material layer 170 and the second reactive interface layer 152 can be significantly increased, and the adhesion between the package cap step portion 130s and the composite thermal interface material layer 170 can be significantly increased.

[0144] Please refer to FIG. 1A to FIG. 10The package structure 100 can include a package substrate 110, a semiconductor module 120 on the package substrate 110, a composite thermal interface material (TIM) layer 170 including a liquid metal in a polymer matrix on the semiconductor module 120, a package cap 130 on the composite TIM layer 170 and attached to the package substrate 110, and a reactive interface layer 150 in contact with the composite TIM layer 170 on at least one of the semiconductor module 120 or the package cap 130.

[0145] In an embodiment, the composite TIM layer 170 can further include a particulate filler in the polymer matrix. In an embodiment, the particulate filler can include a metal oxide particulate filler. In an embodiment, the reactive interface layer 150 can be on the semiconductor module 120 and the package cap 130. In an embodiment, the reactive interface layer 150 can include at least one of gallium (Ga), indium (In), or nickel (Ni). In an embodiment, the total thickness of the reactive interface layer 150 on the semiconductor module 120 and the reactive interface layer 150 on the package cap 130 can be less than or equal to 70% of the TIM layer 170 bondline thickness. In an embodiment, the package cap 130 can include a package cap step portion 130s and the reactive interface layer 150 can be on the package cap step portion 130s. In an embodiment, the package structure 100 can further include an encapsulant 200 around the semiconductor module 120, the composite TIM layer 170, and the package cap step portion 130s. In an embodiment, the encapsulant 200 can have a first width W200 at the composite TIM layer 170 and a second width W200u at the package cap step portion 130s that is less than the first width W200. In an embodiment, the package structure 100 can further include a package underfill layer 119 on the package substrate 110 and under and around the semiconductor module 120, where the encapsulant 200 can be on the package underfill layer 119. In an embodiment, the encapsulant 200 can have a third width W200b at the package underfill layer 119 that is less than or equal to the first width W200. In an embodiment, the third width W200b of the encapsulant 200 can be less than or equal to a width W119o of an outer portion 119o of the package underfill layer 119. In an embodiment, the package cap 130 can further include a bottom surface 135, the package cap step portion 130s can protrude from the bottom surface 135, and a thickness T200u of the encapsulant 200 in contact with the bottom surface 135 of the package cap 130 can be greater than a thickness T130s of the package cap step portion 130s.

[0146] Referring again to FIG. 1A to FIG. 10The method of forming the package structure 100 can include attaching the semiconductor die 120 to the package substrate 110, forming a composite thermal interface material (TIM) layer 170 on the semiconductor die 120, forming the encapsulant 200 around the composite thermal interface material layer 170, and attaching the package cap 130 to the package substrate 110 such that the package cap 130 deforms the composite thermal interface material layer 170 and the encapsulant 200, and such that the composite thermal interface material layer 170 can be in contact with the reactive interface layer 150 on at least one of the semiconductor die 120 or the package cap 130.

[0147] In an embodiment, the method can further include forming a package underfill layer 119 on the package substrate 110 under and around the semiconductor die 120, where forming the encapsulant 200 can include forming the encapsulant 200 on the package underfill layer 119 and around the semiconductor die 120. In an embodiment, attaching the package cap 130 to the package substrate 110 can include deforming the encapsulant 200 using the package cap 130 such that the encapsulant 200 contacts sidewalls of the semiconductor die 120 and a bottom surface of the package cap 130. In an embodiment, attaching the package cap 130 to the package substrate 110 can include deforming the encapsulant 200 using the package cap 130 such that an outer sidewall of the encapsulant 200 can be substantially aligned with an outer periphery of the package underfill layer 119. In an embodiment, the package cap 130 can include a package cap step portion 130s, and attaching the package cap 130 to the package substrate 110 can include deforming the encapsulant 200 using the package cap step portion 130s such that the encapsulant 200 can be formed around the package cap step portion 130s.

[0148] Referring again to ​ The package structure 100 can include a package substrate 110, a semiconductor die 120 including a first reactive interface layer 151 and located on the package substrate 110, a package cap 130 including a second reactive interface layer 152 and located on the semiconductor die 120, a composite thermal interface material (TIM) layer 170 located between the package cap 130 and the semiconductor die 120 and in contact with the first reactive interface layer 151 and the second reactive interface layer 152, where the composite thermal interface material layer 170 includes a polymer matrix 171, a metal-based filler 172, and a particulate filler 173 having a size smaller than the metal-based filler 172 in the polymer matrix 171, and an encapsulant 200 formed around the composite thermal interface material layer 170, in contact with an outer sidewall of the composite thermal interface material layer 170, and to form a hermetic seal around the composite thermal interface material layer 170.

[0149] The features of the above-described embodiments can be combined in any manner deemed appropriate by those skilled in the art. Those skilled in the art will appreciate that other embodiments can be devised and changes made to the described embodiments without departing from the spirit and scope of the application. Accordingly, the described embodiments are to be considered in all respects as illustrative and not restrictive.

Claims

1. A package structure, comprising: a package substrate; a semiconductor die on the package substrate; a composite thermal interface material layer comprising a liquid metal in a polymer matrix on the semiconductor die; a package cap on the composite thermal interface material layer and attached to the package substrate; and a reactive interface layer in contact with the composite thermal interface material layer on at least one of the semiconductor die or the package cap.

2. The package structure of claim 1, wherein the composite thermal interface material layer further comprises a particulate filler in the polymer matrix.

3. The package structure of claim 1, wherein the reactive interface layer is on the semiconductor die and the package cap.

4. The package structure of claim 3, wherein the package cap comprises a package cap step portion and the reactive interface layer is on the package cap step portion.

5. The package structure of claim 4, wherein the encapsulant has a first width at the composite thermal interface material layer and a second width at the package cap step portion that is less than the first width.

6. The package structure of claim 4, further comprising: a package underfill layer on the package substrate and under and around the semiconductor die, wherein the encapsulant is on the package underfill layer.

7. A method of forming a package structure, the method comprising: attaching a semiconductor die to a package substrate; forming a composite thermal interface material layer on the semiconductor die; forming an encapsulant around the composite thermal interface material layer; and attaching a package cap to the package substrate such that the package cap deforms the composite thermal interface material layer and the encapsulant and such that the composite thermal interface material layer contacts a reactive interface layer on at least one of the semiconductor die or the package cap.

8. The method of forming a package structure of claim 7, further comprising: forming a package underfill layer on the package substrate under and around the semiconductor die, wherein forming the encapsulant comprises forming the encapsulant on the package underfill layer and around the semiconductor die.

9. The method of forming a package structure of claim 7, wherein attaching the package cap to the package substrate comprises deforming the encapsulant using the package cap such that the encapsulant contacts a sidewall of the semiconductor die and a bottom surface of the package cap.

10. A package structure, comprising: a package substrate; a semiconductor die comprising a first reactive interface layer and on the package substrate; a package cap comprising a second reactive interface layer and on the semiconductor die; a composite thermal interface material layer between the package cap and the semiconductor die and contacting the first reactive interface layer and the second reactive interface layer, wherein the composite thermal interface material layer comprises a polymer matrix, a metal-based filler, and a particulate filler having a size less than the metal-based filler in the polymer matrix; and an encapsulant formed around the composite thermal interface material layer, contacting an outer sidewall of the composite thermal interface material layer, and to form a hermetic seal around the composite thermal interface material layer. ​ ​

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