Voltage generation circuit and driving method thereof, pixel driving circuit and display device

Abstract

The invention provides a voltage generation circuit, a driving method thereof, a pixel driving circuit and a display device. The voltage generation circuit is configured to generate a threshold voltage (Vth) of a driving transistor (T3); the voltage generation circuit comprises a signal holding sub-circuit which is electrically connected with at least one first control signal end (Conl), an initial signal end (Vinit) and a second electrode of the driving transistor (T3) and is configured to control a signal of the second electrode of the driving transistor (T3) under the control of signals of the at least one first control signal end (Conl) and the initial signal end (Vinit); the preset bias voltage sub-circuit is electrically connected with at least one second control signal end (Con2), a reference signal end (Vref) and the control electrode and the first electrode of the driving transistor (T3), and is configured to control a signal of the control electrode of the driving transistor (T3) under the control of signals of the at least one second control signal end (Con2) and the reference signal end (Vref); in part of the time period, the difference value between the voltage value of the signal of the control electrode of the driving transistor (T3) and the voltage value of the signal of the second electrode of the driving transistor (T3) is the threshold voltage (Vth) of the driving transistor (T3).

Description

Voltage generation circuit and driving method thereof, pixel driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, display technology, in particular to a voltage generation circuit and driving method thereof, a pixel driving circuit and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a voltage generation circuit, which is electrically connected with a driving transistor in a pixel driving circuit and is configured to generate a threshold voltage of the driving transistor, the driving transistor comprising a control electrode, a first electrode and a second electrode, the first electrode of the driving transistor being electrically connected with a first power supply end;

[0006] The voltage generation circuit comprises a signal holding sub-circuit and a preset bias sub-circuit;

[0007] The signal holding sub-circuit is electrically connected with at least one first control signal end, an initial signal end and the second electrode of the driving transistor respectively, and is configured to control the signal of the second electrode of the driving transistor under the control of the signals of the at least one control signal end and the initial signal end;

[0008] The preset bias sub-circuit is electrically connected with at least one second control signal end, a reference signal end, the control electrode and the first electrode of the driving transistor respectively, and is configured to control the signal of the control electrode of the driving transistor under the control of the signals of the at least one control signal end and the reference signal end;

[0009] In a part of the time period, the difference between the voltage value of the signal of the control electrode of the driving transistor and the voltage value of the signal of the second electrode of the driving transistor is the threshold voltage of the driving transistor.

[0010] In some possible implementation manners, the signal holding sub-circuit is further electrically connected with the first bias signal end, and the at least one first control signal end includes a first sub-control signal end and a second sub-control signal end.

[0011] In some possible implementation manners, the signal holding sub-circuit includes a signal holding capacitor, a first switching element and a second switching element.

[0012] The first switching element is configured to be turned on or turned off under the control of a signal of the first sub-control signal end, and the second switching element is configured to be turned on or turned off under the control of a signal of the second sub-control signal end.

[0013] The signal holding capacitor is electrically connected with the first bias signal end and the first node respectively, the first switching element is electrically connected with the initial signal end and the first node respectively, and the second switching element is electrically connected with the first node and the second electrode of the driving transistor respectively.

[0014] In some possible implementation manners, the preset bias sub-circuit is further electrically connected with the first power supply end, and the at least one second control signal end includes a third sub-control signal end.

[0015] In some possible implementation manners, the preset bias sub-circuit includes a bias capacitor and a third switching element.

[0016] The third switching element is configured to be turned on or turned off under the control of a signal of the third sub-control signal end.

[0017] The first end of the bias capacitor is electrically connected with the first power supply end, the second end of the bias capacitor is electrically connected with the control electrode of the driving transistor, and the third switching element is electrically connected with the reference signal end and the control electrode of the driving transistor respectively.

[0018] In some possible implementation manners, the voltage value of the initial signal end is less than the difference between the voltage value of the reference signal end and the voltage value of the threshold voltage of the driving transistor.

[0019] The difference between the voltage value of the first power supply end and the voltage value of the reference signal end is greater than the negative value of the threshold voltage of the driving transistor.

[0020] In some possible implementation manners, the signal holding sub-circuit is further electrically connected with the first electrode of the driving transistor and the first bias signal end, and the at least one first control signal end includes a first sub-control signal end, a second sub-control signal end, a fourth sub-control signal end and a fifth sub-control signal end.

[0021] In some possible implementation manners, the signal holding sub-circuit comprises a signal holding capacitor, a first switch element, a second switch element, a fourth switch element and a fifth switch element.

[0022] The first switch element is configured to be turned on or turned off under the control of a signal at a first sub-control signal terminal, the second switch element is configured to be turned on or turned off under the control of a signal at a second sub-control signal terminal, the fourth switch element is configured to be turned on or turned off under the control of a signal at a fourth sub-control signal terminal, and the fifth switch element is configured to be turned on or turned off under the control of a signal at a fifth sub-control signal terminal.

[0023] The signal holding capacitor is electrically connected to a first node and a second node respectively, the first switch element is electrically connected to an initial signal terminal and the first node respectively, the second switch element is electrically connected to the first node and a second electrode of a driving transistor respectively, the fourth switch element is electrically connected to a first bias signal terminal and the second node respectively, and the fifth switch element is electrically connected to the second node and a first electrode of the driving transistor respectively.

[0024] In some possible implementation manners, the preset bias sub-circuit is further electrically connected to the first electrode of the driving transistor and the first bias signal terminal, and the at least one second control signal terminal comprises a third sub-control signal terminal, a fourth sub-control signal terminal and a fifth sub-control signal terminal.

[0025] In some possible implementation manners, the preset bias sub-circuit comprises a bias capacitor, a third switch element, a fourth switch element and a fifth switch element.

[0026] The third switch element is configured to be turned on or turned off under the control of a signal at a third sub-control signal terminal, the fourth switch element is configured to be turned on or turned off under the control of a signal at a fourth sub-control signal terminal, and the fifth switch element is configured to be turned on or turned off under the control of a signal at a fifth sub-control signal terminal.

[0027] The bias capacitor is electrically connected to a control electrode of the driving transistor and the second node respectively, the third switch element is electrically connected to a reference signal terminal and the control electrode of the driving transistor respectively, the fourth switch element is electrically connected to the first bias signal terminal and the second node respectively, and the fifth switch element is electrically connected to the second node and the first electrode of the driving transistor respectively.

[0028] In some possible implementation manners, a difference between a voltage value of the first bias signal terminal and a voltage value of the reference signal terminal is greater than a negative value of a voltage value of a threshold voltage of the driving transistor.

[0029] A difference between the voltage value of the first bias signal terminal and the voltage value of the initial signal terminal is greater than a sum of the first voltage difference and a threshold voltage of the driving transistor, the first voltage difference being a difference between the voltage value of the first bias signal terminal and a voltage value of the reference signal terminal.

[0030] In some possible implementation manners, the signal holding sub-circuit is further electrically connected with the control electrode of the driving transistor and the reference signal terminal, and the at least one first control signal terminal includes a first sub-control signal terminal, a second sub-control signal terminal and a third sub-control signal terminal.

[0031] In some possible implementation manners, the signal holding sub-circuit includes a signal holding capacitor, a first switching element, a second switching element and a third switching element.

[0032] The first switching element is configured to be turned on or turned off under the control of a signal of the first sub-control signal terminal, the second switching element is configured to be turned on or turned off under the control of a signal of the second sub-control signal terminal, and the third switching element is configured to be turned on or turned off under the control of a signal of the third sub-control signal terminal.

[0033] The signal holding capacitor is electrically connected with the control electrode of the driving transistor and the first node respectively, the first switching element is electrically connected with the initial signal terminal and the first node respectively, the second switching element is electrically connected with the first node and the second electrode of the driving transistor respectively, and the third switching element is electrically connected with the reference signal terminal and the control electrode of the driving transistor respectively.

[0034] In some possible implementation manners, the preset bias sub-circuit is further electrically connected with the first electrode of the driving transistor and the first bias signal terminal, and the at least one second control signal terminal includes a third sub-control signal terminal, a fourth sub-control signal terminal and a fifth sub-control signal terminal.

[0035] In some possible implementation manners, the preset bias sub-circuit includes a bias capacitor, a third switching element, a fourth switching element and a fifth switching element.

[0036] The third switching element is configured to be turned on or turned off under the control of a signal of the third sub-control signal terminal, the fourth switching element is configured to be turned on or turned off under the control of a signal of the fourth sub-control signal terminal, and the fifth switching element is configured to be turned on or turned off under the control of a signal of the fifth sub-control signal terminal.

[0037] The bias capacitor is electrically connected with the control electrode of the driving transistor and the fourth node respectively, the third switching element is electrically connected with the reference signal terminal and the control electrode of the driving transistor respectively, the fourth switching element is electrically connected with the first bias signal terminal and the fourth node respectively, and the fifth switching element is electrically connected with the fourth node and the first electrode of the driving transistor respectively.

[0038] In some possible implementation manners, a difference between the voltage value of the first bias signal end and the voltage value of the reference signal end is greater than a sum of the second voltage difference and a voltage value of the threshold voltage of the driving transistor, the second voltage difference being a difference between the voltage value of the reference signal end and the voltage value of the initial signal end;

[0039] The difference between the voltage value of the initial signal end and the voltage value of the reference signal end is less than the voltage value of the threshold voltage of the driving transistor.

[0040] In a second aspect, the embodiments of the present disclosure provide a pixel driving circuit, including a driving transistor and the voltage generation circuit according to any one of the embodiments of the first aspect.

[0041] In some possible implementation manners, the pixel driving circuit further includes a sixth switching element configured to be turned on or turned off under control of a signal of at least one third control signal end;

[0042] The sixth switching element is electrically connected to the second electrode of the driving transistor and the first electrode of the light emitting device, respectively.

[0043] In some possible implementation manners, the at least one first control signal end includes a first scan signal end and a first light emitting signal end, the at least one second control signal end includes the first scan signal end, the at least one third control signal end includes a second light emitting signal end, the signal holding sub-circuit includes a signal holding capacitor, a first switching element and a second switching element, the preset bias sub-circuit includes a bias capacitor and a third switching element, the first switching element includes a fourth transistor, the second switching element includes a sixth transistor, the third switching element includes a second transistor, and the sixth switching element includes an eighth transistor.

[0044] The signal holding capacitor is electrically connected to the first bias signal end and the first node, respectively.

[0045] The first end of the bias capacitor is electrically connected to the first power supply end, and the second end of the bias capacitor is electrically connected to the control electrode of the driving transistor.

[0046] The control electrode of the second transistor is electrically connected to the first scan signal end, the first electrode of the second transistor is electrically connected to the reference signal end, and the second electrode of the second transistor is electrically connected to the control electrode of the driving transistor and the first end of the bias capacitor, respectively.

[0047] The control electrode of the fourth transistor is electrically connected to the first scan signal end, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial signal end.

[0048] The control electrode of the sixth transistor is electrically connected with the first light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the first electrode of the driving transistor;

[0049] The control electrode of the eighth transistor is electrically connected with the second light-emitting signal end, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the first electrode of the light-emitting device.

[0050] In some possible implementation manners, the pixel driving circuit further includes: a first transistor and a fifth transistor, and the signal holding capacitor and the bias voltage capacitor are electrically connected with the first bias signal end through the fifth transistor respectively;

[0051] The control electrode of the first transistor is electrically connected with the third scan signal end, the first electrode of the first transistor is electrically connected with the data signal end, and the second electrode of the first transistor is electrically connected with the first end of the bias voltage capacitor;

[0052] The control electrode of the fifth transistor is electrically connected with the second scan signal end, the first electrode of the fifth transistor is electrically connected with the first end of the bias voltage capacitor and the signal holding capacitor, and the second electrode of the fifth transistor is electrically connected with the first bias signal end.

[0053] In some possible implementation manners, the at least one first control signal end includes one of the first scan signal end and the third scan signal end, the second scan signal end and the first light-emitting signal end, the at least one second control signal end includes the first scan signal end and the third scan signal end, and the second scan signal end, and the at least one third control signal end includes the first light-emitting signal end; the signal holding sub-circuit includes the signal holding capacitor, the first switch element, the second switch element, the fourth switch element and the fifth switch element, and the preset bias voltage sub-circuit includes the bias voltage capacitor, the third switch element to the fifth switch element, the first switch element includes the fourth transistor, the second switch element includes the sixth transistor, the third switch element includes the second transistor, the fourth switch element includes the fifth transistor, the fifth switch element includes the ninth transistor, and the sixth switch element includes the eighth transistor;

[0054] The signal holding capacitor is electrically connected with the first node and the second node respectively;

[0055] The bias voltage capacitor is electrically connected with the control electrode of the driving transistor and the second node respectively;

[0056] The control electrode of the second transistor is electrically connected with one of the first scan signal end and the third scan signal end, the first electrode of the second transistor is electrically connected with the reference signal end, and the second electrode of the second transistor is electrically connected with the control electrode of the driving transistor and the first end of the bias voltage capacitor respectively;

[0057] A control electrode of the fourth transistor is connected with one of the first scan signal terminal and the third scan signal terminal, a first electrode of the fourth transistor is electrically connected with the first node, and a second electrode of the fourth transistor is electrically connected with the initial signal terminal;

[0058] A control electrode of the fifth transistor is electrically connected with one of the first scan signal terminal and the third scan signal terminal, a first electrode of the fifth transistor is electrically connected with the first bias signal terminal, and a second electrode of the fifth transistor is electrically connected with the second node;

[0059] A control electrode of the sixth transistor is electrically connected with the first emitting signal terminal, a first electrode of the sixth transistor is electrically connected with the first power supply terminal, and a second electrode of the sixth transistor is electrically connected with the first electrode of the driving transistor;

[0060] A control electrode of the eighth transistor is electrically connected with the first emitting signal terminal, a first electrode of the eighth transistor is electrically connected with the first node, and a second electrode of the eighth transistor is electrically connected with the first electrode of the light emitting device;

[0061] A control electrode of the ninth transistor is electrically connected with the second scan signal terminal, a first electrode of the ninth transistor is electrically connected with the second node, and a second electrode of the ninth transistor is electrically connected with the first electrode of the driving transistor.

[0062] In some possible implementation manners, the pixel driving circuit further includes a first transistor and a seventh transistor;

[0063] A control electrode of the first transistor is electrically connected with one of the first scan signal terminal and the third scan signal terminal, a first electrode of the first transistor is electrically connected with the data signal terminal, and a second electrode of the first transistor is electrically connected with the second node;

[0064] A control electrode of the seventh transistor is electrically connected with the first emitting signal terminal, a first electrode of the seventh transistor is electrically connected with the control electrode of the driving transistor, and a second electrode of the seventh transistor is electrically connected with the second node.

[0065] In some possible implementation manners, the at least one first control signal terminal can include the first scan signal terminal, the third scan signal terminal and the first emitting signal terminal, the at least one second control signal terminal can include the first scan signal terminal, the third scan signal terminal and the second scan signal terminal, the at least one third control signal terminal includes the first emitting signal terminal, the signal holding sub-circuit can include a signal holding capacitor, a first switching element, a second switching element and a third switching element, the preset bias sub-circuit can include a bias capacitor, a third switching element, a fourth switching element and a fifth switching element, the first switching element includes the fourth transistor, the second switching element includes the sixth transistor, the third switching element includes the second transistor and the tenth transistor, the fourth switching element includes the fifth transistor, the fifth switching element includes the ninth transistor, and the sixth switching element includes the eighth transistor.

[0066] The signal holding capacitor is electrically connected with the first node and the control electrode of the driving transistor respectively; the bias capacitor is electrically connected with the control electrode of the driving transistor and the fourth node respectively; the control electrode of the second transistor is electrically connected with the first scanning signal terminal, the first electrode of the second transistor is electrically connected with the reference signal terminal, and the second electrode of the second transistor is electrically connected with the control electrode of the driving transistor and the first end of the bias capacitor respectively; the control electrode of the fourth transistor is electrically connected with the first scanning signal terminal, the first electrode of the fourth transistor is electrically connected with the first node, and the second electrode of the fourth transistor is electrically connected with the initial signal terminal; the control electrode of the fifth transistor is electrically connected with the first scanning signal terminal, the first electrode of the fifth transistor is electrically connected with the first bias signal terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node; the control electrode of the sixth transistor is electrically connected with the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected with the first power terminal, and the second electrode of the sixth transistor is electrically connected with the first electrode of the driving transistor; the control electrode of the eighth transistor is electrically connected with the first light-emitting signal terminal, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the first electrode of the light-emitting device; the control electrode of the ninth transistor is electrically connected with the second scanning signal terminal, the first electrode of the ninth transistor is electrically connected with the fourth node, and the second electrode of the ninth transistor is electrically connected with the first electrode of the driving transistor; the control electrode of the tenth transistor is electrically connected with the third scanning signal terminal, the first electrode of the tenth transistor is electrically connected with the reference signal terminal, and the second electrode of the tenth transistor is electrically connected with the control electrode of the driving transistor and the first end of the bias capacitor respectively.

[0067] In some possible implementation manners, the pixel driving circuit can further include a first transistor, a seventh transistor and an eleventh transistor, the signal holding capacitor, the second end of the bias capacitor and the second electrode of the second transistor are electrically connected with the control electrode of the driving transistor through the seventh transistor;

[0068] The control electrode of the first transistor is electrically connected with the third scanning signal terminal, the first electrode of the first transistor is electrically connected with the data signal terminal, and the second electrode of the first transistor is electrically connected with the fourth node; the control electrode of the seventh transistor is electrically connected with the second scanning signal terminal, the first electrode of the seventh transistor is electrically connected with the control electrode of the driving transistor, and the second electrode of the seventh transistor T7 is electrically connected with the second node; the control electrode of the eleventh transistor is electrically connected with the first light-emitting signal terminal, the first electrode of the eleventh transistor is electrically connected with the control electrode of the driving transistor, and the second electrode of the eleventh transistor is electrically connected with the fourth node.

[0069] In a third aspect, the embodiments of the present disclosure provide a display device, including the pixel driving circuit according to any one of the embodiments of the second aspect.

[0070] In a fourth aspect, the embodiments of the present disclosure provide a driving method of a voltage generation circuit, configured to drive the voltage generation circuit according to any one of the embodiments of the first aspect, and the method comprises:

[0071] The signal holding sub-circuit controls the signal of the second electrode of the driving transistor under the control of the signals of the at least one control signal terminal and the initial signal terminal;

[0072] The preset bias sub-circuit controls the signal of the control electrode of the driving transistor under the control of the signals of the at least one control signal terminal and the reference signal terminal;

[0073] The difference between the voltage value of the signal of the control electrode of the driving transistor and the voltage value of the signal of the second electrode of the driving transistor is the threshold voltage of the driving transistor in the partial time period.

[0074] Other aspects can be apparent to those of ordinary skill in the art after reading and understanding the accompanying drawings and detailed description.

[0075] SUMMARY

[0076] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0077] FIG. 1 is a structural schematic diagram of a voltage generation circuit according to an example embodiment of the present disclosure;

[0078] FIG. 2A is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment;

[0079] FIG. 2B is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment;

[0080] FIG. 3A is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment;

[0081] FIG. 3B is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment;

[0082] FIG. 4A is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment;

[0083] FIG. 4B is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment;

[0084] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0085] FIG. 6 is a working timing diagram of the pixel driving circuit according to FIG. 5;

[0086] FIG. 7A is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0087] FIG. 7B is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment;

[0088] FIG. 8A is a timing chart of the pixel driving circuit according to FIG. 7A;

[0089] FIG. 8B is a timing chart of the pixel driving circuit according to FIG. 7B;

[0090] FIG. 9 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment;

[0091] FIG. 10 is a timing chart of the pixel driving circuit according to FIG. 9.

[0092] DETAILED DESCRIPTION

[0093] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below will be specifically described with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the manner and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0094] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of the structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0095] The ordinal numbers "first", "second", "third" and the like in the present specification are set in order to avoid confusion of the components, and are not intended to be limiting in terms of number.

[0096] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0097] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0098] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0099] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0100] In this specification, "electrically connected" includes the case where the components are connected through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0101] In the present specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0102] In the present specification, "film" and "layer" can be replaced with each other. For example, "conductive layer" can be replaced with "conductive film" at times. Similarly, "insulating film" can be replaced with "insulating layer" at times.

[0103] In the present specification, "same layer" refers to two (or more) structures formed by patterning at the same time, and the materials thereof can be the same or different. For example, the materials of the precursors for forming the plurality of structures in the same layer are the same, and the materials finally formed can be the same or different.

[0104] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformation due to a tolerance, and there can be an inside corner, an arc edge, and a deformation, etc.

[0105] In the present disclosure, "about" refers to not strictly limited boundaries, allowing values within a range of process and measurement errors.

[0106] The display panel of the OLED or QLED includes a substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel including a pixel driving circuit. A driving transistor in the pixel driving circuit is used to provide a driving signal to drive the OLED or QLED to emit light. The threshold voltage of the driving transistor largely determines the display quality in compensation for spatial and temporal variability, and the threshold voltage of the driving transistor is easily disturbed by external voltage fluctuations during the generation process, affecting the display effect.

[0107] FIG. 1 is a structural schematic diagram of a voltage generation circuit provided by an example embodiment of the present disclosure. As shown in FIG. 1, the voltage generation circuit can be electrically connected with a driving transistor T3 in a pixel driving circuit, and is configured to generate a threshold voltage of the driving transistor T3. The driving transistor can include a control electrode, a first electrode, and a second electrode, and the first electrode of the driving transistor is electrically connected with a first power supply end Vdd.

[0108] The voltage generation circuit can include a signal holding sub-circuit and a preset bias sub-circuit.

[0109] The signal holding sub-circuit is electrically connected with the at least one first control signal terminal Con1, the initial signal terminal Vinit and the second electrode of the driving transistor respectively, and is configured to control the signal of the second electrode of the driving transistor T3 under the control of the signals of the at least one control signal terminal Con1 and the initial signal terminal Vinit.

[0110] The preset bias sub-circuit is electrically connected with the at least one second control signal terminal Con2, the reference signal terminal Vref, the control electrode and the first electrode of the driving transistor respectively, and is configured to control the signal of the control electrode of the driving transistor T3 under the control of the signals of the at least one control signal terminal Con2 and the reference signal terminal Vref.

[0111] In the partial time period, the difference between the voltage value of the signal of the control electrode of the driving transistor T3 and the voltage value of the signal of the second electrode of the driving transistor T3 is the threshold voltage V th .

[0112] The signal of the second electrode of the driving transistor is controlled by the signal holding sub-circuit, so that the threshold voltage V th of the driving transistor T3 can be reset, obtained and held. The signal of the control electrode of the driving transistor is controlled by the preset bias sub-circuit, so that the preset bias and bootstrap holding can be realized.

[0113] In an example embodiment, the pixel driving circuit includes display frames and refresh frames, and the voltage generation circuit generates and stores the threshold voltage of the driving transistor in the refresh frame between two adjacent display frames.

[0114] In an example embodiment, the partial time period is the time period of the refresh frame between two adjacent display frames in the pixel driving circuit.

[0115] In an example embodiment, the signal of the first power supply terminal Vdd is a positive voltage signal.

[0116] In the embodiments of the present disclosure, the voltage generation circuit includes the signal holding sub-circuit and the preset bias sub-circuit. The signal of the second electrode of the driving transistor is controlled by the signal holding sub-circuit to avoid fluctuation of the signal of the second electrode of the driving transistor, and the signal of the control electrode of the driving transistor is controlled by the preset bias sub-circuit to avoid fluctuation of the signal of the control electrode of the driving transistor. Therefore, the fluctuation of the difference between the voltage value of the signal of the control electrode of the driving transistor and the voltage value of the signal of the second electrode of the driving transistor (i.e. the threshold voltage of the driving transistor) is avoided, so that the threshold voltage of the driving transistor is not easily disturbed by external voltage fluctuation in the generation process, and the display effect is improved.

[0117] In an example embodiment, the signal holding sub-circuit is further electrically connected with a first bias signal terminal Vbas, and the at least one first control signal terminal includes a first sub-control signal terminal and a second sub-control signal terminal.

[0118] FIG. 2A is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment, and FIG. 2B is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment. As shown in FIGS. 2A and 2B, in an example embodiment, the voltage generation circuit can include a signal holding capacitor C hdg , a first switching element SW1, and a second switching element SW2.

[0119] In an example embodiment, as shown in FIGS. 2A and 2B, the first switching element SW1 is configured to be turned on or turned off under the control of a signal of the first sub-control signal terminal, and the second switching element SW2 is configured to be turned on or turned off under the control of a signal of the second sub-control signal terminal; the signal holding capacitor C hdg is electrically connected with the first bias signal terminal Vbas and the first node N1 respectively, the first switching element SW1 is electrically connected with the initial signal terminal Vinit and the first node N1 respectively, and the second switching element SW2 is electrically connected with the first node N1 and the second electrode of the driving transistor T3 respectively.

[0120] In an example embodiment, the preset bias sub-circuit is further electrically connected with a first power supply terminal Vdd, and the at least one second control signal terminal includes a third sub-control signal terminal.

[0121] In an example embodiment, the preset bias sub-circuit can include a bias capacitor C bst and a third switching element SW3; the third switching element SW3 is configured to be turned on or turned off under the control of a signal of the third sub-control signal terminal; a first end of the bias capacitor C bst is electrically connected with the first power supply terminal Vdd, a second end of the bias capacitor C bst is electrically connected with the control electrode of the driving transistor, and the third switching element SW3 is electrically connected with the reference signal terminal Vref and the control electrode of the driving transistor respectively.

[0122] In an example embodiment, the first end of the bias capacitor C bst may be referred to as a bias reference terminal, and the second end of the bias capacitor C bst may be referred to as a bias variation terminal.

[0123] In the embodiments of the present disclosure, the first end of the bias capacitor C bst is connected with the first power supply terminal Vdd, which can avoid the voltage between the first end of the bias capacitor C bst and the first power supply Vdd from being disturbed by the fluctuation of an external voltage (the voltage V dt of the data signal terminal Data).

[0124] In an example embodiment, a first end of the biasing capacitor C bst may be connected to a fixed voltage relative to the first terminal of the driving transistor, or a first end of the biasing capacitor C bst may be connected to a voltage terminal that satisfies the required voltage range between the gate and the first terminal of the driving transistor and is not sensitive to external interference of the charging circuit.

[0125] In an example embodiment, a first end of the signal holding capacitor C hdg connected to the first node (i.e., the second terminal of the driving transistor) is referred to as a voltage variation terminal, and a second end of the signal holding capacitor C hdg is referred to as a voltage reference terminal, wherein the voltage reference terminal of the signal holding capacitor C hdg may be electrically connected to the first biasing signal terminal Vbas.

[0126] The generation mechanism of the threshold voltage of the driving transistor is to charge or discharge the voltage variation terminal of the signal holding capacitor C hdg through the driving transistor by the related power supply. In the generation of the threshold voltage of the driving transistor, due to the need for multiple biasing voltage support, the threshold voltage generation process of the driving transistor is sensitive to the fluctuation of the external gate bias voltage transmitted through the multiple DC voltage network.

[0127] In the embodiments of the present disclosure, the threshold voltage of the driving transistor is generated in a source follower manner for variability compensation, the threshold voltage of the driving transistor is generated based on the second terminal (source) of the driving transistor, and the required gate voltage range of the driving transistor is ensured by the bootstrap biasing of the biasing capacitor C bst , which eliminates the dependence of the threshold voltage generation process of the driving transistor on the external gate bias voltage and realizes the insensitivity of the threshold voltage generation process of the driving transistor to differential mode interference.

[0128] In an example embodiment, the voltage value V init of the initial signal terminal Vinit is less than the difference between the voltage value V ref of the threshold voltage of the driving transistor V th and the voltage value of the reference signal terminal Vref, i.e., V init <V ref -V th .

[0129] In an example embodiment, the difference between the voltage value V d of the first power supply terminal Vdd and the voltage value V ref of the reference signal terminal Vref is greater than the negative value of the voltage value of the threshold voltage of the driving transistor V th , i.e., V d -V ref >-Vth .

[0130] In the embodiments of the present disclosure, the voltage value V d of the first power supply end Vdd is greater than the voltage value V ref of the reference signal end Vref. d The voltage value V ref of the first power supply end Vdd is kept a certain difference from the voltage value V th of the reference signal end Vref, so as to avoid the threshold voltage V th of the driving transistor varying to zero. The threshold voltage V th of the driving transistor varying to zero refers to the case that the driving transistor changes from an enhancement mode transistor to a depletion mode transistor.

[0131] In an exemplary embodiment, FIG. 2A shows a preset bias state of the voltage generation circuit, which refers to the threshold voltage V hdg of the driving transistor at the starting moment t0 of the generation process. By appropriately varying the bias voltage of the varying voltage end, the charging or discharging process is started. FIG. 2B shows an end state of the voltage generation circuit, which refers to the case that the signal holding capacitor C bst and the bias capacitor C hdg vary with the charging or discharging process. The varying voltage of the varying voltage end and the bias capacitor C bst is negatively fed back to the control electrode and the second electrode of the driving transistor, so as to continuously reduce the current passing through the driving transistor. When the difference V gs of the voltage values of the control electrode and the second electrode of the driving transistor caused by the varying of the varying voltage end and the bias capacitor C th is approximately equal to the threshold voltage V th of the driving transistor, the charging or discharging process tends to stop, and the threshold voltage V bst of the driving transistor can be generated at this moment.

[0132] In the embodiments of the present disclosure, the generation mechanism of the voltage generation circuit can be that the first switch element SW1 and the third switch element SW3 are respectively turned on, and the bias capacitor C hdg is initialized and reset synchronously with the varying voltage end of the signal holding capacitor C hdg After the initialization and reset, the first switch element SW1 and the third switch element SW3 are respectively turned off. Then, at the starting moment t0, the charging or discharging is started, the second switch element SW2 is turned on, and the generation process of the threshold voltage of the driving transistor is started. In the generation process, the appropriate bias between the control electrode and the first electrode of the driving transistor is maintained by the bias capacitor C bst until the end moment t off of the process.

[0133] In an example embodiment, in the preset bias state shown in FIG. 2A, the voltage value V hdg of the variable voltage end (i.e., the first node N1) is V var (t0) = V init < V ref -V th , the bias capacitor C bst stores the voltage value V bst (t0) = V d -V ref >-V th , the signal holding capacitor C hdg stores the voltage value V hdg (t0) = V init -V bas .

[0134] In an example embodiment, in the process end state of the voltage generation circuit shown in FIG. 2B, the difference value V gs (t off ) ≈ V th of the voltage values of the control electrode and the second electrode of the driving transistor is V hdg , the voltage value V var (t off ) ≈ V ref -V th of the variable voltage end (i.e., the first node N1) is V bst , the bias capacitor C bst stores the voltage value V off (t d ) = V ref -V th >-V hdg , the signal holding capacitor C hdg stores the voltage value V off (t ref ) = V th -V bas .

[0135] An example structure of the voltage generation circuit is shown in FIG. 2A and FIG. 2B respectively. It is easy for those skilled in the art to understand that the implementation of the voltage generation circuit is not limited to this.

[0136] In an example embodiment, the signal holding sub-circuit is further electrically connected with the first electrode of the driving transistor and the first bias signal end Vbas, and the at least one first control signal end includes: a first sub-control signal end, a second sub-control signal end, a fourth sub-control signal end and a fifth sub-control signal end.

[0137] In the embodiments of the present disclosure, the voltage reference end of the signal holding sub-circuit can also be connected with the first electrode of the driving transistor, and the voltage reference end of the signal holding sub-circuit can share the voltage signal of the first electrode of the driving transistor (the voltage of the first power supply end Vdd), thereby further reducing the dependence on the external direct current voltage and inhibiting the influence of the direct current network transmission voltage fluctuation differential mode interference.

[0138] FIG. 3A is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment, and FIG. 3B is an equivalent circuit diagram of a voltage generation circuit according to an example embodiment. As shown in FIG. 3A and FIG. 3B, in an example embodiment, the voltage generation circuit can include a signal holding capacitor C hdg , a first switching element SW1, a second switching element SW2, a fourth switching element SW4, and a fifth switching element SW5.

[0139] In an example embodiment, as shown in FIG. 3A and FIG. 3B, the first switching element SW1 is configured to be turned on or turned off under the control of the signal of the first sub-control signal end, the second switching element SW2 is configured to be turned on or turned off under the control of the signal of the second sub-control signal end, the fourth switching element SW4 is configured to be turned on or turned off under the control of the signal of the fourth sub-control signal end, and the fifth switching element SW5 is configured to be turned on or turned off under the control of the signal of the fifth sub-control signal end; the signal holding capacitor C hdg is electrically connected with the first node N1 and the second node N2 respectively, the first switching element SW1 is electrically connected with the initial signal end Vinit and the first node N1 respectively, the second switching element SW2 is electrically connected with the first node N1 and the second electrode of the driving transistor respectively, the fourth switching element SW4 is electrically connected with the first bias signal end Vbas and the second node N2 respectively, and the fifth switching element SW5 is electrically connected with the second node N2 and the first electrode of the driving transistor respectively.

[0140] In the embodiments of the present disclosure, the voltage reference end of the signal holding capacitor C hdg may be connected with the first electrode of the driving transistor, and the voltage of the first electrode of the driving transistor can be shared, thereby further reducing the dependence on the external direct current voltage.

[0141] In an example embodiment, the preset bias sub-circuit is further electrically connected with the first electrode of the driving transistor and the first bias signal end Vbas, and the at least one second control signal end includes a third sub-control signal end, a fourth sub-control signal end, and a fifth sub-control signal end.

[0142] In an example embodiment, as shown in FIG. 3A and FIG. 3B, the preset bias sub-circuit can include a bias capacitor C bst, a third switch element SW3, a fourth switch element SW4 and a fifth switch element SW5; the third switch element SW3 is configured to be turned on or turned off under the control of a signal at a third sub-control signal terminal, the fourth switch element SW4 is configured to be turned on or turned off under the control of a signal at a fourth sub-control signal terminal, and the fifth switch element SW5 is configured to be turned on or turned off under the control of a signal at a fifth sub-control signal terminal; a biasing capacitor C bst The third switch element SW3 is electrically connected with the reference signal terminal Vref and the control electrode of the driving transistor respectively, the fourth switch element SW4 is electrically connected with the first biasing signal terminal Vbas and the second node N2 respectively, and the fifth switch element SW5 is electrically connected with the second node N2 and the first electrode of the driving transistor respectively.

[0143] In the embodiments of the present disclosure, the threshold voltage of the driving transistor is generated in a source follower mode for variability compensation, the threshold voltage of the driving transistor is generated based on the second electrode (source electrode) of the driving transistor, the voltage reference terminal of the signal holding sub-circuit can share the voltage signal of the first electrode of the driving transistor (the voltage of the first power supply terminal Vdd), and the biasing capacitor C bst The bootstrap bias ensures the required gate voltage range of the driving transistor, eliminates the dependence on the external gate bias voltage in the threshold voltage generation process of the driving transistor, and realizes the insensitivity of the threshold voltage generation process of the driving transistor to differential mode interference.

[0144] In an exemplary embodiment, the voltage value V bas of the first biasing signal terminal Vbas is greater than the negative value of the voltage value of the threshold voltage V ref of the driving transistor, that is, V th -V bas > -V ref .

[0145] In an exemplary embodiment, the voltage value V bas of the first biasing signal terminal Vbas is greater than the voltage value V init of the initial signal terminal Vinit, and the difference between the voltage value V th of the first biasing signal terminal Vbas and the voltage value V bas of the reference signal terminal Vref is greater than the sum of the first voltage difference and the voltage value of the threshold voltage V ref of the driving transistor, the first voltage difference is the difference between the voltage value V bas of the first biasing signal terminal Vbas and the voltage value V init of the reference signal terminal Vref, and V bas -V ref > (V th -V bst ).

[0146] In an example embodiment, FIG. 3A shows a pre-bias state of the voltage generation circuit, and FIG. 3B shows an end-of-process state of the voltage generation circuit. The generation mechanism of the voltage generation circuit can be that the first switch element SW1, the third switch element SW3, and the fourth switch element SW4 are respectively turned on, and the bias voltage of the bias capacitor C bst After the pre-bias (usually and the initialization reset synchronization of the signal holding capacitor C hdg ) is completed, the first switch element SW1, the third switch element SW3, and the fourth switch element SW4 are respectively turned off. Then, at the start time t0, the bias capacitor C hdg begins to charge or discharge itself, the second switch element SW2 and the fifth switch element SW5 are turned on, and the generation process of the threshold voltage of the driving transistor is started. In the generation process, the appropriate bias voltage between the control electrode and the first electrode of the driving transistor is maintained by the bias capacitor C bst , until the end time t off .

[0147] In an example embodiment of the present disclosure, the signal holding capacitor C hdg discharges itself, which can support the voltage variation of the second electrode of the driving transistor relative to the control electrode in the voltage generation circuit, and the difference V gs between the voltage values of the control electrode and the second electrode of the driving transistor can be fed back negatively. Therefore, in the generation process of the threshold voltage of the driving transistor, the support of the external DC voltage is not needed, and the dependence on the external gate bias voltage in the threshold voltage generation process of the driving transistor is eliminated.

[0148] In an example embodiment, after the pre-bias is completed, the first switch element SW1, the third switch element SW3, and the fourth switch element SW4 are completely open or equivalent open, and the potential of the voltage generation circuit can be floating relative to the external DC voltage. Therefore, the holding node (that is, the first node N1) of the threshold voltage of the driving transistor and other sensitive nodes can be inhibited from being directly disturbed by the fluctuation of the external gate bias voltage through the parasitic capacitance.

[0149] In an example embodiment, in the pre-bias state shown in FIG. 3A, the bias voltage of the bias capacitor C bst stored voltage value V bst (t0) = V bas -V ref > -V th , and the signal holding capacitor C hdg stores the voltage value V hdg (t off ) = V bas -V init >(V bas -V ref )+V th .

[0150] In one exemplary embodiment, Figure 3B shows the voltage difference V between the control electrode and the second electrode of the driving transistor at the end of the process of the voltage generation circuit. gs (t off )≈V th Bias capacitor C bst Stored voltage value V bst (t off ) = V bas -V ref Signal holding capacitor C hdg Stored voltage value V hdg (t off )≈(V bas -V ref )+V th .

[0151] Figures 3A and 3B illustrate exemplary structures of voltage generation circuits, respectively. It will be readily understood by those skilled in the art that the implementation of the voltage generation circuit is not limited to these examples.

[0152] In one exemplary embodiment, the signal holding sub-circuit is also electrically connected to the control electrode and reference signal terminal Vref of the driving transistor, and at least one first control signal terminal includes: a first sub-control signal terminal, a second sub-control signal terminal, and a third sub-control signal terminal.

[0153] In this embodiment of the present disclosure, the voltage reference terminal of the signal holding sub-circuit can also be connected to the control electrode of the driving transistor. That is, the signal of the voltage reference terminal of the signal holding sub-circuit is the same as the signal of the reference signal terminal Vref. The voltage reference terminal of the signal holding sub-circuit can share the voltage signal of the control electrode of the driving transistor (the voltage of the reference signal terminal Vref), further reducing the dependence on the external DC voltage and suppressing the influence of differential mode interference of voltage fluctuation transmitted by the DC network.

[0154] Figure 4A is an equivalent circuit diagram of a voltage generation circuit provided in an exemplary embodiment, and Figure 4B is an equivalent circuit diagram of a voltage generation circuit provided in an exemplary embodiment. As shown in Figures 4A and 4B, in an exemplary embodiment, the voltage generation circuit may include: a signal holding capacitor C. hdg The first switching element SW1, the second switching element SW2, and the third switching element SW3.

[0155] In one exemplary embodiment, as shown in Figures 4A and 4B, the first switching element SW1 is configured to be turned on or off under the control of a signal at the first sub-control signal terminal, the second switching element SW2 is configured to be turned on or off under the control of a signal at the second sub-control signal terminal, and the third switching element SW3 is configured to be turned on or off under the control of a signal at the third sub-control signal terminal; the signal holding capacitor Chdg The first switch element SW1 is electrically connected with the initial signal terminal Vinit and the first node N1 respectively, the second switch element SW2 is electrically connected with the first node N1 and the second electrode of the driving transistor respectively, and the third switch element SW3 is electrically connected with the reference signal terminal Vref and the control electrode of the driving transistor respectively.

[0156] In the embodiments of the present disclosure, the signal holding capacitor C hdg The voltage reference terminal can be connected with the control electrode of the driving transistor, and share the voltage of the control electrode of the driving transistor, thereby further reducing the dependence on the external direct current voltage.

[0157] In an exemplary embodiment, the preset bias sub-circuit is further electrically connected with the first electrode of the driving transistor and the first bias signal terminal Vbas, and the at least one second control signal terminal includes a third sub-control signal terminal, a fourth sub-control signal terminal and a fifth sub-control signal terminal.

[0158] In an exemplary embodiment, as shown in FIG. 4A and FIG. 4B, the preset bias sub-circuit can include a bias capacitor C bst , a third switch element SW3, a fourth switch element SW4 and a fifth switch element SW5; the third switch element SW3 is configured to be turned on or turned off under the control of the signal of the third sub-control signal terminal, the fourth switch element SW4 is configured to be turned on or turned off under the control of the signal of the fourth sub-control signal terminal, and the fifth switch element SW5 is configured to be turned on or turned off under the control of the signal of the fifth sub-control signal terminal; the bias capacitor C bst The third switch element SW3 is electrically connected with the reference signal terminal Vref and the control electrode of the driving transistor respectively, the fourth switch element SW4 is electrically connected with the first bias signal terminal Vbas and the second node N2 respectively, and the fifth switch element SW5 is electrically connected with the second node N2 and the first electrode of the driving transistor respectively.

[0159] In the embodiments of the present disclosure, the threshold voltage of the driving transistor is generated in a source follower mode for variability compensation, the threshold voltage of the driving transistor is generated based on the second electrode (source electrode) of the driving transistor, the voltage reference terminal of the signal holding sub-circuit can share the voltage signal (the voltage of the reference signal terminal Vref) of the control electrode of the driving transistor, and the bootstrap bias ensures the required gate voltage range of the driving transistor, eliminates the dependence on the external gate bias voltage in the threshold voltage generation process of the driving transistor, and realizes the insensitivity of the threshold voltage generation process of the driving transistor to differential mode interference. bst

[0160] In an exemplary embodiment, the voltage value V​bas the voltage value of the reference signal terminal Vref ref is greater than the sum of the second voltage difference and the threshold voltage V th of the driving transistor, and the second voltage difference is the difference between the voltage value of the reference signal terminal Vref ref and the voltage value of the initial signal terminal Vinit init , i.e. V bas -V ref >(V ref -V init )+V th .

[0161] In an exemplary embodiment, the difference between the voltage value of the initial signal terminal Vinit init and the voltage value of the reference signal terminal Vref ref is less than the threshold voltage V th of the driving transistor, i.e. V init -V ref V th .

[0162] In an exemplary embodiment, Fig. 4A shows the preset bias state of the voltage generation circuit, and Fig. 4B shows the process end state of the voltage generation circuit. The generation mechanism of the voltage generation circuit can be that the first switching element SW1, the third switching element SW3 and the fourth switching element SW4 are respectively turned on, the bias capacitor C bst completes the pre-bias (usually and the initialization reset of the variation voltage terminal of the signal holding capacitor C hdg After the pre-bias is completed, the first switching element SW1, the third switching element SW3 and the fourth switching element SW4 are respectively turned off. Then, at the starting time t0, the C hdg itself starts to charge or discharge, the second switching element SW2 and the fifth switching element SW5 are turned on, and the generation process of the threshold voltage of the driving transistor starts. In the generation process, the appropriate bias between the control electrode and the first electrode of the driving transistor is maintained by the bias capacitor C bst until the end time t off process is completed.

[0163] In the embodiment of the disclosure, the charge or discharge between the signal holding capacitor C hdg and the bias capacitor C bst can support the voltage variation of the second electrode of the driving transistor relative to the control electrode in the voltage generation circuit, and the negative feedback of the difference V gs between the voltage values of the control electrode and the second electrode of the driving transistor, so that the generation process of the threshold voltage of the driving transistor does not need the support of the external direct current voltage, and the dependence on the external gate bias voltage in the generation process of the threshold voltage of the driving transistor is eliminated.

[0164] In an example embodiment, after the pre-bias is completed, the first switching element SW1, the third switching element SW3 and the fourth switching element SW4 are completely open-circuited or equivalently open-circuited, and the potential of the voltage generation circuit can be floating with respect to the external DC voltage. The threshold voltage holding node (i.e., the first node N1) of the drive transistor and other sensitive nodes can be prevented from being directly disturbed by fluctuations in the external gate bias voltage through parasitic capacitance.

[0165] In an example embodiment, in the pre-bias state shown in FIG. 4A, the bias capacitor C bst The stored voltage value V bst (t0) = V bas -V ref > (V ref -V init )+V th The signal holding capacitor C hdg stores the voltage value V hdg (t off ) = V init -V ref <V th .

[0166] In an example embodiment, in the process end state of the voltage generation circuit shown in FIG. 4B, the difference between the voltage values of the control electrode and the second electrode of the drive transistor V gs (t off ) ≈ V th The bias capacitor C bst stores the voltage value V bst (t off ) ≈ (V bas -V ref ,)-(V ref -V init )+V th The signal holding capacitor C hdg stores the voltage value V hdg (t off ) ≈ -V th .

[0167] In an example embodiment, the capacitance value of the signal holding capacitor C hdg is the same as or similar to the capacitance value of the bias capacitor C bst .

[0168] An example structure of the voltage generation circuit is shown in FIG. 4A and FIG. 4B, respectively. It is easy for those skilled in the art to understand that the implementation of the voltage generation circuit is not limited thereto.

[0169] In an example embodiment, the first switch element SW1, the third switch element SW3 and the fourth switch element SW4 can be a triplex switch or a duplex switch, and the second switch element SW2 and the fifth switch element SW5 can be a duplex switch or a single-pole switch.

[0170] The pixel driving circuit provided by the embodiments of the present disclosure further includes a driving transistor and a voltage generating circuit. The voltage generating circuit is the voltage generating circuit provided by any of the foregoing embodiments, and has similar implementation principles and effects, which will not be described herein again.

[0171] In an example embodiment, the pixel driving circuit can further include a sixth switch element configured to be turned on or turned off under the control of a signal at at least one third control signal terminal; the sixth switch element is electrically connected to the second electrode of the driving transistor and the first electrode (anode) of the light emitting device L respectively, the second electrode (cathode) of the light emitting device L is electrically connected to a second power terminal Vss, and the signal at the second power terminal Vss is a negative voltage signal.

[0172] The light emitting device L can be an organic electroluminescence diode (OLED) or a quantum dot light emitting diode (QLED). The OLED can include a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked.

[0173] In the embodiments of the present disclosure, a sixth switch element (for example, the eighth transistor T8 in the following embodiments) is added between the second electrode (i.e., the first node N1) of the driving transistor T3 and the anode of the light emitting device L, so that the threshold voltage V th During the generation process, the driving transistor T3 and the light emitting device L are isolated by controlling the turn-off of the sixth switch element, so that the differential mode interference transmitted through the second power terminal Vss can be prevented from being coupled to the threshold voltage V hdg of the driving transistor T3 through the light emitting device L and the signal holding capacitor C th during the generation process.

[0174] FIG. 5 is an equivalent circuit diagram of the pixel driving circuit provided by an example embodiment. As shown in FIG. 5, in an example embodiment, the at least one first control signal terminal Con1 can include a first scan signal terminal Gate1 and a first light emitting signal terminal EM1, the at least one second control signal terminal Con2 can include the first scan signal terminal Gate1, the at least one third control signal terminal Con3 can include a second light emitting signal terminal EM2; the signal holding sub-circuit can include a signal holding capacitor C hdg , a first switch element SW1 and a second switch element SW2, and the preset bias voltage sub-circuit can include a bias voltage capacitor C bstThe third switching element SW3, the first switching element SW1 includes the fourth transistor T4, the second switching element SW2 includes the sixth transistor T6, the third switching element SW3 includes the second transistor T2, and the sixth switching element includes the eighth transistor T8.

[0175] In one exemplary embodiment, as shown in FIG5, the signal holding capacitor C hdg Electrically connected to the first bias signal terminal Vbas and the first node N1 respectively; bias capacitor C bst The first terminal is electrically connected to the first power supply terminal Vdd, and the bias capacitor C bst The second terminal of the second transistor T2 is electrically connected to the control electrode of the driving transistor; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first terminal of the second transistor T2 is electrically connected to the reference signal terminal Vref, and the second terminal of the second transistor T2 is connected to the control electrode of the driving transistor and the bias capacitor C, respectively. bst The first terminal (i.e., the third node N3) is electrically connected; the control terminal of the fourth transistor T4 is connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the first node N1, and the second terminal of the fourth transistor T4 is electrically connected to the initial signal terminal Vinit; the control terminal of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the sixth transistor T6 is electrically connected to the first power supply terminal Vdd, and the second terminal of the sixth transistor T6 is electrically connected to the first terminal of the driving transistor T3; the control terminal of the eighth transistor T8 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the eighth transistor T8 is electrically connected to the first node N1, and the second terminal of the eighth transistor T8 is electrically connected to the first terminal (anode) of the light-emitting device L.

[0176] In one example embodiment, the second switching element SW2 includes, but is not limited to, a sixth transistor T6 located between the first power supply terminal Vdd and the first terminal of the driving transistor T3. The second switching element SW2 can be configured according to the specific circuit of the pixel driving circuit between the first power supply terminal Vdd and the signal holding capacitor C. hdg Any position in the charging path between the voltage fluctuation terminals (i.e., the first node N1).

[0177] In one example embodiment, the pixel driving circuit may further include: a first transistor T1 and a fifth transistor T5, and a signal holding capacitor C. hdg and bias capacitor C bst The fifth transistor T5 is electrically connected to the first bias signal terminal Vbas; the control terminal of the first transistor T1 is electrically connected to the third scan signal terminal Gate3; the first terminal of the first transistor T1 is electrically connected to the data signal terminal Data; and the second terminal of the first transistor T1 is electrically connected to the bias capacitor C. bstconnected with the first end of the bias voltage capacitor C bst connected with the first end of the bias voltage capacitor C hdg and the signal holding capacitor C

[0178] In an example embodiment, as shown in FIG. 5, the first transistor T1 to the sixth transistor T6 and the eighth transistor T8 can be N-type transistors.

[0179] An example structure of the pixel driving circuit is shown in FIG. 5. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0180] FIG. 6 is a timing diagram of the pixel driving circuit provided in FIG. 5. The working process of the pixel driving circuit exemplified by FIG. 5 is described below to illustrate the example embodiment of the present disclosure. The pixel driving circuit can generate and store the threshold voltage of the driving transistor in the refresh frame between two adjacent display frames (e.g., the (n-1)th frame display driving and the nth frame display driving, n is an integer). The working process of the pixel driving circuit can include:

[0181] The first stage S1 is called the reset stage. The signals of the first scan signal end Gate1 and the second scan signal end Gate2 are both high level signals, and the signals of the third scan signal end Gate3, the first emission signal end EM1 and the second emission signal end EM2 are all low level signals. The signal of the first scan signal end Gate1 is a high level signal, the second transistor T2 is turned on, and the voltage of the reference signal end Vref is written to the control electrode of the driving transistor T3; the fourth transistor T4 is turned on, and the voltage of the initial signal end line Vinit is written to the second electrode of the driving transistor T3, completing the initialization of the voltage variation end of the signal holding capacitor C hdg The signal of the second scan signal end Gate2 is a high level signal, the fifth transistor T5 is turned on, and the voltage of the first bias signal end Vbas is written to the voltage reference end (i.e., the second node N2) of the signal holding capacitor C hdg The signal of the second scan signal end Gate2 is a high level signal, the fifth transistor T5 is turned on, and the voltage of the first bias signal end Vbas is written to the voltage reference end (i.e., the second node N2) of the signal holding capacitor C bst The signal of the second scan signal end Gate2 is a high level signal, the fifth transistor T5 is turned on, and the voltage of the first bias signal end Vbas is written to the voltage reference end (i.e., the second node N2) of the signal holding capacitor C bst pre-bias. The first transistor T1, the sixth transistor T6 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0182] The second stage S2 is called the threshold voltage V thIn the generating stage, the signals of the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high level signals, and the signals of the first scanning signal terminal Gate1, the third scanning signal terminal Gate3 and the second light-emitting signal terminal EM2 are low level signals. The signal of the first scanning signal terminal Gate1 is a low level signal, and the second transistor T2 and the fourth transistor T4 are disconnected respectively. The signal of the first light-emitting signal terminal EM1 is a high level signal, the sixth transistor T6 is turned on, and the voltage of the first power supply terminal Vdd is written to the first electrode of the driving transistor T3, and the signal retention capacitor C hdg In the charging or discharging, the threshold voltage of the driving transistor T3 is generated. In the generating process of the threshold voltage of the driving transistor T3, the bias capacitor C bst The bias between the control electrode and the first electrode of the driving transistor T3 is maintained until the threshold voltage V th The generating process is ended. Wherein, the first transistor T1 and the eighth transistor T8 are disconnected.

[0183] The third stage S3 is called a refreshing stage, the signals of the second scanning signal terminal Gate2 and the third scanning signal terminal Gate3 are high level signals, and the signals of the first light-emitting signal terminal EM1, the first scanning signal terminal Gate1 and the second light-emitting signal terminal EM2 are low level signals. The signal of the first light-emitting signal terminal EM1 is a low level signal, and the sixth transistor T6 is disconnected. The signal of the third scanning signal terminal Gate3 is a high level signal, the first transistor T1 is turned on, and after the threshold voltage generating process of the driving transistor T3 is ended, the voltage V bst of the data signal terminal Data is written to the bias capacitor C dt The signal of the second scanning signal terminal Gate2 is a high level signal, the fifth transistor T5 is turned on, and the signal retention capacitor C hdg retains the threshold voltage V th and the bias capacitor C bst retains the voltage V dt . Wherein, the second transistor T2, the fourth transistor T4 and the eighth transistor T8 are disconnected.

[0184] In the embodiment of the present disclosure, after the threshold voltage V th of the driving transistor T3 is generated, the voltage V bst of the data signal terminal Data is written to the bias capacitor C dt , the bias capacitor C bst serves as the retention and coupling capacitor of the voltage V dt of the refreshing data signal terminal Data, and the voltage V dt of the data signal terminal Data and the threshold voltage V th of the driving transistor T3 are superimposed and coupled, so that the pixel circuit structure and layout efficiency can be improved.

[0185] Fig. 7A is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment, and Fig. 7B is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment. As shown in Figs. 7A and 7B, in an exemplary embodiment, the at least one first control signal terminal Con1 can include one of the first scan signal terminal Gate1 and the third scan signal terminal Gate3, the second scan signal terminal Gate2 and the first emission signal terminal EM1, the at least one second control signal terminal Con2 can include one of the first scan signal terminal Gate1 and the third scan signal terminal Gate3, and the second scan signal terminal Gate2, and the at least one third control signal terminal Con3 includes the first emission signal terminal EM1; the signal holding sub-circuit can include the signal holding capacitor C hdg , the first switch element SW1, the second switch element SW2, the fourth switch element SW4 and the fifth switch element SW5, and the preset bias sub-circuit can include the bias capacitor C bst , the third switch element SW3 to the fifth switch element SW5, the first switch element SW1 includes the fourth transistor T4, the second switch element SW2 includes the sixth transistor T6, the third switch element SW3 includes the second transistor T2, the fourth switch element SW4 includes the fifth transistor T5, the fifth switch element SW5 includes the ninth transistor T9, and the sixth switch element includes the eighth transistor T8.

[0186] In an exemplary embodiment, as shown in Figs. 7A and 7B, the signal holding capacitor C hdg is electrically connected to the first node N1 and the second node N2, respectively; the bias capacitor C bst is electrically connected to the control electrode of the driving transistor and the second node N2, respectively; the control electrode of the second transistor T2 is electrically connected to one of the first scan signal terminal Gate1 and the third scan signal terminal Gate3, the first electrode of the second transistor T2 is electrically connected to the reference signal terminal Vref, and the second electrode of the second transistor T2 is electrically connected to the control electrode of the driving transistor and the bias capacitor C bsta first end of the first transistor T1 and a first end of the third transistor T3; a control electrode of the fourth transistor T4 is connected to one of the first scan signal end Gate1 and the third scan signal end Gate3, a first electrode of the fourth transistor T4 is connected to the first node N1, and a second electrode of the fourth transistor T4 is connected to the initial signal end Vinit; a control electrode of the fifth transistor T5 is connected to one of the first scan signal end Gate1 and the third scan signal end Gate3, a first electrode of the fifth transistor T5 is connected to the first bias signal end Vbas, and a second electrode of the fifth transistor T5 is connected to the second node N2; a control electrode of the sixth transistor T6 is connected to the first emitting signal end EM1, a first electrode of the sixth transistor T6 is connected to the first power supply end Vdd, and a second electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor; a control electrode of the eighth transistor T8 is connected to the first emitting signal end EM1, a first electrode of the eighth transistor T8 is connected to the first node N1, and a second electrode of the eighth transistor T8 is connected to the first electrode of the light emitting device L; a control electrode of the ninth transistor T9 is connected to the second scan signal end Gate2, a first electrode of the ninth transistor T9 is connected to the second node N2, and a second electrode of the ninth transistor T9 is connected to the first electrode of the driving transistor.

[0187] In an example embodiment, as shown in FIGS. 7A and 7B, the pixel driving circuit can further include the first transistor T1 and the seventh transistor T7; a control electrode of the first transistor T1 is connected to one of the first scan signal end Gate1 and the third scan signal end Gate3, a first electrode of the first transistor T1 is connected to the data signal end Data, and a second electrode of the first transistor T1 is connected to the second node N2; a control electrode of the seventh transistor T7 is connected to the first emitting signal end EM1, a first electrode of the seventh transistor T7 is connected to the control electrode of the driving transistor, and a second electrode of the seventh transistor T7 is connected to the second node N2.

[0188] In an example embodiment, as shown in FIG. 7A, the first transistor T1 to the ninth transistor T9 can be N-type transistors.

[0189] In an example embodiment, as shown in FIG. 7B, the first transistor T1 to the ninth transistor T9 can be P-type transistors.

[0190] FIGS. 7A and 7B respectively show an example structure of the pixel driving circuit. It is easily understood by those skilled in the art that the implementation of the pixel driving circuit is not limited thereto.

[0191] Fig. 8A is a timing diagram of the pixel driving circuit provided in Fig. 7A, and the working process of the pixel driving circuit exemplified by Fig. 7A is described below to illustrate the exemplary embodiments of the present disclosure. The pixel driving circuit can generate and store the threshold voltage of the driving transistor in the refresh frame between two adjacent display frames (e.g., the (n-1)th frame display driving and the nth frame display driving, where n is an integer), and the working process of the pixel driving circuit can include:

[0192] The first stage S1 is called the reset stage and the refresh stage. The signals of the first scan signal end Gate1 and the third scan signal end Gate3 are high level signals, and the signals of the second scan signal end Gate2 and the first emitting signal end EM1 are low level signals. The signals of the first scan signal end Gate1 and the third scan signal end Gate3 are high level signals, the fourth transistor T4 is turned on, the voltage of the initial signal end line Vinit is written to the first node, and the signal holding capacitor C hdg is initialized. The fifth transistor T5 is turned on, and the voltage of the first bias signal end Vbas is written to the signal holding capacitor C hdg The voltage reference end (i.e., the second node N2) of the signal holding capacitor C bst and the first end of the bias voltage capacitor C bst are initialized. The first transistor T1 is turned on, and the voltage V bst of the data signal end Data is written to the bias voltage capacitor C dt . The second transistor T2 is turned on, and the voltage value V bst of the reference signal end Vref is written to the second end of the bias voltage capacitor C ref . At this time, the difference (V ref -V dt ) between the voltage value V ref of the reference signal end Vref and the voltage V dt of the data signal end Data is taken as the pre-bias voltage of the bias voltage capacitor C bst . The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. In this stage, the light emitting device L does not emit light.

[0193] The second stage S2 is called the threshold voltage V th generation stage. The signal of the second scan signal end Gate2 is a high level signal, and the signals of the first emitting signal end EM1, the first scan signal end Gate1, and the third scan signal end Gate3 are low level signals. The signals of the first scan signal end Gate1 and the third scan signal end Gate3 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off, respectively. The signal of the second scan signal end Gate2 is a high level signal, and the ninth transistor T9 is turned on. The voltage of the reference signal end Vref is written to the signal holding capacitor C hdgItself charges or discharges, and the threshold voltage of the driving transistor T3 begins to be generated. During the generation of the threshold voltage of the driving transistor T3, the bias capacitor C bst The bias between the control electrode and the first electrode of the driving transistor T3 is maintained until the threshold voltage V th The generation process ends. At this time, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0194] Fig. 8B is a timing diagram of the pixel driving circuit provided in Fig. 7B. The working process of the pixel driving circuit exemplified by Fig. 7B is described below. The pixel driving circuit can generate and store the threshold voltage of the driving transistor in the refresh frame between two adjacent display frames (e.g., the (n-1)th frame display driving and the nth frame display driving, where n is an integer). The working process of the pixel driving circuit can include:

[0195] The first stage S1 is called the reset stage and the refresh stage. The signals of the first scan signal end Gate1 and the third scan signal end Gate3 are low-level signals, and the signals of the second scan signal end Gate2 and the first light-emitting signal end EM1 are high-level signals. The signals of the first scan signal end Gate1 and the third scan signal end Gate3 are low-level signals, the fourth transistor T4 is turned on, the voltage of the initial signal end line Vinit is written to the first node, and the signal holding capacitor C hdg The initialization of the voltage variation end. The fifth transistor T5 is turned on, and the voltage of the first bias signal end Vbas is written to the signal holding capacitor C hdg The voltage reference end (i.e., the second node N2) and the bias capacitor C bst The first end of the bias capacitor C bst The pre-bias. The first transistor T1 is turned on, and the voltage V bst of the data signal end Data is written to the bias capacitor C dt The second transistor T2 is turned on, and the voltage value V bst of the reference signal end Vref is written to the second end of the bias capacitor C ref At this time, the voltage value V ref of the reference signal end Vref and the voltage V dt of the data signal end Data are different (V ref -V dt ), which is used as the pre-bias voltage of the bias capacitor C bst . At this time, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. In this stage, the light-emitting device L does not emit light.

[0196] The second stage S2 is called the threshold voltage V thDuring the generation phase, the signal at the second scan signal terminal Gate2 is a low-level signal, while the signals at the first light emission signal terminal EM1, the first scan signal terminal Gate1, and the third scan signal terminal Gate3 are all high-level signals. When the signals at the first scan signal terminal Gate1 and the third scan signal terminal Gate3 are high-level signals, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. When the signal at the second scan signal terminal Gate2 is low-level, the ninth transistor T9 is turned on, and the signal holding capacitor C... hdg The transistor charges or discharges itself, starting to generate the threshold voltage for driving transistor T3. During the generation of the threshold voltage for driving transistor T3, the bias capacitor C... bst Maintain the bias voltage between the control electrode and the first electrode of the driving transistor T3 until the threshold voltage V of the driving transistor T3 is reached. th The generation process is complete. Meanwhile, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are disconnected.

[0197] In this embodiment of the disclosure, the threshold voltage V of the driving transistor T3 th After the generation process is completed, the voltage difference V between the control electrode signal and the second electrode signal of the driving transistor T3 is... gs The threshold voltage V for driving transistor T3 th And held by signal capacitor C hdg and bias capacitor C bst Series connection. Short-circuit bias capacitor C during signal superposition. bst V is equivalent to the voltage difference V of the signal driving the second electrode of transistor T3. gs At the threshold voltage V th A difference V was superimposed on top of it. ref -V dt The signal voltage. The voltage V at the refresh data signal terminal (Data). dt At that time, the difference V can be... ref -V dt The signal voltage is used as the bias capacitor C bst The pre-bias voltage is maintained so that the threshold voltage V th After the generation process is completed, the voltage V at the data signal terminal Data... dt It can be directly compared with the threshold voltage V th Coupling, i.e., threshold voltage V th During the generation process, the bias capacitor C bst Also serves as a refresher V dt The capacitor is held in place to achieve the voltage V at the data signal terminal Data. dt and the threshold voltage V of the driving transistor T3 th Superimposed coupling can improve pixel circuit structure and layout efficiency.

[0198] Figure 9 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment. As shown in Figure 9, in an example embodiment, the at least one first control signal terminal Con1 can include a first scan signal terminal Gate1, a third scan signal terminal Gate3 and a first light emitting signal terminal EM1, the at least one second control signal terminal Con2 can include the first scan signal terminal Gate1, the third scan signal terminal Gate3 and a second scan signal terminal Gate2, and the at least one third control signal terminal Con3 includes the first light emitting signal terminal EM1. The signal holding sub-circuit can include a signal holding capacitor C hdg , a first switch element SW1, a second switch element SW2 and a third switch element SW3, and the preset bias sub-circuit can include a bias capacitor C bst , a fourth switch element SW4 and a fifth switch element SW5. The first switch element SW1 includes a fourth transistor T4, the second switch element SW2 includes a sixth transistor T6, the third switch element SW3 includes a second transistor T2 and a tenth transistor T10, the fourth switch element SW4 includes a fifth transistor T5, the fifth switch element SW5 includes a ninth transistor T9, and the sixth switch element includes an eighth transistor T8.

[0199] In an example embodiment, as shown in Figure 9, the signal holding capacitor C hdg is electrically connected to the first node N1 and the control electrode of the driving transistor T3, respectively; and the bias capacitor C bst is electrically connected to the control electrode of the driving transistor T3 and the fourth node N4, respectively. The control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the reference signal terminal Vref, and the second electrode of the second transistor T2 is electrically connected to the control electrode of the driving transistor T3 and the bias capacitor C bstThe first terminal of the fourth transistor T4 is electrically connected; the control terminal of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the first node N1, and the second terminal of the fourth transistor T4 is electrically connected to the initial signal terminal Vinit; the control terminal of the fifth transistor T5 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fifth transistor T5 is electrically connected to the first bias signal terminal Vbas, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the first light emission signal terminal EM1, the first terminal of the sixth transistor T6 is electrically connected to the first power supply terminal Vdd, and the second terminal of the sixth transistor T6 is electrically connected to the first terminal of the driving transistor. The control electrode of the eighth transistor T8 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the first electrode of the light-emitting device L. The control electrode of the ninth transistor T9 is electrically connected to the second scan signal terminal Gate2, the first electrode of the ninth transistor T9 is electrically connected to the fourth node N4, and the second electrode of the ninth transistor T9 is connected to the first electrode of the driving transistor. The control electrode of the tenth transistor T10 is electrically connected to the third scan signal terminal Gate3, the first electrode of the tenth transistor T10 is electrically connected to the reference signal terminal Vref, and the second electrode of the tenth transistor T10 is connected to both the control electrode of the driving transistor T3 and the bias capacitor C. bst The first terminal is electrically connected.

[0200] In one exemplary embodiment, as shown in FIG9, the pixel driving circuit may further include: a first transistor T1, a seventh transistor T7, and an eleventh transistor T11, and a signal holding capacitor C. hdg Bias capacitor C bst The second terminal of the first transistor T1 and the second terminal of the second transistor T2 are electrically connected to the control terminal of the driving transistor T3 through the seventh transistor T7; the control terminal of the first transistor T1 is electrically connected to the third scan signal terminal Gate3, the first terminal of the first transistor T1 is electrically connected to the data signal terminal Data, and the second terminal of the first transistor T1 is electrically connected to the fourth node N4; the control terminal of the seventh transistor T7 is electrically connected to the second scan signal terminal Gate2, the first terminal of the seventh transistor T7 is electrically connected to the control terminal of the driving transistor T3 (i.e., the fifth node N5), and the second terminal of the seventh transistor T7 is electrically connected to the second node N2; the control terminal of the eleventh transistor T11 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the eleventh transistor T11 is electrically connected to the control terminal of the driving transistor T3 (i.e., the fifth node N5), and the second terminal of the eleventh transistor T11 is electrically connected to the fourth node N4.

[0201] In one example embodiment, as shown in FIG9, the first transistor T1 to the eleventh transistor T11 can be N-type transistors.

[0202] An example structure of the pixel driving circuit is shown in FIG. 9. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0203] FIG. 10 is a timing diagram of the pixel driving circuit provided in FIG. 9. The working process of the pixel driving circuit exemplified by FIG. 9 is described below to illustrate the example embodiments of the present disclosure. The pixel driving circuit can generate and store the threshold voltage of the driving transistor in the refresh frame between two adjacent display frames (e.g., the n-1 frame display driving and the n frame display driving, n is an integer). The working process of the pixel driving circuit can include:

[0204] The first stage S1 is called the reset stage. The signal of the first scan signal end Gate1 is a high level signal, and the signals of the second scan signal end Gate2, the third scan signal end Gate3 and the first light emitting signal end EM1 are all low level signals. The signal of the first scan signal end Gate1 is a high level signal, the second transistor T2 is turned on, and the voltage of the reference signal end Vref is written to the second node N2; the fourth transistor T4 is turned on, and the voltage of the initial signal end line Vinit is written to the first node N1, completing the initialization of the signal holding capacitor C hdg . The fifth transistor T5 is turned on, and the voltage of the first bias signal end Vbas is written to the first end (i.e., the fourth node N4) of the bias capacitor C bst , completing the pre-bias of the bias capacitor C bst . Among them, the first transistor T1, the sixth transistor T6 to the eleventh transistor T11 are turned off. In this stage, the light emitting device L does not emit light.

[0205] The second stage S2 is called the threshold voltage V th generation stage. The signal of the second scan signal end Gate2 is a high level signal, and the signals of the first scan signal end Gate1, the third scan signal end Gate3 and the first light emitting signal end EM1 are all low level signals. The signal of the first scan signal end Gate1 is a low level signal, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off respectively. The signal of the second scan signal end Gate2 is a high level signal, the seventh transistor T7 is turned on, the ninth transistor T9 is turned on, and the signal holding capacitor C hdg and the bias capacitor C bst interact to charge or discharge, starting to generate the threshold voltage of the driving transistor T3. During the generation process of the threshold voltage of the driving transistor T3, the bias capacitor C bst maintains the bias between the control electrode and the first electrode of the driving transistor T3 until the threshold voltage V th generation process of the driving transistor T3 is completed. Among them, the first transistor T1, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are turned off.

[0206] The third stage, S3, is called the refresh stage. During this stage, the signals at the third scan signal terminal (Gate3) are all high, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), and the second scan signal terminal (Gate2) are all low. When the signal at the second scan signal terminal (Gate2) is low, the seventh transistor (T7) and the ninth transistor (T9) are turned off. When the signal at the third scan signal terminal (Gate3) is high, the first transistor (T1) is turned on, and the bias capacitor C... bst The voltage value V written to the data signal terminal Data dt The tenth transistor T10 is turned on, and the voltage value Vref at the reference signal terminal is V. ref Write to the second node N2 (that is, the signal holding capacitor C) hdg and bias capacitor C bst (connection terminal), at this time, the voltage value V of the reference signal terminal Vref is... ref Voltage V at the data signal terminal Data dt The difference (V) ref -V dt ) as bias capacitor C bst The pre-bias voltage. Among them, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the eighth transistor T8 and the eleventh transistor T11 are disconnected.

[0207] In this embodiment of the disclosure, the threshold voltage V of the driving transistor T3 th After the generation process is completed, the voltage difference V between the control electrode signal and the second electrode signal of the driving transistor T3 is... gs The threshold voltage V for driving transistor T3 th And held by signal capacitor C hdg and bias capacitor C bst Series connection. Short-circuit bias capacitor C during signal superposition. bst V is equivalent to the voltage difference V of the signal driving the second electrode of transistor T3. gs At the threshold voltage V th A difference V was superimposed on top of it. ref -V dt The signal voltage. The voltage V at the refresh data signal terminal (Data). dt At that time, the difference V can be... ref -V dt The signal voltage is used as the bias capacitor C bst The pre-bias voltage is maintained so that the threshold voltage V th After the generation process is completed, the voltage V at the data signal terminal Data... dt It can be directly compared with the threshold voltage V th Coupling, i.e., threshold voltage V thThe bias voltage capacitor C in the generation process bst Serves as refresh V th The voltage V of the data signal end Data is realized by the superposition coupling of the threshold voltage V of the driving transistor T3 and the holding capacitor. dt And the threshold voltage V of the driving transistor T3 th The superposition coupling can improve the pixel circuit structure and layout efficiency.

[0208] The display device provided in the embodiments of the present disclosure includes a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided in any one of the preceding embodiments, and has similar implementation principles and effects, which will not be described here.

[0209] The driving method of the voltage generation circuit provided in the embodiments of the present disclosure includes the following steps.

[0210] The signal holding sub-circuit controls the signal of the second electrode of the driving transistor under the control of the signals of the at least one control signal end and the initial signal end.

[0211] The preset bias sub-circuit controls the signal of the control electrode of the driving transistor under the control of the signals of the at least one control signal end and the reference signal end.

[0212] In the partial time period, the difference between the voltage value of the signal of the control electrode of the driving transistor and the voltage value of the signal of the second electrode of the driving transistor is the threshold voltage of the driving transistor.

[0213] The voltage generation circuit provided in the embodiments of the present disclosure includes the following steps.

[0214] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0215] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0216] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A voltage generation circuit electrically connected to a drive transistor in a pixel drive circuit, configured to generate a threshold voltage of the drive transistor, the drive transistor comprising: The control electrode, the first electrode and the second electrode, the first electrode of the drive transistor is electrically connected with the first power supply end; The voltage generating circuit comprises a signal holding sub-circuit and a preset bias sub-circuit; The signal holding sub-circuit is electrically connected with at least one first control signal end, an initial signal end and the second electrode of the drive transistor respectively, and is configured to control the signal of the second electrode of the drive transistor under the control of the signals of the at least one control signal end and the initial signal end; The preset bias sub-circuit is electrically connected with at least one second control signal end, a reference signal end, the control electrode and the first electrode of the drive transistor respectively, and is configured to control the signal of the control electrode of the drive transistor under the control of the signals of the at least one control signal end and the reference signal end; The difference between the voltage value of the signal of the control electrode of the drive transistor and the voltage value of the signal of the second electrode of the drive transistor is the threshold voltage of the drive transistor in a part of time period.

2. The voltage generation circuit of claim 1, wherein, The signal holding sub-circuit is further electrically connected with a first bias signal end, and the at least one first control signal end comprises a first sub-control signal end and a second sub-control signal end.

3. The voltage generation circuit of claim 2, wherein, The signal holding sub-circuit comprises a signal holding capacitor, a first switching element and a second switching element; The first switching element is configured to be turned on or turned off under the control of the signal of the first sub-control signal end, and the second switching element is configured to be turned on or turned off under the control of the signal of the second sub-control signal end; The signal holding capacitor is electrically connected with the first bias signal end and a first node respectively, the first switching element is electrically connected with the initial signal end and the first node respectively, and the second switching element is electrically connected with the first node and the second electrode of the drive transistor respectively.

4. The voltage generation circuit of claim 1, wherein, The preset bias sub-circuit is further electrically connected with the first power supply end, and the at least one second control signal end comprises a third sub-control signal end.

5. The voltage generation circuit of claim 4, wherein, The preset bias sub-circuit comprises a bias capacitor and a third switching element; The third switching element is configured to be turned on or turned off under the control of the signal of the third sub-control signal end; The first end of the bias capacitor is electrically connected with the first power supply end, the second end of the bias capacitor is electrically connected with the control electrode of the drive transistor, and the third switching element is electrically connected with the reference signal end and the control electrode of the drive transistor respectively.

6. The voltage generation circuit of claim 4, wherein, The voltage value of the initial signal end is less than the difference between the voltage value of the reference signal end and the voltage value of the threshold voltage of the drive transistor; The difference between the voltage value of the first power supply end and the voltage value of the reference signal end is greater than the negative value of the voltage value of the threshold voltage of the drive transistor.

7. The voltage generation circuit of claim 1, wherein, The signal holding sub-circuit is further electrically connected with the first electrode of the drive transistor and the first bias signal end, and the at least one first control signal end comprises a first sub-control signal end, a second sub-control signal end, a fourth sub-control signal end and a fifth sub-control signal end.

8. The voltage generation circuit of claim 7, wherein, The signal holding sub-circuit comprises a signal holding capacitor, a first switching element, a second switching element, a fourth switching element and a fifth switching element; The first switch element is configured to be turned on or off under the control of a signal at a first sub-control signal terminal, the second switch element is configured to be turned on or off under the control of a signal at a second sub-control signal terminal, the fourth switch element is configured to be turned on or off under the control of a signal at a fourth sub-control signal terminal, and the fifth switch element is configured to be turned on or off under the control of a signal at a fifth sub-control signal terminal. The signal holding capacitor is electrically connected to the first node and the second node respectively, the first switch element is electrically connected to the initial signal terminal and the first node respectively, the second switch element is electrically connected to the first node and the second electrode of the drive transistor respectively, the fourth switch element is electrically connected to the first bias signal terminal and the second node respectively, and the fifth switch element is electrically connected to the second node and the first electrode of the drive transistor respectively.

9. The voltage generation circuit of claim 1, wherein, The preset bias sub-circuit is further electrically connected to the first electrode of the drive transistor and the first bias signal terminal, and the at least one second control signal terminal includes a third sub-control signal terminal, a fourth sub-control signal terminal and a fifth sub-control signal terminal.

10. The voltage generation circuit of claim 9, wherein, The preset bias sub-circuit includes a bias capacitor, a third switch element, a fourth switch element and a fifth switch element. The third switch element is configured to be turned on or off under the control of a signal at a third sub-control signal terminal, the fourth switch element is configured to be turned on or off under the control of a signal at a fourth sub-control signal terminal, and the fifth switch element is configured to be turned on or off under the control of a signal at a fifth sub-control signal terminal. The bias capacitor is electrically connected to the control electrode of the drive transistor and the second node respectively, the third switch element is electrically connected to the reference signal terminal and the control electrode of the drive transistor respectively, the fourth switch element is electrically connected to the first bias signal terminal and the second node respectively, and the fifth switch element is electrically connected to the second node and the first electrode of the drive transistor respectively. The difference between the voltage value of the first bias signal terminal and the voltage value of the reference signal terminal is greater than the negative value of the threshold voltage of the drive transistor.

11. The voltage generation circuit of claim 10, wherein, The difference between the voltage value of the first bias signal terminal and the voltage value of the initial signal terminal is greater than the sum of the first voltage difference and the threshold voltage of the drive transistor, and the first voltage difference is the difference between the voltage value of the first bias signal terminal and the voltage value of the reference signal terminal. The signal holding sub-circuit is further electrically connected to the control electrode of the drive transistor and the reference signal terminal, and the at least one first control signal terminal includes a first sub-control signal terminal, a second sub-control signal terminal and a third sub-control signal terminal.

12. The voltage generation circuit of claim 1, wherein, The signal holding sub-circuit includes a signal holding capacitor, a first switch element, a second switch element and a third switch element.

13. The voltage generation circuit of claim 12, wherein, The first switch element is configured to be turned on or off under the control of a signal at a first sub-control signal terminal, the second switch element is configured to be turned on or off under the control of a signal at a second sub-control signal terminal, and the third switch element is configured to be turned on or off under the control of a signal at a third sub-control signal terminal. ​ The signal holding capacitor is electrically connected with the control electrode of the driving transistor and the first node respectively, the first switch element is electrically connected with the initial signal terminal and the first node respectively, the second switch element is electrically connected with the first node and the second electrode of the driving transistor respectively, and the third switch element is electrically connected with the reference signal terminal and the control electrode of the driving transistor respectively.

14. The voltage generation circuit of claim 13, wherein, The preset biasing sub-circuit is further electrically connected with the first electrode of the driving transistor and the first biasing signal terminal, and the at least one second control signal terminal comprises a third sub-control signal terminal, a fourth sub-control signal terminal and a fifth sub-control signal terminal.

15. The voltage generation circuit of claim 14, wherein, The preset biasing sub-circuit comprises a biasing capacitor, a third switch element, a fourth switch element and a fifth switch element. The third switch element is configured to be turned on or turned off under the control of the signal of the third sub-control signal terminal, the fourth switch element is configured to be turned on or turned off under the control of the signal of the fourth sub-control signal terminal, and the fifth switch element is configured to be turned on or turned off under the control of the signal of the fifth sub-control signal terminal. The biasing capacitor is electrically connected with the control electrode of the driving transistor and the fourth node respectively, the third switch element is electrically connected with the reference signal terminal and the control electrode of the driving transistor respectively, the fourth switch element is electrically connected with the first biasing signal terminal and the fourth node respectively, and the fifth switch element is electrically connected with the fourth node and the first electrode of the driving transistor respectively.

16. The voltage generation circuit of claim 14, wherein, The difference between the voltage value of the first biasing signal terminal and the voltage value of the reference signal terminal is greater than the sum of the second voltage difference and the threshold voltage of the driving transistor, and the second voltage difference is the difference between the voltage value of the reference signal terminal and the voltage value of the initial signal terminal. The difference between the voltage value of the initial signal terminal and the voltage value of the reference signal terminal is less than the threshold voltage of the driving transistor.

17. A pixel driving circuit, comprising: The driving transistor and the voltage generation circuit according to any one of claims 1 to 16.

18. The pixel driving circuit of claim 17, wherein, The pixel driving circuit further comprises a sixth switch element configured to be turned on or turned off under the control of the signal of the at least one third control signal terminal. The sixth switch element is electrically connected with the second electrode of the driving transistor and the first electrode of the light emitting device respectively.

19. The pixel driving circuit of claim 18, wherein, The at least one first control signal terminal comprises a first scan signal terminal and a first light emitting signal terminal, the at least one second control signal terminal comprises the first scan signal terminal, the at least one third control signal terminal comprises a second light emitting signal terminal, the signal holding sub-circuit comprises a signal holding capacitor, a first switch element and a second switch element, the preset biasing sub-circuit comprises a biasing capacitor and a third switch element, the first switch element comprises a fourth transistor, the second switch element comprises a sixth transistor, the third switch element comprises a second transistor, and the sixth switch element comprises an eighth transistor. The signal holding capacitor is electrically connected with the first biasing signal terminal and the first node respectively. The first end of the biasing capacitor is electrically connected with the first power terminal, and the second end of the biasing capacitor is electrically connected with the control electrode of the driving transistor. The control electrode of the second transistor is electrically connected with the first scan signal end, the first electrode of the second transistor is electrically connected with the reference signal end, and the second electrode of the second transistor is electrically connected with the control electrode of the driving transistor and the first end of the biasing capacitor respectively; The control electrode of the fourth transistor is connected with the first scan signal end, the first electrode of the fourth transistor is electrically connected with the first node, and the second electrode of the fourth transistor is electrically connected with the initial signal end; The control electrode of the sixth transistor is electrically connected with the first light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the first electrode of the driving transistor; The control electrode of the eighth transistor is electrically connected with the second light-emitting signal end, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the first electrode of the light-emitting device.

20. The pixel driving circuit of claim 19, wherein, The pixel driving circuit further comprises a first transistor and a fifth transistor, and the signal holding capacitor and the biasing capacitor are electrically connected with the first biasing signal end through the fifth transistor respectively; The control electrode of the first transistor is electrically connected with the third scan signal end, the first electrode of the first transistor is electrically connected with the data signal end, and the second electrode of the first transistor is electrically connected with the first end of the biasing capacitor; The control electrode of the fifth transistor is electrically connected with the second scan signal end, the first electrode of the fifth transistor is electrically connected with the first end of the biasing capacitor and the signal holding capacitor, and the second electrode of the fifth transistor is electrically connected with the first biasing signal end.

21. The pixel driving circuit of claim 18, wherein, The at least one first control signal end comprises one of the first scan signal end and the third scan signal end, the second scan signal end and the first light-emitting signal end, the at least one second control signal end comprises one of the first scan signal end and the third scan signal end and the second scan signal end, and the at least one third control signal end comprises the first light-emitting signal end; the signal holding sub-circuit comprises a signal holding capacitor, a first switching element, a second switching element, a fourth switching element and a fifth switching element, and the preset biasing sub-circuit comprises a biasing capacitor, a third switching element to a fifth switching element; the first switching element comprises a fourth transistor, the second switching element comprises a sixth transistor, the third switching element comprises a second transistor, the fourth switching element comprises a fifth transistor, the fifth switching element comprises a ninth transistor, and the sixth switching element comprises an eighth transistor; The signal holding capacitor is electrically connected with the first node and the second node respectively; The biasing capacitor is electrically connected with the control electrode of the driving transistor and the second node respectively; The control electrode of the second transistor is electrically connected with one of the first scan signal end and the third scan signal end, the first electrode of the second transistor is electrically connected with the reference signal end, and the second electrode of the second transistor is electrically connected with the control electrode of the driving transistor and the first end of the biasing capacitor respectively; The control electrode of the fourth transistor is connected with one of the first scan signal end and the third scan signal end, the first electrode of the fourth transistor is electrically connected with the first node, and the second electrode of the fourth transistor is electrically connected with the initial signal end. The control electrode of the fifth transistor is electrically connected with one of the first scan signal end and the third scan signal end, the first electrode of the fifth transistor is electrically connected with the first bias signal end, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the first light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the first electrode of the driving transistor; The control electrode of the eighth transistor is electrically connected with the first light-emitting signal end, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the first electrode of the light-emitting device; The control electrode of the ninth transistor is electrically connected with the second scan signal end, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the first electrode of the driving transistor. The pixel driving circuit further comprises a first transistor and a seventh transistor; 22. The pixel driving circuit of claim 21, wherein, The control electrode of the first transistor is electrically connected with one of the first scan signal end and the third scan signal end, the first electrode of the first transistor is electrically connected with the data signal end, and the second electrode of the first transistor is electrically connected with the second node; The control electrode of the seventh transistor is electrically connected with the first light-emitting signal end, the first electrode of the seventh transistor is electrically connected with the control electrode of the driving transistor, and the second electrode of the seventh transistor is electrically connected with the second node. The at least one first control signal end can comprise the first scan signal end, the third scan signal end and the first light-emitting signal end, the at least one second control signal end can comprise the first scan signal end, the third scan signal end and the second scan signal end, the at least one third control signal end comprises the first light-emitting signal end, the signal holding sub-circuit can comprise a signal holding capacitor, a first switching element, a second switching element and a third switching element, the preset bias sub-circuit can comprise a bias capacitor, a third switching element, a fourth switching element and a fifth switching element, the first switching element comprises a fourth transistor, the second switching element comprises a sixth transistor, the third switching element comprises a second transistor and a tenth transistor, the fourth switching element comprises a fifth transistor, the fifth switching element comprises a ninth transistor, and the sixth switching element comprises an eighth transistor; 23. The pixel driving circuit of claim 18, wherein, ​ The signal holding capacitor is electrically connected with the first node and the control electrode of the driving transistor respectively; the bias capacitor is electrically connected with the control electrode of the driving transistor and the fourth node respectively; the control electrode of the second transistor is electrically connected with the first scanning signal terminal, the first electrode of the second transistor is electrically connected with the reference signal terminal, and the second electrode of the second transistor is electrically connected with the control electrode of the driving transistor and the first end of the bias capacitor respectively; the control electrode of the fourth transistor is electrically connected with the first scanning signal terminal, the first electrode of the fourth transistor is electrically connected with the first node, and the second electrode of the fourth transistor is electrically connected with the initial signal terminal; the control electrode of the fifth transistor is electrically connected with the first scanning signal terminal, the first electrode of the fifth transistor is electrically connected with the first bias signal terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node; the control electrode of the sixth transistor is electrically connected with the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected with the first power terminal, and the second electrode of the sixth transistor is electrically connected with the first electrode of the driving transistor; the control electrode of the eighth transistor is electrically connected with the first light-emitting signal terminal, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the first electrode of the light-emitting device; the control electrode of the ninth transistor is electrically connected with the second scanning signal terminal, the first electrode of the ninth transistor is electrically connected with the fourth node, and the second electrode of the ninth transistor is electrically connected with the first electrode of the driving transistor; the control electrode of the tenth transistor is electrically connected with the third scanning signal terminal, the first electrode of the tenth transistor is electrically connected with the reference signal terminal, and the second electrode of the tenth transistor is electrically connected with the control electrode of the driving transistor and the first end of the bias capacitor. The pixel driving circuit can further comprise: a first transistor, a seventh transistor and an eleventh transistor, the signal holding capacitor, the second end of the bias capacitor and the second electrode of the second transistor being electrically connected with the control electrode of the driving transistor through the seventh transistor; 24. The pixel driving circuit of claim 23, wherein, The control electrode of the first transistor is electrically connected with the third scanning signal terminal, the first electrode of the first transistor is electrically connected with the data signal terminal, and the second electrode of the first transistor is electrically connected with the fourth node; the control electrode of the seventh transistor is electrically connected with the second scanning signal terminal, the first electrode of the seventh transistor is electrically connected with the control electrode of the driving transistor, and the second electrode of the seventh transistor T7 is electrically connected with the second node; the control electrode of the eleventh transistor is electrically connected with the first light-emitting signal terminal, the first electrode of the eleventh transistor is electrically connected with the control electrode of the driving transistor, and the second electrode of the eleventh transistor is electrically connected with the fourth node. The pixel driving circuit according to any one of claims 17 to 24.

25. A display device comprising:

26. A driving method of a voltage generation circuit configured to drive the voltage generation circuit according to any one of claims 1 to 16, the method comprising: controlling, by the signal holding sub-circuit, the signal of the second electrode of the driving transistor under the control of the signals of the at least one control signal terminal and the initial signal terminal; controlling, by the preset bias sub-circuit, the signal of the control electrode of the driving transistor under the control of the signals of the at least one control signal terminal and the reference signal terminal; in a part of the time period, the difference between the voltage value of the signal of the control electrode of the driving transistor and the voltage value of the signal of the second electrode of the driving transistor is the threshold voltage of the driving transistor. ​

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