Power switch short circuit protection

Abstract

A short circuit protection circuit includes: an HEMT (High Electron Mobility Transistor) including a source, a drain, and a gate, the HEMT being capable of being controlled to be ON and OFF by a voltage applied to the gate; a comparator having an input coupled to the high pass filter and an output at which, if the voltage filtered by the filter exhibits a voltage surge greater than a threshold voltage, the comparator generates an output signal in response to the voltage induced across the inductor; and a voltage divider controllable to be turned on and off to control a voltage provided to a gate of the HEMT, and wherein the voltage divider is turned on in response to an output signal from the comparator to provide a reduced voltage to the gate, the reduced voltage being less than a turn-on threshold voltage of the HEMT.

Description

[0001] field Embodiments of the present invention relate to providing short-circuit protection for power switches.

[0002] background Almost all types of modern optical and electronic devices (from computers to powertrains) include power switching circuits for generating timing pulses, data packets, and / or delivering power. To deliver power to electric powertrains, such as those used to power electric vehicles, power switches capable of rapidly switching on and off to couple high-voltage power to and decouple from the load are required. III-V high electron mobility transistors (HEMTs), such as GaN (gallium nitride) transistors, are particularly advantageous for this application. III-V HEMTs are wide-bandgap transistors characterized by high breakdown voltage, high current density, and low on-state resistance, enabling operation at high frequencies, making them suitable for providing power to operate the traction motors of modern automotive electric powertrains.

[0003] Although HEMTs can be normally-on, depletion-mode (D-type), or normally-off enhancement-mode (E-type) transistors, D-type HEMTs are generally more advantageous for high-power and current-switching applications, especially because they are characterized by lower on-resistance (R0). on Furthermore, it can support higher current densities. However, since D-type HEMTs are typically normally-on power switching circuits that use HEMT transistors as switching elements, a controller is required to continuously control the on / off states of the transistors, keeping them off as long as they are coupled to the power supply and do not need to be turned on to switch power from the power supply to the load. For high-frequency switching applications (such as powering automotive electric traction motors), the controller typically needs to switch them between on and off at high frequencies with high time resolution.

[0004] Without such control, for example, if the switching circuit is connected to the power supply before it is connected to the controller, or if the controller or HEMT transistor fails during operation, large current transients and / or short circuits may occur, which could damage the power switch, load, and / or power supply.

[0005] Overview One aspect of embodiments of this disclosure relates to providing a power switch including a HEMT transistor and a short-circuit protection circuit configured to detect the onset of a short circuit in a circuit including the power switch with a relatively small time delay, and to respond quickly to the detection to mitigate and prevent the development of the short circuit. The short-circuit protection circuit may be referred to as a "short-stop" circuit or simply as a "short-circuit protection device".

[0006] In one embodiment, the power switch includes a cascode of a D-type (depletion-mode) HEMT connected in series with a MOSFET (metal-semiconductor field-effect transistor). When the power switch operates to couple a load to a DC power supply, a controller included in the power switch turns on the MOSFET transistor and turns the HEMT transistor on and off to supply power to the load using voltage pulses from the power supply. As an example, the voltage pulse may be a pulse width modulation (PWM) pulse, configured to supply power to the load using power that varies harmonicly with time at a desired frequency. A short-circuit protection device includes a comparator that generates an output signal in response to a voltage generated by the current flowing through the stray inductance of the MOSFET in the cascode. When the current through the stray inductance of the MOSFET generates a fast-rise time surge voltage exceeding a predetermined voltage threshold, indicating the onset of a short circuit, the short-circuit protection device operates to turn off the HEMT transistor and cut off the current through the cascode. Alternatively, the short-circuit protection device may first operate to regulate the current through the cascode and then turn off the HEMT to prevent current from flowing through the cascode, thereby preventing further development of the short circuit.

[0007] This overview is provided to introduce, in a simplified form, some selected concepts that are further described in the detailed description below. This overview is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Brief description of the attached diagram Non-limiting examples of embodiments of the invention are described below with reference to the accompanying drawings listed after this paragraph. Identical structures, elements, or parts appearing in more than one drawing are generally labeled with the same numerals in all the drawings in which they appear. The dimensions of parts and features shown in the drawings are chosen for ease of presentation and clarity and are not necessarily shown to scale.

[0009] Figure 1A A schematic diagram of a power switch according to an embodiment of the present disclosure is shown. The power switch includes a common-source cascode protected by short-circuit protection and operates to couple a power supply to a load; and Figure 1B An embodiment according to this disclosure is illustrated schematically. Figure 1A The power switch and short-circuit protection device shown herein detect the onset of a short circuit and operate to regulate the current through the cascode, and then turn off the current through the cascode.

[0010] Detailed description In the discussion, unless otherwise stated, adjectives such as “substantially” and “approximately” modifying conditional or relational features of one or more features of embodiments of this disclosure should be understood to indicate that the condition or feature is defined within acceptable tolerances for operation of the embodiments to which it is intended to be applied. Wherever generic terms in this disclosure are explained by reference to example instances or lists of example instances, the one or more instances mentioned are non-limiting example instances of the generic terms, and the generic terms are not intended to be limited to the one or more specific example instances mentioned. The phrase “in embodiments,” whether or not associated with a license, such as “may,” “optionally,” or “as an example,” is used to introduce examples for consideration but is not necessarily a desired configuration of possible embodiments of this disclosure. Unless otherwise stated, the word “or” in the specification and claims is considered inclusive rather than exclusive and means any combination of at least one or more of the items it combines.

[0011] Figure 1A A power switch 100 according to an embodiment of the present disclosure is schematically illustrated. The power switch 100 includes a cascode 50 and a short-circuit protection device 20. The power switch operates to supply power to a load L using power from an optional high-voltage power supply HV. Optionally, the cascode 50 is connected in series with the power supply HV and the load L between nodes 61 and 62. In an embodiment, the cascode includes a HEMT, optionally a D-type n-channel GaN transistor 51, connected in series at an intermediate node 53 with an optional n-channel MOSFET transistor 52. The HEMT 51 has a source S... 51 Gate G 51 and drain D 51 MOSFET 52 has a source S 52 Gate G 52 and drain D 52 Furthermore, it is characterized by a drain stray inductance L1 and a source stray inductance L2, respectively. The short-circuit protection device 20 may optionally include a comparator 22, a latch 24, and a voltage divider circuit 40.

[0012] HEMT gate G 51 Optionally, it is connected to the gate driver 32 via a buffer 34. The buffer 34 is connected to the gate driver via a voltage divider circuit 40, which may include resistors R1 and R2 and a switch, optionally an n-channel MOSFET transistor 28. A power supply (not shown) provides the same voltage V relative to signal ground 70 for the top rail voltage of node 53 and buffer 34. CC When enabled by an optional enable signal from NAND circuit 30, gate driver 32 generates output signal P32 in response to input signal P31 and transmits output signal P32 to buffer 34. Optionally, as Figure 1A As schematically shown, the input signal P31 is a positive PWM pulse, and the output signal P32 propagating to the buffer 34 is a corresponding positive PWM pulse with a voltage referred to as voltage V-P32. The buffer 34 generates a bias gate G in response to the voltage pulse it receives from the gate driver 32. 51 The output pulse is used to control the on / off state of HEMT 51. Optionally, the pulse generated by buffer 34 is proportional to the pulse received from gate driver 32. Optionally, buffer 34 is a buffer voltage follower.

[0013] When transistor 28 is turned off, as Figure 1A As schematically shown via the "raised" gate G28 of transistor 28, voltage divider 40 is turned off, and essentially only the voltage divider's R1 affects the voltage of the pulse P32 arriving at buffer 34 from gate driver 32. When voltage divider 40 is off, the voltage of pulse P32 arriving at buffer 34 has a voltage optionally referred to as voltage V-P32, and in response to pulse P32 arriving at buffer 34, buffer generates pulse P34 with voltage V-P34. When transistor 28 is on, as discussed below... Figure 1B As schematically shown, the pulse generated by the gate driver 32 that arrives at the buffer 34 after passing through R1 has a voltage reduction of R2 / (R1+R2) times, and is referred to as the reduced voltage pulse P32', characterized by a reduced voltage V-P32'. In response to receiving the reduced voltage pulse P32', the buffer 34 generates a reduced pulse P34' exhibiting a reduced voltage V-P34'.

[0014] If the voltage divider circuit 40 is turned on during the pulse width of the "parent" pulse P32 that generates it, the reduced voltage pulse P32' may present a reduced voltage V-P32' only for a portion of its duration. If the voltage divider circuit 40 is turned on before the start of the parent pulse, the reduced voltage pulse P32' may present a reduced voltage V-P32' for its entire duration. Similarly, the reduced voltage pulse P34' generated by the buffer 34 in response to the voltage pulse P32' received from the gate driver 32 may present a reduced voltage for all or only a portion of the pulse width of P34'.

[0015] In this embodiment, the resistors R1 and R2 of the voltage divider can be determined according to the following constraints: 1) When the voltage divider 40 is turned off, the buffer 34 biases the gate G with voltage V-P34 generated by the pulse P34 generated in response to the pulse P32 that has passed through R1. 511) To turn on HEMT 51; 2) When the voltage divider is turned on, the buffer 34 generates one or more pulses P34' with a reduced voltage V-P34', which is a moderate voltage difference lower than the turn-on threshold of HEMT 51. This causes the feed from buffer 34 to gate G to be delivered. 51 The voltage drop reduces the current through the cascode 50, thereby reducing the probability of large voltage transients; and 3) when on, the voltage divider resistors R1+R2 are advantageously large enough to prevent the amount of current drawn from the gate driver 32 that could damage the gate driver.

[0016] According to embodiments of this disclosure, the gate driver 32 is coupled to the HEMT gate G via buffer 34. 51 The relatively large values ​​of the voltage divider resistors R1 and R2 are achieved, thereby providing a favorable reduction in the voltage of pulse 32 when the voltage divider is on. Furthermore, when the voltage divider is off, the buffer will combine the voltage pulse from the gate driver 32, which has already lost energy while passing through R1, with the directly biased gate G. 51 Decoupling is performed, and these pulses are replaced with voltage pulses from buffer 34 to provide robust on / off switching for HEMT 51.

[0017] In an embodiment, the ratio R2 / R1 may have a value between 0.2 and about 0.3, and the value of R1 may be between about 50 and 150 ohms; and, This is a value between approximately 10% and approximately 30% of the absolute value of the turn-on threshold voltage of the HEMT transistor 51. As an example, assume that HEMT 51 is a GaN D-type HEMT with a turn-on threshold voltage typically between -3 volts and approximately -11 volts. It can have values ​​between about 0.5 volts and about 4 volts.

[0018] In this embodiment, the on / off state of switch 28 and the output of enable circuit NAND 30 are respectively determined by the output Q of latch 24 and The logic level is controlled. Latch 24 receives a set "SET" signal from comparator 22 and a reset "RESET" signal, either manually or generated by a processor (not shown) that initializes the latch. Comparator 22 is optionally coupled to the voltage V between nodes 53 and 62 via a high-pass filter 26. 53-62 And coupled to, optionally by voltage The threshold voltage V determined by voltage divider 23 T The high-pass filter 26 is characterized by its passband, which allows the voltage V expected to characterize the voltage between nodes 53 and 62 to pass through. 53-62The frequency of the surge, generated by stray inductances L1 and L2 in response to the rapid rise of current through the cascode 50 associated with the onset of the short-circuit power supply HV, and the frequency attenuation characterizing the normal operation frequency of the power switch 100, is considered. In this embodiment, the passband has a lower cutoff frequency that is greater than the frequency characterizing the slew rate of current flowing through the MOSFET 52 during normal operation of the power switch 100.

[0019] Under normal operation without a short circuit, such as Figure 1A The voltage V, schematically shown, is input to comparator 22 after being filtered by high-pass filter 26. 53-62 Not exceeding threshold V T The comparator does not generate a SET signal for latch 24, and the latch's Q and Q-bar can optionally present logic levels 0 and 1, respectively. Therefore, in response to a logic 1 received from the Q-bar output and the enable signal PWM EN, NAND 30 generates an enable signal to enable gate driver 32, and in response to a logic 0 received from Q by the voltage divider circuit 40, MOSFET 28 remains off. Therefore, the PWM input pulse P31 input to gate driver 32 generates a voltage pulse P32 from the gate driver, which then... 51 A corresponding voltage output pulse P34 is generated from buffer 34, which pulses HEMT 51 to conduction to supply power to load L using a voltage pulse from power supply HV. Alternatively, as schematically indicated by the curved dashed line 33, voltage pulses P31, P32, and P34 provide power to the load at a desired frequency that varies substantially harmonically over time.

[0020] On the other hand, in the case of a short circuit starting, such as Figure 1B The voltage V between node 53 and node 62 is schematically indicated in the diagram. 53-62 Surge voltage "V" 53-62-浪涌 "And when the surge voltage filtered by the high-pass filter 26 exceeds the threshold voltage V T At this time, comparator 22 generates a SET signal that sets the outputs of Q and Q-bar to logic 1 and 0, respectively. A logic 1 from Q turns on MOSFET 28, thereby turning on voltage divider 40, and after a delay, a logic 0 from Q-bar causes NAND 30 to generate a disable signal that disables gate driver 32. Optionally, the delay is a time delay generated due to signal processing and propagation delays characterizing the operation of NAND 30 and / or gate driver 32.

[0021] As described above, the on-divider 40 reduces the voltage of the pulse P32 from the gate driver 32 to the reduced voltage V-P32' of the reduced pulse P32', and causes the reduced voltage V-P34' of the pulse P34' to be relative to the source S of the HEMT 51. 51 Bias gate G of HEMT 51 51 The NAND 30 then disables the gate driver 32, stops the pulse generation of the gate driver and buffer 34, and shuts down the HEMT 51. Figure 1B The surge voltage V, indicating a short circuit according to an embodiment, is schematically shown during pulse P32, which is shaded in the figure. 53-62-浪涌 Therefore, the logic level from latch 24 turns on the voltage divider 40 to turn pulse P32 into a reduced voltage pulse P32' (also shown in shaded area), causing buffer 34 to bias its gate G with the voltage V-P34' from the reduced voltage pulse P34'. 51 This prevents the generation of further pulses that would activate the HEMT 51.

[0022] Inset 102 in the figure shows a magnified image of pulses P32 and P32' along the timeline, illustrating the short-circuit protection device 20 controlling the power switch 100 in response to voltage surge V5. 3-62-浪涌 The operation at that time. Assume the surge voltage occurs a time after the shadow pulse has begun. And in time The short-circuit protection device 20 activates the voltage divider 40 and reduces the voltage of pulse P32 from V-P32 to V-P32', thus "morphing" the pulse into a reduced voltage pulse P32', which operates to reduce the current through the cascode 50. After the delay, at the subsequent time... The short-circuit protection device 20 disables the gate driver 32, which sets the voltage of the gate G51 to signal ground 70 and prevents further pulses from being generated that would turn on HEMT 51.

[0023] By way of numerical example, under normal operation, an automotive power switch (such as power switch 20) configured to supply power from a high-voltage power source to the automotive electric traction motor can provide a PWM voltage pulse to the traction motor. For this PWM voltage pulse, the current through the cascode 50 exhibits a slew rate between 20 and 30 A / ns (amperes per nanosecond) and a peak voltage between 1 and 1.75 volts. A short circuit is characterized by a slew rate of current through the cascode between 40 and 60 A / ns, and V... TIt can be set to a voltage greater than approximately 2 volts. Optionally, the filter cutoff frequency has a value between 5 MHz and 20 MHz. Time delay It can have values ​​between approximately 25 ns and 50 ns (nanoseconds), and the time delay... It can have values ​​between approximately 200 ns and 400 ns.

[0024] By first increasing the R of HEMT 51 on Then, after a favorable time delay, the HEMT is turned off. The phased response of the short-circuit protection device 20 to the onset of the short circuit mitigates the rate at which the surge current characterizing the short circuit passes through the cascode 50. Therefore, the short-circuit protection device 20 operates to mitigate and prevent large, destructive transients that may be generated when the short-circuit protection device turns off the HEMT 51 in response to detecting and preventing a short circuit.

[0025] Although the above description of embodiments of this disclosure shows short-circuit protection device 20 operating to predict and prevent short circuits in response to the detection of a voltage surge induced by a stray inductance characterizing a transistor in a cascode circuit, embodiments of this disclosure are not limited to detecting surge voltages in a cascode circuit. For example, the short-circuit protection device according to embodiments can be used to control transistors included in a circuit in response to the detection of a voltage surge induced anywhere in the circuit and not necessarily in a transistor or a cascode circuit. Furthermore, although short-circuit protection device 20 is described as controlling the gating of a HEMT n-channel D-type transistor in response to the detection of a surge voltage, embodiments are not limited to such transistors. The short-circuit protection device according to embodiments can, for example, be configured to provide an appropriate voltage to control p-channel and / or E-type transistors in response to the detection of a surge voltage.

[0026] Therefore, according to embodiments of the present disclosure, a short-circuit protection circuit is provided, comprising: a HEMT (High Electron Mobility Transistor) including a source, a drain, and a gate, the HEMT being controllable to be turned on and off by a voltage applied to the gate; a comparator having an input and an output coupled to a high-pass filter, wherein at the output, if a voltage surge greater than a threshold voltage is observed after filtering by the filter, the comparator generates an output signal in response to a voltage induced across an inductor; and a voltage divider controllable to be turned on and off to control the voltage supplied to the gate of the HEMT, wherein the voltage divider is turned on in response to the output signal from the comparator to provide a reduced voltage to the gate, less than the on-threshold voltage of the HEMT.

[0027] Optionally, the short-circuit protection circuit includes a buffer connected to the voltage divider and turns the HEMT on and off by voltage biasing the gate in response to a voltage received from the voltage divider. Optionally, the voltage divider is connected in series with a gate driver to receive a voltage from the gate driver and generates a voltage received by the buffer in response to the voltage received from the gate driver. Optionally, the short-circuit protection circuit includes an enable circuit that generates an enable signal and a disable signal to enable and disable the gate driver, respectively, and disables the gate driver in response to the comparator output signal. Optionally, the short-circuit protection circuit includes a latch that receives and generates at least one output signal in response to the comparator output signal. Optionally, the voltage divider may be connected to the latch and receive a signal from the at least one signal that turns the voltage divider on. Optionally, the voltage divider includes a transistor that turns on a signal from the latch to connect the voltage divider to ground, thereby turning on the voltage divider.

[0028] In one embodiment, the enabling circuit is connected to the latch and receives from the latch a signal from the at least one signal that causes the enabling circuit to generate a disable signal that disables the gate driver. Optionally, the disable signal disables the gate driver at a second time, delayed relative to a first time the voltage divider is turned on. Optionally, the first time is delayed by 25 ns to 50 ns (nanoseconds) relative to the time the voltage surge exceeds the comparator threshold voltage. Additionally or alternatively, the second time may be delayed by 200 ns to 400 ns relative to the first time.

[0029] In one embodiment, the reduced voltage is a voltage difference smaller than the turn-on threshold voltage of the HEMT, and this voltage difference is between 10% and 50% of the absolute value of the turn-on threshold voltage. In another embodiment, the voltage biasing the gate of the HEMT includes a voltage pulse. In another embodiment, the HEMT is a D-type HEMT. In another embodiment, the HEMT is an E-type HEMT. In another embodiment, the HEMT is a first transistor included in a cascode configuration and connected in series with a second cascode transistor. Optionally, the inductor is the stray inductance of the second transistor.

[0030] According to embodiments of this disclosure, a power switch is also provided, the power switch including a short-circuit protection circuit according to any of the preceding claims.

[0031] According to embodiments of the present disclosure, a power switch including a short-circuit protection circuit is also provided. The power switch includes: a cascode transistor operable to provide pulsed power from a power source to a load, the cascode transistor having a first transistor connected in series with a second transistor at an intermediate node; a gate driver generating a gate driver voltage pulse, the gate of the first transistor being biased in response to the gate driver voltage pulse to turn the first transistor on and off and provide pulsed power to the load; and a short-circuit protection circuit including: a comparator connected to the second transistor via a high-pass filter, the comparator receiving a voltage generated by a current flowing through the second transistor and a stray inductance of the second transistor, and generating a comparator output signal indicating when a received voltage filtered by the filter exceeds a threshold voltage; and a voltage pulse control circuit controlling the driver voltage pulse in response to the comparator output signal.

[0032] In the description and claims of this application, each of the verbs “comprise,” “include,” and “have,” and their variations, used to indicate one or more objects of a verb, is not necessarily a complete list of the composition, elements, or parts of one or more subjects of the verb.

[0033] The description of embodiments of the invention in this application is provided by way of example and is not intended to limit the scope of the invention. The described embodiments include different features, and not all embodiments of the invention require all of these features. Some embodiments utilize only some features or possible combinations of features. Variations of the described embodiments of the invention, as well as embodiments of the invention including different combinations of the features mentioned in the described embodiments, will be apparent to those skilled in the art. The scope of the invention is limited only by the claims.

Claims

1. A short circuit protection circuit comprising: a HEMT (high electron mobility transistor) including a source, a drain, and a gate, the HEMT controllable to turn on and turn off by a voltage applied to the gate; a comparator having an input coupled to a high pass filter and an output at which the comparator generates an output signal in response to a voltage induced across an inductance if the voltage after filtering by the filter exhibits a voltage surge greater than a threshold voltage; and a voltage divider controllable to turn on and turn off to control a voltage provided to the gate of the HEMT, and wherein the voltage divider turns on in response to the output signal from the comparator to provide a reduced voltage to the gate that is less than a turn on threshold voltage of the HEMT.

2. The short circuit protection circuit of claim 1, and including a buffer connected to the voltage divider and turning on and off the HEMT in response to a voltage received by the buffer from the voltage divider to bias the gate with the voltage.

3. The short circuit protection circuit of claim 2, wherein, the voltage divider connected in series with a gate driver to receive a voltage from the gate driver and generate the voltage received by the buffer in response to receiving the voltage from the gate driver.

4. The short circuit protection circuit of claim 3, and including an enable circuit generating an enable signal and a disable signal to enable and disable the gate driver, respectively, and disabling the gate driver in response to the comparator output signal.

5. The short circuit protection circuit of claim 4, and including a latch receiving and generating at least one output signal in response to the comparator output signal.

6. The short circuit protection circuit of claim 5, wherein, the voltage divider connected to the latch and receiving a signal of the at least one signal that turns on the voltage divider.

7. The short circuit protection circuit of claim 6, wherein, the voltage divider including a transistor turned on by the signal from the latch to connect the voltage divider to ground to turn on the voltage divider.

8. The short circuit protection circuit of claim 5, wherein, the enable circuit connected to the latch and receiving a signal of the at least one signal that causes the enable circuit to generate the disable signal that disables the gate driver.

9. The short circuit protection circuit of claim 8, wherein, the disable signal disabling the gate driver at a second time delayed relative to a first time at which the voltage surge exceeds the comparator threshold voltage by between 25 ns and 50 ns (nanoseconds).

10. The short circuit protection circuit of claim 9, wherein, the second time delayed relative to the first time by between 200 ns and 400 ns.

11. The short circuit protection circuit of claim 9, wherein, the reduced voltage less than the turn on threshold of the HEMT by a voltage difference equal to between 10% and 50% of an absolute value of the turn on threshold voltage.

12. The short circuit protection circuit of claim 1, wherein, the voltage biasing the gate of the HEMT includes a voltage pulse.

13. The short circuit protection circuit of claim 1, wherein, the HEMT is a D-mode HEMT.

14. The short circuit protection circuit of claim 1, wherein, the HEMT is an E-mode HEMT.

15. The short circuit protection circuit of claim 1, wherein, the HEMT is a first transistor included in a cascode and connected in series with a second transistor of the cascode.

16. The short circuit protection circuit of claim 1, wherein, the inductance is a stray inductance of the second transistor.

17. The short circuit protection circuit of claim 16, wherein, ​ 18. A power switch comprising the short circuit protection circuit of claim 1.

19. A power switch comprising a short circuit protection circuit, the power switch comprising: a cascode operable to provide pulsed power from a power source to a load, the cascode having a first transistor connected in series with a second transistor at an intermediate node; a gate driver generating a gate driver voltage pulse, a gate of the first transistor being biased in response to the gate driver voltage pulse to turn on and off the first transistor and provide pulsed power to the load; and a short circuit protection circuit comprising: a comparator connected to the second transistor via a high pass filter, the comparator receiving a voltage generated by current flowing through the second transistor and a stray inductance of the second transistor, and generating a comparator output signal indicating when the received voltage filtered by the filter exceeds a threshold voltage; and a voltage pulse control circuit controlling the driver voltage pulse in response to the comparator output signal. ​ ​

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