Preparation method of hot bottle neck for quantum magnetic calorimeter

Abstract

The invention relates to the technical field of magnetic calorimeter manufacturing, and provides a preparation method of a thermal bottleneck for a quantum magnetic calorimeter. The preparation method comprises the following steps: forming a paramagnet on a chip wafer; forming a sacrificial layer on the chip wafer and the paramagnet; forming a photoresist layer on the surface of one side, deviating from the chip wafer and the paramagnet, of the sacrificial layer; a mask is arranged on the surface of the side, away from the sacrificial layer, of the photoresist layer, a thermal bottleneck model is formed on the sacrificial layer, and an absorber model is formed on the photoresist layer; and forming a hot bottleneck based on the hot bottleneck model, and forming an absorber based on the absorber model. The same photoresist layer is utilized to realize pattern transfer, a hot bottleneck model is formed on the sacrificial layer, and an absorber model is formed on the photoresist layer, so that secondary deposition of photoresist for forming the hot bottleneck model is not needed, and the risk that the hot bottleneck model is filled with the photoresist and is difficult to remove due to secondary deposition of the photoresist can be avoided.

Description

Technical Field

[0001] This application relates to the field of magnetic calorimeter manufacturing technology, and in particular to a method for preparing a thermal bottleneck for a quantum magnetic calorimeter. Background Technology

[0002] A quantum magnetic calorimeter is a cryogenic particle detector based on calorimetry. It typically operates at extremely low temperatures below 100 mK (millikelvin). It utilizes a paramagnetic medium to convert the temperature rise of the absorber when it absorbs high-energy particles into a magnetic flux signal, which is then sensed by a superconducting quantum interference device (SQUID). A SQUID is a magnetic field device that utilizes the superconducting macroscopic quantum interference effect to measure relative changes in magnetic fields. Its minimum detection threshold can detect 10... -15 T (Tesla) magnetic field change. Due to the high-sensitivity temperature sensor, i.e., paramagnetic, and the near-quantum-limited amplifier, i.e., SQUID, the quantum magnetic calorimeter achieves a very fast signal rise time, excellent energy resolution, large dynamic range, near 100% quantum efficiency, and almost ideal linear detector response. The energy resolution of the quantum magnetic calorimeter is an order of magnitude higher than that of current high-purity germanium (HPGe) detectors.

[0003] In traditional quantum magnetic calorimeter designs, the absorber and paramagnetic body are in direct contact. After absorbing incident particles and converting them into heat energy, the absorber directly conducts the heat to the paramagnetic body. Because heat conduction is isotropic, the temperature rise signal of the absorber will differ depending on the location at which it receives the incident particle's radiation signal, exhibiting a significant positional correlation. Therefore, providing a thermal bottleneck connecting the absorber and the paramagnetic body, as well as a method for fabricating this bottleneck, has become a problem that needs to be solved. Summary of the Invention

[0004] This application provides a method for preparing a thermal bottleneck for a quantum magnetic calorimeter. The method can prepare a thermal bottleneck between the absorber and the paramagnetic body. The thermal bottleneck can fix the thermal link that conducts heat from the absorber to the paramagnetic body, thereby improving positional correlation.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a method for preparing a thermal bottleneck for a quantum magnetic calorimeter, the method comprising: Forming paramagnets on chip wafers; A sacrificial layer is formed on the chip wafer and the paramagnet; A photoresist layer is formed on the surface of the sacrificial layer that is away from the chip wafer and the paramagnet; A mask is disposed on the side of the photoresist layer opposite to the sacrificial layer, a thermal bottleneck model is formed on the sacrificial layer, and an absorber model is formed on the photoresist layer; A thermal bottleneck is formed based on the aforementioned thermal bottleneck model, and an absorber is formed based on the aforementioned absorber model.

[0006] In some embodiments, a sacrificial layer is formed on the chip wafer and the paramagnetic material, including: Seed layers are deposited on the chip wafer and the paramagnet by magnetron sputtering; The sacrificial layer is constructed on the seed layer by electroplating.

[0007] In some embodiments, a thermal bottleneck model is formed on the sacrificial layer and an absorber model is formed on the photoresist layer, including: The thermal bottleneck pattern of the mask is transferred to the photoresist layer through the first photolithography process; The thermal bottleneck model is formed on the sacrificial layer at the location corresponding to the thermal bottleneck pattern using an etchant. The absorber pattern of the mask is transferred to the photoresist layer by a second photolithography process to form the absorber model.

[0008] In some embodiments, the sacrificial layer is made of copper.

[0009] In some embodiments, a photoresist layer is formed on the surface of the sacrificial layer opposite to the chip wafer and the paramagnet, including: Pour the photoresist onto the side of the sacrificial layer that is away from the chip wafer and the paramagnet; Rotate the chip wafer with the photoresist; The rotated chip wafer is left to stand for a first set time. The chip wafer, after being left to stand, is baked for a second set time to form the photoresist layer.

[0010] In some embodiments, the fabrication method includes forming a photoresist layer on the side of the sacrificial layer facing away from the chip wafer and the paramagnetic body before the photoresist layer is formed: The photoresist is left to stand for the third set time.

[0011] In some embodiments, the raw materials are simultaneously deposited into the thermal bottleneck model and the absorber model to form the thermal bottleneck and the absorber.

[0012] In some embodiments, the raw materials are simultaneously deposited into the thermal bottleneck model and the absorber model by electroplating.

[0013] In some embodiments, the material of the thermal bottleneck includes gold; and / or, the material of the absorber includes gold.

[0014] In some embodiments, forming a paramagnetic material on a chip wafer includes: A paramagnetic material is formed on the chip wafer by magnetron sputtering.

[0015] The fabrication method provided in this application forms a photoresist layer on the side of the sacrificial layer facing away from the chip wafer and the paramagnet. This same photoresist layer is used for pattern transfer, forming a thermal bottleneck model on the sacrificial layer and an absorber model on the photoresist layer. This eliminates the need for secondary photoresist deposition to form the thermal bottleneck model, avoiding the risk of photoresist filling the thermal bottleneck model and becoming difficult to remove. This saves steps and prevents secondary photoresist deposition from affecting the normal formation of the thermal bottleneck. The thermal bottleneck connects the absorber and the paramagnet, conducting heat from the absorber to the paramagnet through it. The thermal bottleneck fixes the heat transfer path from the absorber to the paramagnet, optimizing the heat conduction path. Heat from the absorber is transferred to the paramagnet via a fixed path, rather than a random path, thereby improving or even eliminating positional dependence. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of a method for preparing a thermal bottleneck for a quantum magnetic calorimeter according to some embodiments of this application; Figure 2 These are schematic diagrams of the preparation process provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure of a quantum magnetic calorimeter provided in some embodiments of this application. Detailed Implementation

[0017] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this application.

[0019] In the description of the embodiments of this application, the technical terms "first", "second", "third", etc. are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features.

[0020] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that combinations can be made in any suitable manner without contradiction; for example, different combinations of specific technical features / embodiments can form different implementations. To avoid unnecessary repetition, the various possible combinations of specific technical features / embodiments in this application will not be described separately.

[0021] It should be noted that in this application, "multiple" includes two or more.

[0022] In quantum magnetic calorimeters of related technologies, the absorber and paramagnetic body are in direct contact. When incident particles are randomly injected into the absorber, the ray signals received by the incident particles at different positions of the absorber will result in different temperature rise signals of the absorber when the ray signals of the incident particles are received at different positions. Since heat conduction is isotropic, the heat energy of the absorber is transferred to the paramagnetic body through random paths, resulting in errors and a relatively obvious positional correlation.

[0023] Please see Figure 3 The quantum magnetic calorimeter provided in this application includes a magnetic calorimeter chip 700, a paramagnetic body 200, an absorber 600, and a heat neck 500. The paramagnetic body 200 and the absorber 600 are respectively connected to the opposite ends of the heat neck 500, and the magnetic calorimeter chip 700 is connected to the end of the paramagnetic body 200 away from the heat neck 500.

[0024] The absorber 600 absorbs incident particles and converts the energy of the incident particles into heat energy.

[0025] The paramagnet 200 generates a magnetic flux signal based on thermal energy. Specifically, the thermal energy converted by the absorber 600 is conducted to the paramagnet 200 through the thermal bottleneck 500. The thermal energy causes a change in the magnetization state of the paramagnet 200, thereby generating a magnetic flux signal.

[0026] The magnetocalorimetric chip 700 is used to detect magnetic flux signals. Exemplarily, the measurement chip may include a superconducting quantum interference chip.

[0027] The quantum magnetic calorimeter provided in this application embodiment has a thermal bottleneck 500 that connects an absorber 600 and a paramagnetic body 200. The thermal energy of the absorber 600 is conducted to the paramagnetic body 200 through the thermal bottleneck 500. By setting the thermal bottleneck 500 between the absorber 600 and the paramagnetic body 200, the thermal bottleneck 500 is fixed, thus optimizing the heat conduction path. The thermal energy of the absorber 600 is transferred to the paramagnetic body 200 via a fixed path, rather than a random path, thereby improving or even eliminating positional dependence.

[0028] Please see Figure 1 This application provides a method for preparing a thermal bottleneck for a quantum magnetic calorimeter, the method comprising: S1. Forming a paramagnet on a chip wafer; Specifically, please refer to Figure 2 A paramagnetic material 200 is formed on one side surface of the chip wafer 100 along the thickness direction.

[0029] Here, one or more circuits for magnetic calorimeter chips 700 can be formed on the chip wafer 100. The chip wafer 100 is the basis for manufacturing the magnetic calorimeter chips 700, which are products cut and packaged from the chip wafer 100.

[0030] The chip wafer 100 can be a generally circular thin film. The substrate of the chip wafer 100 includes, but is not limited to, a monocrystalline silicon wafer or a polycrystalline silicon wafer.

[0031] S2. A sacrificial layer is formed on the chip wafer and the paramagnet; Please see here. Figure 2 The sacrificial layer 300 can cover the chip wafer 100 and the paramagnetic body 200. Specifically, the sacrificial layer 300 covers at least the surface of the paramagnetic body 200 facing away from the chip wafer 100 and the surface where the chip wafer 100 and the paramagnetic body 200 are connected. The sacrificial layer 300 can also cover the circumferential surface of the paramagnetic body 200 around the thickness direction.

[0032] S3. A photoresist layer is formed on the side of the sacrificial layer that is away from the chip wafer and the paramagnet; S4. A mask is placed on the side of the photoresist layer facing away from the sacrificial layer, a thermal bottleneck model is formed on the sacrificial layer, and an absorber model is formed on the photoresist layer. S5. A thermal bottleneck is formed based on the thermal bottleneck model, and an absorber is formed based on the absorber model.

[0033] Please see Figure 2The thermal bottleneck model 301 is a hollow shape formed by removing part of the solid structure of the sacrificial layer 300, and the remaining solid structure of the sacrificial layer 300 constitutes the sidewall of the thermal bottleneck model 301. In other words, the thermal bottleneck model 301 is a mold used to form the thermal bottleneck 500.

[0034] Specifically, the material of the thermal bottleneck 500 is used to fill the thermal bottleneck model 301 to form the thermal bottleneck 500.

[0035] Please see Figure 2 The absorber model 401 is a hollow shape formed after part of the solid structure of the photoresist layer 400 is removed, and the remaining solid structure of the photoresist layer 400 constitutes the sidewalls of the absorber model 401. In other words, the absorber model 401 is a mold used to form the absorber 600.

[0036] Specifically, the material of absorber 600 fills absorber model 401 to form absorber 600.

[0037] The sacrificial layer 300 is a temporary structure that exists during the preparation process. In the micro-nano manufacturing process, the sacrificial layer 300 serves as an intermediate layer and is removed after the thermal bottleneck 500 is formed.

[0038] The photoresist layer 400 achieves the transfer of the mask pattern through photochemical reaction. The photoresist layer 400 is a temporary structure that exists during the preparation process. In the micro-nano manufacturing process, the photoresist layer 400 serves as an intermediate layer and is removed after the absorber 600 is formed.

[0039] The fabrication method provided in this application embodiment forms a photoresist layer 400 on the side of the sacrificial layer 300 facing away from the chip wafer 100 and the paramagnetic body 200. Pattern transfer is achieved using this same photoresist layer 400. A thermal bottleneck model 301 is formed on the sacrificial layer 300, and an absorber model 401 is formed on the photoresist layer 400. This eliminates the need for secondary photoresist deposition to form the thermal bottleneck model 301, avoiding the risk of photoresist filling the thermal bottleneck model 301 and becoming difficult to remove. This saves steps and prevents secondary photoresist deposition from affecting the normal formation of the thermal bottleneck 500. The thermal bottleneck 500 thermally connects the absorber 600 and the paramagnetic body 200, and the heat energy of the absorber 600 is conducted to the paramagnetic body 200 through the thermal bottleneck 500. The thermal bottleneck 500 can fix the thermal link from the absorber 600 to the paramagnet 200, optimize the heat conduction path, and the heat energy of the absorber 600 is transferred to the paramagnet 200 through a fixed path instead of a random path, thereby improving or even eliminating position dependence.

[0040] In some embodiments, after forming a thermal bottleneck based on the thermal bottleneck model and an absorber based on the absorber model, the preparation method includes: Remove the sacrificial layer and the photoresist layer.

[0041] After the thermal bottleneck 500 and absorber 600 are formed, the sacrificial layer 300 and photoresist layer 400 are removed.

[0042] In this application, the type of photoresist is not limited, and existing photoresists can be used. For example, AZ125nXT photoresist can be used.

[0043] In some embodiments, after removing the sacrificial layer and the photoresist layer, the fabrication method may further include: The chip wafer is divided into one or more dies, and each die may include a paramagnet, a thermal bottleneck, and an absorber.

[0044] The die containing the paramagnetic element 200, the thermal bottleneck 500, and the absorber 600 can be encapsulated as needed.

[0045] The shape of the paramagnetic body 200 is not limited; exemplarily, the paramagnetic body 200 can be approximately hexahedral in shape, for example, see [link to relevant documentation]. Figure 3 The paramagnetic material 200 can be in the form of a relatively small, flat sheet along the thickness direction of the chip wafer 100.

[0046] The shape of the absorber 600 is not limited; for example, the absorber 600 may be approximately hexahedral in shape, see [reference needed]. Figure 3 The absorber 600 can be in the form of a relatively small, flat sheet along the thickness direction of the chip wafer 100.

[0047] The shape of the thermal bottleneck 500 is not limited. For example, the thermal bottleneck 500 may be generally cylindrical, extending along the thickness direction of the chip wafer 100. See, for example, [link to relevant documentation]. Figure 3 The bottleneck of the heat exchanger 500 can be roughly cylindrical or prismatic, etc.

[0048] In some embodiments, one or more paramagnetic bodies 200 may be formed on the chip wafer 100.

[0049] In some embodiments, a single paramagnetic element 200 may be connected to one or more thermal bottlenecks 500.

[0050] In some embodiments, a single absorber 600 may be connected to one or more thermal bottlenecks 500.

[0051] In some embodiments, please refer to Figure 3 Each paramagnetic element 200 can correspond to one absorber 600, and multiple thermal bottlenecks 500 connect the individual paramagnetic element 200 and the individual absorber 600. Here, the arrangement of the multiple thermal bottlenecks 500 is not limited; for example, the multiple thermal bottlenecks 500 can be arranged in a two-dimensional matrix.

[0052] The specific structure of the photomask is not limited in this application.

[0053] In some embodiments, the photomask includes a first sub-photomask and a second sub-photomask that are independent of each other. The first sub-photomask includes a thermal bottleneck pattern, and the second sub-photomask includes an absorber pattern. The first sub-photomask is disposed on the side of the photoresist layer 400 opposite to the sacrificial layer 300, and the thermal bottleneck pattern is transferred to the photoresist layer 400 by a first photolithography. The second sub-photomask is disposed on the side of the photoresist layer 400 opposite to the sacrificial layer 300, and the absorber pattern is transferred to the photoresist layer 400 by a second photolithography.

[0054] The independence of the first sub-mask and the second sub-mask means that the first sub-mask and the second sub-mask can be separated from each other and do not need to be connected.

[0055] In some embodiments, a sacrificial layer is formed on the chip wafer and the paramagnetic material, including: S210. A seed layer is deposited on the chip wafer and the paramagnet by magnetron sputtering; S220. The sacrificial layer is constructed on the seed layer by electroplating.

[0056] Magnetron sputtering utilizes ion bombardment of a target material. During the process of target atoms or molecules sputtered from the target material being deposited onto the chip wafer 100 and the paramagnetic layer 200, the composition of the target material is the same as that of the seed layer.

[0057] Electroplating is a process in which metal ions in a plating solution are reduced to metal atoms by an electrode reaction under the action of an external electric field and deposited onto a cathode. In this application, a chip wafer 100 having a seed layer and a paramagnetic body 200 can be used as a cathode.

[0058] Here, the current density of the electroplating forming the sacrificial layer 300 can be set as needed. For example, the current density of the electroplating can be 5 ASD (Ampere per Square Decimeter).

[0059] In this embodiment, the seed layer is part of the sacrificial layer 300, which is made of a conductive material. The seed layer is deposited on the chip wafer 100 and the paramagnetic body 200 by magnetron sputtering. Magnetron sputtering first prepares a relatively large and uniformly distributed seed layer, and then electroplating is used to further increase the thickness of the seed layer until the sacrificial layer 300 is formed. Magnetron sputtering has the advantage of uniform coating, while electroplating has the advantage of rapid coating. Combining magnetron sputtering and electroplating can both ensure coating uniformity and improve coating efficiency. In some embodiments, the sacrificial layer 300 can also be formed on the chip wafer 100 and the paramagnetic material 200 by magnetron sputtering. That is, the sacrificial layer 300 can be formed directly by magnetron sputtering without using a combination of magnetron sputtering and electroplating.

[0060] In some embodiments, a thermal bottleneck model is formed on the sacrificial layer and an absorber model is formed on the photoresist layer, including: S410. The thermal bottleneck pattern of the mask is transferred to the photoresist layer by the first photolithography; Here, the thermal bottleneck pattern of the mask is transferred to the photoresist layer 400 through the first photolithography. The solid structure of the thermal bottleneck pattern corresponding to the photoresist layer 400 is removed by the first photolithography to form a hollowed-out thermal bottleneck pattern.

[0061] S420. The thermal bottleneck model is formed on the sacrificial layer at the location corresponding to the thermal bottleneck pattern using an etchant. Since the photoresist layer 400 covers the side of the sacrificial layer 300 facing away from the chip wafer 100, the etchant cannot directly contact the sacrificial layer 300. Therefore, the position of the thermal bottleneck model 301 is exposed in step S410, so that the etchant can contact the sacrificial layer 300 through the hollowed-out thermal bottleneck pattern on the photoresist layer 400. Through the chemical reaction between the etchant and the sacrificial layer 300 corresponding to the thermal bottleneck pattern, the solid structure of the sacrificial layer 300 corresponding to the thermal bottleneck pattern is removed by the etchant, forming the hollowed-out thermal bottleneck model 301.

[0062] It is understandable that, with the plane perpendicular to the thickness direction of the chip wafer 100 as the projection plane, the projection of the thermal bottleneck pattern on the photoresist layer 400 coincides with the projection of the thermal bottleneck model 301 on the sacrificial layer 300.

[0063] S430. The absorber pattern of the mask is transferred to the photoresist layer by a second photolithography process to form the absorber model.

[0064] Here, the absorber pattern of the mask is transferred to the photoresist layer 400 through a second photolithography. The solid structure of the absorber pattern corresponding to the photoresist layer 400 is removed by the second photolithography to form a hollow absorber model 401.

[0065] Taking the first sub-mask and the second sub-mask as examples, a mask is disposed on the surface of the photoresist layer 400 opposite to the sacrificial layer 300. A thermal bottleneck model 301 is formed on the sacrificial layer 300, and an absorber model 401 is formed on the photoresist layer 400. This may include: The first sub-mask is placed on the side of the photoresist layer 400 opposite to the sacrificial layer 300, and the thermal bottleneck pattern of the mask is transferred to the photoresist layer 400 by the first photolithography. Remove the first sub-mask and form the thermal bottleneck model 301 on the sacrificial layer 300 at the location corresponding to the thermal bottleneck pattern using an etchant; A second sub-mask is placed on the side of the photoresist layer 400 facing away from the sacrificial layer 300. The absorber pattern of the mask is transferred to the photoresist layer 400 by a second photolithography to form the absorber model 401.

[0066] In this embodiment, the transfer of the thermal bottleneck pattern and the absorber pattern is achieved by photolithography twice using a single-layer photoresist layer 400, which can avoid the problem of photoresist entering the thermal bottleneck model 301 due to secondary photoresist deposition.

[0067] It should be noted that photolithography includes two steps: exposure and development. Exposure involves irradiating the photoresist layer 400 with ultraviolet light to cause a chemical change in the photoresist layer 400, forming a photosensitive pattern corresponding to the pattern on the mask. After exposure, the photoresist layer 400 is immersed in the developing solution, where the photosensitive pattern is located dissolves, thereby transferring the pattern from the mask to the photoresist layer 400.

[0068] The developing solution used in the developing step can be configured according to requirements. For example, a developing solution diluted at a ratio of 1:5 can be used for developing for more than 20 minutes. It is understood that, depending on the developing requirements, the developing time can also be less than 20 minutes or equal to 20 minutes, etc., and this application does not impose any restrictions.

[0069] In some embodiments, the material of the sacrificial layer 300 includes copper.

[0070] When the material of the sacrificial layer 300 includes copper, a copper etchant can be used to form a thermal bottleneck model 301 at the location of the thermal bottleneck pattern corresponding to the sacrificial layer 300.

[0071] Copper etchants include, but are not limited to, CuCl2-HCl solution.

[0072] In this embodiment, metallic copper forms the sacrificial layer 300. A thermal bottleneck model 301 can be formed on the sacrificial layer 300 made of metallic copper using a copper etchant. The remaining sacrificial layer 300 can then be removed by chemical and / or mechanical polishing.

[0073] In some embodiments, a photoresist layer is formed on the surface of the sacrificial layer opposite to the chip wafer and the paramagnet, including: S310. Pour the photoresist onto the side of the sacrificial layer that is away from the chip wafer and the paramagnet; S320, Rotate the chip wafer with the photoresist; Here, the rotation speed and rotation duration can be selected according to the properties of the photoresist.

[0074] S330, After rotating, the chip wafer is left to stand for a first set time; The initial setup time can be set according to requirements; for example, the initial setup time can be 30 minutes to 60 minutes. This design can balance the requirements of uniform distribution of the photoresist layer 400 and reasonable preparation time. For example, the initial setup time can be any value among 30 minutes, 40 minutes, and 60 minutes, or a value between any two of them.

[0075] S340. After the chip wafer has been left to stand, bake it for a second set time to form the photoresist layer.

[0076] The second set duration can be set according to requirements. For example, the second set duration can be 45 seconds to 90 seconds. For instance, the first set duration can be any value among 45 seconds, 60 seconds, and 90 seconds, or a value between any two of them.

[0077] The baking temperature of the chip wafer 100 after resting can be set as needed. For example, the baking temperature can be from 95°C to 105°C. For instance, the baking temperature can be any value of 95°C, 100°C, and 105°C, or a value between any two of them.

[0078] In this embodiment, steps S310, S320, S330, and S340 can be implemented sequentially. The photoresist is directly poured onto the side of the sacrificial layer 300 facing away from the chip wafer 100 and the paramagnetic body 200, without using a dispensing machine. This can, to some extent, avoid the formation of air bubbles and improve the forming effect of the photoresist layer 400. When the chip wafer 100 with photoresist is rotated, centrifugal force allows the photoresist to spread out, thereby covering the side of the sacrificial layer 300 facing away from the chip wafer 100 and the paramagnetic body 200. The rotated chip wafer 100 is left to stand for a first set time to improve the uniformity of the photoresist coverage. The chip wafer 100 is then baked for a second set time, which can, to some extent, eliminate the stress on the photoresist and improve the stability of the photoresist layer 400.

[0079] In some embodiments, the fabrication method includes forming a photoresist layer on the side of the sacrificial layer facing away from the chip wafer and the paramagnetic body before the photoresist layer is formed: S6. Let the photoresist stand for the third set time.

[0080] The third set duration can be set according to requirements. For example, the third set duration can be 8 to 12 hours. For instance, the third set duration can be any value among 8, 9, 10, and 12 hours, or a value between any two of them.

[0081] The photoresist is pretreated in step S6, which is performed before step S3.

[0082] It is understandable that step S6 may not be related to steps S1, S2, etc. Step S6 may be implemented before steps S1 and S2, or it may be implemented simultaneously with steps S1 and S2, or it may be implemented after steps S1 and S2.

[0083] In this embodiment, before the photoresist is applied to the sacrificial layer 300, the photoresist is pretreated in step S6 by allowing it to stand for a third set time, so that any air bubbles that may remain in the photoresist can rise to the surface and be eliminated, thereby improving the forming effect of the photoresist layer 400.

[0084] In some embodiments, the raw materials are simultaneously deposited into the thermal bottleneck model and the absorber model to form the thermal bottleneck and the absorber.

[0085] In this embodiment, the same raw materials are introduced into the thermal bottleneck model 301 and the absorber model 401. The thermal bottleneck model 301 forms the thermal bottleneck 500, and the absorber model 401 forms the absorber 600. The thermal bottleneck 500 and the absorber 600 are formed by using the same raw materials to form an integral structure, which simplifies the manufacturing process and provides good connection strength between the thermal bottleneck 500 and the absorber 600.

[0086] In some embodiments, the raw materials are simultaneously deposited into the thermal bottleneck model and the absorber model via electroplating. Electroplating facilitates the relatively efficient and rapid formation of the thermal bottleneck and absorber.

[0087] The material of the heat neck 500 can be a good conductor of heat. For example, the heat neck 500 can be made of metal. Metal has both good thermal conductivity and electrical conductivity. In this way, the thermal conductivity of the heat neck 500 is relatively high, which can quickly conduct heat energy to the paramagnet 200, reduce heat energy dissipation, and can also be deposited on the heat neck model 301 through electroplating process.

[0088] The material of the absorber 600 can be the same as that of the heat neck 500. For example, the absorber 600 can be made of a metal material that is conductive, so that it can be deposited onto the absorber model 401 by an electroplating process.

[0089] In some embodiments, the materials of the absorber 600 and the thermal bottleneck 500 may also be different.

[0090] In some embodiments, the material of the thermal bottleneck 500 includes gold. Here, gold constitutes the thermal bottleneck 500. Gold has a low heat capacity at extremely low temperatures, thus having a minimal impact on the introduction of the quantum magnetic calorimeter.

[0091] In some embodiments, the absorber 600 is made of gold. Here, gold constitutes the absorber 600. Gold has relatively low reactivity and relatively high density, resulting in good absorption of incident particles.

[0092] In some embodiments, forming a paramagnetic material on a chip wafer includes: S110. A paramagnetic material is formed on the chip wafer by magnetron sputtering.

[0093] Thus, the paramagnetic material 200 formed by magnetron sputtering has the advantage of good uniformity.

[0094] The paramagnet 200 can be made of paramagnetic materials. For example, the heat neck 500 can be made of metallic materials. Exemplarily, the materials of the paramagnet 200 include gold and erbium, etc.

[0095] In one specific embodiment, the preparation method includes: A paramagnetic material 200 is formed on a chip wafer 100 by magnetron sputtering; A seed layer is deposited on the chip wafer 100 and the paramagnetic body 200 by magnetron sputtering, and the sacrificial layer 300 is constructed on the seed layer by electroplating, wherein the material of the sacrificial layer 300 includes copper; The photoresist is left to stand at room temperature for 8 to 12 hours, and then poured onto the surface of the sacrificial layer 300 facing away from the chip wafer 100 and the paramagnetic body 200; the chip wafer 100 with the photoresist is rotated; the rotated chip wafer 100 is left to stand for a first preset time; the stood chip wafer 100 is baked for a second preset time to form the photoresist layer 400, wherein the first preset time is 30 minutes, the second preset time is 1 minute, and the baking temperature is 105°C; A chip wafer 100 having the photoresist layer 400, the sacrificial layer 300, and the paramagnetic body 200 is loaded into a photolithography machine. A first sub-mask is placed on the surface of the photoresist layer 400 facing away from the sacrificial layer 300 and exposed. The wafer is developed for more than 20 minutes using a developer diluted at a ratio of 1:5. After development, the chip wafer 100 is immersed in deionized water to remove residual developer and then rotated to air dry. In this way, the thermal bottleneck pattern of the first sub-mask is transferred to the photoresist layer 400. The thermal bottleneck model 301 is formed on the sacrificial layer 300 at the location corresponding to the pattern of the thermal bottleneck 500 using a copper etchant. The chip wafer 100 with the thermal bottleneck model 301 is reloaded into the photolithography machine. A second sub-mask is placed on the surface of the photoresist layer 400 opposite to the sacrificial layer 300 and exposed. The wafer is developed for more than 20 minutes using a developer diluted at a ratio of 1:5. After development, the chip wafer 100 is immersed in deionized water to remove residual developer and then rotated to air dry. In this way, the absorber pattern of the second sub-mask is transferred to the photoresist layer 400, forming the absorber model 401 on the photoresist layer 400.

[0096] After development is complete, the above structure can be baked again to eliminate stress in the photoresist. Gold is deposited simultaneously into the heat bottleneck model 301 and the absorber model 401 by electroplating to obtain the heat bottleneck 500 and the absorber 600.

[0097] Remove photoresist and sacrificial layer 300.

[0098] In this embodiment, the thermal bottleneck 500 is fabricated using a microelectromechanical system (MEMS) manufacturing method. The transfer of the thermal bottleneck pattern and the absorber pattern is achieved by developing a single-layer photoresist layer 400 twice, which can avoid the photoresist entering the thermal bottleneck model 301 due to secondary photoresist deposition.

[0099] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way.

Claims

1. A method for preparing the thermal bottleneck of a quantum magnetic calorimeter, characterized in that, The preparation method includes: Forming paramagnets on chip wafers; A sacrificial layer is formed on the chip wafer and the paramagnet; A photoresist layer is formed on the surface of the sacrificial layer that is away from the chip wafer and the paramagnet; A mask is disposed on the side of the photoresist layer opposite to the sacrificial layer, a thermal bottleneck model is formed on the sacrificial layer, and an absorber model is formed on the photoresist layer; A thermal bottleneck is formed based on the aforementioned thermal bottleneck model, and an absorber is formed based on the aforementioned absorber model.

2. The preparation method according to claim 1, characterized in that, A sacrificial layer is formed on the chip wafer and the paramagnetic material, including: Seed layers are deposited on the chip wafer and the paramagnet by magnetron sputtering; The sacrificial layer is constructed on the seed layer by electroplating.

3. The preparation method according to claim 1, characterized in that, A thermal bottleneck model is formed in the sacrificial layer, and an absorber model is formed in the photoresist layer, including: The thermal bottleneck pattern of the mask is transferred to the photoresist layer through the first photolithography process; The thermal bottleneck model is formed on the sacrificial layer at the location corresponding to the thermal bottleneck pattern using an etchant. The absorber pattern of the mask is transferred to the photoresist layer by a second photolithography process to form the absorber model.

4. The preparation method according to claim 1, characterized in that, The material of the sacrificial layer includes copper.

5. The preparation method according to claim 1, characterized in that, A photoresist layer is formed on the side of the sacrificial layer facing away from the chip wafer and the paramagnet, comprising: Pour the photoresist onto the side of the sacrificial layer that is away from the chip wafer and the paramagnet; Rotate the chip wafer with the photoresist; The rotated chip wafer is left to stand for a first set time. The chip wafer, after being left to stand, is baked for a second set time to form the photoresist layer.

6. The preparation method according to claim 1, characterized in that, Before forming a photoresist layer on the side of the sacrificial layer facing away from the chip wafer and the paramagnet, the fabrication method includes: The photoresist is left to stand for the third set time.

7. The preparation method according to claim 1, characterized in that, The raw materials are simultaneously deposited into the thermal bottleneck model and the absorber model to form the thermal bottleneck and the absorber.

8. The preparation method according to claim 7, characterized in that, The raw materials are simultaneously deposited into the thermal bottleneck model and the absorber model by electroplating.

9. The preparation method according to claim 1, characterized in that, The material of the thermal bottleneck includes gold; and / or, the material of the absorber includes gold.

10. The preparation method according to claim 1, characterized in that, Forming paramagnets on chip wafers includes: A paramagnetic material is formed on the chip wafer by magnetron sputtering.

Images