S parameter test method and system based on TRL calibration
By designing PCB test fixtures and calibration methods tailored to the parameters of the components under test, systematic errors were eliminated, high-frequency testing accuracy was improved, costs were reduced, and the compatibility and high cost of TRL calibration components were resolved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-03-13
AI Technical Summary
Existing TRL calibration kits are expensive and have fixed physical interfaces, making it difficult to fully adapt to the specific package or port layout of the device under test, resulting in high testing costs and low accuracy.
Design a PCB test fixture for the parameters of the component under test, including a TRL calibration area and a DUT test area. Perform SOLT calibration using a standard calibration piece, calculate the systematic error model, and measure and correct the original S-parameters using the calibrated probe.
It improves the accuracy of high-frequency testing, reduces costs, solves the problem of testing non-standard devices, ensures the consistency between the calibration environment and the testing environment, and eliminates systematic errors.
Smart Images
Figure CN121656715A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of parameter testing technology, and in particular to a method for testing S-parameters based on TRL calibration. Background Technology
[0002] S-parameters, also known as scattering parameters, are core indicators describing the incident, reflected, and transmitted characteristics of electromagnetic waves in radio frequency (RF) and microwave circuits. They are fundamental to the design and verification of modern wireless communications, radar, and high-speed digital circuits. Whether it's a chip, RF amplifier, filter, high-speed connector, or PCB transmission line, its performance is directly reflected in its S-parameters; therefore, high-precision measurement of S-parameters is crucial. During S-parameter measurement, the test system (including vector network analyzers, cables, test fixtures, etc.) itself introduces errors. Therefore, the test system needs to be calibrated before measuring S-parameters.
[0003] Currently, there are some mature TRL calibration kits on the market that can be directly used for calibration operations of test systems. However, the existing TRL calibration kits are expensive, which will increase the testing cost. At the same time, the physical interfaces (such as connector type and probe spacing) of the commonly used TRL calibration kits on the market are fixed, making it difficult to fully adapt to the specific package or port layout of the device under test (DUT). Summary of the Invention
[0004] To address the issues of high cost of existing TRL calibration kits leading to high testing costs, and the fixed physical interface of general-purpose TRL calibration kits making it difficult to fully adapt to the specific package or port layout of the device under test (DUT), this application provides an S-parameter testing method and system based on TRL calibration.
[0005] Firstly, this application provides an S-parameter testing method based on TRL calibration, employing the following technical solution: The method includes: Obtain the interface parameters of the component under test; A PCB test fixture is designed based on the interface parameters of the component under test. The PCB test fixture includes a TRL calibration area and a DUT test area. The PCB test fixture is SOLT calibrated using a preset standard calibration piece to calibrate the probe pair; The S-parameters of the TRL calibration area of the PCB test fixture are measured using the calibrated probe, and the system error model is calculated based on the measured S-parameters. The component under test is placed in the DUT test area of the PCB test fixture, and the raw S-parameters of the component under test are measured using a calibrated probe. The original S-parameters are input into the system error model to calculate and obtain the high-precision S-parameters after error correction.
[0006] In one specific implementation, the PCB test fixture includes a PCB substrate, on which the DUT test area and the TRL calibration area are disposed.
[0007] In one specific implementation, the TRL calibration area includes a reflection calibration area, a through calibration area, and a delay line calibration area; The reflection calibration area is equipped with a reflection standard, the through calibration area is equipped with a through standard, and the delay line calibration area is equipped with a delay line standard.
[0008] In one specific implementation, the delay line standard includes at least one delay line.
[0009] In one specific implementation, the step of using a calibrated probe to measure the S-parameters of the TRL calibration area of the PCB test fixture, and calculating and obtaining the system error model based on the measured S-parameters, includes: The calibrated probe is used to measure the TRL calibration piece corresponding to the TRL calibration area of the PCB test fixture, and the S-parameters of the TRL calibration piece corresponding to the TRL calibration area are recorded. A system error model is calculated and obtained based on the S-parameters of the TRL calibration piece using a preset calibration algorithm.
[0010] In one specific implementation, the step of calibrating the TRL calibration piece corresponding to the TRL calibration area of the PCB test fixture using the calibrated probe, and measuring and recording the S-parameters of the TRL calibration piece corresponding to the TRL calibration area, includes: The calibrated probe is used to contact the through standard component, and the S-parameters of the through standard component are measured using a preset vector network analyzer to obtain the S-parameters of the through standard component. The calibrated probe is used to contact the reflective standard, and the S-parameters of the reflective standard are measured using a preset vector network analyzer to obtain the S-parameters of the reflective standard. The delayed line standard is contacted using a calibrated probe, and the S-parameters of the delayed line standard are measured using a preset vector network analyzer to obtain the S-parameters of the delayed line standard. The process of calculating and obtaining the system error model based on the S-parameters of the TRL calibration component using a preset calibration algorithm includes: A system error model is calculated and obtained based on the S-parameters of the through standard component, the reflection standard component, and the delay line standard component using a preset calibration algorithm.
[0011] In one specific implementation, the systematic error model is a systematic error model with 12 errors.
[0012] In one specific implementation, the TRL calibration area and the DUT test area are located on the same signal layer of the PCB substrate, and the impedance, linewidth, and dielectric layer thickness of the TRL calibration area and the DUT test area are consistent.
[0013] In one specific implementation, the reflective standard, the through standard, and the delay line standard are each provided with two calibration ports for probe contact.
[0014] Secondly, this application provides an S-parameter testing system based on TRL calibration, which adopts the following technical solution: the system includes: a PCB test fixture, a probe, a vector network analyzer, and a data processing module; The PCB test fixture is used to provide a TRL calibration piece, a TRL calibration area, and a DUT test area; The probe is connected to the PCB test fixture and is used to measure the original S-parameters of the components under test mounted in the DUT test area; The vector network analyzer is connected to the probe and is used to generate excitation signals and receive the raw S-parameters measured by the probe. The data processing module is connected to the vector network analyzer and is used to receive the original S-parameters, eliminate errors using a preset calibration algorithm, and output high-precision S-parameters after error correction.
[0015] In summary, this application has the following beneficial technical effects: By designing PCB test fixtures with parameters consistent with the DUT, the matching degree between the PCB test fixture and the DUT can be improved. This ensures a high degree of consistency in the electrical characteristics (impedance, loss, parasitic effects) between the calibration environment and the test environment, eliminating systematic errors introduced by mismatch between the calibration component and the DUT, and significantly improving the testing accuracy in the high-frequency band. Simultaneously, the TRL calibration operation and the actual DUT test are performed on the same fixture and the same pair of probes, ensuring that the calibration reference surface coincides with the device test surface, eliminating mismatch errors. Secondly, matching PCB fixtures and calibration components can be quickly designed and manufactured according to the port layout, pin spacing, and package form of any DUT, solving the pain point of difficult testing of non-standard devices. Furthermore, using mature PCB technology to manufacture calibration components and fixtures results in a shorter production cycle and significantly reduced costs compared to purchasing dedicated high-frequency calibration components or custom probe cards. Attached Figure Description
[0016] Figure 1This is a flowchart of the S-parameter testing method based on TRL calibration in the embodiments of this application; Figure 2 This is a schematic diagram of the planar structure of the PCB test fixture in the embodiments of this application; Figure 3 This is the actual test environment for the S-parameter test provided in the embodiments of this application; Figure 4 This is a comparison chart of the four S-parameter curves before and after the embedding removal process in the embodiments of this application; Figure 5 This is a measured data conversion impedance diagram of S-parameters after de-embedding in an embodiment of this application; Figure 6 This is a schematic diagram of the S-parameter testing system based on TRL calibration in an embodiment of this application.
[0017] Reference numerals: 1. DUT test area; 2. Reflection calibration area; 3. Through calibration area; 4. Delay line calibration area; 5. Signal trace; 601. PCB test fixture; 602. Probe; 603. Vector network analyzer; 604. Data processing module. Detailed Implementation
[0018] The following combination Figures 1-6 This application will be described in further detail.
[0019] This application discloses an S-parameter testing method based on TRL calibration. This method eliminates systematic errors introduced by mismatch between the calibration component and the device under test (DUT), significantly improving testing accuracy in the high-frequency band. Furthermore, it allows for the rapid design and fabrication of matching PCB fixtures and calibration components based on the port layout, pin spacing, and package type of any DUT, addressing the challenge of testing non-standard devices.
[0020] S-parameters, also known as scattering parameters, are core indicators describing the incident, reflected, and transmitted characteristics of electromagnetic waves in radio frequency (RF) and microwave circuits. They are fundamental to the design and verification of modern wireless communications, radar, and high-speed digital circuits. Whether it's a chip, RF amplifier, filter, high-speed connector, or PCB transmission line, its performance is directly reflected in its S-parameters; therefore, high-precision measurement of S-parameters is crucial. During S-parameter measurement, the test system (including vector network analyzers, cables, test fixtures, etc.) itself introduces errors. Therefore, the test system needs to be calibrated before measuring S-parameters.
[0021] Currently, there are some mature TRL calibration kits available on the market that can be directly used for calibration operations of test systems. However, these existing TRL calibration kits are expensive, leading to increased testing costs. Furthermore, the physical interfaces (such as connector type and probe spacing) of commonly used TRL calibration kits are fixed, making it difficult to fully adapt to the specific package or port layout of the device under test (DUT). In addition, when using general calibration kits to test non-standard DUTs, mismatches between the "calibration surface" and the "test surface" can be introduced, reducing the reliability of the test results. To improve the accuracy of S-parameter testing and reduce testing costs, this application provides an S-parameter testing method based on TRL calibration.
[0022] Reference Figure 1 The method includes the following steps: S10: Obtain the interface parameters of the component under test.
[0023] Specifically, the interface parameters of the component under test are obtained, and a PCB test fixture with a high degree of matching can be designed based on the electrical interface and size of the component under test.
[0024] S20, design PCB test fixtures according to the interface parameters of the component under test. The PCB test fixtures include a TRL calibration area and a DUT test area.
[0025] Specifically, based on the obtained parameters of the component under test (DUT), a PCB test fixture is designed to ensure a good match between the designed PCB test fixture and the DUT, thereby resolving errors caused by mismatch and improving the testing accuracy of S-parameters. The designed PCB test fixture includes a TRL calibration area and a DUT test area.
[0026] S30 uses a preset standard calibration piece to perform SOLT calibration on the PCB test fixture to calibrate the probe pair.
[0027] Specifically, after designing the PCB test fixture, the fixture is first SOLT calibrated using a preset standard calibration plate to calibrate the probe pairs and the overall system error of the probe system (including probe tips, probe traces, fixture, and VNA ports). This achieves de-embedding of the probe system, allowing the calibration surface to be defined on the probe tip surface, eliminating the difference in signal strength from the cable to the probe tip. In actual operation, the system includes a probe station, with probes connected to the probe station. The PCB test fixture is vacuum-attached to the probe station using a probe station chunk 4. In this embodiment, GSG probes are used.
[0028] S40 uses a calibrated probe to measure the S-parameters of the TRL calibration area of the PCB test fixture, and calculates and obtains the system error model based on the measured S-parameters.
[0029] Specifically, after calibrating the probe system, the calibrated probe is used to measure the S-parameters of the TRL calibration area of the PCB test fixture, and the system error model is calculated and obtained based on the measured S-parameters. In this embodiment, the system error model used is a system error model with 12 errors.
[0030] S50 places the component under test (DUT) in the DUT test area of the PCB test fixture and uses calibrated probes to measure the original S-parameters of the DUT.
[0031] Specifically, after calibrating the probe system and calculating the system error model, the component under test (DUT) whose S-parameters need to be measured is mounted in the DUT test area of the PCB test fixture. The calibrated probes are then used to measure the raw S-parameters of the DUT in the DUT test area. In actual operation, the DUT, such as a chip, is placed in the DUT test area and then fixed by vacuum adsorption. The probe stage is moved so that the same pair of GSG probes are positioned on the test port of the DUT to perform S-parameter scanning measurements, thus achieving the measurement of the raw S-parameters.
[0032] S60 inputs the original S-parameters into the system error model to calculate and obtain the high-precision S-parameters after error correction.
[0033] Specifically, after obtaining the original S-parameters of the device under test, the original S-parameters are input into the system error model, and the measured original data is mathematically corrected and embedded into the test end face of the device to remove the influence of system error. Finally, the true and accurate S-parameters of the chip are obtained, which is the high-precision S-parameters obtained.
[0034] In this application, by specifically designing a PCB test fixture with parameters consistent with the DUT, the matching degree between the PCB test fixture and the DUT can be improved. This ensures a high degree of consistency in the electrical characteristics (impedance, loss, parasitic effects) between the calibration environment and the test environment, eliminating systematic errors introduced by mismatch between the calibration component and the DUT, and significantly improving the testing accuracy in the high-frequency band. Simultaneously, the TRL calibration operation and the actual DUT test are performed on the same fixture and the same pair of probes, ensuring that the calibration reference surface coincides with the device test surface, eliminating mismatch errors. Secondly, matching PCB fixtures and calibration components can be quickly designed and manufactured according to the port layout, pin spacing, and package form of any DUT, solving the pain point of difficult testing of non-standard devices. Furthermore, using mature PCB technology to manufacture calibration components and fixtures results in a shorter production cycle and significantly reduced costs compared to purchasing dedicated high-frequency calibration components or custom probe cards.
[0035] In one embodiment, refer to Figure 2This is a schematic diagram of the planar structure of a PCB test fixture. The designed and manufactured PCB test fixture includes a PCB substrate, which comprises multiple layers. A DUT test area and a TRL calibration area are set on the top signal layer of the PCB substrate. The TRL calibration area and the DUT test area are located on the same signal layer of the PCB substrate, and the impedance, line width, and dielectric layer thickness of the TRL calibration area and the DUT test area are consistent. Figure 2 In the diagram, area 1 is the DUT testing area, and areas 2-4 represent the TRL calibration area, which includes reflection calibration area 2, through calibration area 3, and delay line calibration area 4. The reflection calibration area has reflection standards, the through calibration area has through standards, and the delay line calibration area has delay line standards. Area 5 represents the signal traces for each standard, where each delay line standard includes at least one delay line. Each reflection, through, and delay line standard has two calibration ports for probe contact. It should be noted that the TRL calibration components include all three types of standards: reflection, through, and delay line.
[0036] When designing the PCB test fixture, the signal trace 5 led out from the calibration port and the signal trace 5 led out from the test port have the exact same trace width and share the same dielectric layer and ground layer structure, thereby ensuring that their characteristic impedance (e.g., 50Ω) is strictly consistent. The size and ground distance of the calibration port and the test port are also exactly the same.
[0037] In this application, a PCB test fixture with a high degree of matching is specifically designed according to the interface parameters of the component under test (DUT). This ensures a high degree of consistency in the electrical characteristics of the calibration environment and the test environment, eliminating systematic errors introduced by the mismatch between the calibration component and the DUT, and significantly improving the test accuracy in the high-frequency band. Furthermore, TRL calibration and DUT testing are performed on the same fixture and the same pair of probes, ensuring precise alignment of the calibration reference surface and the device test surface, thus eliminating mismatch errors at their source.
[0038] In one embodiment, the method of using a calibrated probe to measure the S-parameters of the TRL calibration area of the PCB test fixture, and calculating and obtaining the system error model based on the measured S-parameters, can be specifically performed as follows: First, the calibrated probes are used to measure the TRL calibration components corresponding to the TRL calibration area of the PCB test fixture, and the S-parameters of the TRL calibration components corresponding to the TRL calibration area are recorded. The TRL calibration components include reflection standards, through-line standards, and delay line standards. Specifically, this step can be performed as follows: The S-parameters of a through-type standard were measured using a calibrated probe and a pre-defined vector network analyzer (VNA). Similarly, the S-parameters of a reflection standard were measured using the same calibrated probe and a VNA. The S-parameters of a delay-line standard were also measured using the same VNA and a pre-defined VNA. These three types of standards can be measured using calibrated GSG probes and a VNA. Then, a systematic error model was calculated based on the S-parameters of the TRL calibrated standard using the VNA's built-in pre-defined calibration algorithm. In this embodiment, a 12-term systematic error model is used.
[0039] In this application, by testing the S-parameters of the TRL calibration area set on the PCB test fixture, a systematic error model can be calculated and obtained. In actual use, based on the calculated systematic error model and the original S-parameters of the tested component obtained from the actual DUT test area, the original S-parameters can be corrected to obtain high-precision S-parameters.
[0040] Reference Figure 3 This refers to the actual test environment for the S-parameter test provided in the embodiments of this application. (Refer to...) Figure 4 This is a comparison chart of the four S-parameter curves before and after the embedding process in the embodiments of this application. Figure 4 In the diagram, the blue curve represents the curves of the four S-parameters when the de-embedding process is only performed up to the tip of the probe, while the green curve represents the curves of the four S-parameters after the entire system has undergone de-embedding processing. Comparing the two curves, it can be seen that the curves of the S-parameters after complete de-embedding processing are closer to the actual performance of the component. Figure 5 This is a measured data transformation impedance diagram of the S-parameters after de-embedding in an embodiment of this application. Figure 5 As can be seen, the resonance point is clearer, which demonstrates the higher measurement accuracy and reliability of the proposed solution.
[0041] Figure 1 This is a flowchart illustrating an S-parameter testing method based on TRL calibration in one embodiment. It should be understood that, although... Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; unless explicitly stated otherwise, there is no strict order requirement for the execution of these steps, and they can be executed in other orders; and Figure 1At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0042] Based on the above method, this application also discloses an S-parameter testing system based on TRL calibration.
[0043] Reference Figure 6 The system includes the following modules: PCB test fixture 601, probe 602, vector network analyzer 603, and data processing module 604.
[0044] PCB test fixture 601 provides a TRL calibration kit, a TRL calibration area, and a DUT test area. Probe 602 connects to the PCB test fixture and measures the raw S-parameters of the components under test (DUTs) mounted in the DUT test area. It should be noted that the probe is generally not used alone; it needs to be used in conjunction with a probe station. In actual use, the PCB test fixture can be placed and fixed on the probe station, the probe connected to the probe station, and then the probe is used to calibrate and measure the S-parameters. Vector network analyzer 603 connects to the probe and generates excitation signals and receives the raw S-parameters measured by the probe. Data processing module 604 connects to the vector network analyzer and receives the raw S-parameters, uses a preset calibration algorithm to eliminate errors, and outputs high-precision S-parameters after error correction.
[0045] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.
Claims
1. A method for testing S-parameters based on TRL calibration, characterized in that: The method includes: Obtain the interface parameters of the component under test; A PCB test fixture is designed based on the interface parameters of the component under test. The PCB test fixture includes a TRL calibration area and a DUT test area. The PCB test fixture is SOLT calibrated using a preset standard calibration piece to calibrate the probe pair; The S-parameters of the TRL calibration area of the PCB test fixture are measured using the calibrated probe, and the system error model is calculated based on the measured S-parameters. The component under test is placed in the DUT test area of the PCB test fixture, and the raw S-parameters of the component under test are measured using a calibrated probe. The original S-parameters are input into the system error model to calculate and obtain the high-precision S-parameters after error correction.
2. The method according to claim 1, characterized in that: The PCB test fixture includes a PCB substrate, on which the DUT test area and the TRL calibration area are provided.
3. The method according to claim 2, characterized in that: The TRL calibration area includes a reflection calibration area, a through calibration area, and a delay line calibration area. The reflection calibration area is equipped with a reflection standard, the through calibration area is equipped with a through standard, and the delay line calibration area is equipped with a delay line standard.
4. The method according to claim 3, characterized in that: The delay line standard includes at least one delay line.
5. The method according to claim 3, characterized in that: The process of using calibrated probes to measure the S-parameters of the TRL calibration area of the PCB test fixture, and calculating and obtaining the system error model based on the measured S-parameters, includes: The calibrated probe is used to measure the TRL calibration piece corresponding to the TRL calibration area of the PCB test fixture, and the S-parameters of the TRL calibration piece corresponding to the TRL calibration area are recorded. A system error model is calculated and obtained based on the S-parameters of the TRL calibration piece using a preset calibration algorithm.
6. The method according to claim 5, characterized in that: The step of calibrating the TRL calibration piece corresponding to the TRL calibration area of the PCB test fixture using the calibrated probe, and measuring and recording the S-parameters of the TRL calibration piece corresponding to the TRL calibration area includes: The calibrated probe is used to contact the through standard component, and the S-parameters of the through standard component are measured using a preset vector network analyzer to obtain the S-parameters of the through standard component. The calibrated probe is used to contact the reflective standard, and the S-parameters of the reflective standard are measured using a preset vector network analyzer to obtain the S-parameters of the reflective standard. The delayed line standard was contacted using a calibrated probe, and the S-parameters of the delayed line standard were measured using a preset vector network analyzer to obtain the S-parameters of the delayed line standard. The process of calculating and obtaining the system error model based on the S-parameters of the TRL calibration component using a preset calibration algorithm includes: A system error model is calculated and obtained based on the S-parameters of the through standard component, the reflection standard component, and the delay line standard component using a preset calibration algorithm.
7. The method according to claim 5, characterized in that: The systematic error model is a systematic error model with 12 errors.
8. The method according to claim 2, characterized in that: The TRL calibration area and the DUT test area are located on the same signal layer of the PCB substrate, and the impedance, linewidth and dielectric layer thickness of the TRL calibration area and the DUT test area are consistent.
9. The method according to claim 3, characterized in that: The reflection standard, the through standard, and the delay line standard are all provided with two calibration ports for probe contact.
10. An S-parameter testing system based on TRL calibration, characterized in that: The system includes: PCB test fixtures, probes, a vector network analyzer, and a data processing module; The PCB test fixture is used to provide a TRL calibration piece, a TRL calibration area, and a DUT test area; The probe is connected to the PCB test fixture and is used to measure the original S-parameters of the components under test mounted in the DUT test area; The vector network analyzer is connected to the probe and is used to generate excitation signals and receive the raw S-parameters measured by the probe. The data processing module is connected to the vector network analyzer and is used to receive the original S-parameters, eliminate errors using a preset calibration algorithm, and output high-precision S-parameters after error correction.